| blob | 429983c06f9126e6991497a543d9c7c21912ff2e |
1 /*
2 * Boot code and exception vectors for Book3E processors
3 *
4 * Copyright (C) 2007 Ben. Herrenschmidt (benh@kernel.crashing.org), IBM Corp.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
12 #include <linux/threads.h>
13 #include <asm/reg.h>
14 #include <asm/page.h>
15 #include <asm/ppc_asm.h>
16 #include <asm/asm-offsets.h>
17 #include <asm/cputable.h>
18 #include <asm/setup.h>
19 #include <asm/thread_info.h>
20 #include <asm/reg_a2.h>
21 #include <asm/exception-64e.h>
22 #include <asm/bug.h>
23 #include <asm/irqflags.h>
24 #include <asm/ptrace.h>
25 #include <asm/ppc-opcode.h>
26 #include <asm/mmu.h>
28 /* XXX This will ultimately add space for a special exception save
29 * structure used to save things like SRR0/SRR1, SPRGs, MAS, etc...
30 * when taking special interrupts. For now we don't support that,
31 * special interrupts from within a non-standard level will probably
32 * blow you up
33 */
34 #define SPECIAL_EXC_FRAME_SIZE INT_FRAME_SIZE
36 /* Exception prolog code for all exceptions */
37 #define EXCEPTION_PROLOG(n, type, addition) \
38 mtspr SPRN_SPRG_##type##_SCRATCH,r13; /* get spare registers */ \
39 mfspr r13,SPRN_SPRG_PACA; /* get PACA */ \
40 std r10,PACA_EX##type+EX_R10(r13); \
41 std r11,PACA_EX##type+EX_R11(r13); \
42 mfcr r10; /* save CR */ \
43 addition; /* additional code for that exc. */ \
44 std r1,PACA_EX##type+EX_R1(r13); /* save old r1 in the PACA */ \
45 stw r10,PACA_EX##type+EX_CR(r13); /* save old CR in the PACA */ \
46 mfspr r11,SPRN_##type##_SRR1;/* what are we coming from */ \
47 type##_SET_KSTACK; /* get special stack if necessary */\
48 andi. r10,r11,MSR_PR; /* save stack pointer */ \
49 beq 1f; /* branch around if supervisor */ \
50 ld r1,PACAKSAVE(r13); /* get kernel stack coming from usr */\
51 1: cmpdi cr1,r1,0; /* check if SP makes sense */ \
52 bge- cr1,exc_##n##_bad_stack;/* bad stack (TODO: out of line) */ \
53 mfspr r10,SPRN_##type##_SRR0; /* read SRR0 before touching stack */
55 /* Exception type-specific macros */
56 #define GEN_SET_KSTACK \
57 subi r1,r1,INT_FRAME_SIZE; /* alloc frame on kernel stack */
58 #define SPRN_GEN_SRR0 SPRN_SRR0
59 #define SPRN_GEN_SRR1 SPRN_SRR1
61 #define CRIT_SET_KSTACK \
62 ld r1,PACA_CRIT_STACK(r13); \
63 subi r1,r1,SPECIAL_EXC_FRAME_SIZE;
64 #define SPRN_CRIT_SRR0 SPRN_CSRR0
65 #define SPRN_CRIT_SRR1 SPRN_CSRR1
67 #define DBG_SET_KSTACK \
68 ld r1,PACA_DBG_STACK(r13); \
69 subi r1,r1,SPECIAL_EXC_FRAME_SIZE;
70 #define SPRN_DBG_SRR0 SPRN_DSRR0
71 #define SPRN_DBG_SRR1 SPRN_DSRR1
73 #define MC_SET_KSTACK \
74 ld r1,PACA_MC_STACK(r13); \
75 subi r1,r1,SPECIAL_EXC_FRAME_SIZE;
76 #define SPRN_MC_SRR0 SPRN_MCSRR0
77 #define SPRN_MC_SRR1 SPRN_MCSRR1
79 #define NORMAL_EXCEPTION_PROLOG(n, addition) \
80 EXCEPTION_PROLOG(n, GEN, addition##_GEN)
82 #define CRIT_EXCEPTION_PROLOG(n, addition) \
83 EXCEPTION_PROLOG(n, CRIT, addition##_CRIT)
85 #define DBG_EXCEPTION_PROLOG(n, addition) \
86 EXCEPTION_PROLOG(n, DBG, addition##_DBG)
88 #define MC_EXCEPTION_PROLOG(n, addition) \
89 EXCEPTION_PROLOG(n, MC, addition##_MC)
92 /* Variants of the "addition" argument for the prolog
93 */
94 #define PROLOG_ADDITION_NONE_GEN
95 #define PROLOG_ADDITION_NONE_CRIT
96 #define PROLOG_ADDITION_NONE_DBG
97 #define PROLOG_ADDITION_NONE_MC
99 #define PROLOG_ADDITION_MASKABLE_GEN \
100 lbz r11,PACASOFTIRQEN(r13); /* are irqs soft-disabled ? */ \
101 cmpwi cr0,r11,0; /* yes -> go out of line */ \
102 beq masked_interrupt_book3e;
104 #define PROLOG_ADDITION_2REGS_GEN \
105 std r14,PACA_EXGEN+EX_R14(r13); \
106 std r15,PACA_EXGEN+EX_R15(r13)
108 #define PROLOG_ADDITION_1REG_GEN \
109 std r14,PACA_EXGEN+EX_R14(r13);
111 #define PROLOG_ADDITION_2REGS_CRIT \
112 std r14,PACA_EXCRIT+EX_R14(r13); \
113 std r15,PACA_EXCRIT+EX_R15(r13)
115 #define PROLOG_ADDITION_2REGS_DBG \
116 std r14,PACA_EXDBG+EX_R14(r13); \
117 std r15,PACA_EXDBG+EX_R15(r13)
119 #define PROLOG_ADDITION_2REGS_MC \
120 std r14,PACA_EXMC+EX_R14(r13); \
121 std r15,PACA_EXMC+EX_R15(r13)
123 #define PROLOG_ADDITION_DOORBELL_GEN \
124 lbz r11,PACASOFTIRQEN(r13); /* are irqs soft-disabled ? */ \
125 cmpwi cr0,r11,0; /* yes -> go out of line */ \
126 beq masked_doorbell_book3e
129 /* Core exception code for all exceptions except TLB misses.
130 * XXX: Needs to make SPRN_SPRG_GEN depend on exception type
131 */
132 #define EXCEPTION_COMMON(n, excf, ints) \
133 std r0,GPR0(r1); /* save r0 in stackframe */ \
134 std r2,GPR2(r1); /* save r2 in stackframe */ \
135 SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \
136 SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \
137 std r9,GPR9(r1); /* save r9 in stackframe */ \
138 std r10,_NIP(r1); /* save SRR0 to stackframe */ \
139 std r11,_MSR(r1); /* save SRR1 to stackframe */ \
140 ACCOUNT_CPU_USER_ENTRY(r10,r11);/* accounting (uses cr0+eq) */ \
141 ld r3,excf+EX_R10(r13); /* get back r10 */ \
142 ld r4,excf+EX_R11(r13); /* get back r11 */ \
143 mfspr r5,SPRN_SPRG_GEN_SCRATCH;/* get back r13 */ \
144 std r12,GPR12(r1); /* save r12 in stackframe */ \
145 ld r2,PACATOC(r13); /* get kernel TOC into r2 */ \
146 mflr r6; /* save LR in stackframe */ \
147 mfctr r7; /* save CTR in stackframe */ \
148 mfspr r8,SPRN_XER; /* save XER in stackframe */ \
149 ld r9,excf+EX_R1(r13); /* load orig r1 back from PACA */ \
150 lwz r10,excf+EX_CR(r13); /* load orig CR back from PACA */ \
151 lbz r11,PACASOFTIRQEN(r13); /* get current IRQ softe */ \
152 ld r12,exception_marker@toc(r2); \
153 li r0,0; \
154 std r3,GPR10(r1); /* save r10 to stackframe */ \
155 std r4,GPR11(r1); /* save r11 to stackframe */ \
156 std r5,GPR13(r1); /* save it to stackframe */ \
157 std r6,_LINK(r1); \
158 std r7,_CTR(r1); \
159 std r8,_XER(r1); \
160 li r3,(n)+1; /* indicate partial regs in trap */ \
161 std r9,0(r1); /* store stack frame back link */ \
162 std r10,_CCR(r1); /* store orig CR in stackframe */ \
163 std r9,GPR1(r1); /* store stack frame back link */ \
164 std r11,SOFTE(r1); /* and save it to stackframe */ \
165 std r12,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */ \
166 std r3,_TRAP(r1); /* set trap number */ \
167 std r0,RESULT(r1); /* clear regs->result */ \
168 ints;
170 /* Variants for the "ints" argument */
171 #define INTS_KEEP
172 #define INTS_DISABLE_SOFT \
173 stb r0,PACASOFTIRQEN(r13); /* mark interrupts soft-disabled */ \
174 TRACE_DISABLE_INTS;
175 #define INTS_DISABLE_HARD \
176 stb r0,PACAHARDIRQEN(r13); /* and hard disabled */
177 #define INTS_DISABLE_ALL \
178 INTS_DISABLE_SOFT \
179 INTS_DISABLE_HARD
181 /* This is called by exceptions that used INTS_KEEP (that is did not clear
182 * neither soft nor hard IRQ indicators in the PACA. This will restore MSR:EE
183 * to it's previous value
184 *
185 * XXX In the long run, we may want to open-code it in order to separate the
186 * load from the wrtee, thus limiting the latency caused by the dependency
187 * but at this point, I'll favor code clarity until we have a near to final
188 * implementation
189 */
190 #define INTS_RESTORE_HARD \
191 ld r11,_MSR(r1); \
192 wrtee r11;
194 /* XXX FIXME: Restore r14/r15 when necessary */
195 #define BAD_STACK_TRAMPOLINE(n) \
196 exc_##n##_bad_stack: \
197 li r1,(n); /* get exception number */ \
198 sth r1,PACA_TRAP_SAVE(r13); /* store trap */ \
199 b bad_stack_book3e; /* bad stack error */
201 /* WARNING: If you change the layout of this stub, make sure you chcek
202 * the debug exception handler which handles single stepping
203 * into exceptions from userspace, and the MM code in
204 * arch/powerpc/mm/tlb_nohash.c which patches the branch here
205 * and would need to be updated if that branch is moved
206 */
207 #define EXCEPTION_STUB(loc, label) \
208 . = interrupt_base_book3e + loc; \
209 nop; /* To make debug interrupts happy */ \
210 b exc_##label##_book3e;
212 #define ACK_NONE(r)
213 #define ACK_DEC(r) \
214 lis r,TSR_DIS@h; \
215 mtspr SPRN_TSR,r
216 #define ACK_FIT(r) \
217 lis r,TSR_FIS@h; \
218 mtspr SPRN_TSR,r
220 /* Used by asynchronous interrupt that may happen in the idle loop.
221 *
222 * This check if the thread was in the idle loop, and if yes, returns
223 * to the caller rather than the PC. This is to avoid a race if
224 * interrupts happen before the wait instruction.
225 */
226 #define CHECK_NAPPING() \
227 clrrdi r11,r1,THREAD_SHIFT; \
228 ld r10,TI_LOCAL_FLAGS(r11); \
229 andi. r9,r10,_TLF_NAPPING; \
230 beq+ 1f; \
231 ld r8,_LINK(r1); \
232 rlwinm r7,r10,0,~_TLF_NAPPING; \
233 std r8,_NIP(r1); \
234 std r7,TI_LOCAL_FLAGS(r11); \
235 1:
238 #define MASKABLE_EXCEPTION(trapnum, label, hdlr, ack) \
239 START_EXCEPTION(label); \
240 NORMAL_EXCEPTION_PROLOG(trapnum, PROLOG_ADDITION_MASKABLE) \
241 EXCEPTION_COMMON(trapnum, PACA_EXGEN, INTS_DISABLE_ALL) \
242 ack(r8); \
243 CHECK_NAPPING(); \
244 addi r3,r1,STACK_FRAME_OVERHEAD; \
245 bl hdlr; \
246 b .ret_from_except_lite;
248 /* This value is used to mark exception frames on the stack. */
249 .section ".toc","aw"
250 exception_marker:
251 .tc ID_EXC_MARKER[TC],STACK_FRAME_REGS_MARKER
254 /*
255 * And here we have the exception vectors !
256 */
258 .text
259 .balign 0x1000
260 .globl interrupt_base_book3e
261 interrupt_base_book3e: /* fake trap */
262 EXCEPTION_STUB(0x000, machine_check) /* 0x0200 */
263 EXCEPTION_STUB(0x020, critical_input) /* 0x0580 */
264 EXCEPTION_STUB(0x040, debug_crit) /* 0x0d00 */
265 EXCEPTION_STUB(0x060, data_storage) /* 0x0300 */
266 EXCEPTION_STUB(0x080, instruction_storage) /* 0x0400 */
267 EXCEPTION_STUB(0x0a0, external_input) /* 0x0500 */
268 EXCEPTION_STUB(0x0c0, alignment) /* 0x0600 */
269 EXCEPTION_STUB(0x0e0, program) /* 0x0700 */
270 EXCEPTION_STUB(0x100, fp_unavailable) /* 0x0800 */
271 EXCEPTION_STUB(0x120, system_call) /* 0x0c00 */
272 EXCEPTION_STUB(0x140, ap_unavailable) /* 0x0f20 */
273 EXCEPTION_STUB(0x160, decrementer) /* 0x0900 */
274 EXCEPTION_STUB(0x180, fixed_interval) /* 0x0980 */
275 EXCEPTION_STUB(0x1a0, watchdog) /* 0x09f0 */
276 EXCEPTION_STUB(0x1c0, data_tlb_miss)
277 EXCEPTION_STUB(0x1e0, instruction_tlb_miss)
278 EXCEPTION_STUB(0x260, perfmon)
279 EXCEPTION_STUB(0x280, doorbell)
280 EXCEPTION_STUB(0x2a0, doorbell_crit)
281 EXCEPTION_STUB(0x2c0, guest_doorbell)
282 EXCEPTION_STUB(0x2e0, guest_doorbell_crit)
283 EXCEPTION_STUB(0x300, hypercall)
284 EXCEPTION_STUB(0x320, ehpriv)
286 .globl interrupt_end_book3e
287 interrupt_end_book3e:
289 /* Critical Input Interrupt */
290 START_EXCEPTION(critical_input);
291 CRIT_EXCEPTION_PROLOG(0x100, PROLOG_ADDITION_NONE)
292 // EXCEPTION_COMMON(0x100, PACA_EXCRIT, INTS_DISABLE_ALL)
293 // bl special_reg_save_crit
294 // CHECK_NAPPING();
295 // addi r3,r1,STACK_FRAME_OVERHEAD
296 // bl .critical_exception
297 // b ret_from_crit_except
298 b .
300 /* Machine Check Interrupt */
301 START_EXCEPTION(machine_check);
302 CRIT_EXCEPTION_PROLOG(0x200, PROLOG_ADDITION_NONE)
303 // EXCEPTION_COMMON(0x200, PACA_EXMC, INTS_DISABLE_ALL)
304 // bl special_reg_save_mc
305 // addi r3,r1,STACK_FRAME_OVERHEAD
306 // CHECK_NAPPING();
307 // bl .machine_check_exception
308 // b ret_from_mc_except
309 b .
311 /* Data Storage Interrupt */
312 START_EXCEPTION(data_storage)
313 NORMAL_EXCEPTION_PROLOG(0x300, PROLOG_ADDITION_2REGS)
314 mfspr r14,SPRN_DEAR
315 mfspr r15,SPRN_ESR
316 EXCEPTION_COMMON(0x300, PACA_EXGEN, INTS_KEEP)
317 b storage_fault_common
319 /* Instruction Storage Interrupt */
320 START_EXCEPTION(instruction_storage);
321 NORMAL_EXCEPTION_PROLOG(0x400, PROLOG_ADDITION_2REGS)
322 li r15,0
323 mr r14,r10
324 EXCEPTION_COMMON(0x400, PACA_EXGEN, INTS_KEEP)
325 b storage_fault_common
327 /* External Input Interrupt */
328 MASKABLE_EXCEPTION(0x500, external_input, .do_IRQ, ACK_NONE)
330 /* Alignment */
331 START_EXCEPTION(alignment);
332 NORMAL_EXCEPTION_PROLOG(0x600, PROLOG_ADDITION_2REGS)
333 mfspr r14,SPRN_DEAR
334 mfspr r15,SPRN_ESR
335 EXCEPTION_COMMON(0x600, PACA_EXGEN, INTS_KEEP)
336 b alignment_more /* no room, go out of line */
338 /* Program Interrupt */
339 START_EXCEPTION(program);
340 NORMAL_EXCEPTION_PROLOG(0x700, PROLOG_ADDITION_1REG)
341 mfspr r14,SPRN_ESR
342 EXCEPTION_COMMON(0x700, PACA_EXGEN, INTS_DISABLE_SOFT)
343 std r14,_DSISR(r1)
344 addi r3,r1,STACK_FRAME_OVERHEAD
345 ld r14,PACA_EXGEN+EX_R14(r13)
346 bl .save_nvgprs
347 INTS_RESTORE_HARD
348 bl .program_check_exception
349 b .ret_from_except
351 /* Floating Point Unavailable Interrupt */
352 START_EXCEPTION(fp_unavailable);
353 NORMAL_EXCEPTION_PROLOG(0x800, PROLOG_ADDITION_NONE)
354 /* we can probably do a shorter exception entry for that one... */
355 EXCEPTION_COMMON(0x800, PACA_EXGEN, INTS_KEEP)
356 bne 1f /* if from user, just load it up */
357 bl .save_nvgprs
358 addi r3,r1,STACK_FRAME_OVERHEAD
359 INTS_RESTORE_HARD
360 bl .kernel_fp_unavailable_exception
361 BUG_OPCODE
362 1: ld r12,_MSR(r1)
363 bl .load_up_fpu
364 b fast_exception_return
366 /* Decrementer Interrupt */
367 MASKABLE_EXCEPTION(0x900, decrementer, .timer_interrupt, ACK_DEC)
369 /* Fixed Interval Timer Interrupt */
370 MASKABLE_EXCEPTION(0x980, fixed_interval, .unknown_exception, ACK_FIT)
372 /* Watchdog Timer Interrupt */
373 START_EXCEPTION(watchdog);
374 CRIT_EXCEPTION_PROLOG(0x9f0, PROLOG_ADDITION_NONE)
375 // EXCEPTION_COMMON(0x9f0, PACA_EXCRIT, INTS_DISABLE_ALL)
376 // bl special_reg_save_crit
377 // CHECK_NAPPING();
378 // addi r3,r1,STACK_FRAME_OVERHEAD
379 // bl .unknown_exception
380 // b ret_from_crit_except
381 b .
383 /* System Call Interrupt */
384 START_EXCEPTION(system_call)
385 mr r9,r13 /* keep a copy of userland r13 */
386 mfspr r11,SPRN_SRR0 /* get return address */
387 mfspr r12,SPRN_SRR1 /* get previous MSR */
388 mfspr r13,SPRN_SPRG_PACA /* get our PACA */
389 b system_call_common
391 /* Auxiliary Processor Unavailable Interrupt */
392 START_EXCEPTION(ap_unavailable);
393 NORMAL_EXCEPTION_PROLOG(0xf20, PROLOG_ADDITION_NONE)
394 EXCEPTION_COMMON(0xf20, PACA_EXGEN, INTS_KEEP)
395 addi r3,r1,STACK_FRAME_OVERHEAD
396 bl .save_nvgprs
397 INTS_RESTORE_HARD
398 bl .unknown_exception
399 b .ret_from_except
401 /* Debug exception as a critical interrupt*/
402 START_EXCEPTION(debug_crit);
403 CRIT_EXCEPTION_PROLOG(0xd00, PROLOG_ADDITION_2REGS)
405 /*
406 * If there is a single step or branch-taken exception in an
407 * exception entry sequence, it was probably meant to apply to
408 * the code where the exception occurred (since exception entry
409 * doesn't turn off DE automatically). We simulate the effect
410 * of turning off DE on entry to an exception handler by turning
411 * off DE in the CSRR1 value and clearing the debug status.
412 */
414 mfspr r14,SPRN_DBSR /* check single-step/branch taken */
415 andis. r15,r14,DBSR_IC@h
416 beq+ 1f
418 LOAD_REG_IMMEDIATE(r14,interrupt_base_book3e)
419 LOAD_REG_IMMEDIATE(r15,interrupt_end_book3e)
420 cmpld cr0,r10,r14
421 cmpld cr1,r10,r15
422 blt+ cr0,1f
423 bge+ cr1,1f
425 /* here it looks like we got an inappropriate debug exception. */
426 lis r14,DBSR_IC@h /* clear the IC event */
427 rlwinm r11,r11,0,~MSR_DE /* clear DE in the CSRR1 value */
428 mtspr SPRN_DBSR,r14
429 mtspr SPRN_CSRR1,r11
430 lwz r10,PACA_EXCRIT+EX_CR(r13) /* restore registers */
431 ld r1,PACA_EXCRIT+EX_R1(r13)
432 ld r14,PACA_EXCRIT+EX_R14(r13)
433 ld r15,PACA_EXCRIT+EX_R15(r13)
434 mtcr r10
435 ld r10,PACA_EXCRIT+EX_R10(r13) /* restore registers */
436 ld r11,PACA_EXCRIT+EX_R11(r13)
437 mfspr r13,SPRN_SPRG_CRIT_SCRATCH
438 rfci
440 /* Normal debug exception */
441 /* XXX We only handle coming from userspace for now since we can't
442 * quite save properly an interrupted kernel state yet
443 */
444 1: andi. r14,r11,MSR_PR; /* check for userspace again */
445 beq kernel_dbg_exc; /* if from kernel mode */
447 /* Now we mash up things to make it look like we are coming on a
448 * normal exception
449 */
450 mfspr r15,SPRN_SPRG_CRIT_SCRATCH
451 mtspr SPRN_SPRG_GEN_SCRATCH,r15
452 mfspr r14,SPRN_DBSR
453 EXCEPTION_COMMON(0xd00, PACA_EXCRIT, INTS_DISABLE_ALL)
454 std r14,_DSISR(r1)
455 addi r3,r1,STACK_FRAME_OVERHEAD
456 mr r4,r14
457 ld r14,PACA_EXCRIT+EX_R14(r13)
458 ld r15,PACA_EXCRIT+EX_R15(r13)
459 bl .save_nvgprs
460 bl .DebugException
461 b .ret_from_except
463 kernel_dbg_exc:
464 b . /* NYI */
466 /* Debug exception as a debug interrupt*/
467 START_EXCEPTION(debug_debug);
468 DBG_EXCEPTION_PROLOG(0xd00, PROLOG_ADDITION_2REGS)
470 /*
471 * If there is a single step or branch-taken exception in an
472 * exception entry sequence, it was probably meant to apply to
473 * the code where the exception occurred (since exception entry
474 * doesn't turn off DE automatically). We simulate the effect
475 * of turning off DE on entry to an exception handler by turning
476 * off DE in the DSRR1 value and clearing the debug status.
477 */
479 mfspr r14,SPRN_DBSR /* check single-step/branch taken */
480 andis. r15,r14,DBSR_IC@h
481 beq+ 1f
483 LOAD_REG_IMMEDIATE(r14,interrupt_base_book3e)
484 LOAD_REG_IMMEDIATE(r15,interrupt_end_book3e)
485 cmpld cr0,r10,r14
486 cmpld cr1,r10,r15
487 blt+ cr0,1f
488 bge+ cr1,1f
490 /* here it looks like we got an inappropriate debug exception. */
491 lis r14,DBSR_IC@h /* clear the IC event */
492 rlwinm r11,r11,0,~MSR_DE /* clear DE in the DSRR1 value */
493 mtspr SPRN_DBSR,r14
494 mtspr SPRN_DSRR1,r11
495 lwz r10,PACA_EXDBG+EX_CR(r13) /* restore registers */
496 ld r1,PACA_EXDBG+EX_R1(r13)
497 ld r14,PACA_EXDBG+EX_R14(r13)
498 ld r15,PACA_EXDBG+EX_R15(r13)
499 mtcr r10
500 ld r10,PACA_EXDBG+EX_R10(r13) /* restore registers */
501 ld r11,PACA_EXDBG+EX_R11(r13)
502 mfspr r13,SPRN_SPRG_DBG_SCRATCH
503 rfdi
505 /* Normal debug exception */
506 /* XXX We only handle coming from userspace for now since we can't
507 * quite save properly an interrupted kernel state yet
508 */
509 1: andi. r14,r11,MSR_PR; /* check for userspace again */
510 beq kernel_dbg_exc; /* if from kernel mode */
512 /* Now we mash up things to make it look like we are coming on a
513 * normal exception
514 */
515 mfspr r15,SPRN_SPRG_DBG_SCRATCH
516 mtspr SPRN_SPRG_GEN_SCRATCH,r15
517 mfspr r14,SPRN_DBSR
518 EXCEPTION_COMMON(0xd00, PACA_EXDBG, INTS_DISABLE_ALL)
519 std r14,_DSISR(r1)
520 addi r3,r1,STACK_FRAME_OVERHEAD
521 mr r4,r14
522 ld r14,PACA_EXDBG+EX_R14(r13)
523 ld r15,PACA_EXDBG+EX_R15(r13)
524 bl .save_nvgprs
525 bl .DebugException
526 b .ret_from_except
528 MASKABLE_EXCEPTION(0x260, perfmon, .performance_monitor_exception, ACK_NONE)
530 /* Doorbell interrupt */
531 START_EXCEPTION(doorbell)
532 NORMAL_EXCEPTION_PROLOG(0x2070, PROLOG_ADDITION_DOORBELL)
533 EXCEPTION_COMMON(0x2070, PACA_EXGEN, INTS_DISABLE_ALL)
534 CHECK_NAPPING()
535 addi r3,r1,STACK_FRAME_OVERHEAD
536 bl .doorbell_exception
537 b .ret_from_except_lite
539 /* Doorbell critical Interrupt */
540 START_EXCEPTION(doorbell_crit);
541 CRIT_EXCEPTION_PROLOG(0x2080, PROLOG_ADDITION_NONE)
542 // EXCEPTION_COMMON(0x2080, PACA_EXCRIT, INTS_DISABLE_ALL)
543 // bl special_reg_save_crit
544 // CHECK_NAPPING();
545 // addi r3,r1,STACK_FRAME_OVERHEAD
546 // bl .doorbell_critical_exception
547 // b ret_from_crit_except
548 b .
550 MASKABLE_EXCEPTION(0x2c0, guest_doorbell, .unknown_exception, ACK_NONE)
551 MASKABLE_EXCEPTION(0x2e0, guest_doorbell_crit, .unknown_exception, ACK_NONE)
552 MASKABLE_EXCEPTION(0x310, hypercall, .unknown_exception, ACK_NONE)
553 MASKABLE_EXCEPTION(0x320, ehpriv, .unknown_exception, ACK_NONE)
556 /*
557 * An interrupt came in while soft-disabled; clear EE in SRR1,
558 * clear paca->hard_enabled and return.
559 */
560 masked_doorbell_book3e:
561 mtcr r10
562 /* Resend the doorbell to fire again when ints enabled */
563 mfspr r10,SPRN_PIR
564 PPC_MSGSND(r10)
565 b masked_interrupt_book3e_common
567 masked_interrupt_book3e:
568 mtcr r10
569 masked_interrupt_book3e_common:
570 stb r11,PACAHARDIRQEN(r13)
571 mfspr r10,SPRN_SRR1
572 rldicl r11,r10,48,1 /* clear MSR_EE */
573 rotldi r10,r11,16
574 mtspr SPRN_SRR1,r10
575 ld r10,PACA_EXGEN+EX_R10(r13); /* restore registers */
576 ld r11,PACA_EXGEN+EX_R11(r13);
577 mfspr r13,SPRN_SPRG_GEN_SCRATCH;
578 rfi
579 b .
581 /*
582 * This is called from 0x300 and 0x400 handlers after the prologs with
583 * r14 and r15 containing the fault address and error code, with the
584 * original values stashed away in the PACA
585 */
586 storage_fault_common:
587 std r14,_DAR(r1)
588 std r15,_DSISR(r1)
589 addi r3,r1,STACK_FRAME_OVERHEAD
590 mr r4,r14
591 mr r5,r15
592 ld r14,PACA_EXGEN+EX_R14(r13)
593 ld r15,PACA_EXGEN+EX_R15(r13)
594 INTS_RESTORE_HARD
595 bl .do_page_fault
596 cmpdi r3,0
597 bne- 1f
598 b .ret_from_except_lite
599 1: bl .save_nvgprs
600 mr r5,r3
601 addi r3,r1,STACK_FRAME_OVERHEAD
602 ld r4,_DAR(r1)
603 bl .bad_page_fault
604 b .ret_from_except
606 /*
607 * Alignment exception doesn't fit entirely in the 0x100 bytes so it
608 * continues here.
609 */
610 alignment_more:
611 std r14,_DAR(r1)
612 std r15,_DSISR(r1)
613 addi r3,r1,STACK_FRAME_OVERHEAD
614 ld r14,PACA_EXGEN+EX_R14(r13)
615 ld r15,PACA_EXGEN+EX_R15(r13)
616 bl .save_nvgprs
617 INTS_RESTORE_HARD
618 bl .alignment_exception
619 b .ret_from_except
621 /*
622 * We branch here from entry_64.S for the last stage of the exception
623 * return code path. MSR:EE is expected to be off at that point
624 */
625 _GLOBAL(exception_return_book3e)
626 b 1f
628 /* This is the return from load_up_fpu fast path which could do with
629 * less GPR restores in fact, but for now we have a single return path
630 */
631 .globl fast_exception_return
632 fast_exception_return:
633 wrteei 0
634 1: mr r0,r13
635 ld r10,_MSR(r1)
636 REST_4GPRS(2, r1)
637 andi. r6,r10,MSR_PR
638 REST_2GPRS(6, r1)
639 beq 1f
640 ACCOUNT_CPU_USER_EXIT(r10, r11)
641 ld r0,GPR13(r1)
643 1: stdcx. r0,0,r1 /* to clear the reservation */
645 ld r8,_CCR(r1)
646 ld r9,_LINK(r1)
647 ld r10,_CTR(r1)
648 ld r11,_XER(r1)
649 mtcr r8
650 mtlr r9
651 mtctr r10
652 mtxer r11
653 REST_2GPRS(8, r1)
654 ld r10,GPR10(r1)
655 ld r11,GPR11(r1)
656 ld r12,GPR12(r1)
657 mtspr SPRN_SPRG_GEN_SCRATCH,r0
659 std r10,PACA_EXGEN+EX_R10(r13);
660 std r11,PACA_EXGEN+EX_R11(r13);
661 ld r10,_NIP(r1)
662 ld r11,_MSR(r1)
663 ld r0,GPR0(r1)
664 ld r1,GPR1(r1)
665 mtspr SPRN_SRR0,r10
666 mtspr SPRN_SRR1,r11
667 ld r10,PACA_EXGEN+EX_R10(r13)
668 ld r11,PACA_EXGEN+EX_R11(r13)
669 mfspr r13,SPRN_SPRG_GEN_SCRATCH
670 rfi
672 /*
673 * Trampolines used when spotting a bad kernel stack pointer in
674 * the exception entry code.
675 *
676 * TODO: move some bits like SRR0 read to trampoline, pass PACA
677 * index around, etc... to handle crit & mcheck
678 */
679 BAD_STACK_TRAMPOLINE(0x000)
680 BAD_STACK_TRAMPOLINE(0x100)
681 BAD_STACK_TRAMPOLINE(0x200)
682 BAD_STACK_TRAMPOLINE(0x260)
683 BAD_STACK_TRAMPOLINE(0x2c0)
684 BAD_STACK_TRAMPOLINE(0x2e0)
685 BAD_STACK_TRAMPOLINE(0x300)
686 BAD_STACK_TRAMPOLINE(0x310)
687 BAD_STACK_TRAMPOLINE(0x320)
688 BAD_STACK_TRAMPOLINE(0x400)
689 BAD_STACK_TRAMPOLINE(0x500)
690 BAD_STACK_TRAMPOLINE(0x600)
691 BAD_STACK_TRAMPOLINE(0x700)
692 BAD_STACK_TRAMPOLINE(0x800)
693 BAD_STACK_TRAMPOLINE(0x900)
694 BAD_STACK_TRAMPOLINE(0x980)
695 BAD_STACK_TRAMPOLINE(0x9f0)
696 BAD_STACK_TRAMPOLINE(0xa00)
697 BAD_STACK_TRAMPOLINE(0xb00)
698 BAD_STACK_TRAMPOLINE(0xc00)
699 BAD_STACK_TRAMPOLINE(0xd00)
700 BAD_STACK_TRAMPOLINE(0xe00)
701 BAD_STACK_TRAMPOLINE(0xf00)
702 BAD_STACK_TRAMPOLINE(0xf20)
703 BAD_STACK_TRAMPOLINE(0x2070)
704 BAD_STACK_TRAMPOLINE(0x2080)
706 .globl bad_stack_book3e
707 bad_stack_book3e:
708 /* XXX: Needs to make SPRN_SPRG_GEN depend on exception type */
709 mfspr r10,SPRN_SRR0; /* read SRR0 before touching stack */
710 ld r1,PACAEMERGSP(r13)
711 subi r1,r1,64+INT_FRAME_SIZE
712 std r10,_NIP(r1)
713 std r11,_MSR(r1)
714 ld r10,PACA_EXGEN+EX_R1(r13) /* FIXME for crit & mcheck */
715 lwz r11,PACA_EXGEN+EX_CR(r13) /* FIXME for crit & mcheck */
716 std r10,GPR1(r1)
717 std r11,_CCR(r1)
718 mfspr r10,SPRN_DEAR
719 mfspr r11,SPRN_ESR
720 std r10,_DAR(r1)
721 std r11,_DSISR(r1)
722 std r0,GPR0(r1); /* save r0 in stackframe */ \
723 std r2,GPR2(r1); /* save r2 in stackframe */ \
724 SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \
725 SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \
726 std r9,GPR9(r1); /* save r9 in stackframe */ \
727 ld r3,PACA_EXGEN+EX_R10(r13);/* get back r10 */ \
728 ld r4,PACA_EXGEN+EX_R11(r13);/* get back r11 */ \
729 mfspr r5,SPRN_SPRG_GEN_SCRATCH;/* get back r13 XXX can be wrong */ \
730 std r3,GPR10(r1); /* save r10 to stackframe */ \
731 std r4,GPR11(r1); /* save r11 to stackframe */ \
732 std r12,GPR12(r1); /* save r12 in stackframe */ \
733 std r5,GPR13(r1); /* save it to stackframe */ \
734 mflr r10
735 mfctr r11
736 mfxer r12
737 std r10,_LINK(r1)
738 std r11,_CTR(r1)
739 std r12,_XER(r1)
740 SAVE_10GPRS(14,r1)
741 SAVE_8GPRS(24,r1)
742 lhz r12,PACA_TRAP_SAVE(r13)
743 std r12,_TRAP(r1)
744 addi r11,r1,INT_FRAME_SIZE
745 std r11,0(r1)
746 li r12,0
747 std r12,0(r11)
748 ld r2,PACATOC(r13)
749 1: addi r3,r1,STACK_FRAME_OVERHEAD
750 bl .kernel_bad_stack
751 b 1b
753 /*
754 * Setup the initial TLB for a core. This current implementation
755 * assume that whatever we are running off will not conflict with
756 * the new mapping at PAGE_OFFSET.
757 */
758 _GLOBAL(initial_tlb_book3e)
760 /* Look for the first TLB with IPROT set */
761 mfspr r4,SPRN_TLB0CFG
762 andi. r3,r4,TLBnCFG_IPROT
763 lis r3,MAS0_TLBSEL(0)@h
764 bne found_iprot
766 mfspr r4,SPRN_TLB1CFG
767 andi. r3,r4,TLBnCFG_IPROT
768 lis r3,MAS0_TLBSEL(1)@h
769 bne found_iprot
771 mfspr r4,SPRN_TLB2CFG
772 andi. r3,r4,TLBnCFG_IPROT
773 lis r3,MAS0_TLBSEL(2)@h
774 bne found_iprot
776 lis r3,MAS0_TLBSEL(3)@h
777 mfspr r4,SPRN_TLB3CFG
778 /* fall through */
780 found_iprot:
781 andi. r5,r4,TLBnCFG_HES
782 bne have_hes
784 mflr r8 /* save LR */
785 /* 1. Find the index of the entry we're executing in
786 *
787 * r3 = MAS0_TLBSEL (for the iprot array)
788 * r4 = SPRN_TLBnCFG
789 */
790 bl invstr /* Find our address */
791 invstr: mflr r6 /* Make it accessible */
792 mfmsr r7
793 rlwinm r5,r7,27,31,31 /* extract MSR[IS] */
794 mfspr r7,SPRN_PID
795 slwi r7,r7,16
796 or r7,r7,r5
797 mtspr SPRN_MAS6,r7
798 tlbsx 0,r6 /* search MSR[IS], SPID=PID */
800 mfspr r3,SPRN_MAS0
801 rlwinm r5,r3,16,20,31 /* Extract MAS0(Entry) */
803 mfspr r7,SPRN_MAS1 /* Insure IPROT set */
804 oris r7,r7,MAS1_IPROT@h
805 mtspr SPRN_MAS1,r7
806 tlbwe
808 /* 2. Invalidate all entries except the entry we're executing in
809 *
810 * r3 = MAS0 w/TLBSEL & ESEL for the entry we are running in
811 * r4 = SPRN_TLBnCFG
812 * r5 = ESEL of entry we are running in
813 */
814 andi. r4,r4,TLBnCFG_N_ENTRY /* Extract # entries */
815 li r6,0 /* Set Entry counter to 0 */
816 1: mr r7,r3 /* Set MAS0(TLBSEL) */
817 rlwimi r7,r6,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r6) */
818 mtspr SPRN_MAS0,r7
819 tlbre
820 mfspr r7,SPRN_MAS1
821 rlwinm r7,r7,0,2,31 /* Clear MAS1 Valid and IPROT */
822 cmpw r5,r6
823 beq skpinv /* Dont update the current execution TLB */
824 mtspr SPRN_MAS1,r7
825 tlbwe
826 isync
827 skpinv: addi r6,r6,1 /* Increment */
828 cmpw r6,r4 /* Are we done? */
829 bne 1b /* If not, repeat */
831 /* Invalidate all TLBs */
832 PPC_TLBILX_ALL(0,0)
833 sync
834 isync
836 /* 3. Setup a temp mapping and jump to it
837 *
838 * r3 = MAS0 w/TLBSEL & ESEL for the entry we are running in
839 * r5 = ESEL of entry we are running in
840 */
841 andi. r7,r5,0x1 /* Find an entry not used and is non-zero */
842 addi r7,r7,0x1
843 mr r4,r3 /* Set MAS0(TLBSEL) = 1 */
844 mtspr SPRN_MAS0,r4
845 tlbre
847 rlwimi r4,r7,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r7) */
848 mtspr SPRN_MAS0,r4
850 mfspr r7,SPRN_MAS1
851 xori r6,r7,MAS1_TS /* Setup TMP mapping in the other Address space */
852 mtspr SPRN_MAS1,r6
854 tlbwe
856 mfmsr r6
857 xori r6,r6,MSR_IS
858 mtspr SPRN_SRR1,r6
859 bl 1f /* Find our address */
860 1: mflr r6
861 addi r6,r6,(2f - 1b)
862 mtspr SPRN_SRR0,r6
863 rfi
864 2:
866 /* 4. Clear out PIDs & Search info
867 *
868 * r3 = MAS0 w/TLBSEL & ESEL for the entry we started in
869 * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping
870 * r5 = MAS3
871 */
872 li r6,0
873 mtspr SPRN_MAS6,r6
874 mtspr SPRN_PID,r6
876 /* 5. Invalidate mapping we started in
877 *
878 * r3 = MAS0 w/TLBSEL & ESEL for the entry we started in
879 * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping
880 * r5 = MAS3
881 */
882 mtspr SPRN_MAS0,r3
883 tlbre
884 mfspr r6,SPRN_MAS1
885 rlwinm r6,r6,0,2,0 /* clear IPROT */
886 mtspr SPRN_MAS1,r6
887 tlbwe
889 /* Invalidate TLB1 */
890 PPC_TLBILX_ALL(0,0)
891 sync
892 isync
894 /* The mapping only needs to be cache-coherent on SMP */
895 #ifdef CONFIG_SMP
896 #define M_IF_SMP MAS2_M
897 #else
898 #define M_IF_SMP 0
899 #endif
901 /* 6. Setup KERNELBASE mapping in TLB[0]
902 *
903 * r3 = MAS0 w/TLBSEL & ESEL for the entry we started in
904 * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping
905 * r5 = MAS3
906 */
907 rlwinm r3,r3,0,16,3 /* clear ESEL */
908 mtspr SPRN_MAS0,r3
909 lis r6,(MAS1_VALID|MAS1_IPROT)@h
910 ori r6,r6,(MAS1_TSIZE(BOOK3E_PAGESZ_1GB))@l
911 mtspr SPRN_MAS1,r6
913 LOAD_REG_IMMEDIATE(r6, PAGE_OFFSET | M_IF_SMP)
914 mtspr SPRN_MAS2,r6
916 rlwinm r5,r5,0,0,25
917 ori r5,r5,MAS3_SR | MAS3_SW | MAS3_SX
918 mtspr SPRN_MAS3,r5
919 li r5,-1
920 rlwinm r5,r5,0,0,25
922 tlbwe
924 /* 7. Jump to KERNELBASE mapping
925 *
926 * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping
927 */
928 /* Now we branch the new virtual address mapped by this entry */
929 LOAD_REG_IMMEDIATE(r6,2f)
930 lis r7,MSR_KERNEL@h
931 ori r7,r7,MSR_KERNEL@l
932 mtspr SPRN_SRR0,r6
933 mtspr SPRN_SRR1,r7
934 rfi /* start execution out of TLB1[0] entry */
935 2:
937 /* 8. Clear out the temp mapping
938 *
939 * r4 = MAS0 w/TLBSEL & ESEL for the entry we are running in
940 */
941 mtspr SPRN_MAS0,r4
942 tlbre
943 mfspr r5,SPRN_MAS1
944 rlwinm r5,r5,0,2,0 /* clear IPROT */
945 mtspr SPRN_MAS1,r5
946 tlbwe
948 /* Invalidate TLB1 */
949 PPC_TLBILX_ALL(0,0)
950 sync
951 isync
953 /* We translate LR and return */
954 tovirt(r8,r8)
955 mtlr r8
956 blr
958 have_hes:
959 /* Setup MAS 0,1,2,3 and 7 for tlbwe of a 1G entry that maps the
960 * kernel linear mapping. We also set MAS8 once for all here though
961 * that will have to be made dependent on whether we are running under
962 * a hypervisor I suppose.
963 */
965 /* BEWARE, MAGIC
966 * This code is called as an ordinary function on the boot CPU. But to
967 * avoid duplication, this code is also used in SCOM bringup of
968 * secondary CPUs. We read the code between the initial_tlb_code_start
969 * and initial_tlb_code_end labels one instruction at a time and RAM it
970 * into the new core via SCOM. That doesn't process branches, so there
971 * must be none between those two labels. It also means if this code
972 * ever takes any parameters, the SCOM code must also be updated to
973 * provide them.
974 */
975 .globl a2_tlbinit_code_start
976 a2_tlbinit_code_start:
978 ori r11,r3,MAS0_WQ_ALLWAYS
979 oris r11,r11,MAS0_ESEL(3)@h /* Use way 3: workaround A2 erratum 376 */
980 mtspr SPRN_MAS0,r11
981 lis r3,(MAS1_VALID | MAS1_IPROT)@h
982 ori r3,r3,BOOK3E_PAGESZ_1GB << MAS1_TSIZE_SHIFT
983 mtspr SPRN_MAS1,r3
984 LOAD_REG_IMMEDIATE(r3, PAGE_OFFSET | MAS2_M)
985 mtspr SPRN_MAS2,r3
986 li r3,MAS3_SR | MAS3_SW | MAS3_SX
987 mtspr SPRN_MAS7_MAS3,r3
988 li r3,0
989 mtspr SPRN_MAS8,r3
991 /* Write the TLB entry */
992 tlbwe
994 .globl a2_tlbinit_after_linear_map
995 a2_tlbinit_after_linear_map:
997 /* Now we branch the new virtual address mapped by this entry */
998 LOAD_REG_IMMEDIATE(r3,1f)
999 mtctr r3
1000 bctr
1002 1: /* We are now running at PAGE_OFFSET, clean the TLB of everything
1003 * else (including IPROTed things left by firmware)
1004 * r4 = TLBnCFG
1005 * r3 = current address (more or less)
1006 */
1008 li r5,0
1009 mtspr SPRN_MAS6,r5
1010 tlbsx 0,r3
1012 rlwinm r9,r4,0,TLBnCFG_N_ENTRY
1013 rlwinm r10,r4,8,0xff
1014 addi r10,r10,-1 /* Get inner loop mask */
1016 li r3,1
1018 mfspr r5,SPRN_MAS1
1019 rlwinm r5,r5,0,(~(MAS1_VALID|MAS1_IPROT))
1021 mfspr r6,SPRN_MAS2
1022 rldicr r6,r6,0,51 /* Extract EPN */
1024 mfspr r7,SPRN_MAS0
1025 rlwinm r7,r7,0,0xffff0fff /* Clear HES and WQ */
1027 rlwinm r8,r7,16,0xfff /* Extract ESEL */
1029 2: add r4,r3,r8
1030 and r4,r4,r10
1032 rlwimi r7,r4,16,MAS0_ESEL_MASK
1034 mtspr SPRN_MAS0,r7
1035 mtspr SPRN_MAS1,r5
1036 mtspr SPRN_MAS2,r6
1037 tlbwe
1039 addi r3,r3,1
1040 and. r4,r3,r10
1042 bne 3f
1043 addis r6,r6,(1<<30)@h
1044 3:
1045 cmpw r3,r9
1046 blt 2b
1048 .globl a2_tlbinit_after_iprot_flush
1049 a2_tlbinit_after_iprot_flush:
1051 #ifdef CONFIG_PPC_EARLY_DEBUG_WSP
1052 /* Now establish early debug mappings if applicable */
1053 /* Restore the MAS0 we used for linear mapping load */
1054 mtspr SPRN_MAS0,r11
1056 lis r3,(MAS1_VALID | MAS1_IPROT)@h
1057 ori r3,r3,(BOOK3E_PAGESZ_4K << MAS1_TSIZE_SHIFT)
1058 mtspr SPRN_MAS1,r3
1059 LOAD_REG_IMMEDIATE(r3, WSP_UART_VIRT | MAS2_I | MAS2_G)
1060 mtspr SPRN_MAS2,r3
1061 LOAD_REG_IMMEDIATE(r3, WSP_UART_PHYS | MAS3_SR | MAS3_SW)
1062 mtspr SPRN_MAS7_MAS3,r3
1063 /* re-use the MAS8 value from the linear mapping */
1064 tlbwe
1065 #endif /* CONFIG_PPC_EARLY_DEBUG_WSP */
1067 PPC_TLBILX(0,0,0)
1068 sync
1069 isync
1071 .globl a2_tlbinit_code_end
1072 a2_tlbinit_code_end:
1074 /* We translate LR and return */
1075 mflr r3
1076 tovirt(r3,r3)
1077 mtlr r3
1078 blr
1080 /*
1081 * Main entry (boot CPU, thread 0)
1082 *
1083 * We enter here from head_64.S, possibly after the prom_init trampoline
1084 * with r3 and r4 already saved to r31 and 30 respectively and in 64 bits
1085 * mode. Anything else is as it was left by the bootloader
1086 *
1087 * Initial requirements of this port:
1088 *
1089 * - Kernel loaded at 0 physical
1090 * - A good lump of memory mapped 0:0 by UTLB entry 0
1091 * - MSR:IS & MSR:DS set to 0
1092 *
1093 * Note that some of the above requirements will be relaxed in the future
1094 * as the kernel becomes smarter at dealing with different initial conditions
1095 * but for now you have to be careful
1096 */
1097 _GLOBAL(start_initialization_book3e)
1098 mflr r28
1100 /* First, we need to setup some initial TLBs to map the kernel
1101 * text, data and bss at PAGE_OFFSET. We don't have a real mode
1102 * and always use AS 0, so we just set it up to match our link
1103 * address and never use 0 based addresses.
1104 */
1105 bl .initial_tlb_book3e
1107 /* Init global core bits */
1108 bl .init_core_book3e
1110 /* Init per-thread bits */
1111 bl .init_thread_book3e
1113 /* Return to common init code */
1114 tovirt(r28,r28)
1115 mtlr r28
1116 blr
1119 /*
1120 * Secondary core/processor entry
1121 *
1122 * This is entered for thread 0 of a secondary core, all other threads
1123 * are expected to be stopped. It's similar to start_initialization_book3e
1124 * except that it's generally entered from the holding loop in head_64.S
1125 * after CPUs have been gathered by Open Firmware.
1126 *
1127 * We assume we are in 32 bits mode running with whatever TLB entry was
1128 * set for us by the firmware or POR engine.
1129 */
1130 _GLOBAL(book3e_secondary_core_init_tlb_set)
1131 li r4,1
1132 b .generic_secondary_smp_init
1134 _GLOBAL(book3e_secondary_core_init)
1135 mflr r28
1137 /* Do we need to setup initial TLB entry ? */
1138 cmplwi r4,0
1139 bne 2f
1141 /* Setup TLB for this core */
1142 bl .initial_tlb_book3e
1144 /* We can return from the above running at a different
1145 * address, so recalculate r2 (TOC)
1146 */
1147 bl .relative_toc
1149 /* Init global core bits */
1150 2: bl .init_core_book3e
1152 /* Init per-thread bits */
1153 3: bl .init_thread_book3e
1155 /* Return to common init code at proper virtual address.
1156 *
1157 * Due to various previous assumptions, we know we entered this
1158 * function at either the final PAGE_OFFSET mapping or using a
1159 * 1:1 mapping at 0, so we don't bother doing a complicated check
1160 * here, we just ensure the return address has the right top bits.
1161 *
1162 * Note that if we ever want to be smarter about where we can be
1163 * started from, we have to be careful that by the time we reach
1164 * the code below we may already be running at a different location
1165 * than the one we were called from since initial_tlb_book3e can
1166 * have moved us already.
1167 */
1168 cmpdi cr0,r28,0
1169 blt 1f
1170 lis r3,PAGE_OFFSET@highest
1171 sldi r3,r3,32
1172 or r28,r28,r3
1173 1: mtlr r28
1174 blr
1176 _GLOBAL(book3e_secondary_thread_init)
1177 mflr r28
1178 b 3b
1180 _STATIC(init_core_book3e)
1181 /* Establish the interrupt vector base */
1182 LOAD_REG_IMMEDIATE(r3, interrupt_base_book3e)
1183 mtspr SPRN_IVPR,r3
1184 sync
1185 blr
1187 _STATIC(init_thread_book3e)
1188 lis r3,(SPRN_EPCR_ICM | SPRN_EPCR_GICM)@h
1189 mtspr SPRN_EPCR,r3
1191 /* Make sure interrupts are off */
1192 wrteei 0
1194 /* disable all timers and clear out status */
1195 li r3,0
1196 mtspr SPRN_TCR,r3
1197 mfspr r3,SPRN_TSR
1198 mtspr SPRN_TSR,r3
1200 blr
1202 _GLOBAL(__setup_base_ivors)
1203 SET_IVOR(0, 0x020) /* Critical Input */
1204 SET_IVOR(1, 0x000) /* Machine Check */
1205 SET_IVOR(2, 0x060) /* Data Storage */
1206 SET_IVOR(3, 0x080) /* Instruction Storage */
1207 SET_IVOR(4, 0x0a0) /* External Input */
1208 SET_IVOR(5, 0x0c0) /* Alignment */
1209 SET_IVOR(6, 0x0e0) /* Program */
1210 SET_IVOR(7, 0x100) /* FP Unavailable */
1211 SET_IVOR(8, 0x120) /* System Call */
1212 SET_IVOR(9, 0x140) /* Auxiliary Processor Unavailable */
1213 SET_IVOR(10, 0x160) /* Decrementer */
1214 SET_IVOR(11, 0x180) /* Fixed Interval Timer */
1215 SET_IVOR(12, 0x1a0) /* Watchdog Timer */
1216 SET_IVOR(13, 0x1c0) /* Data TLB Error */
1217 SET_IVOR(14, 0x1e0) /* Instruction TLB Error */
1218 SET_IVOR(15, 0x040) /* Debug */
1220 sync
1222 blr
1224 _GLOBAL(setup_perfmon_ivor)
1225 SET_IVOR(35, 0x260) /* Performance Monitor */
1226 blr
1228 _GLOBAL(setup_doorbell_ivors)
1229 SET_IVOR(36, 0x280) /* Processor Doorbell */
1230 SET_IVOR(37, 0x2a0) /* Processor Doorbell Crit */
1232 /* Check MMUCFG[LPIDSIZE] to determine if we have category E.HV */
1233 mfspr r10,SPRN_MMUCFG
1234 rlwinm. r10,r10,0,MMUCFG_LPIDSIZE
1235 beqlr
1237 SET_IVOR(38, 0x2c0) /* Guest Processor Doorbell */
1238 SET_IVOR(39, 0x2e0) /* Guest Processor Doorbell Crit/MC */
1239 blr
1241 _GLOBAL(setup_ehv_ivors)
1242 /*
1243 * We may be running as a guest and lack E.HV even on a chip
1244 * that normally has it.
1245 */
1246 mfspr r10,SPRN_MMUCFG
1247 rlwinm. r10,r10,0,MMUCFG_LPIDSIZE
1248 beqlr
1250 SET_IVOR(40, 0x300) /* Embedded Hypervisor System Call */
1251 SET_IVOR(41, 0x320) /* Embedded Hypervisor Privilege */
1252 blr