arch/powerpc/platforms/86xx/gef_ppc9a.c

   1 /*
   2  * GE PPC9A board support
   3  *
   4  * Author: Martyn Welch <martyn.welch@ge.com>
   5  *
   6  * Copyright 2008 GE Intelligent Platforms Embedded Systems, Inc.
   7  *
   8  * This program is free software; you can redistribute  it and/or modify it
   9  * under  the terms of  the GNU General  Public License as published by the
  10  * Free Software Foundation;  either version 2 of the  License, or (at your
  11  * option) any later version.
  12  *
  13  * Based on: mpc86xx_hpcn.c (MPC86xx HPCN board specific routines)
  14  * Copyright 2006 Freescale Semiconductor Inc.
  15  *
  16  * NEC fixup adapted from arch/mips/pci/fixup-lm2e.c
  17  */
  18
  19 #include <linux/stddef.h>
  20 #include <linux/kernel.h>
  21 #include <linux/pci.h>
  22 #include <linux/kdev_t.h>
  23 #include <linux/delay.h>
  24 #include <linux/seq_file.h>
  25 #include <linux/of_platform.h>
  26
  27 #include <asm/system.h>
  28 #include <asm/time.h>
  29 #include <asm/machdep.h>
  30 #include <asm/pci-bridge.h>
  31 #include <asm/prom.h>
  32 #include <mm/mmu_decl.h>
  33 #include <asm/udbg.h>
  34
  35 #include <asm/mpic.h>
  36 #include <asm/nvram.h>
  37
  38 #include <sysdev/fsl_pci.h>
  39 #include <sysdev/fsl_soc.h>
  40
  41 #include "mpc86xx.h"
  42 #include "gef_pic.h"
  43
  44 #undef DEBUG
  45
  46 #ifdef DEBUG
  47 #define DBG (fmt...) do { printk(KERN_ERR "PPC9A: " fmt); } while (0)
  48 #else
  49 #define DBG (fmt...) do { } while (0)
  50 #endif
  51
  52 void __iomem *ppc9a_regs;
  53
  54 static void __init gef_ppc9a_init_irq(void)
  55 {
  56         struct device_node *cascade_node = NULL;
  57
  58         mpc86xx_init_irq();
  59
  60         /*
  61          * There is a simple interrupt handler in the main FPGA, this needs
  62          * to be cascaded into the MPIC
  63          */
  64         cascade_node = of_find_compatible_node(NULL, NULL, "gef,fpga-pic-1.00");
  65         if (!cascade_node) {
  66                 printk(KERN_WARNING "PPC9A: No FPGA PIC\n");
  67                 return;
  68         }
  69
  70         gef_pic_init(cascade_node);
  71         of_node_put(cascade_node);
  72 }
  73
  74 static void __init gef_ppc9a_setup_arch(void)
  75 {
  76         struct device_node *regs;
  77 #ifdef CONFIG_PCI
  78         struct device_node *np;
  79
  80         for_each_compatible_node(np, "pci", "fsl,mpc8641-pcie") {
  81                 fsl_add_bridge(np, 1);
  82         }
  83 #endif
  84
  85         printk(KERN_INFO "GE Intelligent Platforms PPC9A 6U VME SBC\n");
  86
  87 #ifdef CONFIG_SMP
  88         mpc86xx_smp_init();
  89 #endif
  90
  91         /* Remap basic board registers */
  92         regs = of_find_compatible_node(NULL, NULL, "gef,ppc9a-fpga-regs");
  93         if (regs) {
  94                 ppc9a_regs = of_iomap(regs, 0);
  95                 if (ppc9a_regs == NULL)
  96                         printk(KERN_WARNING "Unable to map board registers\n");
  97                 of_node_put(regs);
  98         }
  99
 100 #if defined(CONFIG_MMIO_NVRAM)
 101         mmio_nvram_init();
 102 #endif
 103 }
 104
 105 /* Return the PCB revision */
 106 static unsigned int gef_ppc9a_get_pcb_rev(void)
 107 {
 108         unsigned int reg;
 109
 110         reg = ioread32be(ppc9a_regs);
 111         return (reg >> 16) & 0xff;
 112 }
 113
 114 /* Return the board (software) revision */
 115 static unsigned int gef_ppc9a_get_board_rev(void)
 116 {
 117         unsigned int reg;
 118
 119         reg = ioread32be(ppc9a_regs);
 120         return (reg >> 8) & 0xff;
 121 }
 122
 123 /* Return the FPGA revision */
 124 static unsigned int gef_ppc9a_get_fpga_rev(void)
 125 {
 126         unsigned int reg;
 127
 128         reg = ioread32be(ppc9a_regs);
 129         return reg & 0xf;
 130 }
 131
 132 /* Return VME Geographical Address */
 133 static unsigned int gef_ppc9a_get_vme_geo_addr(void)
 134 {
 135         unsigned int reg;
 136
 137         reg = ioread32be(ppc9a_regs + 0x4);
 138         return reg & 0x1f;
 139 }
 140
 141 /* Return VME System Controller Status */
 142 static unsigned int gef_ppc9a_get_vme_is_syscon(void)
 143 {
 144         unsigned int reg;
 145
 146         reg = ioread32be(ppc9a_regs + 0x4);
 147         return (reg >> 9) & 0x1;
 148 }
 149
 150 static void gef_ppc9a_show_cpuinfo(struct seq_file *m)
 151 {
 152         uint svid = mfspr(SPRN_SVR);
 153
 154         seq_printf(m, "Vendor\t\t: GE Intelligent Platforms\n");
 155
 156         seq_printf(m, "Revision\t: %u%c\n", gef_ppc9a_get_pcb_rev(),
 157                 ('A' + gef_ppc9a_get_board_rev()));
 158         seq_printf(m, "FPGA Revision\t: %u\n", gef_ppc9a_get_fpga_rev());
 159
 160         seq_printf(m, "SVR\t\t: 0x%x\n", svid);
 161
 162         seq_printf(m, "VME geo. addr\t: %u\n", gef_ppc9a_get_vme_geo_addr());
 163
 164         seq_printf(m, "VME syscon\t: %s\n",
 165                 gef_ppc9a_get_vme_is_syscon() ? "yes" : "no");
 166 }
 167
 168 static void __init gef_ppc9a_nec_fixup(struct pci_dev *pdev)
 169 {
 170         unsigned int val;
 171
 172         /* Do not do the fixup on other platforms! */
 173         if (!machine_is(gef_ppc9a))
 174                 return;
 175
 176         printk(KERN_INFO "Running NEC uPD720101 Fixup\n");
 177
 178         /* Ensure ports 1, 2, 3, 4 & 5 are enabled */
 179         pci_read_config_dword(pdev, 0xe0, &val);
 180         pci_write_config_dword(pdev, 0xe0, (val & ~7) | 0x5);
 181
 182         /* System clock is 48-MHz Oscillator and EHCI Enabled. */
 183         pci_write_config_dword(pdev, 0xe4, 1 << 5);
 184 }
 185 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_USB,
 186         gef_ppc9a_nec_fixup);
 187
 188 /*
 189  * Called very early, device-tree isn't unflattened
 190  *
 191  * This function is called to determine whether the BSP is compatible with the
 192  * supplied device-tree, which is assumed to be the correct one for the actual
 193  * board. It is expected thati, in the future, a kernel may support multiple
 194  * boards.
 195  */
 196 static int __init gef_ppc9a_probe(void)
 197 {
 198         unsigned long root = of_get_flat_dt_root();
 199
 200         if (of_flat_dt_is_compatible(root, "gef,ppc9a"))
 201                 return 1;
 202
 203         return 0;
 204 }
 205
 206 static long __init mpc86xx_time_init(void)
 207 {
 208         unsigned int temp;
 209
 210         /* Set the time base to zero */
 211         mtspr(SPRN_TBWL, 0);
 212         mtspr(SPRN_TBWU, 0);
 213
 214         temp = mfspr(SPRN_HID0);
 215         temp |= HID0_TBEN;
 216         mtspr(SPRN_HID0, temp);
 217         asm volatile("isync");
 218
 219         return 0;
 220 }
 221
 222 static __initdata struct of_device_id of_bus_ids[] = {
 223         { .compatible = "simple-bus", },
 224         { .compatible = "gianfar", },
 225         {},
 226 };
 227
 228 static int __init declare_of_platform_devices(void)
 229 {
 230         printk(KERN_DEBUG "Probe platform devices\n");
 231         of_platform_bus_probe(NULL, of_bus_ids, NULL);
 232
 233         return 0;
 234 }
 235 machine_device_initcall(gef_ppc9a, declare_of_platform_devices);
 236
 237 define_machine(gef_ppc9a) {
 238         .name                   = "GE PPC9A",
 239         .probe                  = gef_ppc9a_probe,
 240         .setup_arch             = gef_ppc9a_setup_arch,
 241         .init_IRQ               = gef_ppc9a_init_irq,
 242         .show_cpuinfo           = gef_ppc9a_show_cpuinfo,
 243         .get_irq                = mpic_get_irq,
 244         .restart                = fsl_rstcr_restart,
 245         .time_init              = mpc86xx_time_init,
 246         .calibrate_decr         = generic_calibrate_decr,
 247         .progress               = udbg_progress,
 248 #ifdef CONFIG_PCI
 249         .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
 250 #endif
 251 };