5 This option selects whether a 32-bit or a 64-bit kernel
8 menu "Processor support"
10 prompt "Processor Type"
13 There are five families of 32 bit PowerPC chips supported.
14 The most common ones are the desktop and server CPUs (601, 603,
15 604, 740, 750, 74xx) CPUs from Freescale and IBM, with their
16 embedded 512x/52xx/82xx/83xx/86xx counterparts.
17 The other embeeded parts, namely 4xx, 8xx, e200 (55xx) and e500
18 (85xx) each form a family of their own that is not compatible
21 If unsure, select 52xx/6xx/7xx/74xx/82xx/83xx/86xx.
24 bool "512x/52xx/6xx/7xx/74xx/82xx/83xx/86xx"
45 bool "AMCC 44x, 46x or 47x"
58 prompt "Processor Type"
61 There are two families of 64 bit PowerPC chips supported.
62 The most common ones are the desktop and server CPUs
63 (POWER3, RS64, POWER4, POWER5, POWER5+, POWER6, ...)
65 The other are the "embedded" processors compliant with the
66 "Book 3E" variant of the architecture
69 bool "Server processors"
71 select PPC_HAVE_PMU_SUPPORT
72 select SYS_SUPPORTS_HUGETLBFS
75 bool "Embedded processors"
76 select PPC_FPU # Make it a choice ?
77 select PPC_SMP_MUXED_IPI
83 depends on PPC_BOOK3S_32 || PPC_BOOK3S_64
87 depends on PPC_BOOK3E_64
90 bool "Optimize for POWER4"
91 depends on PPC64 && PPC_BOOK3S
94 Cause the compiler to optimize for POWER4/POWER5/PPC970 processors.
95 The resulting binary will not work on POWER3 or RS64 processors
96 when compiled with binutils 2.15 or later.
100 depends on PPC32 && PPC_BOOK3S
101 select PPC_HAVE_PMU_SUPPORT
105 depends on PPC64 && PPC_BOOK3S
106 default y if !POWER4_ONLY
109 depends on PPC64 && PPC_BOOK3S
114 depends on PPC_BOOK3E_64
117 bool "Optimize for Cell Broadband Engine"
118 depends on PPC64 && PPC_BOOK3S
120 Cause the compiler to optimize for the PPE of the Cell Broadband
121 Engine. This will make the code run considerably faster on Cell
122 but somewhat slower on other machines. This option only changes
123 the scheduling of instructions, not the selection of instructions
124 itself, so the resulting kernel will keep running on all other
125 machines. When building a kernel that is supposed to run only
126 on Cell, you should also select the POWER4_ONLY option.
128 # this is temp to handle compat with arch=ppc
133 select FSL_EMB_PERFMON
134 select PPC_FSL_BOOK3E
138 bool "e500mc Support"
146 config FSL_EMB_PERFMON
147 bool "Freescale Embedded Perfmon"
148 depends on E500 || PPC_83xx
150 This is the Performance Monitor support found on the e500 core
151 and some e300 cores (c3 and c4). Select this only if your
152 core supports the Embedded Performance Monitor APU
154 config FSL_EMB_PERF_EVENT
156 depends on FSL_EMB_PERFMON && PERF_EVENTS && !PPC_PERF_CTRS
159 config FSL_EMB_PERF_EVENT_E500
161 depends on FSL_EMB_PERF_EVENT && E500
166 depends on 40x || 44x
171 depends on E200 || E500 || 44x || PPC_BOOK3E
176 depends on (E200 || E500) && PPC32
179 # this is for common code between PPC32 & PPC64 FSL BOOKE
180 config PPC_FSL_BOOK3E
182 select FSL_EMB_PERFMON
183 select PPC_SMP_MUXED_IPI
184 select SYS_SUPPORTS_HUGETLBFS if PHYS_64BIT || PPC64
185 default y if FSL_BOOKE
189 depends on 44x || E500 || PPC_86xx
190 default y if PHYS_64BIT
193 bool 'Large physical address support' if E500 || PPC_86xx
194 depends on (44x || E500 || PPC_86xx) && !PPC_83xx && !PPC_82xx
196 This option enables kernel support for larger than 32-bit physical
197 addresses. This feature may not be available on all cores.
199 If you have more than 3.5GB of RAM or so, you also need to enable
200 SWIOTLB under Kernel Options for this to work. The actual number
201 is platform-dependent.
203 If in doubt, say N here.
206 bool "AltiVec Support"
207 depends on 6xx || POWER4
209 This option enables kernel support for the Altivec extensions to the
210 PowerPC processor. The kernel currently supports saving and restoring
211 altivec registers, and turning on the 'altivec enable' bit so user
212 processes can execute altivec instructions.
214 This option is only usefully if you have a processor that supports
215 altivec (G4, otherwise known as 74xx series), but does not have
216 any affect on a non-altivec cpu (it does, however add code to the
219 If in doubt, say Y here.
223 depends on POWER4 && ALTIVEC && PPC_FPU
226 This option enables kernel support for the Vector Scaler extensions
227 to the PowerPC processor. The kernel currently supports saving and
228 restoring VSX registers, and turning on the 'VSX enable' bit so user
229 processes can execute VSX instructions.
231 This option is only useful if you have a processor that supports
232 VSX (P7 and above), but does not have any affect on a non-VSX
233 CPUs (it does, however add code to the kernel).
235 If in doubt, say Y here.
238 bool "Support for PowerPC icswx coprocessor instruction"
239 depends on POWER4 || PPC_A2
243 This option enables kernel support for the PowerPC Initiate
244 Coprocessor Store Word (icswx) coprocessor instruction on POWER7
247 This option is only useful if you have a processor that supports
248 the icswx coprocessor instruction. It does not have any effect
249 on processors without the icswx coprocessor instruction.
251 This option slightly increases kernel memory usage.
253 If in doubt, say N here.
256 bool "icswx requires direct PID management"
257 depends on PPC_ICSWX && POWER4
260 The PID register in server is used explicitly for ICSWX. In
261 embedded systems PID managment is done by the system.
263 config PPC_ICSWX_USE_SIGILL
264 bool "Should a bad CT cause a SIGILL?"
268 Should a bad CT used for "non-record form ICSWX" cause an
269 illegal intruction signal or should it be silent as
272 If in doubt, say N here.
276 depends on E200 || (E500 && !PPC_E500MC)
279 This option enables kernel support for the Signal Processing
280 Extensions (SPE) to the PowerPC processor. The kernel currently
281 supports saving and restoring SPE registers, and turning on the
282 'spe enable' bit so user processes can execute SPE instructions.
284 This option is only useful if you have a processor that supports
285 SPE (e500, otherwise known as 85xx series), but does not have any
286 effect on a non-spe cpu (it does, however add code to the kernel).
288 If in doubt, say Y here.
292 depends on PPC_BOOK3S
294 config PPC_STD_MMU_32
296 depends on PPC_STD_MMU && PPC32
298 config PPC_STD_MMU_64
300 depends on PPC_STD_MMU && PPC64
302 config PPC_MMU_NOHASH
304 depends on !PPC_STD_MMU
306 config PPC_BOOK3E_MMU
308 depends on FSL_BOOKE || PPC_BOOK3E
312 default y if (!PPC_FSL_BOOK3E && PPC64 && HUGETLB_PAGE) || (PPC_STD_MMU_64 && PPC_64K_PAGES)
315 config VIRT_CPU_ACCOUNTING
316 bool "Deterministic task and CPU time accounting"
320 Select this option to enable more accurate task and CPU time
321 accounting. This is done by reading a CPU counter on each
322 kernel entry and exit and on transitions within the kernel
323 between system, softirq and hardirq state, so there is a
324 small performance impact. This also enables accounting of
325 stolen time on logically-partitioned systems running on
326 IBM POWER5-based machines.
328 If in doubt, say Y here.
330 config PPC_HAVE_PMU_SUPPORT
335 depends on PERF_EVENTS && PPC_HAVE_PMU_SUPPORT
337 This enables the powerpc-specific perf_event back-end.
340 depends on PPC_BOOK3S || PPC_BOOK3E || FSL_BOOKE || PPC_47x
341 bool "Symmetric multi-processing support"
343 This enables support for systems with more than one CPU. If you have
344 a system with only one CPU, say N. If you have a system with more
345 than one CPU, say Y. Note that the kernel does not currently
346 support SMP machines with 603/603e/603ev or PPC750 ("G3") processors
347 since they have inadequate hardware support for multiprocessor
350 If you say N here, the kernel will run on single and multiprocessor
351 machines, but will use only one CPU of a multiprocessor machine. If
352 you say Y here, the kernel will run on single-processor machines.
353 On a single-processor machine, the kernel will run faster if you say
356 If you don't know what to do here, say N.
359 int "Maximum number of CPUs (2-8192)"
362 default "32" if PPC64
365 config NOT_COHERENT_CACHE
367 depends on 4xx || 8xx || E200 || PPC_MPC512x || GAMECUBE_COMMON
371 config CHECK_CACHE_COHERENCY