arch/sh/kernel/cpu/irq/intc-sh5.c

   1 /*
   2  * arch/sh/kernel/cpu/irq/intc-sh5.c
   3  *
   4  * Interrupt Controller support for SH5 INTC.
   5  *
   6  * Copyright (C) 2000, 2001  Paolo Alberelli
   7  * Copyright (C) 2003  Paul Mundt
   8  *
   9  * Per-interrupt selective. IRLM=0 (Fixed priority) is not
  10  * supported being useless without a cascaded interrupt
  11  * controller.
  12  *
  13  * This file is subject to the terms and conditions of the GNU General Public
  14  * License.  See the file "COPYING" in the main directory of this archive
  15  * for more details.
  16  */
  17 #include <linux/init.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/irq.h>
  20 #include <linux/io.h>
  21 #include <linux/kernel.h>
  22 #include <linux/bitops.h>
  23 #include <cpu/irq.h>
  24 #include <asm/page.h>
  25
  26 /*
  27  * Maybe the generic Peripheral block could move to a more
  28  * generic include file. INTC Block will be defined here
  29  * and only here to make INTC self-contained in a single
  30  * file.
  31  */
  32 #define INTC_BLOCK_OFFSET       0x01000000
  33
  34 /* Base */
  35 #define INTC_BASE               PHYS_PERIPHERAL_BLOCK + \
  36                                 INTC_BLOCK_OFFSET
  37
  38 /* Address */
  39 #define INTC_ICR_SET            (intc_virt + 0x0)
  40 #define INTC_ICR_CLEAR          (intc_virt + 0x8)
  41 #define INTC_INTPRI_0           (intc_virt + 0x10)
  42 #define INTC_INTSRC_0           (intc_virt + 0x50)
  43 #define INTC_INTSRC_1           (intc_virt + 0x58)
  44 #define INTC_INTREQ_0           (intc_virt + 0x60)
  45 #define INTC_INTREQ_1           (intc_virt + 0x68)
  46 #define INTC_INTENB_0           (intc_virt + 0x70)
  47 #define INTC_INTENB_1           (intc_virt + 0x78)
  48 #define INTC_INTDSB_0           (intc_virt + 0x80)
  49 #define INTC_INTDSB_1           (intc_virt + 0x88)
  50
  51 #define INTC_ICR_IRLM           0x1
  52 #define INTC_INTPRI_PREGS       8               /* 8 Priority Registers */
  53 #define INTC_INTPRI_PPREG       8               /* 8 Priorities per Register */
  54
  55
  56 /*
  57  * Mapper between the vector ordinal and the IRQ number
  58  * passed to kernel/device drivers.
  59  */
  60 int intc_evt_to_irq[(0xE20/0x20)+1] = {
  61         -1, -1, -1, -1, -1, -1, -1, -1, /* 0x000 - 0x0E0 */
  62         -1, -1, -1, -1, -1, -1, -1, -1, /* 0x100 - 0x1E0 */
  63          0,  0,  0,  0,  0,  1,  0,  0, /* 0x200 - 0x2E0 */
  64          2,  0,  0,  3,  0,  0,  0, -1, /* 0x300 - 0x3E0 */
  65         32, 33, 34, 35, 36, 37, 38, -1, /* 0x400 - 0x4E0 */
  66         -1, -1, -1, 63, -1, -1, -1, -1, /* 0x500 - 0x5E0 */
  67         -1, -1, 18, 19, 20, 21, 22, -1, /* 0x600 - 0x6E0 */
  68         39, 40, 41, 42, -1, -1, -1, -1, /* 0x700 - 0x7E0 */
  69          4,  5,  6,  7, -1, -1, -1, -1, /* 0x800 - 0x8E0 */
  70         -1, -1, -1, -1, -1, -1, -1, -1, /* 0x900 - 0x9E0 */
  71         12, 13, 14, 15, 16, 17, -1, -1, /* 0xA00 - 0xAE0 */
  72         -1, -1, -1, -1, -1, -1, -1, -1, /* 0xB00 - 0xBE0 */
  73         -1, -1, -1, -1, -1, -1, -1, -1, /* 0xC00 - 0xCE0 */
  74         -1, -1, -1, -1, -1, -1, -1, -1, /* 0xD00 - 0xDE0 */
  75         -1, -1                          /* 0xE00 - 0xE20 */
  76 };
  77
  78 static unsigned long intc_virt;
  79 static int irlm;                /* IRL mode */
  80
  81 static void enable_intc_irq(struct irq_data *data)
  82 {
  83         unsigned int irq = data->irq;
  84         unsigned long reg;
  85         unsigned long bitmask;
  86
  87         if ((irq <= IRQ_IRL3) && (irlm == NO_PRIORITY))
  88                 printk("Trying to use straight IRL0-3 with an encoding platform.\n");
  89
  90         if (irq < 32) {
  91                 reg = INTC_INTENB_0;
  92                 bitmask = 1 << irq;
  93         } else {
  94                 reg = INTC_INTENB_1;
  95                 bitmask = 1 << (irq - 32);
  96         }
  97
  98         __raw_writel(bitmask, reg);
  99 }
 100
 101 static void disable_intc_irq(struct irq_data *data)
 102 {
 103         unsigned int irq = data->irq;
 104         unsigned long reg;
 105         unsigned long bitmask;
 106
 107         if (irq < 32) {
 108                 reg = INTC_INTDSB_0;
 109                 bitmask = 1 << irq;
 110         } else {
 111                 reg = INTC_INTDSB_1;
 112                 bitmask = 1 << (irq - 32);
 113         }
 114
 115         __raw_writel(bitmask, reg);
 116 }
 117
 118 static struct irq_chip intc_irq_type = {
 119         .name = "INTC",
 120         .irq_enable = enable_intc_irq,
 121         .irq_disable = disable_intc_irq,
 122 };
 123
 124 void __init plat_irq_setup(void)
 125 {
 126         unsigned long long __dummy0, __dummy1=~0x00000000100000f0;
 127         unsigned long reg;
 128         int i;
 129
 130         intc_virt = (unsigned long)ioremap_nocache(INTC_BASE, 1024);
 131         if (!intc_virt) {
 132                 panic("Unable to remap INTC\n");
 133         }
 134
 135
 136         /* Set default: per-line enable/disable, priority driven ack/eoi */
 137         for (i = 0; i < NR_INTC_IRQS; i++)
 138                 irq_set_chip_and_handler(i, &intc_irq_type, handle_level_irq);
 139
 140
 141         /* Disable all interrupts and set all priorities to 0 to avoid trouble */
 142         __raw_writel(-1, INTC_INTDSB_0);
 143         __raw_writel(-1, INTC_INTDSB_1);
 144
 145         for (reg = INTC_INTPRI_0, i = 0; i < INTC_INTPRI_PREGS; i++, reg += 8)
 146                 __raw_writel( NO_PRIORITY, reg);
 147
 148
 149 #ifdef CONFIG_SH_CAYMAN
 150         {
 151                 unsigned long data;
 152
 153                 /* Set IRLM */
 154                 /* If all the priorities are set to 'no priority', then
 155                  * assume we are using encoded mode.
 156                  */
 157                 irlm = platform_int_priority[IRQ_IRL0] +
 158                        platform_int_priority[IRQ_IRL1] +
 159                        platform_int_priority[IRQ_IRL2] +
 160                        platform_int_priority[IRQ_IRL3];
 161                 if (irlm == NO_PRIORITY) {
 162                         /* IRLM = 0 */
 163                         reg = INTC_ICR_CLEAR;
 164                         i = IRQ_INTA;
 165                         printk("Trying to use encoded IRL0-3. IRLs unsupported.\n");
 166                 } else {
 167                         /* IRLM = 1 */
 168                         reg = INTC_ICR_SET;
 169                         i = IRQ_IRL0;
 170                 }
 171                 __raw_writel(INTC_ICR_IRLM, reg);
 172
 173                 /* Set interrupt priorities according to platform description */
 174                 for (data = 0, reg = INTC_INTPRI_0; i < NR_INTC_IRQS; i++) {
 175                         data |= platform_int_priority[i] <<
 176                                 ((i % INTC_INTPRI_PPREG) * 4);
 177                         if ((i % INTC_INTPRI_PPREG) == (INTC_INTPRI_PPREG - 1)) {
 178                                 /* Upon the 7th, set Priority Register */
 179                                 __raw_writel(data, reg);
 180                                 data = 0;
 181                                 reg += 8;
 182                         }
 183                 }
 184         }
 185 #endif
 186
 187         /*
 188          * And now let interrupts come in.
 189          * sti() is not enough, we need to
 190          * lower priority, too.
 191          */
 192         __asm__ __volatile__("getcon    " __SR ", %0\n\t"
 193                              "and       %0, %1, %0\n\t"
 194                              "putcon    %0, " __SR "\n\t"
 195                              : "=&r" (__dummy0)
 196                              : "r" (__dummy1));
 197 }