spi-topcliff-pch: add recovery processing in case wait-event timeout
[zen-stable.git] / arch / sh / kernel / cpu / sh3 / setup-sh7705.c
blob2309618c015d06ec8b86d75882a21ce036db2cce
1 /*
2 * SH7705 Setup
4 * Copyright (C) 2006 - 2009 Paul Mundt
5 * Copyright (C) 2007 Nobuhiro Iwamatsu
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
9 * for more details.
11 #include <linux/platform_device.h>
12 #include <linux/init.h>
13 #include <linux/irq.h>
14 #include <linux/serial.h>
15 #include <linux/serial_sci.h>
16 #include <linux/sh_timer.h>
17 #include <asm/rtc.h>
18 #include <cpu/serial.h>
20 enum {
21 UNUSED = 0,
23 /* interrupt sources */
24 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5,
25 PINT07, PINT815,
27 DMAC, SCIF0, SCIF2, ADC_ADI, USB,
29 TPU0, TPU1, TPU2, TPU3,
30 TMU0, TMU1, TMU2,
32 RTC, WDT, REF_RCMI,
35 static struct intc_vect vectors[] __initdata = {
36 /* IRQ0->5 are handled in setup-sh3.c */
37 INTC_VECT(PINT07, 0x700), INTC_VECT(PINT815, 0x720),
38 INTC_VECT(DMAC, 0x800), INTC_VECT(DMAC, 0x820),
39 INTC_VECT(DMAC, 0x840), INTC_VECT(DMAC, 0x860),
40 INTC_VECT(SCIF0, 0x880), INTC_VECT(SCIF0, 0x8a0),
41 INTC_VECT(SCIF0, 0x8e0),
42 INTC_VECT(SCIF2, 0x900), INTC_VECT(SCIF2, 0x920),
43 INTC_VECT(SCIF2, 0x960),
44 INTC_VECT(ADC_ADI, 0x980),
45 INTC_VECT(USB, 0xa20), INTC_VECT(USB, 0xa40),
46 INTC_VECT(TPU0, 0xc00), INTC_VECT(TPU1, 0xc20),
47 INTC_VECT(TPU2, 0xc80), INTC_VECT(TPU3, 0xca0),
48 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
49 INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2, 0x460),
50 INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
51 INTC_VECT(RTC, 0x4c0),
52 INTC_VECT(WDT, 0x560),
53 INTC_VECT(REF_RCMI, 0x580),
56 static struct intc_prio_reg prio_registers[] __initdata = {
57 { 0xfffffee2, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
58 { 0xfffffee4, 0, 16, 4, /* IPRB */ { WDT, REF_RCMI, 0, 0 } },
59 { 0xa4000016, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } },
60 { 0xa4000018, 0, 16, 4, /* IPRD */ { PINT07, PINT815, IRQ5, IRQ4 } },
61 { 0xa400001a, 0, 16, 4, /* IPRE */ { DMAC, SCIF0, SCIF2, ADC_ADI } },
62 { 0xa4080000, 0, 16, 4, /* IPRF */ { 0, 0, USB } },
63 { 0xa4080002, 0, 16, 4, /* IPRG */ { TPU0, TPU1 } },
64 { 0xa4080004, 0, 16, 4, /* IPRH */ { TPU2, TPU3 } },
68 static DECLARE_INTC_DESC(intc_desc, "sh7705", vectors, NULL,
69 NULL, prio_registers, NULL);
71 static struct plat_sci_port scif0_platform_data = {
72 .mapbase = 0xa4410000,
73 .flags = UPF_BOOT_AUTOCONF,
74 .scscr = SCSCR_TIE | SCSCR_RIE | SCSCR_TE |
75 SCSCR_RE | SCSCR_CKE1 | SCSCR_CKE0,
76 .scbrr_algo_id = SCBRR_ALGO_4,
77 .type = PORT_SCIF,
78 .irqs = { 56, 56, 56 },
79 .ops = &sh770x_sci_port_ops,
80 .regtype = SCIx_SH7705_SCIF_REGTYPE,
83 static struct platform_device scif0_device = {
84 .name = "sh-sci",
85 .id = 0,
86 .dev = {
87 .platform_data = &scif0_platform_data,
91 static struct plat_sci_port scif1_platform_data = {
92 .mapbase = 0xa4400000,
93 .flags = UPF_BOOT_AUTOCONF,
94 .scscr = SCSCR_TIE | SCSCR_RIE | SCSCR_TE | SCSCR_RE,
95 .scbrr_algo_id = SCBRR_ALGO_4,
96 .type = PORT_SCIF,
97 .irqs = { 52, 52, 52 },
98 .ops = &sh770x_sci_port_ops,
99 .regtype = SCIx_SH7705_SCIF_REGTYPE,
102 static struct platform_device scif1_device = {
103 .name = "sh-sci",
104 .id = 1,
105 .dev = {
106 .platform_data = &scif1_platform_data,
110 static struct resource rtc_resources[] = {
111 [0] = {
112 .start = 0xfffffec0,
113 .end = 0xfffffec0 + 0x1e,
114 .flags = IORESOURCE_IO,
116 [1] = {
117 .start = 20,
118 .flags = IORESOURCE_IRQ,
122 static struct sh_rtc_platform_info rtc_info = {
123 .capabilities = RTC_CAP_4_DIGIT_YEAR,
126 static struct platform_device rtc_device = {
127 .name = "sh-rtc",
128 .id = -1,
129 .num_resources = ARRAY_SIZE(rtc_resources),
130 .resource = rtc_resources,
131 .dev = {
132 .platform_data = &rtc_info,
136 static struct sh_timer_config tmu0_platform_data = {
137 .channel_offset = 0x02,
138 .timer_bit = 0,
139 .clockevent_rating = 200,
142 static struct resource tmu0_resources[] = {
143 [0] = {
144 .start = 0xfffffe94,
145 .end = 0xfffffe9f,
146 .flags = IORESOURCE_MEM,
148 [1] = {
149 .start = 16,
150 .flags = IORESOURCE_IRQ,
154 static struct platform_device tmu0_device = {
155 .name = "sh_tmu",
156 .id = 0,
157 .dev = {
158 .platform_data = &tmu0_platform_data,
160 .resource = tmu0_resources,
161 .num_resources = ARRAY_SIZE(tmu0_resources),
164 static struct sh_timer_config tmu1_platform_data = {
165 .channel_offset = 0xe,
166 .timer_bit = 1,
167 .clocksource_rating = 200,
170 static struct resource tmu1_resources[] = {
171 [0] = {
172 .start = 0xfffffea0,
173 .end = 0xfffffeab,
174 .flags = IORESOURCE_MEM,
176 [1] = {
177 .start = 17,
178 .flags = IORESOURCE_IRQ,
182 static struct platform_device tmu1_device = {
183 .name = "sh_tmu",
184 .id = 1,
185 .dev = {
186 .platform_data = &tmu1_platform_data,
188 .resource = tmu1_resources,
189 .num_resources = ARRAY_SIZE(tmu1_resources),
192 static struct sh_timer_config tmu2_platform_data = {
193 .channel_offset = 0x1a,
194 .timer_bit = 2,
197 static struct resource tmu2_resources[] = {
198 [0] = {
199 .start = 0xfffffeac,
200 .end = 0xfffffebb,
201 .flags = IORESOURCE_MEM,
203 [1] = {
204 .start = 18,
205 .flags = IORESOURCE_IRQ,
209 static struct platform_device tmu2_device = {
210 .name = "sh_tmu",
211 .id = 2,
212 .dev = {
213 .platform_data = &tmu2_platform_data,
215 .resource = tmu2_resources,
216 .num_resources = ARRAY_SIZE(tmu2_resources),
219 static struct platform_device *sh7705_devices[] __initdata = {
220 &scif0_device,
221 &scif1_device,
222 &tmu0_device,
223 &tmu1_device,
224 &tmu2_device,
225 &rtc_device,
228 static int __init sh7705_devices_setup(void)
230 return platform_add_devices(sh7705_devices,
231 ARRAY_SIZE(sh7705_devices));
233 arch_initcall(sh7705_devices_setup);
235 static struct platform_device *sh7705_early_devices[] __initdata = {
236 &scif0_device,
237 &scif1_device,
238 &tmu0_device,
239 &tmu1_device,
240 &tmu2_device,
243 void __init plat_early_device_setup(void)
245 early_platform_add_devices(sh7705_early_devices,
246 ARRAY_SIZE(sh7705_early_devices));
249 void __init plat_irq_setup(void)
251 register_intc_controller(&intc_desc);
252 plat_irq_setup_sh3();