arch/x86/include/asm/apic.h

   1 #ifndef _ASM_X86_APIC_H
   2 #define _ASM_X86_APIC_H
   3
   4 #include <linux/cpumask.h>
   5 #include <linux/pm.h>
   6
   7 #include <asm/alternative.h>
   8 #include <asm/cpufeature.h>
   9 #include <asm/processor.h>
  10 #include <asm/apicdef.h>
  11 #include <linux/atomic.h>
  12 #include <asm/fixmap.h>
  13 #include <asm/mpspec.h>
  14 #include <asm/system.h>
  15 #include <asm/msr.h>
  16
  17 #define ARCH_APICTIMER_STOPS_ON_C3      1
  18
  19 /*
  20  * Debugging macros
  21  */
  22 #define APIC_QUIET   0
  23 #define APIC_VERBOSE 1
  24 #define APIC_DEBUG   2
  25
  26 /*
  27  * Define the default level of output to be very little
  28  * This can be turned up by using apic=verbose for more
  29  * information and apic=debug for _lots_ of information.
  30  * apic_verbosity is defined in apic.c
  31  */
  32 #define apic_printk(v, s, a...) do {       \
  33                 if ((v) <= apic_verbosity) \
  34                         printk(s, ##a);    \
  35         } while (0)
  36
  37
  38 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32)
  39 extern void generic_apic_probe(void);
  40 #else
  41 static inline void generic_apic_probe(void)
  42 {
  43 }
  44 #endif
  45
  46 #ifdef CONFIG_X86_LOCAL_APIC
  47
  48 extern unsigned int apic_verbosity;
  49 extern int local_apic_timer_c2_ok;
  50
  51 extern int disable_apic;
  52 extern unsigned int lapic_timer_frequency;
  53
  54 #ifdef CONFIG_SMP
  55 extern void __inquire_remote_apic(int apicid);
  56 #else /* CONFIG_SMP */
  57 static inline void __inquire_remote_apic(int apicid)
  58 {
  59 }
  60 #endif /* CONFIG_SMP */
  61
  62 static inline void default_inquire_remote_apic(int apicid)
  63 {
  64         if (apic_verbosity >= APIC_DEBUG)
  65                 __inquire_remote_apic(apicid);
  66 }
  67
  68 /*
  69  * With 82489DX we can't rely on apic feature bit
  70  * retrieved via cpuid but still have to deal with
  71  * such an apic chip so we assume that SMP configuration
  72  * is found from MP table (64bit case uses ACPI mostly
  73  * which set smp presence flag as well so we are safe
  74  * to use this helper too).
  75  */
  76 static inline bool apic_from_smp_config(void)
  77 {
  78         return smp_found_config && !disable_apic;
  79 }
  80
  81 /*
  82  * Basic functions accessing APICs.
  83  */
  84 #ifdef CONFIG_PARAVIRT
  85 #include <asm/paravirt.h>
  86 #endif
  87
  88 #ifdef CONFIG_X86_64
  89 extern int is_vsmp_box(void);
  90 #else
  91 static inline int is_vsmp_box(void)
  92 {
  93         return 0;
  94 }
  95 #endif
  96 extern void xapic_wait_icr_idle(void);
  97 extern u32 safe_xapic_wait_icr_idle(void);
  98 extern void xapic_icr_write(u32, u32);
  99 extern int setup_profiling_timer(unsigned int);
 100
 101 static inline void native_apic_mem_write(u32 reg, u32 v)
 102 {
 103         volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg);
 104
 105         alternative_io("movl %0, %1", "xchgl %0, %1", X86_FEATURE_11AP,
 106                        ASM_OUTPUT2("=r" (v), "=m" (*addr)),
 107                        ASM_OUTPUT2("0" (v), "m" (*addr)));
 108 }
 109
 110 static inline u32 native_apic_mem_read(u32 reg)
 111 {
 112         return *((volatile u32 *)(APIC_BASE + reg));
 113 }
 114
 115 extern void native_apic_wait_icr_idle(void);
 116 extern u32 native_safe_apic_wait_icr_idle(void);
 117 extern void native_apic_icr_write(u32 low, u32 id);
 118 extern u64 native_apic_icr_read(void);
 119
 120 extern int x2apic_mode;
 121
 122 #ifdef CONFIG_X86_X2APIC
 123 /*
 124  * Make previous memory operations globally visible before
 125  * sending the IPI through x2apic wrmsr. We need a serializing instruction or
 126  * mfence for this.
 127  */
 128 static inline void x2apic_wrmsr_fence(void)
 129 {
 130         asm volatile("mfence" : : : "memory");
 131 }
 132
 133 static inline void native_apic_msr_write(u32 reg, u32 v)
 134 {
 135         if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR ||
 136             reg == APIC_LVR)
 137                 return;
 138
 139         wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0);
 140 }
 141
 142 static inline u32 native_apic_msr_read(u32 reg)
 143 {
 144         u64 msr;
 145
 146         if (reg == APIC_DFR)
 147                 return -1;
 148
 149         rdmsrl(APIC_BASE_MSR + (reg >> 4), msr);
 150         return (u32)msr;
 151 }
 152
 153 static inline void native_x2apic_wait_icr_idle(void)
 154 {
 155         /* no need to wait for icr idle in x2apic */
 156         return;
 157 }
 158
 159 static inline u32 native_safe_x2apic_wait_icr_idle(void)
 160 {
 161         /* no need to wait for icr idle in x2apic */
 162         return 0;
 163 }
 164
 165 static inline void native_x2apic_icr_write(u32 low, u32 id)
 166 {
 167         wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low);
 168 }
 169
 170 static inline u64 native_x2apic_icr_read(void)
 171 {
 172         unsigned long val;
 173
 174         rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val);
 175         return val;
 176 }
 177
 178 extern int x2apic_phys;
 179 extern int x2apic_preenabled;
 180 extern void check_x2apic(void);
 181 extern void enable_x2apic(void);
 182 extern void x2apic_icr_write(u32 low, u32 id);
 183 static inline int x2apic_enabled(void)
 184 {
 185         u64 msr;
 186
 187         if (!cpu_has_x2apic)
 188                 return 0;
 189
 190         rdmsrl(MSR_IA32_APICBASE, msr);
 191         if (msr & X2APIC_ENABLE)
 192                 return 1;
 193         return 0;
 194 }
 195
 196 #define x2apic_supported()      (cpu_has_x2apic)
 197 static inline void x2apic_force_phys(void)
 198 {
 199         x2apic_phys = 1;
 200 }
 201 #else
 202 static inline void disable_x2apic(void)
 203 {
 204 }
 205 static inline void check_x2apic(void)
 206 {
 207 }
 208 static inline void enable_x2apic(void)
 209 {
 210 }
 211 static inline int x2apic_enabled(void)
 212 {
 213         return 0;
 214 }
 215 static inline void x2apic_force_phys(void)
 216 {
 217 }
 218
 219 #define nox2apic        0
 220 #define x2apic_preenabled 0
 221 #define x2apic_supported()      0
 222 #endif
 223
 224 extern void enable_IR_x2apic(void);
 225
 226 extern int get_physical_broadcast(void);
 227
 228 extern int lapic_get_maxlvt(void);
 229 extern void clear_local_APIC(void);
 230 extern void connect_bsp_APIC(void);
 231 extern void disconnect_bsp_APIC(int virt_wire_setup);
 232 extern void disable_local_APIC(void);
 233 extern void lapic_shutdown(void);
 234 extern int verify_local_APIC(void);
 235 extern void sync_Arb_IDs(void);
 236 extern void init_bsp_APIC(void);
 237 extern void setup_local_APIC(void);
 238 extern void end_local_APIC_setup(void);
 239 extern void bsp_end_local_APIC_setup(void);
 240 extern void init_apic_mappings(void);
 241 void register_lapic_address(unsigned long address);
 242 extern void setup_boot_APIC_clock(void);
 243 extern void setup_secondary_APIC_clock(void);
 244 extern int APIC_init_uniprocessor(void);
 245 extern int apic_force_enable(unsigned long addr);
 246
 247 /*
 248  * On 32bit this is mach-xxx local
 249  */
 250 #ifdef CONFIG_X86_64
 251 extern int apic_is_clustered_box(void);
 252 #else
 253 static inline int apic_is_clustered_box(void)
 254 {
 255         return 0;
 256 }
 257 #endif
 258
 259 extern int setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask);
 260
 261 #else /* !CONFIG_X86_LOCAL_APIC */
 262 static inline void lapic_shutdown(void) { }
 263 #define local_apic_timer_c2_ok          1
 264 static inline void init_apic_mappings(void) { }
 265 static inline void disable_local_APIC(void) { }
 266 # define setup_boot_APIC_clock x86_init_noop
 267 # define setup_secondary_APIC_clock x86_init_noop
 268 #endif /* !CONFIG_X86_LOCAL_APIC */
 269
 270 #ifdef CONFIG_X86_64
 271 #define SET_APIC_ID(x)          (apic->set_apic_id(x))
 272 #else
 273
 274 #endif
 275
 276 /*
 277  * Copyright 2004 James Cleverdon, IBM.
 278  * Subject to the GNU Public License, v.2
 279  *
 280  * Generic APIC sub-arch data struct.
 281  *
 282  * Hacked for x86-64 by James Cleverdon from i386 architecture code by
 283  * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and
 284  * James Cleverdon.
 285  */
 286 struct apic {
 287         char *name;
 288
 289         int (*probe)(void);
 290         int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id);
 291         int (*apic_id_registered)(void);
 292
 293         u32 irq_delivery_mode;
 294         u32 irq_dest_mode;
 295
 296         const struct cpumask *(*target_cpus)(void);
 297
 298         int disable_esr;
 299
 300         int dest_logical;
 301         unsigned long (*check_apicid_used)(physid_mask_t *map, int apicid);
 302         unsigned long (*check_apicid_present)(int apicid);
 303
 304         void (*vector_allocation_domain)(int cpu, struct cpumask *retmask);
 305         void (*init_apic_ldr)(void);
 306
 307         void (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap);
 308
 309         void (*setup_apic_routing)(void);
 310         int (*multi_timer_check)(int apic, int irq);
 311         int (*cpu_present_to_apicid)(int mps_cpu);
 312         void (*apicid_to_cpu_present)(int phys_apicid, physid_mask_t *retmap);
 313         void (*setup_portio_remap)(void);
 314         int (*check_phys_apicid_present)(int phys_apicid);
 315         void (*enable_apic_mode)(void);
 316         int (*phys_pkg_id)(int cpuid_apic, int index_msb);
 317
 318         /*
 319          * When one of the next two hooks returns 1 the apic
 320          * is switched to this. Essentially they are additional
 321          * probe functions:
 322          */
 323         int (*mps_oem_check)(struct mpc_table *mpc, char *oem, char *productid);
 324
 325         unsigned int (*get_apic_id)(unsigned long x);
 326         unsigned long (*set_apic_id)(unsigned int id);
 327         unsigned long apic_id_mask;
 328
 329         unsigned int (*cpu_mask_to_apicid)(const struct cpumask *cpumask);
 330         unsigned int (*cpu_mask_to_apicid_and)(const struct cpumask *cpumask,
 331                                                const struct cpumask *andmask);
 332
 333         /* ipi */
 334         void (*send_IPI_mask)(const struct cpumask *mask, int vector);
 335         void (*send_IPI_mask_allbutself)(const struct cpumask *mask,
 336                                          int vector);
 337         void (*send_IPI_allbutself)(int vector);
 338         void (*send_IPI_all)(int vector);
 339         void (*send_IPI_self)(int vector);
 340
 341         /* wakeup_secondary_cpu */
 342         int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip);
 343
 344         int trampoline_phys_low;
 345         int trampoline_phys_high;
 346
 347         void (*wait_for_init_deassert)(atomic_t *deassert);
 348         void (*smp_callin_clear_local_apic)(void);
 349         void (*inquire_remote_apic)(int apicid);
 350
 351         /* apic ops */
 352         u32 (*read)(u32 reg);
 353         void (*write)(u32 reg, u32 v);
 354         u64 (*icr_read)(void);
 355         void (*icr_write)(u32 low, u32 high);
 356         void (*wait_icr_idle)(void);
 357         u32 (*safe_wait_icr_idle)(void);
 358
 359 #ifdef CONFIG_X86_32
 360         /*
 361          * Called very early during boot from get_smp_config().  It should
 362          * return the logical apicid.  x86_[bios]_cpu_to_apicid is
 363          * initialized before this function is called.
 364          *
 365          * If logical apicid can't be determined that early, the function
 366          * may return BAD_APICID.  Logical apicid will be configured after
 367          * init_apic_ldr() while bringing up CPUs.  Note that NUMA affinity
 368          * won't be applied properly during early boot in this case.
 369          */
 370         int (*x86_32_early_logical_apicid)(int cpu);
 371
 372         /*
 373          * Optional method called from setup_local_APIC() after logical
 374          * apicid is guaranteed to be known to initialize apicid -> node
 375          * mapping if NUMA initialization hasn't done so already.  Don't
 376          * add new users.
 377          */
 378         int (*x86_32_numa_cpu_node)(int cpu);
 379 #endif
 380 };
 381
 382 /*
 383  * Pointer to the local APIC driver in use on this system (there's
 384  * always just one such driver in use - the kernel decides via an
 385  * early probing process which one it picks - and then sticks to it):
 386  */
 387 extern struct apic *apic;
 388
 389 /*
 390  * APIC drivers are probed based on how they are listed in the .apicdrivers
 391  * section. So the order is important and enforced by the ordering
 392  * of different apic driver files in the Makefile.
 393  *
 394  * For the files having two apic drivers, we use apic_drivers()
 395  * to enforce the order with in them.
 396  */
 397 #define apic_driver(sym)                                        \
 398         static struct apic *__apicdrivers_##sym __used          \
 399         __aligned(sizeof(struct apic *))                        \
 400         __section(.apicdrivers) = { &sym }
 401
 402 #define apic_drivers(sym1, sym2)                                        \
 403         static struct apic *__apicdrivers_##sym1##sym2[2] __used        \
 404         __aligned(sizeof(struct apic *))                                \
 405         __section(.apicdrivers) = { &sym1, &sym2 }
 406
 407 extern struct apic *__apicdrivers[], *__apicdrivers_end[];
 408
 409 /*
 410  * APIC functionality to boot other CPUs - only used on SMP:
 411  */
 412 #ifdef CONFIG_SMP
 413 extern atomic_t init_deasserted;
 414 extern int wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip);
 415 #endif
 416
 417 #ifdef CONFIG_X86_LOCAL_APIC
 418
 419 static inline u32 apic_read(u32 reg)
 420 {
 421         return apic->read(reg);
 422 }
 423
 424 static inline void apic_write(u32 reg, u32 val)
 425 {
 426         apic->write(reg, val);
 427 }
 428
 429 static inline u64 apic_icr_read(void)
 430 {
 431         return apic->icr_read();
 432 }
 433
 434 static inline void apic_icr_write(u32 low, u32 high)
 435 {
 436         apic->icr_write(low, high);
 437 }
 438
 439 static inline void apic_wait_icr_idle(void)
 440 {
 441         apic->wait_icr_idle();
 442 }
 443
 444 static inline u32 safe_apic_wait_icr_idle(void)
 445 {
 446         return apic->safe_wait_icr_idle();
 447 }
 448
 449 #else /* CONFIG_X86_LOCAL_APIC */
 450
 451 static inline u32 apic_read(u32 reg) { return 0; }
 452 static inline void apic_write(u32 reg, u32 val) { }
 453 static inline u64 apic_icr_read(void) { return 0; }
 454 static inline void apic_icr_write(u32 low, u32 high) { }
 455 static inline void apic_wait_icr_idle(void) { }
 456 static inline u32 safe_apic_wait_icr_idle(void) { return 0; }
 457
 458 #endif /* CONFIG_X86_LOCAL_APIC */
 459
 460 static inline void ack_APIC_irq(void)
 461 {
 462         /*
 463          * ack_APIC_irq() actually gets compiled as a single instruction
 464          * ... yummie.
 465          */
 466
 467         /* Docs say use 0 for future compatibility */
 468         apic_write(APIC_EOI, 0);
 469 }
 470
 471 static inline unsigned default_get_apic_id(unsigned long x)
 472 {
 473         unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR));
 474
 475         if (APIC_XAPIC(ver) || boot_cpu_has(X86_FEATURE_EXTD_APICID))
 476                 return (x >> 24) & 0xFF;
 477         else
 478                 return (x >> 24) & 0x0F;
 479 }
 480
 481 /*
 482  * Warm reset vector default position:
 483  */
 484 #define DEFAULT_TRAMPOLINE_PHYS_LOW             0x467
 485 #define DEFAULT_TRAMPOLINE_PHYS_HIGH            0x469
 486
 487 #ifdef CONFIG_X86_64
 488 extern int default_acpi_madt_oem_check(char *, char *);
 489
 490 extern void apic_send_IPI_self(int vector);
 491
 492 DECLARE_PER_CPU(int, x2apic_extra_bits);
 493
 494 extern int default_cpu_present_to_apicid(int mps_cpu);
 495 extern int default_check_phys_apicid_present(int phys_apicid);
 496 #endif
 497
 498 static inline void default_wait_for_init_deassert(atomic_t *deassert)
 499 {
 500         while (!atomic_read(deassert))
 501                 cpu_relax();
 502         return;
 503 }
 504
 505 extern void generic_bigsmp_probe(void);
 506
 507
 508 #ifdef CONFIG_X86_LOCAL_APIC
 509
 510 #include <asm/smp.h>
 511
 512 #define APIC_DFR_VALUE  (APIC_DFR_FLAT)
 513
 514 static inline const struct cpumask *default_target_cpus(void)
 515 {
 516 #ifdef CONFIG_SMP
 517         return cpu_online_mask;
 518 #else
 519         return cpumask_of(0);
 520 #endif
 521 }
 522
 523 DECLARE_EARLY_PER_CPU(u16, x86_bios_cpu_apicid);
 524
 525
 526 static inline unsigned int read_apic_id(void)
 527 {
 528         unsigned int reg;
 529
 530         reg = apic_read(APIC_ID);
 531
 532         return apic->get_apic_id(reg);
 533 }
 534
 535 extern void default_setup_apic_routing(void);
 536
 537 extern struct apic apic_noop;
 538
 539 #ifdef CONFIG_X86_32
 540
 541 static inline int noop_x86_32_early_logical_apicid(int cpu)
 542 {
 543         return BAD_APICID;
 544 }
 545
 546 /*
 547  * Set up the logical destination ID.
 548  *
 549  * Intel recommends to set DFR, LDR and TPR before enabling
 550  * an APIC.  See e.g. "AP-388 82489DX User's Manual" (Intel
 551  * document number 292116).  So here it goes...
 552  */
 553 extern void default_init_apic_ldr(void);
 554
 555 static inline int default_apic_id_registered(void)
 556 {
 557         return physid_isset(read_apic_id(), phys_cpu_present_map);
 558 }
 559
 560 static inline int default_phys_pkg_id(int cpuid_apic, int index_msb)
 561 {
 562         return cpuid_apic >> index_msb;
 563 }
 564
 565 #endif
 566
 567 static inline unsigned int
 568 default_cpu_mask_to_apicid(const struct cpumask *cpumask)
 569 {
 570         return cpumask_bits(cpumask)[0] & APIC_ALL_CPUS;
 571 }
 572
 573 static inline unsigned int
 574 default_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
 575                                const struct cpumask *andmask)
 576 {
 577         unsigned long mask1 = cpumask_bits(cpumask)[0];
 578         unsigned long mask2 = cpumask_bits(andmask)[0];
 579         unsigned long mask3 = cpumask_bits(cpu_online_mask)[0];
 580
 581         return (unsigned int)(mask1 & mask2 & mask3);
 582 }
 583
 584 static inline unsigned long default_check_apicid_used(physid_mask_t *map, int apicid)
 585 {
 586         return physid_isset(apicid, *map);
 587 }
 588
 589 static inline unsigned long default_check_apicid_present(int bit)
 590 {
 591         return physid_isset(bit, phys_cpu_present_map);
 592 }
 593
 594 static inline void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap)
 595 {
 596         *retmap = *phys_map;
 597 }
 598
 599 static inline int __default_cpu_present_to_apicid(int mps_cpu)
 600 {
 601         if (mps_cpu < nr_cpu_ids && cpu_present(mps_cpu))
 602                 return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu);
 603         else
 604                 return BAD_APICID;
 605 }
 606
 607 static inline int
 608 __default_check_phys_apicid_present(int phys_apicid)
 609 {
 610         return physid_isset(phys_apicid, phys_cpu_present_map);
 611 }
 612
 613 #ifdef CONFIG_X86_32
 614 static inline int default_cpu_present_to_apicid(int mps_cpu)
 615 {
 616         return __default_cpu_present_to_apicid(mps_cpu);
 617 }
 618
 619 static inline int
 620 default_check_phys_apicid_present(int phys_apicid)
 621 {
 622         return __default_check_phys_apicid_present(phys_apicid);
 623 }
 624 #else
 625 extern int default_cpu_present_to_apicid(int mps_cpu);
 626 extern int default_check_phys_apicid_present(int phys_apicid);
 627 #endif
 628
 629 #endif /* CONFIG_X86_LOCAL_APIC */
 630
 631 #endif /* _ASM_X86_APIC_H */