arch/x86/include/asm/desc.h

   1 #ifndef _ASM_X86_DESC_H
   2 #define _ASM_X86_DESC_H
   3
   4 #include <asm/desc_defs.h>
   5 #include <asm/ldt.h>
   6 #include <asm/mmu.h>
   7
   8 #include <linux/smp.h>
   9
  10 static inline void fill_ldt(struct desc_struct *desc, const struct user_desc *info)
  11 {
  12         desc->limit0            = info->limit & 0x0ffff;
  13
  14         desc->base0             = (info->base_addr & 0x0000ffff);
  15         desc->base1             = (info->base_addr & 0x00ff0000) >> 16;
  16
  17         desc->type              = (info->read_exec_only ^ 1) << 1;
  18         desc->type             |= info->contents << 2;
  19
  20         desc->s                 = 1;
  21         desc->dpl               = 0x3;
  22         desc->p                 = info->seg_not_present ^ 1;
  23         desc->limit             = (info->limit & 0xf0000) >> 16;
  24         desc->avl               = info->useable;
  25         desc->d                 = info->seg_32bit;
  26         desc->g                 = info->limit_in_pages;
  27
  28         desc->base2             = (info->base_addr & 0xff000000) >> 24;
  29         /*
  30          * Don't allow setting of the lm bit. It would confuse
  31          * user_64bit_mode and would get overridden by sysret anyway.
  32          */
  33         desc->l                 = 0;
  34 }
  35
  36 extern struct desc_ptr idt_descr;
  37 extern gate_desc idt_table[];
  38 extern struct desc_ptr nmi_idt_descr;
  39 extern gate_desc nmi_idt_table[];
  40
  41 struct gdt_page {
  42         struct desc_struct gdt[GDT_ENTRIES];
  43 } __attribute__((aligned(PAGE_SIZE)));
  44
  45 DECLARE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page);
  46
  47 static inline struct desc_struct *get_cpu_gdt_table(unsigned int cpu)
  48 {
  49         return per_cpu(gdt_page, cpu).gdt;
  50 }
  51
  52 #ifdef CONFIG_X86_64
  53
  54 static inline void pack_gate(gate_desc *gate, unsigned type, unsigned long func,
  55                              unsigned dpl, unsigned ist, unsigned seg)
  56 {
  57         gate->offset_low        = PTR_LOW(func);
  58         gate->segment           = __KERNEL_CS;
  59         gate->ist               = ist;
  60         gate->p                 = 1;
  61         gate->dpl               = dpl;
  62         gate->zero0             = 0;
  63         gate->zero1             = 0;
  64         gate->type              = type;
  65         gate->offset_middle     = PTR_MIDDLE(func);
  66         gate->offset_high       = PTR_HIGH(func);
  67 }
  68
  69 #else
  70 static inline void pack_gate(gate_desc *gate, unsigned char type,
  71                              unsigned long base, unsigned dpl, unsigned flags,
  72                              unsigned short seg)
  73 {
  74         gate->a = (seg << 16) | (base & 0xffff);
  75         gate->b = (base & 0xffff0000) | (((0x80 | type | (dpl << 5)) & 0xff) << 8);
  76 }
  77
  78 #endif
  79
  80 static inline int desc_empty(const void *ptr)
  81 {
  82         const u32 *desc = ptr;
  83
  84         return !(desc[0] | desc[1]);
  85 }
  86
  87 #ifdef CONFIG_PARAVIRT
  88 #include <asm/paravirt.h>
  89 #else
  90 #define load_TR_desc()                          native_load_tr_desc()
  91 #define load_gdt(dtr)                           native_load_gdt(dtr)
  92 #define load_idt(dtr)                           native_load_idt(dtr)
  93 #define load_tr(tr)                             asm volatile("ltr %0"::"m" (tr))
  94 #define load_ldt(ldt)                           asm volatile("lldt %0"::"m" (ldt))
  95
  96 #define store_gdt(dtr)                          native_store_gdt(dtr)
  97 #define store_idt(dtr)                          native_store_idt(dtr)
  98 #define store_tr(tr)                            (tr = native_store_tr())
  99
 100 #define load_TLS(t, cpu)                        native_load_tls(t, cpu)
 101 #define set_ldt                                 native_set_ldt
 102
 103 #define write_ldt_entry(dt, entry, desc)        native_write_ldt_entry(dt, entry, desc)
 104 #define write_gdt_entry(dt, entry, desc, type)  native_write_gdt_entry(dt, entry, desc, type)
 105 #define write_idt_entry(dt, entry, g)           native_write_idt_entry(dt, entry, g)
 106
 107 static inline void paravirt_alloc_ldt(struct desc_struct *ldt, unsigned entries)
 108 {
 109 }
 110
 111 static inline void paravirt_free_ldt(struct desc_struct *ldt, unsigned entries)
 112 {
 113 }
 114 #endif  /* CONFIG_PARAVIRT */
 115
 116 #define store_ldt(ldt) asm("sldt %0" : "=m"(ldt))
 117
 118 static inline void native_write_idt_entry(gate_desc *idt, int entry, const gate_desc *gate)
 119 {
 120         memcpy(&idt[entry], gate, sizeof(*gate));
 121 }
 122
 123 static inline void native_write_ldt_entry(struct desc_struct *ldt, int entry, const void *desc)
 124 {
 125         memcpy(&ldt[entry], desc, 8);
 126 }
 127
 128 static inline void
 129 native_write_gdt_entry(struct desc_struct *gdt, int entry, const void *desc, int type)
 130 {
 131         unsigned int size;
 132
 133         switch (type) {
 134         case DESC_TSS:  size = sizeof(tss_desc);        break;
 135         case DESC_LDT:  size = sizeof(ldt_desc);        break;
 136         default:        size = sizeof(*gdt);            break;
 137         }
 138
 139         memcpy(&gdt[entry], desc, size);
 140 }
 141
 142 static inline void pack_descriptor(struct desc_struct *desc, unsigned long base,
 143                                    unsigned long limit, unsigned char type,
 144                                    unsigned char flags)
 145 {
 146         desc->a = ((base & 0xffff) << 16) | (limit & 0xffff);
 147         desc->b = (base & 0xff000000) | ((base & 0xff0000) >> 16) |
 148                 (limit & 0x000f0000) | ((type & 0xff) << 8) |
 149                 ((flags & 0xf) << 20);
 150         desc->p = 1;
 151 }
 152
 153
 154 static inline void set_tssldt_descriptor(void *d, unsigned long addr, unsigned type, unsigned size)
 155 {
 156 #ifdef CONFIG_X86_64
 157         struct ldttss_desc64 *desc = d;
 158
 159         memset(desc, 0, sizeof(*desc));
 160
 161         desc->limit0            = size & 0xFFFF;
 162         desc->base0             = PTR_LOW(addr);
 163         desc->base1             = PTR_MIDDLE(addr) & 0xFF;
 164         desc->type              = type;
 165         desc->p                 = 1;
 166         desc->limit1            = (size >> 16) & 0xF;
 167         desc->base2             = (PTR_MIDDLE(addr) >> 8) & 0xFF;
 168         desc->base3             = PTR_HIGH(addr);
 169 #else
 170         pack_descriptor((struct desc_struct *)d, addr, size, 0x80 | type, 0);
 171 #endif
 172 }
 173
 174 static inline void __set_tss_desc(unsigned cpu, unsigned int entry, void *addr)
 175 {
 176         struct desc_struct *d = get_cpu_gdt_table(cpu);
 177         tss_desc tss;
 178
 179         /*
 180          * sizeof(unsigned long) coming from an extra "long" at the end
 181          * of the iobitmap. See tss_struct definition in processor.h
 182          *
 183          * -1? seg base+limit should be pointing to the address of the
 184          * last valid byte
 185          */
 186         set_tssldt_descriptor(&tss, (unsigned long)addr, DESC_TSS,
 187                               IO_BITMAP_OFFSET + IO_BITMAP_BYTES +
 188                               sizeof(unsigned long) - 1);
 189         write_gdt_entry(d, entry, &tss, DESC_TSS);
 190 }
 191
 192 #define set_tss_desc(cpu, addr) __set_tss_desc(cpu, GDT_ENTRY_TSS, addr)
 193
 194 static inline void native_set_ldt(const void *addr, unsigned int entries)
 195 {
 196         if (likely(entries == 0))
 197                 asm volatile("lldt %w0"::"q" (0));
 198         else {
 199                 unsigned cpu = smp_processor_id();
 200                 ldt_desc ldt;
 201
 202                 set_tssldt_descriptor(&ldt, (unsigned long)addr, DESC_LDT,
 203                                       entries * LDT_ENTRY_SIZE - 1);
 204                 write_gdt_entry(get_cpu_gdt_table(cpu), GDT_ENTRY_LDT,
 205                                 &ldt, DESC_LDT);
 206                 asm volatile("lldt %w0"::"q" (GDT_ENTRY_LDT*8));
 207         }
 208 }
 209
 210 static inline void native_load_tr_desc(void)
 211 {
 212         asm volatile("ltr %w0"::"q" (GDT_ENTRY_TSS*8));
 213 }
 214
 215 static inline void native_load_gdt(const struct desc_ptr *dtr)
 216 {
 217         asm volatile("lgdt %0"::"m" (*dtr));
 218 }
 219
 220 static inline void native_load_idt(const struct desc_ptr *dtr)
 221 {
 222         asm volatile("lidt %0"::"m" (*dtr));
 223 }
 224
 225 static inline void native_store_gdt(struct desc_ptr *dtr)
 226 {
 227         asm volatile("sgdt %0":"=m" (*dtr));
 228 }
 229
 230 static inline void native_store_idt(struct desc_ptr *dtr)
 231 {
 232         asm volatile("sidt %0":"=m" (*dtr));
 233 }
 234
 235 static inline unsigned long native_store_tr(void)
 236 {
 237         unsigned long tr;
 238
 239         asm volatile("str %0":"=r" (tr));
 240
 241         return tr;
 242 }
 243
 244 static inline void native_load_tls(struct thread_struct *t, unsigned int cpu)
 245 {
 246         struct desc_struct *gdt = get_cpu_gdt_table(cpu);
 247         unsigned int i;
 248
 249         for (i = 0; i < GDT_ENTRY_TLS_ENTRIES; i++)
 250                 gdt[GDT_ENTRY_TLS_MIN + i] = t->tls_array[i];
 251 }
 252
 253 #define _LDT_empty(info)                                \
 254         ((info)->base_addr              == 0    &&      \
 255          (info)->limit                  == 0    &&      \
 256          (info)->contents               == 0    &&      \
 257          (info)->read_exec_only         == 1    &&      \
 258          (info)->seg_32bit              == 0    &&      \
 259          (info)->limit_in_pages         == 0    &&      \
 260          (info)->seg_not_present        == 1    &&      \
 261          (info)->useable                == 0)
 262
 263 #ifdef CONFIG_X86_64
 264 #define LDT_empty(info) (_LDT_empty(info) && ((info)->lm == 0))
 265 #else
 266 #define LDT_empty(info) (_LDT_empty(info))
 267 #endif
 268
 269 static inline void clear_LDT(void)
 270 {
 271         set_ldt(NULL, 0);
 272 }
 273
 274 /*
 275  * load one particular LDT into the current CPU
 276  */
 277 static inline void load_LDT_nolock(mm_context_t *pc)
 278 {
 279         set_ldt(pc->ldt, pc->size);
 280 }
 281
 282 static inline void load_LDT(mm_context_t *pc)
 283 {
 284         preempt_disable();
 285         load_LDT_nolock(pc);
 286         preempt_enable();
 287 }
 288
 289 static inline unsigned long get_desc_base(const struct desc_struct *desc)
 290 {
 291         return (unsigned)(desc->base0 | ((desc->base1) << 16) | ((desc->base2) << 24));
 292 }
 293
 294 static inline void set_desc_base(struct desc_struct *desc, unsigned long base)
 295 {
 296         desc->base0 = base & 0xffff;
 297         desc->base1 = (base >> 16) & 0xff;
 298         desc->base2 = (base >> 24) & 0xff;
 299 }
 300
 301 static inline unsigned long get_desc_limit(const struct desc_struct *desc)
 302 {
 303         return desc->limit0 | (desc->limit << 16);
 304 }
 305
 306 static inline void set_desc_limit(struct desc_struct *desc, unsigned long limit)
 307 {
 308         desc->limit0 = limit & 0xffff;
 309         desc->limit = (limit >> 16) & 0xf;
 310 }
 311
 312 #ifdef CONFIG_X86_64
 313 static inline void set_nmi_gate(int gate, void *addr)
 314 {
 315         gate_desc s;
 316
 317         pack_gate(&s, GATE_INTERRUPT, (unsigned long)addr, 0, 0, __KERNEL_CS);
 318         write_idt_entry(nmi_idt_table, gate, &s);
 319 }
 320 #endif
 321
 322 static inline void _set_gate(int gate, unsigned type, void *addr,
 323                              unsigned dpl, unsigned ist, unsigned seg)
 324 {
 325         gate_desc s;
 326
 327         pack_gate(&s, type, (unsigned long)addr, dpl, ist, seg);
 328         /*
 329          * does not need to be atomic because it is only done once at
 330          * setup time
 331          */
 332         write_idt_entry(idt_table, gate, &s);
 333 }
 334
 335 /*
 336  * This needs to use 'idt_table' rather than 'idt', and
 337  * thus use the _nonmapped_ version of the IDT, as the
 338  * Pentium F0 0F bugfix can have resulted in the mapped
 339  * IDT being write-protected.
 340  */
 341 static inline void set_intr_gate(unsigned int n, void *addr)
 342 {
 343         BUG_ON((unsigned)n > 0xFF);
 344         _set_gate(n, GATE_INTERRUPT, addr, 0, 0, __KERNEL_CS);
 345 }
 346
 347 extern int first_system_vector;
 348 /* used_vectors is BITMAP for irq is not managed by percpu vector_irq */
 349 extern unsigned long used_vectors[];
 350
 351 static inline void alloc_system_vector(int vector)
 352 {
 353         if (!test_bit(vector, used_vectors)) {
 354                 set_bit(vector, used_vectors);
 355                 if (first_system_vector > vector)
 356                         first_system_vector = vector;
 357         } else {
 358                 BUG();
 359         }
 360 }
 361
 362 static inline void alloc_intr_gate(unsigned int n, void *addr)
 363 {
 364         alloc_system_vector(n);
 365         set_intr_gate(n, addr);
 366 }
 367
 368 /*
 369  * This routine sets up an interrupt gate at directory privilege level 3.
 370  */
 371 static inline void set_system_intr_gate(unsigned int n, void *addr)
 372 {
 373         BUG_ON((unsigned)n > 0xFF);
 374         _set_gate(n, GATE_INTERRUPT, addr, 0x3, 0, __KERNEL_CS);
 375 }
 376
 377 static inline void set_system_trap_gate(unsigned int n, void *addr)
 378 {
 379         BUG_ON((unsigned)n > 0xFF);
 380         _set_gate(n, GATE_TRAP, addr, 0x3, 0, __KERNEL_CS);
 381 }
 382
 383 static inline void set_trap_gate(unsigned int n, void *addr)
 384 {
 385         BUG_ON((unsigned)n > 0xFF);
 386         _set_gate(n, GATE_TRAP, addr, 0, 0, __KERNEL_CS);
 387 }
 388
 389 static inline void set_task_gate(unsigned int n, unsigned int gdt_entry)
 390 {
 391         BUG_ON((unsigned)n > 0xFF);
 392         _set_gate(n, GATE_TASK, (void *)0, 0, 0, (gdt_entry<<3));
 393 }
 394
 395 static inline void set_intr_gate_ist(int n, void *addr, unsigned ist)
 396 {
 397         BUG_ON((unsigned)n > 0xFF);
 398         _set_gate(n, GATE_INTERRUPT, addr, 0, ist, __KERNEL_CS);
 399 }
 400
 401 static inline void set_system_intr_gate_ist(int n, void *addr, unsigned ist)
 402 {
 403         BUG_ON((unsigned)n > 0xFF);
 404         _set_gate(n, GATE_INTERRUPT, addr, 0x3, ist, __KERNEL_CS);
 405 }
 406
 407 #endif /* _ASM_X86_DESC_H */