2 * Intel SMP support routines.
4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
5 * (c) 1998-99, 2000, 2009 Ingo Molnar <mingo@redhat.com>
6 * (c) 2002,2003 Andi Kleen, SuSE Labs.
8 * i386 and x86_64 integration by Glauber Costa <gcosta@redhat.com>
10 * This code is released under the GNU General Public License version 2 or
14 #include <linux/init.h>
17 #include <linux/delay.h>
18 #include <linux/spinlock.h>
19 #include <linux/export.h>
20 #include <linux/kernel_stat.h>
21 #include <linux/mc146818rtc.h>
22 #include <linux/cache.h>
23 #include <linux/interrupt.h>
24 #include <linux/cpu.h>
25 #include <linux/gfp.h>
28 #include <asm/tlbflush.h>
29 #include <asm/mmu_context.h>
30 #include <asm/proto.h>
34 * Some notes on x86 processor bugs affecting SMP operation:
36 * Pentium, Pentium Pro, II, III (and all CPUs) have bugs.
37 * The Linux implications for SMP are handled as follows:
39 * Pentium III / [Xeon]
40 * None of the E1AP-E3AP errata are visible to the user.
47 * None of the A1AP-A3AP errata are visible to the user.
54 * None of 1AP-9AP errata are visible to the normal user,
55 * except occasional delivery of 'spurious interrupt' as trap #15.
56 * This is very rare and a non-problem.
58 * 1AP. Linux maps APIC as non-cacheable
59 * 2AP. worked around in hardware
60 * 3AP. fixed in C0 and above steppings microcode update.
61 * Linux does not use excessive STARTUP_IPIs.
62 * 4AP. worked around in hardware
63 * 5AP. symmetric IO mode (normal Linux operation) not affected.
64 * 'noapic' mode has vector 0xf filled out properly.
65 * 6AP. 'noapic' mode might be affected - fixed in later steppings
66 * 7AP. We do not assume writes to the LVT deassering IRQs
67 * 8AP. We do not enable low power mode (deep sleep) during MP bootup
68 * 9AP. We do not use mixed mode
71 * There is a marginal case where REP MOVS on 100MHz SMP
72 * machines with B stepping processors can fail. XXX should provide
73 * an L1cache=Writethrough or L1cache=off option.
75 * B stepping CPUs may hang. There are hardware work arounds
76 * for this. We warn about it in case your board doesn't have the work
77 * arounds. Basically that's so I can tell anyone with a B stepping
78 * CPU and SMP problems "tough".
80 * Specific items [From Pentium Processor Specification Update]
82 * 1AP. Linux doesn't use remote read
83 * 2AP. Linux doesn't trust APIC errors
84 * 3AP. We work around this
85 * 4AP. Linux never generated 3 interrupts of the same priority
86 * to cause a lost local interrupt.
87 * 5AP. Remote read is never used
88 * 6AP. not affected - worked around in hardware
89 * 7AP. not affected - worked around in hardware
90 * 8AP. worked around in hardware - we get explicit CS errors if not
91 * 9AP. only 'noapic' mode affected. Might generate spurious
92 * interrupts, we log only the first one and count the
94 * 10AP. not affected - worked around in hardware
95 * 11AP. Linux reads the APIC between writes to avoid this, as per
96 * the documentation. Make sure you preserve this as it affects
97 * the C stepping chips too.
98 * 12AP. not affected - worked around in hardware
99 * 13AP. not affected - worked around in hardware
100 * 14AP. we always deassert INIT during bootup
101 * 15AP. not affected - worked around in hardware
102 * 16AP. not affected - worked around in hardware
103 * 17AP. not affected - worked around in hardware
104 * 18AP. not affected - worked around in hardware
105 * 19AP. not affected - worked around in BIOS
107 * If this sounds worrying believe me these bugs are either ___RARE___,
108 * or are signal timing bugs worked around in hardware and there's
109 * about nothing of note with C stepping upwards.
113 * this function sends a 'reschedule' IPI to another CPU.
114 * it goes straight through and wastes no time serializing
115 * anything. Worst case is that we lose a reschedule ...
117 static void native_smp_send_reschedule(int cpu
)
119 if (unlikely(cpu_is_offline(cpu
))) {
123 apic
->send_IPI_mask(cpumask_of(cpu
), RESCHEDULE_VECTOR
);
126 void native_send_call_func_single_ipi(int cpu
)
128 apic
->send_IPI_mask(cpumask_of(cpu
), CALL_FUNCTION_SINGLE_VECTOR
);
131 void native_send_call_func_ipi(const struct cpumask
*mask
)
133 cpumask_var_t allbutself
;
135 if (!alloc_cpumask_var(&allbutself
, GFP_ATOMIC
)) {
136 apic
->send_IPI_mask(mask
, CALL_FUNCTION_VECTOR
);
140 cpumask_copy(allbutself
, cpu_online_mask
);
141 cpumask_clear_cpu(smp_processor_id(), allbutself
);
143 if (cpumask_equal(mask
, allbutself
) &&
144 cpumask_equal(cpu_online_mask
, cpu_callout_mask
))
145 apic
->send_IPI_allbutself(CALL_FUNCTION_VECTOR
);
147 apic
->send_IPI_mask(mask
, CALL_FUNCTION_VECTOR
);
149 free_cpumask_var(allbutself
);
152 static atomic_t stopping_cpu
= ATOMIC_INIT(-1);
154 static int smp_stop_nmi_callback(unsigned int val
, struct pt_regs
*regs
)
156 /* We are registered on stopping cpu too, avoid spurious NMI */
157 if (raw_smp_processor_id() == atomic_read(&stopping_cpu
))
165 static void native_nmi_stop_other_cpus(int wait
)
168 unsigned long timeout
;
174 * Use an own vector here because smp_call_function
175 * does lots of things not suitable in a panic situation.
177 if (num_online_cpus() > 1) {
178 /* did someone beat us here? */
179 if (atomic_cmpxchg(&stopping_cpu
, -1, safe_smp_processor_id()) != -1)
182 if (register_nmi_handler(NMI_LOCAL
, smp_stop_nmi_callback
,
183 NMI_FLAG_FIRST
, "smp_stop"))
184 /* Note: we ignore failures here */
187 /* sync above data before sending NMI */
190 apic
->send_IPI_allbutself(NMI_VECTOR
);
193 * Don't wait longer than a second if the caller
194 * didn't ask us to wait.
196 timeout
= USEC_PER_SEC
;
197 while (num_online_cpus() > 1 && (wait
|| timeout
--))
201 local_irq_save(flags
);
202 disable_local_APIC();
203 local_irq_restore(flags
);
207 * this function calls the 'stop' function on all other CPUs in the system.
210 asmlinkage
void smp_reboot_interrupt(void)
218 static void native_irq_stop_other_cpus(int wait
)
221 unsigned long timeout
;
227 * Use an own vector here because smp_call_function
228 * does lots of things not suitable in a panic situation.
229 * On most systems we could also use an NMI here,
230 * but there are a few systems around where NMI
231 * is problematic so stay with an non NMI for now
232 * (this implies we cannot stop CPUs spinning with irq off
235 if (num_online_cpus() > 1) {
236 apic
->send_IPI_allbutself(REBOOT_VECTOR
);
239 * Don't wait longer than a second if the caller
240 * didn't ask us to wait.
242 timeout
= USEC_PER_SEC
;
243 while (num_online_cpus() > 1 && (wait
|| timeout
--))
247 local_irq_save(flags
);
248 disable_local_APIC();
249 local_irq_restore(flags
);
252 static void native_smp_disable_nmi_ipi(void)
254 smp_ops
.stop_other_cpus
= native_irq_stop_other_cpus
;
258 * Reschedule call back.
260 void smp_reschedule_interrupt(struct pt_regs
*regs
)
263 inc_irq_stat(irq_resched_count
);
266 * KVM uses this interrupt to force a cpu out of guest mode
270 void smp_call_function_interrupt(struct pt_regs
*regs
)
274 generic_smp_call_function_interrupt();
275 inc_irq_stat(irq_call_count
);
279 void smp_call_function_single_interrupt(struct pt_regs
*regs
)
283 generic_smp_call_function_single_interrupt();
284 inc_irq_stat(irq_call_count
);
288 static int __init
nonmi_ipi_setup(char *str
)
290 native_smp_disable_nmi_ipi();
294 __setup("nonmi_ipi", nonmi_ipi_setup
);
296 struct smp_ops smp_ops
= {
297 .smp_prepare_boot_cpu
= native_smp_prepare_boot_cpu
,
298 .smp_prepare_cpus
= native_smp_prepare_cpus
,
299 .smp_cpus_done
= native_smp_cpus_done
,
301 .stop_other_cpus
= native_nmi_stop_other_cpus
,
302 .smp_send_reschedule
= native_smp_send_reschedule
,
304 .cpu_up
= native_cpu_up
,
305 .cpu_die
= native_cpu_die
,
306 .cpu_disable
= native_cpu_disable
,
307 .play_dead
= native_play_dead
,
309 .send_call_func_ipi
= native_send_call_func_ipi
,
310 .send_call_func_single_ipi
= native_send_call_func_single_ipi
,
312 EXPORT_SYMBOL_GPL(smp_ops
);