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spi-topcliff-pch: add recovery processing in case wait-event timeout
[zen-stable.git] / drivers / net / ethernet / atheros / atlx / atl1.c
blob3c4daca8012b00d156e080e9c686cc361c39bad0
1 /*
2 * Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved.
3 * Copyright(c) 2006 - 2007 Chris Snook <csnook@redhat.com>
4 * Copyright(c) 2006 - 2008 Jay Cliburn <jcliburn@gmail.com>
5 *
6 * Derived from Intel e1000 driver
7 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the Free
11 * Software Foundation; either version 2 of the License, or (at your option)
12 * any later version.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program; if not, write to the Free Software Foundation, Inc., 59
21 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22 *
23 * The full GNU General Public License is included in this distribution in the
24 * file called COPYING.
25 *
26 * Contact Information:
27 * Xiong Huang <xiong.huang@atheros.com>
28 * Jie Yang <jie.yang@atheros.com>
29 * Chris Snook <csnook@redhat.com>
30 * Jay Cliburn <jcliburn@gmail.com>
31 *
32 * This version is adapted from the Attansic reference driver.
33 *
34 * TODO:
35 * Add more ethtool functions.
36 * Fix abstruse irq enable/disable condition described here:
37 * http://marc.theaimsgroup.com/?l=linux-netdev&m=116398508500553&w=2
38 *
39 * NEEDS TESTING:
40 * VLAN
41 * multicast
42 * promiscuous mode
43 * interrupt coalescing
44 * SMP torture testing
45 */
46
47 #include <linux/atomic.h>
48 #include <asm/byteorder.h>
49
50 #include <linux/compiler.h>
51 #include <linux/crc32.h>
52 #include <linux/delay.h>
53 #include <linux/dma-mapping.h>
54 #include <linux/etherdevice.h>
55 #include <linux/hardirq.h>
56 #include <linux/if_ether.h>
57 #include <linux/if_vlan.h>
58 #include <linux/in.h>
59 #include <linux/interrupt.h>
60 #include <linux/ip.h>
61 #include <linux/irqflags.h>
62 #include <linux/irqreturn.h>
63 #include <linux/jiffies.h>
64 #include <linux/mii.h>
65 #include <linux/module.h>
66 #include <linux/moduleparam.h>
67 #include <linux/net.h>
68 #include <linux/netdevice.h>
69 #include <linux/pci.h>
70 #include <linux/pci_ids.h>
71 #include <linux/pm.h>
72 #include <linux/skbuff.h>
73 #include <linux/slab.h>
74 #include <linux/spinlock.h>
75 #include <linux/string.h>
76 #include <linux/tcp.h>
77 #include <linux/timer.h>
78 #include <linux/types.h>
79 #include <linux/workqueue.h>
80
81 #include <net/checksum.h>
82
83 #include "atl1.h"
84
85 #define ATLX_DRIVER_VERSION "2.1.3"
86 MODULE_AUTHOR("Xiong Huang <xiong.huang@atheros.com>, "
87 "Chris Snook <csnook@redhat.com>, "
88 "Jay Cliburn <jcliburn@gmail.com>");
89 MODULE_LICENSE("GPL");
90 MODULE_VERSION(ATLX_DRIVER_VERSION);
91
92 /* Temporary hack for merging atl1 and atl2 */
93 #include "atlx.c"
94
95 static const struct ethtool_ops atl1_ethtool_ops;
96
97 /*
98 * This is the only thing that needs to be changed to adjust the
99 * maximum number of ports that the driver can manage.
100 */
101 #define ATL1_MAX_NIC 4
102
103 #define OPTION_UNSET -1
104 #define OPTION_DISABLED 0
105 #define OPTION_ENABLED 1
106
107 #define ATL1_PARAM_INIT { [0 ... ATL1_MAX_NIC] = OPTION_UNSET }
108
109 /*
110 * Interrupt Moderate Timer in units of 2 us
111 *
112 * Valid Range: 10-65535
113 *
114 * Default Value: 100 (200us)
115 */
116 static int __devinitdata int_mod_timer[ATL1_MAX_NIC+1] = ATL1_PARAM_INIT;
117 static unsigned int num_int_mod_timer;
118 module_param_array_named(int_mod_timer, int_mod_timer, int,
119 &num_int_mod_timer, 0);
120 MODULE_PARM_DESC(int_mod_timer, "Interrupt moderator timer");
121
122 #define DEFAULT_INT_MOD_CNT 100 /* 200us */
123 #define MAX_INT_MOD_CNT 65000
124 #define MIN_INT_MOD_CNT 50
125
126 struct atl1_option {
127 enum { enable_option, range_option, list_option } type;
128 char *name;
129 char *err;
130 int def;
131 union {
132 struct { /* range_option info */
133 int min;
134 int max;
135 } r;
136 struct { /* list_option info */
137 int nr;
138 struct atl1_opt_list {
139 int i;
140 char *str;
141 } *p;
142 } l;
143 } arg;
144 };
145
146 static int __devinit atl1_validate_option(int *value, struct atl1_option *opt,
147 struct pci_dev *pdev)
148 {
149 if (*value == OPTION_UNSET) {
150 *value = opt->def;
151 return 0;
152 }
153
154 switch (opt->type) {
155 case enable_option:
156 switch (*value) {
157 case OPTION_ENABLED:
158 dev_info(&pdev->dev, "%s enabled\n", opt->name);
159 return 0;
160 case OPTION_DISABLED:
161 dev_info(&pdev->dev, "%s disabled\n", opt->name);
162 return 0;
163 }
164 break;
165 case range_option:
166 if (*value >= opt->arg.r.min && *value <= opt->arg.r.max) {
167 dev_info(&pdev->dev, "%s set to %i\n", opt->name,
168 *value);
169 return 0;
170 }
171 break;
172 case list_option:{
173 int i;
174 struct atl1_opt_list *ent;
175
176 for (i = 0; i < opt->arg.l.nr; i++) {
177 ent = &opt->arg.l.p[i];
178 if (*value == ent->i) {
179 if (ent->str[0] != '\0')
180 dev_info(&pdev->dev, "%s\n",
181 ent->str);
182 return 0;
183 }
184 }
185 }
186 break;
187
188 default:
189 break;
190 }
191
192 dev_info(&pdev->dev, "invalid %s specified (%i) %s\n",
193 opt->name, *value, opt->err);
194 *value = opt->def;
195 return -1;
196 }
197
198 /*
199 * atl1_check_options - Range Checking for Command Line Parameters
200 * @adapter: board private structure
201 *
202 * This routine checks all command line parameters for valid user
203 * input. If an invalid value is given, or if no user specified
204 * value exists, a default value is used. The final value is stored
205 * in a variable in the adapter structure.
206 */
207 static void __devinit atl1_check_options(struct atl1_adapter *adapter)
208 {
209 struct pci_dev *pdev = adapter->pdev;
210 int bd = adapter->bd_number;
211 if (bd >= ATL1_MAX_NIC) {
212 dev_notice(&pdev->dev, "no configuration for board#%i\n", bd);
213 dev_notice(&pdev->dev, "using defaults for all values\n");
214 }
215 { /* Interrupt Moderate Timer */
216 struct atl1_option opt = {
217 .type = range_option,
218 .name = "Interrupt Moderator Timer",
219 .err = "using default of "
220 __MODULE_STRING(DEFAULT_INT_MOD_CNT),
221 .def = DEFAULT_INT_MOD_CNT,
222 .arg = {.r = {.min = MIN_INT_MOD_CNT,
223 .max = MAX_INT_MOD_CNT} }
224 };
225 int val;
226 if (num_int_mod_timer > bd) {
227 val = int_mod_timer[bd];
228 atl1_validate_option(&val, &opt, pdev);
229 adapter->imt = (u16) val;
230 } else
231 adapter->imt = (u16) (opt.def);
232 }
233 }
234
235 /*
236 * atl1_pci_tbl - PCI Device ID Table
237 */
238 static DEFINE_PCI_DEVICE_TABLE(atl1_pci_tbl) = {
239 {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATTANSIC_L1)},
240 /* required last entry */
241 {0,}
242 };
243 MODULE_DEVICE_TABLE(pci, atl1_pci_tbl);
244
245 static const u32 atl1_default_msg = NETIF_MSG_DRV | NETIF_MSG_PROBE |
246 NETIF_MSG_LINK | NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP;
247
248 static int debug = -1;
249 module_param(debug, int, 0);
250 MODULE_PARM_DESC(debug, "Message level (0=none,...,16=all)");
251
252 /*
253 * Reset the transmit and receive units; mask and clear all interrupts.
254 * hw - Struct containing variables accessed by shared code
255 * return : 0 or idle status (if error)
256 */
257 static s32 atl1_reset_hw(struct atl1_hw *hw)
258 {
259 struct pci_dev *pdev = hw->back->pdev;
260 struct atl1_adapter *adapter = hw->back;
261 u32 icr;
262 int i;
263
264 /*
265 * Clear Interrupt mask to stop board from generating
266 * interrupts & Clear any pending interrupt events
267 */
268 /*
269 * iowrite32(0, hw->hw_addr + REG_IMR);
270 * iowrite32(0xffffffff, hw->hw_addr + REG_ISR);
271 */
272
273 /*
274 * Issue Soft Reset to the MAC. This will reset the chip's
275 * transmit, receive, DMA. It will not effect
276 * the current PCI configuration. The global reset bit is self-
277 * clearing, and should clear within a microsecond.
278 */
279 iowrite32(MASTER_CTRL_SOFT_RST, hw->hw_addr + REG_MASTER_CTRL);
280 ioread32(hw->hw_addr + REG_MASTER_CTRL);
281
282 iowrite16(1, hw->hw_addr + REG_PHY_ENABLE);
283 ioread16(hw->hw_addr + REG_PHY_ENABLE);
284
285 /* delay about 1ms */
286 msleep(1);
287
288 /* Wait at least 10ms for All module to be Idle */
289 for (i = 0; i < 10; i++) {
290 icr = ioread32(hw->hw_addr + REG_IDLE_STATUS);
291 if (!icr)
292 break;
293 /* delay 1 ms */
294 msleep(1);
295 /* FIXME: still the right way to do this? */
296 cpu_relax();
297 }
298
299 if (icr) {
300 if (netif_msg_hw(adapter))
301 dev_dbg(&pdev->dev, "ICR = 0x%x\n", icr);
302 return icr;
303 }
304
305 return 0;
306 }
307
308 /* function about EEPROM
309 *
310 * check_eeprom_exist
311 * return 0 if eeprom exist
312 */
313 static int atl1_check_eeprom_exist(struct atl1_hw *hw)
314 {
315 u32 value;
316 value = ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL);
317 if (value & SPI_FLASH_CTRL_EN_VPD) {
318 value &= ~SPI_FLASH_CTRL_EN_VPD;
319 iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL);
320 }
321
322 value = ioread16(hw->hw_addr + REG_PCIE_CAP_LIST);
323 return ((value & 0xFF00) == 0x6C00) ? 0 : 1;
324 }
325
326 static bool atl1_read_eeprom(struct atl1_hw *hw, u32 offset, u32 *p_value)
327 {
328 int i;
329 u32 control;
330
331 if (offset & 3)
332 /* address do not align */
333 return false;
334
335 iowrite32(0, hw->hw_addr + REG_VPD_DATA);
336 control = (offset & VPD_CAP_VPD_ADDR_MASK) << VPD_CAP_VPD_ADDR_SHIFT;
337 iowrite32(control, hw->hw_addr + REG_VPD_CAP);
338 ioread32(hw->hw_addr + REG_VPD_CAP);
339
340 for (i = 0; i < 10; i++) {
341 msleep(2);
342 control = ioread32(hw->hw_addr + REG_VPD_CAP);
343 if (control & VPD_CAP_VPD_FLAG)
344 break;
345 }
346 if (control & VPD_CAP_VPD_FLAG) {
347 *p_value = ioread32(hw->hw_addr + REG_VPD_DATA);
348 return true;
349 }
350 /* timeout */
351 return false;
352 }
353
354 /*
355 * Reads the value from a PHY register
356 * hw - Struct containing variables accessed by shared code
357 * reg_addr - address of the PHY register to read
358 */
359 static s32 atl1_read_phy_reg(struct atl1_hw *hw, u16 reg_addr, u16 *phy_data)
360 {
361 u32 val;
362 int i;
363
364 val = ((u32) (reg_addr & MDIO_REG_ADDR_MASK)) << MDIO_REG_ADDR_SHIFT |
365 MDIO_START | MDIO_SUP_PREAMBLE | MDIO_RW | MDIO_CLK_25_4 <<
366 MDIO_CLK_SEL_SHIFT;
367 iowrite32(val, hw->hw_addr + REG_MDIO_CTRL);
368 ioread32(hw->hw_addr + REG_MDIO_CTRL);
369
370 for (i = 0; i < MDIO_WAIT_TIMES; i++) {
371 udelay(2);
372 val = ioread32(hw->hw_addr + REG_MDIO_CTRL);
373 if (!(val & (MDIO_START | MDIO_BUSY)))
374 break;
375 }
376 if (!(val & (MDIO_START | MDIO_BUSY))) {
377 *phy_data = (u16) val;
378 return 0;
379 }
380 return ATLX_ERR_PHY;
381 }
382
383 #define CUSTOM_SPI_CS_SETUP 2
384 #define CUSTOM_SPI_CLK_HI 2
385 #define CUSTOM_SPI_CLK_LO 2
386 #define CUSTOM_SPI_CS_HOLD 2
387 #define CUSTOM_SPI_CS_HI 3
388
389 static bool atl1_spi_read(struct atl1_hw *hw, u32 addr, u32 *buf)
390 {
391 int i;
392 u32 value;
393
394 iowrite32(0, hw->hw_addr + REG_SPI_DATA);
395 iowrite32(addr, hw->hw_addr + REG_SPI_ADDR);
396
397 value = SPI_FLASH_CTRL_WAIT_READY |
398 (CUSTOM_SPI_CS_SETUP & SPI_FLASH_CTRL_CS_SETUP_MASK) <<
399 SPI_FLASH_CTRL_CS_SETUP_SHIFT | (CUSTOM_SPI_CLK_HI &
400 SPI_FLASH_CTRL_CLK_HI_MASK) <<
401 SPI_FLASH_CTRL_CLK_HI_SHIFT | (CUSTOM_SPI_CLK_LO &
402 SPI_FLASH_CTRL_CLK_LO_MASK) <<
403 SPI_FLASH_CTRL_CLK_LO_SHIFT | (CUSTOM_SPI_CS_HOLD &
404 SPI_FLASH_CTRL_CS_HOLD_MASK) <<
405 SPI_FLASH_CTRL_CS_HOLD_SHIFT | (CUSTOM_SPI_CS_HI &
406 SPI_FLASH_CTRL_CS_HI_MASK) <<
407 SPI_FLASH_CTRL_CS_HI_SHIFT | (1 & SPI_FLASH_CTRL_INS_MASK) <<
408 SPI_FLASH_CTRL_INS_SHIFT;
409
410 iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL);
411
412 value |= SPI_FLASH_CTRL_START;
413 iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL);
414 ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL);
415
416 for (i = 0; i < 10; i++) {
417 msleep(1);
418 value = ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL);
419 if (!(value & SPI_FLASH_CTRL_START))
420 break;
421 }
422
423 if (value & SPI_FLASH_CTRL_START)
424 return false;
425
426 *buf = ioread32(hw->hw_addr + REG_SPI_DATA);
427
428 return true;
429 }
430
431 /*
432 * get_permanent_address
433 * return 0 if get valid mac address,
434 */
435 static int atl1_get_permanent_address(struct atl1_hw *hw)
436 {
437 u32 addr[2];
438 u32 i, control;
439 u16 reg;
440 u8 eth_addr[ETH_ALEN];
441 bool key_valid;
442
443 if (is_valid_ether_addr(hw->perm_mac_addr))
444 return 0;
445
446 /* init */
447 addr[0] = addr[1] = 0;
448
449 if (!atl1_check_eeprom_exist(hw)) {
450 reg = 0;
451 key_valid = false;
452 /* Read out all EEPROM content */
453 i = 0;
454 while (1) {
455 if (atl1_read_eeprom(hw, i + 0x100, &control)) {
456 if (key_valid) {
457 if (reg == REG_MAC_STA_ADDR)
458 addr[0] = control;
459 else if (reg == (REG_MAC_STA_ADDR + 4))
460 addr[1] = control;
461 key_valid = false;
462 } else if ((control & 0xff) == 0x5A) {
463 key_valid = true;
464 reg = (u16) (control >> 16);
465 } else
466 break;
467 } else
468 /* read error */
469 break;
470 i += 4;
471 }
472
473 *(u32 *) &eth_addr[2] = swab32(addr[0]);
474 *(u16 *) &eth_addr[0] = swab16(*(u16 *) &addr[1]);
475 if (is_valid_ether_addr(eth_addr)) {
476 memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
477 return 0;
478 }
479 }
480
481 /* see if SPI FLAGS exist ? */
482 addr[0] = addr[1] = 0;
483 reg = 0;
484 key_valid = false;
485 i = 0;
486 while (1) {
487 if (atl1_spi_read(hw, i + 0x1f000, &control)) {
488 if (key_valid) {
489 if (reg == REG_MAC_STA_ADDR)
490 addr[0] = control;
491 else if (reg == (REG_MAC_STA_ADDR + 4))
492 addr[1] = control;
493 key_valid = false;
494 } else if ((control & 0xff) == 0x5A) {
495 key_valid = true;
496 reg = (u16) (control >> 16);
497 } else
498 /* data end */
499 break;
500 } else
501 /* read error */
502 break;
503 i += 4;
504 }
505
506 *(u32 *) &eth_addr[2] = swab32(addr[0]);
507 *(u16 *) &eth_addr[0] = swab16(*(u16 *) &addr[1]);
508 if (is_valid_ether_addr(eth_addr)) {
509 memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
510 return 0;
511 }
512
513 /*
514 * On some motherboards, the MAC address is written by the
515 * BIOS directly to the MAC register during POST, and is
516 * not stored in eeprom. If all else thus far has failed
517 * to fetch the permanent MAC address, try reading it directly.
518 */
519 addr[0] = ioread32(hw->hw_addr + REG_MAC_STA_ADDR);
520 addr[1] = ioread16(hw->hw_addr + (REG_MAC_STA_ADDR + 4));
521 *(u32 *) &eth_addr[2] = swab32(addr[0]);
522 *(u16 *) &eth_addr[0] = swab16(*(u16 *) &addr[1]);
523 if (is_valid_ether_addr(eth_addr)) {
524 memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
525 return 0;
526 }
527
528 return 1;
529 }
530
531 /*
532 * Reads the adapter's MAC address from the EEPROM
533 * hw - Struct containing variables accessed by shared code
534 */
535 static s32 atl1_read_mac_addr(struct atl1_hw *hw)
536 {
537 u16 i;
538
539 if (atl1_get_permanent_address(hw))
540 random_ether_addr(hw->perm_mac_addr);
541
542 for (i = 0; i < ETH_ALEN; i++)
543 hw->mac_addr[i] = hw->perm_mac_addr[i];
544 return 0;
545 }
546
547 /*
548 * Hashes an address to determine its location in the multicast table
549 * hw - Struct containing variables accessed by shared code
550 * mc_addr - the multicast address to hash
551 *
552 * atl1_hash_mc_addr
553 * purpose
554 * set hash value for a multicast address
555 * hash calcu processing :
556 * 1. calcu 32bit CRC for multicast address
557 * 2. reverse crc with MSB to LSB
558 */
559 static u32 atl1_hash_mc_addr(struct atl1_hw *hw, u8 *mc_addr)
560 {
561 u32 crc32, value = 0;
562 int i;
563
564 crc32 = ether_crc_le(6, mc_addr);
565 for (i = 0; i < 32; i++)
566 value |= (((crc32 >> i) & 1) << (31 - i));
567
568 return value;
569 }
570
571 /*
572 * Sets the bit in the multicast table corresponding to the hash value.
573 * hw - Struct containing variables accessed by shared code
574 * hash_value - Multicast address hash value
575 */
576 static void atl1_hash_set(struct atl1_hw *hw, u32 hash_value)
577 {
578 u32 hash_bit, hash_reg;
579 u32 mta;
580
581 /*
582 * The HASH Table is a register array of 2 32-bit registers.
583 * It is treated like an array of 64 bits. We want to set
584 * bit BitArray[hash_value]. So we figure out what register
585 * the bit is in, read it, OR in the new bit, then write
586 * back the new value. The register is determined by the
587 * upper 7 bits of the hash value and the bit within that
588 * register are determined by the lower 5 bits of the value.
589 */
590 hash_reg = (hash_value >> 31) & 0x1;
591 hash_bit = (hash_value >> 26) & 0x1F;
592 mta = ioread32((hw->hw_addr + REG_RX_HASH_TABLE) + (hash_reg << 2));
593 mta |= (1 << hash_bit);
594 iowrite32(mta, (hw->hw_addr + REG_RX_HASH_TABLE) + (hash_reg << 2));
595 }
596
597 /*
598 * Writes a value to a PHY register
599 * hw - Struct containing variables accessed by shared code
600 * reg_addr - address of the PHY register to write
601 * data - data to write to the PHY
602 */
603 static s32 atl1_write_phy_reg(struct atl1_hw *hw, u32 reg_addr, u16 phy_data)
604 {
605 int i;
606 u32 val;
607
608 val = ((u32) (phy_data & MDIO_DATA_MASK)) << MDIO_DATA_SHIFT |
609 (reg_addr & MDIO_REG_ADDR_MASK) << MDIO_REG_ADDR_SHIFT |
610 MDIO_SUP_PREAMBLE |
611 MDIO_START | MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
612 iowrite32(val, hw->hw_addr + REG_MDIO_CTRL);
613 ioread32(hw->hw_addr + REG_MDIO_CTRL);
614
615 for (i = 0; i < MDIO_WAIT_TIMES; i++) {
616 udelay(2);
617 val = ioread32(hw->hw_addr + REG_MDIO_CTRL);
618 if (!(val & (MDIO_START | MDIO_BUSY)))
619 break;
620 }
621
622 if (!(val & (MDIO_START | MDIO_BUSY)))
623 return 0;
624
625 return ATLX_ERR_PHY;
626 }
627
628 /*
629 * Make L001's PHY out of Power Saving State (bug)
630 * hw - Struct containing variables accessed by shared code
631 * when power on, L001's PHY always on Power saving State
632 * (Gigabit Link forbidden)
633 */
634 static s32 atl1_phy_leave_power_saving(struct atl1_hw *hw)
635 {
636 s32 ret;
637 ret = atl1_write_phy_reg(hw, 29, 0x0029);
638 if (ret)
639 return ret;
640 return atl1_write_phy_reg(hw, 30, 0);
641 }
642
643 /*
644 * Resets the PHY and make all config validate
645 * hw - Struct containing variables accessed by shared code
646 *
647 * Sets bit 15 and 12 of the MII Control regiser (for F001 bug)
648 */
649 static s32 atl1_phy_reset(struct atl1_hw *hw)
650 {
651 struct pci_dev *pdev = hw->back->pdev;
652 struct atl1_adapter *adapter = hw->back;
653 s32 ret_val;
654 u16 phy_data;
655
656 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
657 hw->media_type == MEDIA_TYPE_1000M_FULL)
658 phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN;
659 else {
660 switch (hw->media_type) {
661 case MEDIA_TYPE_100M_FULL:
662 phy_data =
663 MII_CR_FULL_DUPLEX | MII_CR_SPEED_100 |
664 MII_CR_RESET;
665 break;
666 case MEDIA_TYPE_100M_HALF:
667 phy_data = MII_CR_SPEED_100 | MII_CR_RESET;
668 break;
669 case MEDIA_TYPE_10M_FULL:
670 phy_data =
671 MII_CR_FULL_DUPLEX | MII_CR_SPEED_10 | MII_CR_RESET;
672 break;
673 default:
674 /* MEDIA_TYPE_10M_HALF: */
675 phy_data = MII_CR_SPEED_10 | MII_CR_RESET;
676 break;
677 }
678 }
679
680 ret_val = atl1_write_phy_reg(hw, MII_BMCR, phy_data);
681 if (ret_val) {
682 u32 val;
683 int i;
684 /* pcie serdes link may be down! */
685 if (netif_msg_hw(adapter))
686 dev_dbg(&pdev->dev, "pcie phy link down\n");
687
688 for (i = 0; i < 25; i++) {
689 msleep(1);
690 val = ioread32(hw->hw_addr + REG_MDIO_CTRL);
691 if (!(val & (MDIO_START | MDIO_BUSY)))
692 break;
693 }
694
695 if ((val & (MDIO_START | MDIO_BUSY)) != 0) {
696 if (netif_msg_hw(adapter))
697 dev_warn(&pdev->dev,
698 "pcie link down at least 25ms\n");
699 return ret_val;
700 }
701 }
702 return 0;
703 }
704
705 /*
706 * Configures PHY autoneg and flow control advertisement settings
707 * hw - Struct containing variables accessed by shared code
708 */
709 static s32 atl1_phy_setup_autoneg_adv(struct atl1_hw *hw)
710 {
711 s32 ret_val;
712 s16 mii_autoneg_adv_reg;
713 s16 mii_1000t_ctrl_reg;
714
715 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
716 mii_autoneg_adv_reg = MII_AR_DEFAULT_CAP_MASK;
717
718 /* Read the MII 1000Base-T Control Register (Address 9). */
719 mii_1000t_ctrl_reg = MII_ATLX_CR_1000T_DEFAULT_CAP_MASK;
720
721 /*
722 * First we clear all the 10/100 mb speed bits in the Auto-Neg
723 * Advertisement Register (Address 4) and the 1000 mb speed bits in
724 * the 1000Base-T Control Register (Address 9).
725 */
726 mii_autoneg_adv_reg &= ~MII_AR_SPEED_MASK;
727 mii_1000t_ctrl_reg &= ~MII_ATLX_CR_1000T_SPEED_MASK;
728
729 /*
730 * Need to parse media_type and set up
731 * the appropriate PHY registers.
732 */
733 switch (hw->media_type) {
734 case MEDIA_TYPE_AUTO_SENSOR:
735 mii_autoneg_adv_reg |= (MII_AR_10T_HD_CAPS |
736 MII_AR_10T_FD_CAPS |
737 MII_AR_100TX_HD_CAPS |
738 MII_AR_100TX_FD_CAPS);
739 mii_1000t_ctrl_reg |= MII_ATLX_CR_1000T_FD_CAPS;
740 break;
741
742 case MEDIA_TYPE_1000M_FULL:
743 mii_1000t_ctrl_reg |= MII_ATLX_CR_1000T_FD_CAPS;
744 break;
745
746 case MEDIA_TYPE_100M_FULL:
747 mii_autoneg_adv_reg |= MII_AR_100TX_FD_CAPS;
748 break;
749
750 case MEDIA_TYPE_100M_HALF:
751 mii_autoneg_adv_reg |= MII_AR_100TX_HD_CAPS;
752 break;
753
754 case MEDIA_TYPE_10M_FULL:
755 mii_autoneg_adv_reg |= MII_AR_10T_FD_CAPS;
756 break;
757
758 default:
759 mii_autoneg_adv_reg |= MII_AR_10T_HD_CAPS;
760 break;
761 }
762
763 /* flow control fixed to enable all */
764 mii_autoneg_adv_reg |= (MII_AR_ASM_DIR | MII_AR_PAUSE);
765
766 hw->mii_autoneg_adv_reg = mii_autoneg_adv_reg;
767 hw->mii_1000t_ctrl_reg = mii_1000t_ctrl_reg;
768
769 ret_val = atl1_write_phy_reg(hw, MII_ADVERTISE, mii_autoneg_adv_reg);
770 if (ret_val)
771 return ret_val;
772
773 ret_val = atl1_write_phy_reg(hw, MII_ATLX_CR, mii_1000t_ctrl_reg);
774 if (ret_val)
775 return ret_val;
776
777 return 0;
778 }
779
780 /*
781 * Configures link settings.
782 * hw - Struct containing variables accessed by shared code
783 * Assumes the hardware has previously been reset and the
784 * transmitter and receiver are not enabled.
785 */
786 static s32 atl1_setup_link(struct atl1_hw *hw)
787 {
788 struct pci_dev *pdev = hw->back->pdev;
789 struct atl1_adapter *adapter = hw->back;
790 s32 ret_val;
791
792 /*
793 * Options:
794 * PHY will advertise value(s) parsed from
795 * autoneg_advertised and fc
796 * no matter what autoneg is , We will not wait link result.
797 */
798 ret_val = atl1_phy_setup_autoneg_adv(hw);
799 if (ret_val) {
800 if (netif_msg_link(adapter))
801 dev_dbg(&pdev->dev,
802 "error setting up autonegotiation\n");
803 return ret_val;
804 }
805 /* SW.Reset , En-Auto-Neg if needed */
806 ret_val = atl1_phy_reset(hw);
807 if (ret_val) {
808 if (netif_msg_link(adapter))
809 dev_dbg(&pdev->dev, "error resetting phy\n");
810 return ret_val;
811 }
812 hw->phy_configured = true;
813 return ret_val;
814 }
815
816 static void atl1_init_flash_opcode(struct atl1_hw *hw)
817 {
818 if (hw->flash_vendor >= ARRAY_SIZE(flash_table))
819 /* Atmel */
820 hw->flash_vendor = 0;
821
822 /* Init OP table */
823 iowrite8(flash_table[hw->flash_vendor].cmd_program,
824 hw->hw_addr + REG_SPI_FLASH_OP_PROGRAM);
825 iowrite8(flash_table[hw->flash_vendor].cmd_sector_erase,
826 hw->hw_addr + REG_SPI_FLASH_OP_SC_ERASE);
827 iowrite8(flash_table[hw->flash_vendor].cmd_chip_erase,
828 hw->hw_addr + REG_SPI_FLASH_OP_CHIP_ERASE);
829 iowrite8(flash_table[hw->flash_vendor].cmd_rdid,
830 hw->hw_addr + REG_SPI_FLASH_OP_RDID);
831 iowrite8(flash_table[hw->flash_vendor].cmd_wren,
832 hw->hw_addr + REG_SPI_FLASH_OP_WREN);
833 iowrite8(flash_table[hw->flash_vendor].cmd_rdsr,
834 hw->hw_addr + REG_SPI_FLASH_OP_RDSR);
835 iowrite8(flash_table[hw->flash_vendor].cmd_wrsr,
836 hw->hw_addr + REG_SPI_FLASH_OP_WRSR);
837 iowrite8(flash_table[hw->flash_vendor].cmd_read,
838 hw->hw_addr + REG_SPI_FLASH_OP_READ);
839 }
840
841 /*
842 * Performs basic configuration of the adapter.
843 * hw - Struct containing variables accessed by shared code
844 * Assumes that the controller has previously been reset and is in a
845 * post-reset uninitialized state. Initializes multicast table,
846 * and Calls routines to setup link
847 * Leaves the transmit and receive units disabled and uninitialized.
848 */
849 static s32 atl1_init_hw(struct atl1_hw *hw)
850 {
851 u32 ret_val = 0;
852
853 /* Zero out the Multicast HASH table */
854 iowrite32(0, hw->hw_addr + REG_RX_HASH_TABLE);
855 /* clear the old settings from the multicast hash table */
856 iowrite32(0, (hw->hw_addr + REG_RX_HASH_TABLE) + (1 << 2));
857
858 atl1_init_flash_opcode(hw);
859
860 if (!hw->phy_configured) {
861 /* enable GPHY LinkChange Interrupt */
862 ret_val = atl1_write_phy_reg(hw, 18, 0xC00);
863 if (ret_val)
864 return ret_val;
865 /* make PHY out of power-saving state */
866 ret_val = atl1_phy_leave_power_saving(hw);
867 if (ret_val)
868 return ret_val;
869 /* Call a subroutine to configure the link */
870 ret_val = atl1_setup_link(hw);
871 }
872 return ret_val;
873 }
874
875 /*
876 * Detects the current speed and duplex settings of the hardware.
877 * hw - Struct containing variables accessed by shared code
878 * speed - Speed of the connection
879 * duplex - Duplex setting of the connection
880 */
881 static s32 atl1_get_speed_and_duplex(struct atl1_hw *hw, u16 *speed, u16 *duplex)
882 {
883 struct pci_dev *pdev = hw->back->pdev;
884 struct atl1_adapter *adapter = hw->back;
885 s32 ret_val;
886 u16 phy_data;
887
888 /* ; --- Read PHY Specific Status Register (17) */
889 ret_val = atl1_read_phy_reg(hw, MII_ATLX_PSSR, &phy_data);
890 if (ret_val)
891 return ret_val;
892
893 if (!(phy_data & MII_ATLX_PSSR_SPD_DPLX_RESOLVED))
894 return ATLX_ERR_PHY_RES;
895
896 switch (phy_data & MII_ATLX_PSSR_SPEED) {
897 case MII_ATLX_PSSR_1000MBS:
898 *speed = SPEED_1000;
899 break;
900 case MII_ATLX_PSSR_100MBS:
901 *speed = SPEED_100;
902 break;
903 case MII_ATLX_PSSR_10MBS:
904 *speed = SPEED_10;
905 break;
906 default:
907 if (netif_msg_hw(adapter))
908 dev_dbg(&pdev->dev, "error getting speed\n");
909 return ATLX_ERR_PHY_SPEED;
910 break;
911 }
912 if (phy_data & MII_ATLX_PSSR_DPLX)
913 *duplex = FULL_DUPLEX;
914 else
915 *duplex = HALF_DUPLEX;
916
917 return 0;
918 }
919
920 static void atl1_set_mac_addr(struct atl1_hw *hw)
921 {
922 u32 value;
923 /*
924 * 00-0B-6A-F6-00-DC
925 * 0: 6AF600DC 1: 000B
926 * low dword
927 */
928 value = (((u32) hw->mac_addr[2]) << 24) |
929 (((u32) hw->mac_addr[3]) << 16) |
930 (((u32) hw->mac_addr[4]) << 8) | (((u32) hw->mac_addr[5]));
931 iowrite32(value, hw->hw_addr + REG_MAC_STA_ADDR);
932 /* high dword */
933 value = (((u32) hw->mac_addr[0]) << 8) | (((u32) hw->mac_addr[1]));
934 iowrite32(value, (hw->hw_addr + REG_MAC_STA_ADDR) + (1 << 2));
935 }
936
937 /*
938 * atl1_sw_init - Initialize general software structures (struct atl1_adapter)
939 * @adapter: board private structure to initialize
940 *
941 * atl1_sw_init initializes the Adapter private data structure.
942 * Fields are initialized based on PCI device information and
943 * OS network device settings (MTU size).
944 */
945 static int __devinit atl1_sw_init(struct atl1_adapter *adapter)
946 {
947 struct atl1_hw *hw = &adapter->hw;
948 struct net_device *netdev = adapter->netdev;
949
950 hw->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
951 hw->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
952
953 adapter->wol = 0;
954 device_set_wakeup_enable(&adapter->pdev->dev, false);
955 adapter->rx_buffer_len = (hw->max_frame_size + 7) & ~7;
956 adapter->ict = 50000; /* 100ms */
957 adapter->link_speed = SPEED_0; /* hardware init */
958 adapter->link_duplex = FULL_DUPLEX;
959
960 hw->phy_configured = false;
961 hw->preamble_len = 7;
962 hw->ipgt = 0x60;
963 hw->min_ifg = 0x50;
964 hw->ipgr1 = 0x40;
965 hw->ipgr2 = 0x60;
966 hw->max_retry = 0xf;
967 hw->lcol = 0x37;
968 hw->jam_ipg = 7;
969 hw->rfd_burst = 8;
970 hw->rrd_burst = 8;
971 hw->rfd_fetch_gap = 1;
972 hw->rx_jumbo_th = adapter->rx_buffer_len / 8;
973 hw->rx_jumbo_lkah = 1;
974 hw->rrd_ret_timer = 16;
975 hw->tpd_burst = 4;
976 hw->tpd_fetch_th = 16;
977 hw->txf_burst = 0x100;
978 hw->tx_jumbo_task_th = (hw->max_frame_size + 7) >> 3;
979 hw->tpd_fetch_gap = 1;
980 hw->rcb_value = atl1_rcb_64;
981 hw->dma_ord = atl1_dma_ord_enh;
982 hw->dmar_block = atl1_dma_req_256;
983 hw->dmaw_block = atl1_dma_req_256;
984 hw->cmb_rrd = 4;
985 hw->cmb_tpd = 4;
986 hw->cmb_rx_timer = 1; /* about 2us */
987 hw->cmb_tx_timer = 1; /* about 2us */
988 hw->smb_timer = 100000; /* about 200ms */
989
990 spin_lock_init(&adapter->lock);
991 spin_lock_init(&adapter->mb_lock);
992
993 return 0;
994 }
995
996 static int mdio_read(struct net_device *netdev, int phy_id, int reg_num)
997 {
998 struct atl1_adapter *adapter = netdev_priv(netdev);
999 u16 result;
1000
1001 atl1_read_phy_reg(&adapter->hw, reg_num & 0x1f, &result);
1002
1003 return result;
1004 }
1005
1006 static void mdio_write(struct net_device *netdev, int phy_id, int reg_num,
1007 int val)
1008 {
1009 struct atl1_adapter *adapter = netdev_priv(netdev);
1010
1011 atl1_write_phy_reg(&adapter->hw, reg_num, val);
1012 }
1013
1014 /*
1015 * atl1_mii_ioctl -
1016 * @netdev:
1017 * @ifreq:
1018 * @cmd:
1019 */
1020 static int atl1_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
1021 {
1022 struct atl1_adapter *adapter = netdev_priv(netdev);
1023 unsigned long flags;
1024 int retval;
1025
1026 if (!netif_running(netdev))
1027 return -EINVAL;
1028
1029 spin_lock_irqsave(&adapter->lock, flags);
1030 retval = generic_mii_ioctl(&adapter->mii, if_mii(ifr), cmd, NULL);
1031 spin_unlock_irqrestore(&adapter->lock, flags);
1032
1033 return retval;
1034 }
1035
1036 /*
1037 * atl1_setup_mem_resources - allocate Tx / RX descriptor resources
1038 * @adapter: board private structure
1039 *
1040 * Return 0 on success, negative on failure
1041 */
1042 static s32 atl1_setup_ring_resources(struct atl1_adapter *adapter)
1043 {
1044 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
1045 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
1046 struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring;
1047 struct atl1_ring_header *ring_header = &adapter->ring_header;
1048 struct pci_dev *pdev = adapter->pdev;
1049 int size;
1050 u8 offset = 0;
1051
1052 size = sizeof(struct atl1_buffer) * (tpd_ring->count + rfd_ring->count);
1053 tpd_ring->buffer_info = kzalloc(size, GFP_KERNEL);
1054 if (unlikely(!tpd_ring->buffer_info)) {
1055 if (netif_msg_drv(adapter))
1056 dev_err(&pdev->dev, "kzalloc failed , size = D%d\n",
1057 size);
1058 goto err_nomem;
1059 }
1060 rfd_ring->buffer_info =
1061 (struct atl1_buffer *)(tpd_ring->buffer_info + tpd_ring->count);
1062
1063 /*
1064 * real ring DMA buffer
1065 * each ring/block may need up to 8 bytes for alignment, hence the
1066 * additional 40 bytes tacked onto the end.
1067 */
1068 ring_header->size = size =
1069 sizeof(struct tx_packet_desc) * tpd_ring->count
1070 + sizeof(struct rx_free_desc) * rfd_ring->count
1071 + sizeof(struct rx_return_desc) * rrd_ring->count
1072 + sizeof(struct coals_msg_block)
1073 + sizeof(struct stats_msg_block)
1074 + 40;
1075
1076 ring_header->desc = pci_alloc_consistent(pdev, ring_header->size,
1077 &ring_header->dma);
1078 if (unlikely(!ring_header->desc)) {
1079 if (netif_msg_drv(adapter))
1080 dev_err(&pdev->dev, "pci_alloc_consistent failed\n");
1081 goto err_nomem;
1082 }
1083
1084 memset(ring_header->desc, 0, ring_header->size);
1085
1086 /* init TPD ring */
1087 tpd_ring->dma = ring_header->dma;
1088 offset = (tpd_ring->dma & 0x7) ? (8 - (ring_header->dma & 0x7)) : 0;
1089 tpd_ring->dma += offset;
1090 tpd_ring->desc = (u8 *) ring_header->desc + offset;
1091 tpd_ring->size = sizeof(struct tx_packet_desc) * tpd_ring->count;
1092
1093 /* init RFD ring */
1094 rfd_ring->dma = tpd_ring->dma + tpd_ring->size;
1095 offset = (rfd_ring->dma & 0x7) ? (8 - (rfd_ring->dma & 0x7)) : 0;
1096 rfd_ring->dma += offset;
1097 rfd_ring->desc = (u8 *) tpd_ring->desc + (tpd_ring->size + offset);
1098 rfd_ring->size = sizeof(struct rx_free_desc) * rfd_ring->count;
1099
1100
1101 /* init RRD ring */
1102 rrd_ring->dma = rfd_ring->dma + rfd_ring->size;
1103 offset = (rrd_ring->dma & 0x7) ? (8 - (rrd_ring->dma & 0x7)) : 0;
1104 rrd_ring->dma += offset;
1105 rrd_ring->desc = (u8 *) rfd_ring->desc + (rfd_ring->size + offset);
1106 rrd_ring->size = sizeof(struct rx_return_desc) * rrd_ring->count;
1107
1108
1109 /* init CMB */
1110 adapter->cmb.dma = rrd_ring->dma + rrd_ring->size;
1111 offset = (adapter->cmb.dma & 0x7) ? (8 - (adapter->cmb.dma & 0x7)) : 0;
1112 adapter->cmb.dma += offset;
1113 adapter->cmb.cmb = (struct coals_msg_block *)
1114 ((u8 *) rrd_ring->desc + (rrd_ring->size + offset));
1115
1116 /* init SMB */
1117 adapter->smb.dma = adapter->cmb.dma + sizeof(struct coals_msg_block);
1118 offset = (adapter->smb.dma & 0x7) ? (8 - (adapter->smb.dma & 0x7)) : 0;
1119 adapter->smb.dma += offset;
1120 adapter->smb.smb = (struct stats_msg_block *)
1121 ((u8 *) adapter->cmb.cmb +
1122 (sizeof(struct coals_msg_block) + offset));
1123
1124 return 0;
1125
1126 err_nomem:
1127 kfree(tpd_ring->buffer_info);
1128 return -ENOMEM;
1129 }
1130
1131 static void atl1_init_ring_ptrs(struct atl1_adapter *adapter)
1132 {
1133 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
1134 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
1135 struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring;
1136
1137 atomic_set(&tpd_ring->next_to_use, 0);
1138 atomic_set(&tpd_ring->next_to_clean, 0);
1139
1140 rfd_ring->next_to_clean = 0;
1141 atomic_set(&rfd_ring->next_to_use, 0);
1142
1143 rrd_ring->next_to_use = 0;
1144 atomic_set(&rrd_ring->next_to_clean, 0);
1145 }
1146
1147 /*
1148 * atl1_clean_rx_ring - Free RFD Buffers
1149 * @adapter: board private structure
1150 */
1151 static void atl1_clean_rx_ring(struct atl1_adapter *adapter)
1152 {
1153 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
1154 struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring;
1155 struct atl1_buffer *buffer_info;
1156 struct pci_dev *pdev = adapter->pdev;
1157 unsigned long size;
1158 unsigned int i;
1159
1160 /* Free all the Rx ring sk_buffs */
1161 for (i = 0; i < rfd_ring->count; i++) {
1162 buffer_info = &rfd_ring->buffer_info[i];
1163 if (buffer_info->dma) {
1164 pci_unmap_page(pdev, buffer_info->dma,
1165 buffer_info->length, PCI_DMA_FROMDEVICE);
1166 buffer_info->dma = 0;
1167 }
1168 if (buffer_info->skb) {
1169 dev_kfree_skb(buffer_info->skb);
1170 buffer_info->skb = NULL;
1171 }
1172 }
1173
1174 size = sizeof(struct atl1_buffer) * rfd_ring->count;
1175 memset(rfd_ring->buffer_info, 0, size);
1176
1177 /* Zero out the descriptor ring */
1178 memset(rfd_ring->desc, 0, rfd_ring->size);
1179
1180 rfd_ring->next_to_clean = 0;
1181 atomic_set(&rfd_ring->next_to_use, 0);
1182
1183 rrd_ring->next_to_use = 0;
1184 atomic_set(&rrd_ring->next_to_clean, 0);
1185 }
1186
1187 /*
1188 * atl1_clean_tx_ring - Free Tx Buffers
1189 * @adapter: board private structure
1190 */
1191 static void atl1_clean_tx_ring(struct atl1_adapter *adapter)
1192 {
1193 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
1194 struct atl1_buffer *buffer_info;
1195 struct pci_dev *pdev = adapter->pdev;
1196 unsigned long size;
1197 unsigned int i;
1198
1199 /* Free all the Tx ring sk_buffs */
1200 for (i = 0; i < tpd_ring->count; i++) {
1201 buffer_info = &tpd_ring->buffer_info[i];
1202 if (buffer_info->dma) {
1203 pci_unmap_page(pdev, buffer_info->dma,
1204 buffer_info->length, PCI_DMA_TODEVICE);
1205 buffer_info->dma = 0;
1206 }
1207 }
1208
1209 for (i = 0; i < tpd_ring->count; i++) {
1210 buffer_info = &tpd_ring->buffer_info[i];
1211 if (buffer_info->skb) {
1212 dev_kfree_skb_any(buffer_info->skb);
1213 buffer_info->skb = NULL;
1214 }
1215 }
1216
1217 size = sizeof(struct atl1_buffer) * tpd_ring->count;
1218 memset(tpd_ring->buffer_info, 0, size);
1219
1220 /* Zero out the descriptor ring */
1221 memset(tpd_ring->desc, 0, tpd_ring->size);
1222
1223 atomic_set(&tpd_ring->next_to_use, 0);
1224 atomic_set(&tpd_ring->next_to_clean, 0);
1225 }
1226
1227 /*
1228 * atl1_free_ring_resources - Free Tx / RX descriptor Resources
1229 * @adapter: board private structure
1230 *
1231 * Free all transmit software resources
1232 */
1233 static void atl1_free_ring_resources(struct atl1_adapter *adapter)
1234 {
1235 struct pci_dev *pdev = adapter->pdev;
1236 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
1237 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
1238 struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring;
1239 struct atl1_ring_header *ring_header = &adapter->ring_header;
1240
1241 atl1_clean_tx_ring(adapter);
1242 atl1_clean_rx_ring(adapter);
1243
1244 kfree(tpd_ring->buffer_info);
1245 pci_free_consistent(pdev, ring_header->size, ring_header->desc,
1246 ring_header->dma);
1247
1248 tpd_ring->buffer_info = NULL;
1249 tpd_ring->desc = NULL;
1250 tpd_ring->dma = 0;
1251
1252 rfd_ring->buffer_info = NULL;
1253 rfd_ring->desc = NULL;
1254 rfd_ring->dma = 0;
1255
1256 rrd_ring->desc = NULL;
1257 rrd_ring->dma = 0;
1258
1259 adapter->cmb.dma = 0;
1260 adapter->cmb.cmb = NULL;
1261
1262 adapter->smb.dma = 0;
1263 adapter->smb.smb = NULL;
1264 }
1265
1266 static void atl1_setup_mac_ctrl(struct atl1_adapter *adapter)
1267 {
1268 u32 value;
1269 struct atl1_hw *hw = &adapter->hw;
1270 struct net_device *netdev = adapter->netdev;
1271 /* Config MAC CTRL Register */
1272 value = MAC_CTRL_TX_EN | MAC_CTRL_RX_EN;
1273 /* duplex */
1274 if (FULL_DUPLEX == adapter->link_duplex)
1275 value |= MAC_CTRL_DUPLX;
1276 /* speed */
1277 value |= ((u32) ((SPEED_1000 == adapter->link_speed) ?
1278 MAC_CTRL_SPEED_1000 : MAC_CTRL_SPEED_10_100) <<
1279 MAC_CTRL_SPEED_SHIFT);
1280 /* flow control */
1281 value |= (MAC_CTRL_TX_FLOW | MAC_CTRL_RX_FLOW);
1282 /* PAD & CRC */
1283 value |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD);
1284 /* preamble length */
1285 value |= (((u32) adapter->hw.preamble_len
1286 & MAC_CTRL_PRMLEN_MASK) << MAC_CTRL_PRMLEN_SHIFT);
1287 /* vlan */
1288 __atlx_vlan_mode(netdev->features, &value);
1289 /* rx checksum
1290 if (adapter->rx_csum)
1291 value |= MAC_CTRL_RX_CHKSUM_EN;
1292 */
1293 /* filter mode */
1294 value |= MAC_CTRL_BC_EN;
1295 if (netdev->flags & IFF_PROMISC)
1296 value |= MAC_CTRL_PROMIS_EN;
1297 else if (netdev->flags & IFF_ALLMULTI)
1298 value |= MAC_CTRL_MC_ALL_EN;
1299 /* value |= MAC_CTRL_LOOPBACK; */
1300 iowrite32(value, hw->hw_addr + REG_MAC_CTRL);
1301 }
1302
1303 static u32 atl1_check_link(struct atl1_adapter *adapter)
1304 {
1305 struct atl1_hw *hw = &adapter->hw;
1306 struct net_device *netdev = adapter->netdev;
1307 u32 ret_val;
1308 u16 speed, duplex, phy_data;
1309 int reconfig = 0;
1310
1311 /* MII_BMSR must read twice */
1312 atl1_read_phy_reg(hw, MII_BMSR, &phy_data);
1313 atl1_read_phy_reg(hw, MII_BMSR, &phy_data);
1314 if (!(phy_data & BMSR_LSTATUS)) {
1315 /* link down */
1316 if (netif_carrier_ok(netdev)) {
1317 /* old link state: Up */
1318 if (netif_msg_link(adapter))
1319 dev_info(&adapter->pdev->dev, "link is down\n");
1320 adapter->link_speed = SPEED_0;
1321 netif_carrier_off(netdev);
1322 }
1323 return 0;
1324 }
1325
1326 /* Link Up */
1327 ret_val = atl1_get_speed_and_duplex(hw, &speed, &duplex);
1328 if (ret_val)
1329 return ret_val;
1330
1331 switch (hw->media_type) {
1332 case MEDIA_TYPE_1000M_FULL:
1333 if (speed != SPEED_1000 || duplex != FULL_DUPLEX)
1334 reconfig = 1;
1335 break;
1336 case MEDIA_TYPE_100M_FULL:
1337 if (speed != SPEED_100 || duplex != FULL_DUPLEX)
1338 reconfig = 1;
1339 break;
1340 case MEDIA_TYPE_100M_HALF:
1341 if (speed != SPEED_100 || duplex != HALF_DUPLEX)
1342 reconfig = 1;
1343 break;
1344 case MEDIA_TYPE_10M_FULL:
1345 if (speed != SPEED_10 || duplex != FULL_DUPLEX)
1346 reconfig = 1;
1347 break;
1348 case MEDIA_TYPE_10M_HALF:
1349 if (speed != SPEED_10 || duplex != HALF_DUPLEX)
1350 reconfig = 1;
1351 break;
1352 }
1353
1354 /* link result is our setting */
1355 if (!reconfig) {
1356 if (adapter->link_speed != speed ||
1357 adapter->link_duplex != duplex) {
1358 adapter->link_speed = speed;
1359 adapter->link_duplex = duplex;
1360 atl1_setup_mac_ctrl(adapter);
1361 if (netif_msg_link(adapter))
1362 dev_info(&adapter->pdev->dev,
1363 "%s link is up %d Mbps %s\n",
1364 netdev->name, adapter->link_speed,
1365 adapter->link_duplex == FULL_DUPLEX ?
1366 "full duplex" : "half duplex");
1367 }
1368 if (!netif_carrier_ok(netdev)) {
1369 /* Link down -> Up */
1370 netif_carrier_on(netdev);
1371 }
1372 return 0;
1373 }
1374
1375 /* change original link status */
1376 if (netif_carrier_ok(netdev)) {
1377 adapter->link_speed = SPEED_0;
1378 netif_carrier_off(netdev);
1379 netif_stop_queue(netdev);
1380 }
1381
1382 if (hw->media_type != MEDIA_TYPE_AUTO_SENSOR &&
1383 hw->media_type != MEDIA_TYPE_1000M_FULL) {
1384 switch (hw->media_type) {
1385 case MEDIA_TYPE_100M_FULL:
1386 phy_data = MII_CR_FULL_DUPLEX | MII_CR_SPEED_100 |
1387 MII_CR_RESET;
1388 break;
1389 case MEDIA_TYPE_100M_HALF:
1390 phy_data = MII_CR_SPEED_100 | MII_CR_RESET;
1391 break;
1392 case MEDIA_TYPE_10M_FULL:
1393 phy_data =
1394 MII_CR_FULL_DUPLEX | MII_CR_SPEED_10 | MII_CR_RESET;
1395 break;
1396 default:
1397 /* MEDIA_TYPE_10M_HALF: */
1398 phy_data = MII_CR_SPEED_10 | MII_CR_RESET;
1399 break;
1400 }
1401 atl1_write_phy_reg(hw, MII_BMCR, phy_data);
1402 return 0;
1403 }
1404
1405 /* auto-neg, insert timer to re-config phy */
1406 if (!adapter->phy_timer_pending) {
1407 adapter->phy_timer_pending = true;
1408 mod_timer(&adapter->phy_config_timer,
1409 round_jiffies(jiffies + 3 * HZ));
1410 }
1411
1412 return 0;
1413 }
1414
1415 static void set_flow_ctrl_old(struct atl1_adapter *adapter)
1416 {
1417 u32 hi, lo, value;
1418
1419 /* RFD Flow Control */
1420 value = adapter->rfd_ring.count;
1421 hi = value / 16;
1422 if (hi < 2)
1423 hi = 2;
1424 lo = value * 7 / 8;
1425
1426 value = ((hi & RXQ_RXF_PAUSE_TH_HI_MASK) << RXQ_RXF_PAUSE_TH_HI_SHIFT) |
1427 ((lo & RXQ_RXF_PAUSE_TH_LO_MASK) << RXQ_RXF_PAUSE_TH_LO_SHIFT);
1428 iowrite32(value, adapter->hw.hw_addr + REG_RXQ_RXF_PAUSE_THRESH);
1429
1430 /* RRD Flow Control */
1431 value = adapter->rrd_ring.count;
1432 lo = value / 16;
1433 hi = value * 7 / 8;
1434 if (lo < 2)
1435 lo = 2;
1436 value = ((hi & RXQ_RRD_PAUSE_TH_HI_MASK) << RXQ_RRD_PAUSE_TH_HI_SHIFT) |
1437 ((lo & RXQ_RRD_PAUSE_TH_LO_MASK) << RXQ_RRD_PAUSE_TH_LO_SHIFT);
1438 iowrite32(value, adapter->hw.hw_addr + REG_RXQ_RRD_PAUSE_THRESH);
1439 }
1440
1441 static void set_flow_ctrl_new(struct atl1_hw *hw)
1442 {
1443 u32 hi, lo, value;
1444
1445 /* RXF Flow Control */
1446 value = ioread32(hw->hw_addr + REG_SRAM_RXF_LEN);
1447 lo = value / 16;
1448 if (lo < 192)
1449 lo = 192;
1450 hi = value * 7 / 8;
1451 if (hi < lo)
1452 hi = lo + 16;
1453 value = ((hi & RXQ_RXF_PAUSE_TH_HI_MASK) << RXQ_RXF_PAUSE_TH_HI_SHIFT) |
1454 ((lo & RXQ_RXF_PAUSE_TH_LO_MASK) << RXQ_RXF_PAUSE_TH_LO_SHIFT);
1455 iowrite32(value, hw->hw_addr + REG_RXQ_RXF_PAUSE_THRESH);
1456
1457 /* RRD Flow Control */
1458 value = ioread32(hw->hw_addr + REG_SRAM_RRD_LEN);
1459 lo = value / 8;
1460 hi = value * 7 / 8;
1461 if (lo < 2)
1462 lo = 2;
1463 if (hi < lo)
1464 hi = lo + 3;
1465 value = ((hi & RXQ_RRD_PAUSE_TH_HI_MASK) << RXQ_RRD_PAUSE_TH_HI_SHIFT) |
1466 ((lo & RXQ_RRD_PAUSE_TH_LO_MASK) << RXQ_RRD_PAUSE_TH_LO_SHIFT);
1467 iowrite32(value, hw->hw_addr + REG_RXQ_RRD_PAUSE_THRESH);
1468 }
1469
1470 /*
1471 * atl1_configure - Configure Transmit&Receive Unit after Reset
1472 * @adapter: board private structure
1473 *
1474 * Configure the Tx /Rx unit of the MAC after a reset.
1475 */
1476 static u32 atl1_configure(struct atl1_adapter *adapter)
1477 {
1478 struct atl1_hw *hw = &adapter->hw;
1479 u32 value;
1480
1481 /* clear interrupt status */
1482 iowrite32(0xffffffff, adapter->hw.hw_addr + REG_ISR);
1483
1484 /* set MAC Address */
1485 value = (((u32) hw->mac_addr[2]) << 24) |
1486 (((u32) hw->mac_addr[3]) << 16) |
1487 (((u32) hw->mac_addr[4]) << 8) |
1488 (((u32) hw->mac_addr[5]));
1489 iowrite32(value, hw->hw_addr + REG_MAC_STA_ADDR);
1490 value = (((u32) hw->mac_addr[0]) << 8) | (((u32) hw->mac_addr[1]));
1491 iowrite32(value, hw->hw_addr + (REG_MAC_STA_ADDR + 4));
1492
1493 /* tx / rx ring */
1494
1495 /* HI base address */
1496 iowrite32((u32) ((adapter->tpd_ring.dma & 0xffffffff00000000ULL) >> 32),
1497 hw->hw_addr + REG_DESC_BASE_ADDR_HI);
1498 /* LO base address */
1499 iowrite32((u32) (adapter->rfd_ring.dma & 0x00000000ffffffffULL),
1500 hw->hw_addr + REG_DESC_RFD_ADDR_LO);
1501 iowrite32((u32) (adapter->rrd_ring.dma & 0x00000000ffffffffULL),
1502 hw->hw_addr + REG_DESC_RRD_ADDR_LO);
1503 iowrite32((u32) (adapter->tpd_ring.dma & 0x00000000ffffffffULL),
1504 hw->hw_addr + REG_DESC_TPD_ADDR_LO);
1505 iowrite32((u32) (adapter->cmb.dma & 0x00000000ffffffffULL),
1506 hw->hw_addr + REG_DESC_CMB_ADDR_LO);
1507 iowrite32((u32) (adapter->smb.dma & 0x00000000ffffffffULL),
1508 hw->hw_addr + REG_DESC_SMB_ADDR_LO);
1509
1510 /* element count */
1511 value = adapter->rrd_ring.count;
1512 value <<= 16;
1513 value += adapter->rfd_ring.count;
1514 iowrite32(value, hw->hw_addr + REG_DESC_RFD_RRD_RING_SIZE);
1515 iowrite32(adapter->tpd_ring.count, hw->hw_addr +
1516 REG_DESC_TPD_RING_SIZE);
1517
1518 /* Load Ptr */
1519 iowrite32(1, hw->hw_addr + REG_LOAD_PTR);
1520
1521 /* config Mailbox */
1522 value = ((atomic_read(&adapter->tpd_ring.next_to_use)
1523 & MB_TPD_PROD_INDX_MASK) << MB_TPD_PROD_INDX_SHIFT) |
1524 ((atomic_read(&adapter->rrd_ring.next_to_clean)
1525 & MB_RRD_CONS_INDX_MASK) << MB_RRD_CONS_INDX_SHIFT) |
1526 ((atomic_read(&adapter->rfd_ring.next_to_use)
1527 & MB_RFD_PROD_INDX_MASK) << MB_RFD_PROD_INDX_SHIFT);
1528 iowrite32(value, hw->hw_addr + REG_MAILBOX);
1529
1530 /* config IPG/IFG */
1531 value = (((u32) hw->ipgt & MAC_IPG_IFG_IPGT_MASK)
1532 << MAC_IPG_IFG_IPGT_SHIFT) |
1533 (((u32) hw->min_ifg & MAC_IPG_IFG_MIFG_MASK)
1534 << MAC_IPG_IFG_MIFG_SHIFT) |
1535 (((u32) hw->ipgr1 & MAC_IPG_IFG_IPGR1_MASK)
1536 << MAC_IPG_IFG_IPGR1_SHIFT) |
1537 (((u32) hw->ipgr2 & MAC_IPG_IFG_IPGR2_MASK)
1538 << MAC_IPG_IFG_IPGR2_SHIFT);
1539 iowrite32(value, hw->hw_addr + REG_MAC_IPG_IFG);
1540
1541 /* config Half-Duplex Control */
1542 value = ((u32) hw->lcol & MAC_HALF_DUPLX_CTRL_LCOL_MASK) |
1543 (((u32) hw->max_retry & MAC_HALF_DUPLX_CTRL_RETRY_MASK)
1544 << MAC_HALF_DUPLX_CTRL_RETRY_SHIFT) |
1545 MAC_HALF_DUPLX_CTRL_EXC_DEF_EN |
1546 (0xa << MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT) |
1547 (((u32) hw->jam_ipg & MAC_HALF_DUPLX_CTRL_JAMIPG_MASK)
1548 << MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT);
1549 iowrite32(value, hw->hw_addr + REG_MAC_HALF_DUPLX_CTRL);
1550
1551 /* set Interrupt Moderator Timer */
1552 iowrite16(adapter->imt, hw->hw_addr + REG_IRQ_MODU_TIMER_INIT);
1553 iowrite32(MASTER_CTRL_ITIMER_EN, hw->hw_addr + REG_MASTER_CTRL);
1554
1555 /* set Interrupt Clear Timer */
1556 iowrite16(adapter->ict, hw->hw_addr + REG_CMBDISDMA_TIMER);
1557
1558 /* set max frame size hw will accept */
1559 iowrite32(hw->max_frame_size, hw->hw_addr + REG_MTU);
1560
1561 /* jumbo size & rrd retirement timer */
1562 value = (((u32) hw->rx_jumbo_th & RXQ_JMBOSZ_TH_MASK)
1563 << RXQ_JMBOSZ_TH_SHIFT) |
1564 (((u32) hw->rx_jumbo_lkah & RXQ_JMBO_LKAH_MASK)
1565 << RXQ_JMBO_LKAH_SHIFT) |
1566 (((u32) hw->rrd_ret_timer & RXQ_RRD_TIMER_MASK)
1567 << RXQ_RRD_TIMER_SHIFT);
1568 iowrite32(value, hw->hw_addr + REG_RXQ_JMBOSZ_RRDTIM);
1569
1570 /* Flow Control */
1571 switch (hw->dev_rev) {
1572 case 0x8001:
1573 case 0x9001:
1574 case 0x9002:
1575 case 0x9003:
1576 set_flow_ctrl_old(adapter);
1577 break;
1578 default:
1579 set_flow_ctrl_new(hw);
1580 break;
1581 }
1582
1583 /* config TXQ */
1584 value = (((u32) hw->tpd_burst & TXQ_CTRL_TPD_BURST_NUM_MASK)
1585 << TXQ_CTRL_TPD_BURST_NUM_SHIFT) |
1586 (((u32) hw->txf_burst & TXQ_CTRL_TXF_BURST_NUM_MASK)
1587 << TXQ_CTRL_TXF_BURST_NUM_SHIFT) |
1588 (((u32) hw->tpd_fetch_th & TXQ_CTRL_TPD_FETCH_TH_MASK)
1589 << TXQ_CTRL_TPD_FETCH_TH_SHIFT) | TXQ_CTRL_ENH_MODE |
1590 TXQ_CTRL_EN;
1591 iowrite32(value, hw->hw_addr + REG_TXQ_CTRL);
1592
1593 /* min tpd fetch gap & tx jumbo packet size threshold for taskoffload */
1594 value = (((u32) hw->tx_jumbo_task_th & TX_JUMBO_TASK_TH_MASK)
1595 << TX_JUMBO_TASK_TH_SHIFT) |
1596 (((u32) hw->tpd_fetch_gap & TX_TPD_MIN_IPG_MASK)
1597 << TX_TPD_MIN_IPG_SHIFT);
1598 iowrite32(value, hw->hw_addr + REG_TX_JUMBO_TASK_TH_TPD_IPG);
1599
1600 /* config RXQ */
1601 value = (((u32) hw->rfd_burst & RXQ_CTRL_RFD_BURST_NUM_MASK)
1602 << RXQ_CTRL_RFD_BURST_NUM_SHIFT) |
1603 (((u32) hw->rrd_burst & RXQ_CTRL_RRD_BURST_THRESH_MASK)
1604 << RXQ_CTRL_RRD_BURST_THRESH_SHIFT) |
1605 (((u32) hw->rfd_fetch_gap & RXQ_CTRL_RFD_PREF_MIN_IPG_MASK)
1606 << RXQ_CTRL_RFD_PREF_MIN_IPG_SHIFT) | RXQ_CTRL_CUT_THRU_EN |
1607 RXQ_CTRL_EN;
1608 iowrite32(value, hw->hw_addr + REG_RXQ_CTRL);
1609
1610 /* config DMA Engine */
1611 value = ((((u32) hw->dmar_block) & DMA_CTRL_DMAR_BURST_LEN_MASK)
1612 << DMA_CTRL_DMAR_BURST_LEN_SHIFT) |
1613 ((((u32) hw->dmaw_block) & DMA_CTRL_DMAW_BURST_LEN_MASK)
1614 << DMA_CTRL_DMAW_BURST_LEN_SHIFT) | DMA_CTRL_DMAR_EN |
1615 DMA_CTRL_DMAW_EN;
1616 value |= (u32) hw->dma_ord;
1617 if (atl1_rcb_128 == hw->rcb_value)
1618 value |= DMA_CTRL_RCB_VALUE;
1619 iowrite32(value, hw->hw_addr + REG_DMA_CTRL);
1620
1621 /* config CMB / SMB */
1622 value = (hw->cmb_tpd > adapter->tpd_ring.count) ?
1623 hw->cmb_tpd : adapter->tpd_ring.count;
1624 value <<= 16;
1625 value |= hw->cmb_rrd;
1626 iowrite32(value, hw->hw_addr + REG_CMB_WRITE_TH);
1627 value = hw->cmb_rx_timer | ((u32) hw->cmb_tx_timer << 16);
1628 iowrite32(value, hw->hw_addr + REG_CMB_WRITE_TIMER);
1629 iowrite32(hw->smb_timer, hw->hw_addr + REG_SMB_TIMER);
1630
1631 /* --- enable CMB / SMB */
1632 value = CSMB_CTRL_CMB_EN | CSMB_CTRL_SMB_EN;
1633 iowrite32(value, hw->hw_addr + REG_CSMB_CTRL);
1634
1635 value = ioread32(adapter->hw.hw_addr + REG_ISR);
1636 if (unlikely((value & ISR_PHY_LINKDOWN) != 0))
1637 value = 1; /* config failed */
1638 else
1639 value = 0;
1640
1641 /* clear all interrupt status */
1642 iowrite32(0x3fffffff, adapter->hw.hw_addr + REG_ISR);
1643 iowrite32(0, adapter->hw.hw_addr + REG_ISR);
1644 return value;
1645 }
1646
1647 /*
1648 * atl1_pcie_patch - Patch for PCIE module
1649 */
1650 static void atl1_pcie_patch(struct atl1_adapter *adapter)
1651 {
1652 u32 value;
1653
1654 /* much vendor magic here */
1655 value = 0x6500;
1656 iowrite32(value, adapter->hw.hw_addr + 0x12FC);
1657 /* pcie flow control mode change */
1658 value = ioread32(adapter->hw.hw_addr + 0x1008);
1659 value |= 0x8000;
1660 iowrite32(value, adapter->hw.hw_addr + 0x1008);
1661 }
1662
1663 /*
1664 * When ACPI resume on some VIA MotherBoard, the Interrupt Disable bit/0x400
1665 * on PCI Command register is disable.
1666 * The function enable this bit.
1667 * Brackett, 2006/03/15
1668 */
1669 static void atl1_via_workaround(struct atl1_adapter *adapter)
1670 {
1671 unsigned long value;
1672
1673 value = ioread16(adapter->hw.hw_addr + PCI_COMMAND);
1674 if (value & PCI_COMMAND_INTX_DISABLE)
1675 value &= ~PCI_COMMAND_INTX_DISABLE;
1676 iowrite32(value, adapter->hw.hw_addr + PCI_COMMAND);
1677 }
1678
1679 static void atl1_inc_smb(struct atl1_adapter *adapter)
1680 {
1681 struct net_device *netdev = adapter->netdev;
1682 struct stats_msg_block *smb = adapter->smb.smb;
1683
1684 /* Fill out the OS statistics structure */
1685 adapter->soft_stats.rx_packets += smb->rx_ok;
1686 adapter->soft_stats.tx_packets += smb->tx_ok;
1687 adapter->soft_stats.rx_bytes += smb->rx_byte_cnt;
1688 adapter->soft_stats.tx_bytes += smb->tx_byte_cnt;
1689 adapter->soft_stats.multicast += smb->rx_mcast;
1690 adapter->soft_stats.collisions += (smb->tx_1_col + smb->tx_2_col * 2 +
1691 smb->tx_late_col + smb->tx_abort_col * adapter->hw.max_retry);
1692
1693 /* Rx Errors */
1694 adapter->soft_stats.rx_errors += (smb->rx_frag + smb->rx_fcs_err +
1695 smb->rx_len_err + smb->rx_sz_ov + smb->rx_rxf_ov +
1696 smb->rx_rrd_ov + smb->rx_align_err);
1697 adapter->soft_stats.rx_fifo_errors += smb->rx_rxf_ov;
1698 adapter->soft_stats.rx_length_errors += smb->rx_len_err;
1699 adapter->soft_stats.rx_crc_errors += smb->rx_fcs_err;
1700 adapter->soft_stats.rx_frame_errors += smb->rx_align_err;
1701 adapter->soft_stats.rx_missed_errors += (smb->rx_rrd_ov +
1702 smb->rx_rxf_ov);
1703
1704 adapter->soft_stats.rx_pause += smb->rx_pause;
1705 adapter->soft_stats.rx_rrd_ov += smb->rx_rrd_ov;
1706 adapter->soft_stats.rx_trunc += smb->rx_sz_ov;
1707
1708 /* Tx Errors */
1709 adapter->soft_stats.tx_errors += (smb->tx_late_col +
1710 smb->tx_abort_col + smb->tx_underrun + smb->tx_trunc);
1711 adapter->soft_stats.tx_fifo_errors += smb->tx_underrun;
1712 adapter->soft_stats.tx_aborted_errors += smb->tx_abort_col;
1713 adapter->soft_stats.tx_window_errors += smb->tx_late_col;
1714
1715 adapter->soft_stats.excecol += smb->tx_abort_col;
1716 adapter->soft_stats.deffer += smb->tx_defer;
1717 adapter->soft_stats.scc += smb->tx_1_col;
1718 adapter->soft_stats.mcc += smb->tx_2_col;
1719 adapter->soft_stats.latecol += smb->tx_late_col;
1720 adapter->soft_stats.tx_underun += smb->tx_underrun;
1721 adapter->soft_stats.tx_trunc += smb->tx_trunc;
1722 adapter->soft_stats.tx_pause += smb->tx_pause;
1723
1724 netdev->stats.rx_packets = adapter->soft_stats.rx_packets;
1725 netdev->stats.tx_packets = adapter->soft_stats.tx_packets;
1726 netdev->stats.rx_bytes = adapter->soft_stats.rx_bytes;
1727 netdev->stats.tx_bytes = adapter->soft_stats.tx_bytes;
1728 netdev->stats.multicast = adapter->soft_stats.multicast;
1729 netdev->stats.collisions = adapter->soft_stats.collisions;
1730 netdev->stats.rx_errors = adapter->soft_stats.rx_errors;
1731 netdev->stats.rx_over_errors =
1732 adapter->soft_stats.rx_missed_errors;
1733 netdev->stats.rx_length_errors =
1734 adapter->soft_stats.rx_length_errors;
1735 netdev->stats.rx_crc_errors = adapter->soft_stats.rx_crc_errors;
1736 netdev->stats.rx_frame_errors =
1737 adapter->soft_stats.rx_frame_errors;
1738 netdev->stats.rx_fifo_errors = adapter->soft_stats.rx_fifo_errors;
1739 netdev->stats.rx_missed_errors =
1740 adapter->soft_stats.rx_missed_errors;
1741 netdev->stats.tx_errors = adapter->soft_stats.tx_errors;
1742 netdev->stats.tx_fifo_errors = adapter->soft_stats.tx_fifo_errors;
1743 netdev->stats.tx_aborted_errors =
1744 adapter->soft_stats.tx_aborted_errors;
1745 netdev->stats.tx_window_errors =
1746 adapter->soft_stats.tx_window_errors;
1747 netdev->stats.tx_carrier_errors =
1748 adapter->soft_stats.tx_carrier_errors;
1749 }
1750
1751 static void atl1_update_mailbox(struct atl1_adapter *adapter)
1752 {
1753 unsigned long flags;
1754 u32 tpd_next_to_use;
1755 u32 rfd_next_to_use;
1756 u32 rrd_next_to_clean;
1757 u32 value;
1758
1759 spin_lock_irqsave(&adapter->mb_lock, flags);
1760
1761 tpd_next_to_use = atomic_read(&adapter->tpd_ring.next_to_use);
1762 rfd_next_to_use = atomic_read(&adapter->rfd_ring.next_to_use);
1763 rrd_next_to_clean = atomic_read(&adapter->rrd_ring.next_to_clean);
1764
1765 value = ((rfd_next_to_use & MB_RFD_PROD_INDX_MASK) <<
1766 MB_RFD_PROD_INDX_SHIFT) |
1767 ((rrd_next_to_clean & MB_RRD_CONS_INDX_MASK) <<
1768 MB_RRD_CONS_INDX_SHIFT) |
1769 ((tpd_next_to_use & MB_TPD_PROD_INDX_MASK) <<
1770 MB_TPD_PROD_INDX_SHIFT);
1771 iowrite32(value, adapter->hw.hw_addr + REG_MAILBOX);
1772
1773 spin_unlock_irqrestore(&adapter->mb_lock, flags);
1774 }
1775
1776 static void atl1_clean_alloc_flag(struct atl1_adapter *adapter,
1777 struct rx_return_desc *rrd, u16 offset)
1778 {
1779 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
1780
1781 while (rfd_ring->next_to_clean != (rrd->buf_indx + offset)) {
1782 rfd_ring->buffer_info[rfd_ring->next_to_clean].alloced = 0;
1783 if (++rfd_ring->next_to_clean == rfd_ring->count) {
1784 rfd_ring->next_to_clean = 0;
1785 }
1786 }
1787 }
1788
1789 static void atl1_update_rfd_index(struct atl1_adapter *adapter,
1790 struct rx_return_desc *rrd)
1791 {
1792 u16 num_buf;
1793
1794 num_buf = (rrd->xsz.xsum_sz.pkt_size + adapter->rx_buffer_len - 1) /
1795 adapter->rx_buffer_len;
1796 if (rrd->num_buf == num_buf)
1797 /* clean alloc flag for bad rrd */
1798 atl1_clean_alloc_flag(adapter, rrd, num_buf);
1799 }
1800
1801 static void atl1_rx_checksum(struct atl1_adapter *adapter,
1802 struct rx_return_desc *rrd, struct sk_buff *skb)
1803 {
1804 struct pci_dev *pdev = adapter->pdev;
1805
1806 /*
1807 * The L1 hardware contains a bug that erroneously sets the
1808 * PACKET_FLAG_ERR and ERR_FLAG_L4_CHKSUM bits whenever a
1809 * fragmented IP packet is received, even though the packet
1810 * is perfectly valid and its checksum is correct. There's
1811 * no way to distinguish between one of these good packets
1812 * and a packet that actually contains a TCP/UDP checksum
1813 * error, so all we can do is allow it to be handed up to
1814 * the higher layers and let it be sorted out there.
1815 */
1816
1817 skb_checksum_none_assert(skb);
1818
1819 if (unlikely(rrd->pkt_flg & PACKET_FLAG_ERR)) {
1820 if (rrd->err_flg & (ERR_FLAG_CRC | ERR_FLAG_TRUNC |
1821 ERR_FLAG_CODE | ERR_FLAG_OV)) {
1822 adapter->hw_csum_err++;
1823 if (netif_msg_rx_err(adapter))
1824 dev_printk(KERN_DEBUG, &pdev->dev,
1825 "rx checksum error\n");
1826 return;
1827 }
1828 }
1829
1830 /* not IPv4 */
1831 if (!(rrd->pkt_flg & PACKET_FLAG_IPV4))
1832 /* checksum is invalid, but it's not an IPv4 pkt, so ok */
1833 return;
1834
1835 /* IPv4 packet */
1836 if (likely(!(rrd->err_flg &
1837 (ERR_FLAG_IP_CHKSUM | ERR_FLAG_L4_CHKSUM)))) {
1838 skb->ip_summed = CHECKSUM_UNNECESSARY;
1839 adapter->hw_csum_good++;
1840 return;
1841 }
1842 }
1843
1844 /*
1845 * atl1_alloc_rx_buffers - Replace used receive buffers
1846 * @adapter: address of board private structure
1847 */
1848 static u16 atl1_alloc_rx_buffers(struct atl1_adapter *adapter)
1849 {
1850 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
1851 struct pci_dev *pdev = adapter->pdev;
1852 struct page *page;
1853 unsigned long offset;
1854 struct atl1_buffer *buffer_info, *next_info;
1855 struct sk_buff *skb;
1856 u16 num_alloc = 0;
1857 u16 rfd_next_to_use, next_next;
1858 struct rx_free_desc *rfd_desc;
1859
1860 next_next = rfd_next_to_use = atomic_read(&rfd_ring->next_to_use);
1861 if (++next_next == rfd_ring->count)
1862 next_next = 0;
1863 buffer_info = &rfd_ring->buffer_info[rfd_next_to_use];
1864 next_info = &rfd_ring->buffer_info[next_next];
1865
1866 while (!buffer_info->alloced && !next_info->alloced) {
1867 if (buffer_info->skb) {
1868 buffer_info->alloced = 1;
1869 goto next;
1870 }
1871
1872 rfd_desc = ATL1_RFD_DESC(rfd_ring, rfd_next_to_use);
1873
1874 skb = netdev_alloc_skb_ip_align(adapter->netdev,
1875 adapter->rx_buffer_len);
1876 if (unlikely(!skb)) {
1877 /* Better luck next round */
1878 adapter->netdev->stats.rx_dropped++;
1879 break;
1880 }
1881
1882 buffer_info->alloced = 1;
1883 buffer_info->skb = skb;
1884 buffer_info->length = (u16) adapter->rx_buffer_len;
1885 page = virt_to_page(skb->data);
1886 offset = (unsigned long)skb->data & ~PAGE_MASK;
1887 buffer_info->dma = pci_map_page(pdev, page, offset,
1888 adapter->rx_buffer_len,
1889 PCI_DMA_FROMDEVICE);
1890 rfd_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
1891 rfd_desc->buf_len = cpu_to_le16(adapter->rx_buffer_len);
1892 rfd_desc->coalese = 0;
1893
1894 next:
1895 rfd_next_to_use = next_next;
1896 if (unlikely(++next_next == rfd_ring->count))
1897 next_next = 0;
1898
1899 buffer_info = &rfd_ring->buffer_info[rfd_next_to_use];
1900 next_info = &rfd_ring->buffer_info[next_next];
1901 num_alloc++;
1902 }
1903
1904 if (num_alloc) {
1905 /*
1906 * Force memory writes to complete before letting h/w
1907 * know there are new descriptors to fetch. (Only
1908 * applicable for weak-ordered memory model archs,
1909 * such as IA-64).
1910 */
1911 wmb();
1912 atomic_set(&rfd_ring->next_to_use, (int)rfd_next_to_use);
1913 }
1914 return num_alloc;
1915 }
1916
1917 static void atl1_intr_rx(struct atl1_adapter *adapter)
1918 {
1919 int i, count;
1920 u16 length;
1921 u16 rrd_next_to_clean;
1922 u32 value;
1923 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
1924 struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring;
1925 struct atl1_buffer *buffer_info;
1926 struct rx_return_desc *rrd;
1927 struct sk_buff *skb;
1928
1929 count = 0;
1930
1931 rrd_next_to_clean = atomic_read(&rrd_ring->next_to_clean);
1932
1933 while (1) {
1934 rrd = ATL1_RRD_DESC(rrd_ring, rrd_next_to_clean);
1935 i = 1;
1936 if (likely(rrd->xsz.valid)) { /* packet valid */
1937 chk_rrd:
1938 /* check rrd status */
1939 if (likely(rrd->num_buf == 1))
1940 goto rrd_ok;
1941 else if (netif_msg_rx_err(adapter)) {
1942 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
1943 "unexpected RRD buffer count\n");
1944 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
1945 "rx_buf_len = %d\n",
1946 adapter->rx_buffer_len);
1947 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
1948 "RRD num_buf = %d\n",
1949 rrd->num_buf);
1950 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
1951 "RRD pkt_len = %d\n",
1952 rrd->xsz.xsum_sz.pkt_size);
1953 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
1954 "RRD pkt_flg = 0x%08X\n",
1955 rrd->pkt_flg);
1956 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
1957 "RRD err_flg = 0x%08X\n",
1958 rrd->err_flg);
1959 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
1960 "RRD vlan_tag = 0x%08X\n",
1961 rrd->vlan_tag);
1962 }
1963
1964 /* rrd seems to be bad */
1965 if (unlikely(i-- > 0)) {
1966 /* rrd may not be DMAed completely */
1967 udelay(1);
1968 goto chk_rrd;
1969 }
1970 /* bad rrd */
1971 if (netif_msg_rx_err(adapter))
1972 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
1973 "bad RRD\n");
1974 /* see if update RFD index */
1975 if (rrd->num_buf > 1)
1976 atl1_update_rfd_index(adapter, rrd);
1977
1978 /* update rrd */
1979 rrd->xsz.valid = 0;
1980 if (++rrd_next_to_clean == rrd_ring->count)
1981 rrd_next_to_clean = 0;
1982 count++;
1983 continue;
1984 } else { /* current rrd still not be updated */
1985
1986 break;
1987 }
1988 rrd_ok:
1989 /* clean alloc flag for bad rrd */
1990 atl1_clean_alloc_flag(adapter, rrd, 0);
1991
1992 buffer_info = &rfd_ring->buffer_info[rrd->buf_indx];
1993 if (++rfd_ring->next_to_clean == rfd_ring->count)
1994 rfd_ring->next_to_clean = 0;
1995
1996 /* update rrd next to clean */
1997 if (++rrd_next_to_clean == rrd_ring->count)
1998 rrd_next_to_clean = 0;
1999 count++;
2000
2001 if (unlikely(rrd->pkt_flg & PACKET_FLAG_ERR)) {
2002 if (!(rrd->err_flg &
2003 (ERR_FLAG_IP_CHKSUM | ERR_FLAG_L4_CHKSUM
2004 | ERR_FLAG_LEN))) {
2005 /* packet error, don't need upstream */
2006 buffer_info->alloced = 0;
2007 rrd->xsz.valid = 0;
2008 continue;
2009 }
2010 }
2011
2012 /* Good Receive */
2013 pci_unmap_page(adapter->pdev, buffer_info->dma,
2014 buffer_info->length, PCI_DMA_FROMDEVICE);
2015 buffer_info->dma = 0;
2016 skb = buffer_info->skb;
2017 length = le16_to_cpu(rrd->xsz.xsum_sz.pkt_size);
2018
2019 skb_put(skb, length - ETH_FCS_LEN);
2020
2021 /* Receive Checksum Offload */
2022 atl1_rx_checksum(adapter, rrd, skb);
2023 skb->protocol = eth_type_trans(skb, adapter->netdev);
2024
2025 if (rrd->pkt_flg & PACKET_FLAG_VLAN_INS) {
2026 u16 vlan_tag = (rrd->vlan_tag >> 4) |
2027 ((rrd->vlan_tag & 7) << 13) |
2028 ((rrd->vlan_tag & 8) << 9);
2029
2030 __vlan_hwaccel_put_tag(skb, vlan_tag);
2031 }
2032 netif_rx(skb);
2033
2034 /* let protocol layer free skb */
2035 buffer_info->skb = NULL;
2036 buffer_info->alloced = 0;
2037 rrd->xsz.valid = 0;
2038 }
2039
2040 atomic_set(&rrd_ring->next_to_clean, rrd_next_to_clean);
2041
2042 atl1_alloc_rx_buffers(adapter);
2043
2044 /* update mailbox ? */
2045 if (count) {
2046 u32 tpd_next_to_use;
2047 u32 rfd_next_to_use;
2048
2049 spin_lock(&adapter->mb_lock);
2050
2051 tpd_next_to_use = atomic_read(&adapter->tpd_ring.next_to_use);
2052 rfd_next_to_use =
2053 atomic_read(&adapter->rfd_ring.next_to_use);
2054 rrd_next_to_clean =
2055 atomic_read(&adapter->rrd_ring.next_to_clean);
2056 value = ((rfd_next_to_use & MB_RFD_PROD_INDX_MASK) <<
2057 MB_RFD_PROD_INDX_SHIFT) |
2058 ((rrd_next_to_clean & MB_RRD_CONS_INDX_MASK) <<
2059 MB_RRD_CONS_INDX_SHIFT) |
2060 ((tpd_next_to_use & MB_TPD_PROD_INDX_MASK) <<
2061 MB_TPD_PROD_INDX_SHIFT);
2062 iowrite32(value, adapter->hw.hw_addr + REG_MAILBOX);
2063 spin_unlock(&adapter->mb_lock);
2064 }
2065 }
2066
2067 static void atl1_intr_tx(struct atl1_adapter *adapter)
2068 {
2069 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
2070 struct atl1_buffer *buffer_info;
2071 u16 sw_tpd_next_to_clean;
2072 u16 cmb_tpd_next_to_clean;
2073
2074 sw_tpd_next_to_clean = atomic_read(&tpd_ring->next_to_clean);
2075 cmb_tpd_next_to_clean = le16_to_cpu(adapter->cmb.cmb->tpd_cons_idx);
2076
2077 while (cmb_tpd_next_to_clean != sw_tpd_next_to_clean) {
2078 buffer_info = &tpd_ring->buffer_info[sw_tpd_next_to_clean];
2079 if (buffer_info->dma) {
2080 pci_unmap_page(adapter->pdev, buffer_info->dma,
2081 buffer_info->length, PCI_DMA_TODEVICE);
2082 buffer_info->dma = 0;
2083 }
2084
2085 if (buffer_info->skb) {
2086 dev_kfree_skb_irq(buffer_info->skb);
2087 buffer_info->skb = NULL;
2088 }
2089
2090 if (++sw_tpd_next_to_clean == tpd_ring->count)
2091 sw_tpd_next_to_clean = 0;
2092 }
2093 atomic_set(&tpd_ring->next_to_clean, sw_tpd_next_to_clean);
2094
2095 if (netif_queue_stopped(adapter->netdev) &&
2096 netif_carrier_ok(adapter->netdev))
2097 netif_wake_queue(adapter->netdev);
2098 }
2099
2100 static u16 atl1_tpd_avail(struct atl1_tpd_ring *tpd_ring)
2101 {
2102 u16 next_to_clean = atomic_read(&tpd_ring->next_to_clean);
2103 u16 next_to_use = atomic_read(&tpd_ring->next_to_use);
2104 return (next_to_clean > next_to_use) ?
2105 next_to_clean - next_to_use - 1 :
2106 tpd_ring->count + next_to_clean - next_to_use - 1;
2107 }
2108
2109 static int atl1_tso(struct atl1_adapter *adapter, struct sk_buff *skb,
2110 struct tx_packet_desc *ptpd)
2111 {
2112 u8 hdr_len, ip_off;
2113 u32 real_len;
2114 int err;
2115
2116 if (skb_shinfo(skb)->gso_size) {
2117 if (skb_header_cloned(skb)) {
2118 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2119 if (unlikely(err))
2120 return -1;
2121 }
2122
2123 if (skb->protocol == htons(ETH_P_IP)) {
2124 struct iphdr *iph = ip_hdr(skb);
2125
2126 real_len = (((unsigned char *)iph - skb->data) +
2127 ntohs(iph->tot_len));
2128 if (real_len < skb->len)
2129 pskb_trim(skb, real_len);
2130 hdr_len = (skb_transport_offset(skb) + tcp_hdrlen(skb));
2131 if (skb->len == hdr_len) {
2132 iph->check = 0;
2133 tcp_hdr(skb)->check =
2134 ~csum_tcpudp_magic(iph->saddr,
2135 iph->daddr, tcp_hdrlen(skb),
2136 IPPROTO_TCP, 0);
2137 ptpd->word3 |= (iph->ihl & TPD_IPHL_MASK) <<
2138 TPD_IPHL_SHIFT;
2139 ptpd->word3 |= ((tcp_hdrlen(skb) >> 2) &
2140 TPD_TCPHDRLEN_MASK) <<
2141 TPD_TCPHDRLEN_SHIFT;
2142 ptpd->word3 |= 1 << TPD_IP_CSUM_SHIFT;
2143 ptpd->word3 |= 1 << TPD_TCP_CSUM_SHIFT;
2144 return 1;
2145 }
2146
2147 iph->check = 0;
2148 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2149 iph->daddr, 0, IPPROTO_TCP, 0);
2150 ip_off = (unsigned char *)iph -
2151 (unsigned char *) skb_network_header(skb);
2152 if (ip_off == 8) /* 802.3-SNAP frame */
2153 ptpd->word3 |= 1 << TPD_ETHTYPE_SHIFT;
2154 else if (ip_off != 0)
2155 return -2;
2156
2157 ptpd->word3 |= (iph->ihl & TPD_IPHL_MASK) <<
2158 TPD_IPHL_SHIFT;
2159 ptpd->word3 |= ((tcp_hdrlen(skb) >> 2) &
2160 TPD_TCPHDRLEN_MASK) << TPD_TCPHDRLEN_SHIFT;
2161 ptpd->word3 |= (skb_shinfo(skb)->gso_size &
2162 TPD_MSS_MASK) << TPD_MSS_SHIFT;
2163 ptpd->word3 |= 1 << TPD_SEGMENT_EN_SHIFT;
2164 return 3;
2165 }
2166 }
2167 return false;
2168 }
2169
2170 static int atl1_tx_csum(struct atl1_adapter *adapter, struct sk_buff *skb,
2171 struct tx_packet_desc *ptpd)
2172 {
2173 u8 css, cso;
2174
2175 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
2176 css = skb_checksum_start_offset(skb);
2177 cso = css + (u8) skb->csum_offset;
2178 if (unlikely(css & 0x1)) {
2179 /* L1 hardware requires an even number here */
2180 if (netif_msg_tx_err(adapter))
2181 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
2182 "payload offset not an even number\n");
2183 return -1;
2184 }
2185 ptpd->word3 |= (css & TPD_PLOADOFFSET_MASK) <<
2186 TPD_PLOADOFFSET_SHIFT;
2187 ptpd->word3 |= (cso & TPD_CCSUMOFFSET_MASK) <<
2188 TPD_CCSUMOFFSET_SHIFT;
2189 ptpd->word3 |= 1 << TPD_CUST_CSUM_EN_SHIFT;
2190 return true;
2191 }
2192 return 0;
2193 }
2194
2195 static void atl1_tx_map(struct atl1_adapter *adapter, struct sk_buff *skb,
2196 struct tx_packet_desc *ptpd)
2197 {
2198 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
2199 struct atl1_buffer *buffer_info;
2200 u16 buf_len = skb->len;
2201 struct page *page;
2202 unsigned long offset;
2203 unsigned int nr_frags;
2204 unsigned int f;
2205 int retval;
2206 u16 next_to_use;
2207 u16 data_len;
2208 u8 hdr_len;
2209
2210 buf_len -= skb->data_len;
2211 nr_frags = skb_shinfo(skb)->nr_frags;
2212 next_to_use = atomic_read(&tpd_ring->next_to_use);
2213 buffer_info = &tpd_ring->buffer_info[next_to_use];
2214 BUG_ON(buffer_info->skb);
2215 /* put skb in last TPD */
2216 buffer_info->skb = NULL;
2217
2218 retval = (ptpd->word3 >> TPD_SEGMENT_EN_SHIFT) & TPD_SEGMENT_EN_MASK;
2219 if (retval) {
2220 /* TSO */
2221 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
2222 buffer_info->length = hdr_len;
2223 page = virt_to_page(skb->data);
2224 offset = (unsigned long)skb->data & ~PAGE_MASK;
2225 buffer_info->dma = pci_map_page(adapter->pdev, page,
2226 offset, hdr_len,
2227 PCI_DMA_TODEVICE);
2228
2229 if (++next_to_use == tpd_ring->count)
2230 next_to_use = 0;
2231
2232 if (buf_len > hdr_len) {
2233 int i, nseg;
2234
2235 data_len = buf_len - hdr_len;
2236 nseg = (data_len + ATL1_MAX_TX_BUF_LEN - 1) /
2237 ATL1_MAX_TX_BUF_LEN;
2238 for (i = 0; i < nseg; i++) {
2239 buffer_info =
2240 &tpd_ring->buffer_info[next_to_use];
2241 buffer_info->skb = NULL;
2242 buffer_info->length =
2243 (ATL1_MAX_TX_BUF_LEN >=
2244 data_len) ? ATL1_MAX_TX_BUF_LEN : data_len;
2245 data_len -= buffer_info->length;
2246 page = virt_to_page(skb->data +
2247 (hdr_len + i * ATL1_MAX_TX_BUF_LEN));
2248 offset = (unsigned long)(skb->data +
2249 (hdr_len + i * ATL1_MAX_TX_BUF_LEN)) &
2250 ~PAGE_MASK;
2251 buffer_info->dma = pci_map_page(adapter->pdev,
2252 page, offset, buffer_info->length,
2253 PCI_DMA_TODEVICE);
2254 if (++next_to_use == tpd_ring->count)
2255 next_to_use = 0;
2256 }
2257 }
2258 } else {
2259 /* not TSO */
2260 buffer_info->length = buf_len;
2261 page = virt_to_page(skb->data);
2262 offset = (unsigned long)skb->data & ~PAGE_MASK;
2263 buffer_info->dma = pci_map_page(adapter->pdev, page,
2264 offset, buf_len, PCI_DMA_TODEVICE);
2265 if (++next_to_use == tpd_ring->count)
2266 next_to_use = 0;
2267 }
2268
2269 for (f = 0; f < nr_frags; f++) {
2270 const struct skb_frag_struct *frag;
2271 u16 i, nseg;
2272
2273 frag = &skb_shinfo(skb)->frags[f];
2274 buf_len = skb_frag_size(frag);
2275
2276 nseg = (buf_len + ATL1_MAX_TX_BUF_LEN - 1) /
2277 ATL1_MAX_TX_BUF_LEN;
2278 for (i = 0; i < nseg; i++) {
2279 buffer_info = &tpd_ring->buffer_info[next_to_use];
2280 BUG_ON(buffer_info->skb);
2281
2282 buffer_info->skb = NULL;
2283 buffer_info->length = (buf_len > ATL1_MAX_TX_BUF_LEN) ?
2284 ATL1_MAX_TX_BUF_LEN : buf_len;
2285 buf_len -= buffer_info->length;
2286 buffer_info->dma = skb_frag_dma_map(&adapter->pdev->dev,
2287 frag, i * ATL1_MAX_TX_BUF_LEN,
2288 buffer_info->length, DMA_TO_DEVICE);
2289
2290 if (++next_to_use == tpd_ring->count)
2291 next_to_use = 0;
2292 }
2293 }
2294
2295 /* last tpd's buffer-info */
2296 buffer_info->skb = skb;
2297 }
2298
2299 static void atl1_tx_queue(struct atl1_adapter *adapter, u16 count,
2300 struct tx_packet_desc *ptpd)
2301 {
2302 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
2303 struct atl1_buffer *buffer_info;
2304 struct tx_packet_desc *tpd;
2305 u16 j;
2306 u32 val;
2307 u16 next_to_use = (u16) atomic_read(&tpd_ring->next_to_use);
2308
2309 for (j = 0; j < count; j++) {
2310 buffer_info = &tpd_ring->buffer_info[next_to_use];
2311 tpd = ATL1_TPD_DESC(&adapter->tpd_ring, next_to_use);
2312 if (tpd != ptpd)
2313 memcpy(tpd, ptpd, sizeof(struct tx_packet_desc));
2314 tpd->buffer_addr = cpu_to_le64(buffer_info->dma);
2315 tpd->word2 &= ~(TPD_BUFLEN_MASK << TPD_BUFLEN_SHIFT);
2316 tpd->word2 |= (cpu_to_le16(buffer_info->length) &
2317 TPD_BUFLEN_MASK) << TPD_BUFLEN_SHIFT;
2318
2319 /*
2320 * if this is the first packet in a TSO chain, set
2321 * TPD_HDRFLAG, otherwise, clear it.
2322 */
2323 val = (tpd->word3 >> TPD_SEGMENT_EN_SHIFT) &
2324 TPD_SEGMENT_EN_MASK;
2325 if (val) {
2326 if (!j)
2327 tpd->word3 |= 1 << TPD_HDRFLAG_SHIFT;
2328 else
2329 tpd->word3 &= ~(1 << TPD_HDRFLAG_SHIFT);
2330 }
2331
2332 if (j == (count - 1))
2333 tpd->word3 |= 1 << TPD_EOP_SHIFT;
2334
2335 if (++next_to_use == tpd_ring->count)
2336 next_to_use = 0;
2337 }
2338 /*
2339 * Force memory writes to complete before letting h/w
2340 * know there are new descriptors to fetch. (Only
2341 * applicable for weak-ordered memory model archs,
2342 * such as IA-64).
2343 */
2344 wmb();
2345
2346 atomic_set(&tpd_ring->next_to_use, next_to_use);
2347 }
2348
2349 static netdev_tx_t atl1_xmit_frame(struct sk_buff *skb,
2350 struct net_device *netdev)
2351 {
2352 struct atl1_adapter *adapter = netdev_priv(netdev);
2353 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
2354 int len;
2355 int tso;
2356 int count = 1;
2357 int ret_val;
2358 struct tx_packet_desc *ptpd;
2359 u16 vlan_tag;
2360 unsigned int nr_frags = 0;
2361 unsigned int mss = 0;
2362 unsigned int f;
2363 unsigned int proto_hdr_len;
2364
2365 len = skb_headlen(skb);
2366
2367 if (unlikely(skb->len <= 0)) {
2368 dev_kfree_skb_any(skb);
2369 return NETDEV_TX_OK;
2370 }
2371
2372 nr_frags = skb_shinfo(skb)->nr_frags;
2373 for (f = 0; f < nr_frags; f++) {
2374 unsigned int f_size = skb_frag_size(&skb_shinfo(skb)->frags[f]);
2375 count += (f_size + ATL1_MAX_TX_BUF_LEN - 1) /
2376 ATL1_MAX_TX_BUF_LEN;
2377 }
2378
2379 mss = skb_shinfo(skb)->gso_size;
2380 if (mss) {
2381 if (skb->protocol == htons(ETH_P_IP)) {
2382 proto_hdr_len = (skb_transport_offset(skb) +
2383 tcp_hdrlen(skb));
2384 if (unlikely(proto_hdr_len > len)) {
2385 dev_kfree_skb_any(skb);
2386 return NETDEV_TX_OK;
2387 }
2388 /* need additional TPD ? */
2389 if (proto_hdr_len != len)
2390 count += (len - proto_hdr_len +
2391 ATL1_MAX_TX_BUF_LEN - 1) /
2392 ATL1_MAX_TX_BUF_LEN;
2393 }
2394 }
2395
2396 if (atl1_tpd_avail(&adapter->tpd_ring) < count) {
2397 /* not enough descriptors */
2398 netif_stop_queue(netdev);
2399 if (netif_msg_tx_queued(adapter))
2400 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
2401 "tx busy\n");
2402 return NETDEV_TX_BUSY;
2403 }
2404
2405 ptpd = ATL1_TPD_DESC(tpd_ring,
2406 (u16) atomic_read(&tpd_ring->next_to_use));
2407 memset(ptpd, 0, sizeof(struct tx_packet_desc));
2408
2409 if (vlan_tx_tag_present(skb)) {
2410 vlan_tag = vlan_tx_tag_get(skb);
2411 vlan_tag = (vlan_tag << 4) | (vlan_tag >> 13) |
2412 ((vlan_tag >> 9) & 0x8);
2413 ptpd->word3 |= 1 << TPD_INS_VL_TAG_SHIFT;
2414 ptpd->word2 |= (vlan_tag & TPD_VLANTAG_MASK) <<
2415 TPD_VLANTAG_SHIFT;
2416 }
2417
2418 tso = atl1_tso(adapter, skb, ptpd);
2419 if (tso < 0) {
2420 dev_kfree_skb_any(skb);
2421 return NETDEV_TX_OK;
2422 }
2423
2424 if (!tso) {
2425 ret_val = atl1_tx_csum(adapter, skb, ptpd);
2426 if (ret_val < 0) {
2427 dev_kfree_skb_any(skb);
2428 return NETDEV_TX_OK;
2429 }
2430 }
2431
2432 atl1_tx_map(adapter, skb, ptpd);
2433 atl1_tx_queue(adapter, count, ptpd);
2434 atl1_update_mailbox(adapter);
2435 mmiowb();
2436 return NETDEV_TX_OK;
2437 }
2438
2439 /*
2440 * atl1_intr - Interrupt Handler
2441 * @irq: interrupt number
2442 * @data: pointer to a network interface device structure
2443 * @pt_regs: CPU registers structure
2444 */
2445 static irqreturn_t atl1_intr(int irq, void *data)
2446 {
2447 struct atl1_adapter *adapter = netdev_priv(data);
2448 u32 status;
2449 int max_ints = 10;
2450
2451 status = adapter->cmb.cmb->int_stats;
2452 if (!status)
2453 return IRQ_NONE;
2454
2455 do {
2456 /* clear CMB interrupt status at once */
2457 adapter->cmb.cmb->int_stats = 0;
2458
2459 if (status & ISR_GPHY) /* clear phy status */
2460 atlx_clear_phy_int(adapter);
2461
2462 /* clear ISR status, and Enable CMB DMA/Disable Interrupt */
2463 iowrite32(status | ISR_DIS_INT, adapter->hw.hw_addr + REG_ISR);
2464
2465 /* check if SMB intr */
2466 if (status & ISR_SMB)
2467 atl1_inc_smb(adapter);
2468
2469 /* check if PCIE PHY Link down */
2470 if (status & ISR_PHY_LINKDOWN) {
2471 if (netif_msg_intr(adapter))
2472 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
2473 "pcie phy link down %x\n", status);
2474 if (netif_running(adapter->netdev)) { /* reset MAC */
2475 iowrite32(0, adapter->hw.hw_addr + REG_IMR);
2476 schedule_work(&adapter->reset_dev_task);
2477 return IRQ_HANDLED;
2478 }
2479 }
2480
2481 /* check if DMA read/write error ? */
2482 if (status & (ISR_DMAR_TO_RST | ISR_DMAW_TO_RST)) {
2483 if (netif_msg_intr(adapter))
2484 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
2485 "pcie DMA r/w error (status = 0x%x)\n",
2486 status);
2487 iowrite32(0, adapter->hw.hw_addr + REG_IMR);
2488 schedule_work(&adapter->reset_dev_task);
2489 return IRQ_HANDLED;
2490 }
2491
2492 /* link event */
2493 if (status & ISR_GPHY) {
2494 adapter->soft_stats.tx_carrier_errors++;
2495 atl1_check_for_link(adapter);
2496 }
2497
2498 /* transmit event */
2499 if (status & ISR_CMB_TX)
2500 atl1_intr_tx(adapter);
2501
2502 /* rx exception */
2503 if (unlikely(status & (ISR_RXF_OV | ISR_RFD_UNRUN |
2504 ISR_RRD_OV | ISR_HOST_RFD_UNRUN |
2505 ISR_HOST_RRD_OV | ISR_CMB_RX))) {
2506 if (status & (ISR_RXF_OV | ISR_RFD_UNRUN |
2507 ISR_RRD_OV | ISR_HOST_RFD_UNRUN |
2508 ISR_HOST_RRD_OV))
2509 if (netif_msg_intr(adapter))
2510 dev_printk(KERN_DEBUG,
2511 &adapter->pdev->dev,
2512 "rx exception, ISR = 0x%x\n",
2513 status);
2514 atl1_intr_rx(adapter);
2515 }
2516
2517 if (--max_ints < 0)
2518 break;
2519
2520 } while ((status = adapter->cmb.cmb->int_stats));
2521
2522 /* re-enable Interrupt */
2523 iowrite32(ISR_DIS_SMB | ISR_DIS_DMA, adapter->hw.hw_addr + REG_ISR);
2524 return IRQ_HANDLED;
2525 }
2526
2527
2528 /*
2529 * atl1_phy_config - Timer Call-back
2530 * @data: pointer to netdev cast into an unsigned long
2531 */
2532 static void atl1_phy_config(unsigned long data)
2533 {
2534 struct atl1_adapter *adapter = (struct atl1_adapter *)data;
2535 struct atl1_hw *hw = &adapter->hw;
2536 unsigned long flags;
2537
2538 spin_lock_irqsave(&adapter->lock, flags);
2539 adapter->phy_timer_pending = false;
2540 atl1_write_phy_reg(hw, MII_ADVERTISE, hw->mii_autoneg_adv_reg);
2541 atl1_write_phy_reg(hw, MII_ATLX_CR, hw->mii_1000t_ctrl_reg);
2542 atl1_write_phy_reg(hw, MII_BMCR, MII_CR_RESET | MII_CR_AUTO_NEG_EN);
2543 spin_unlock_irqrestore(&adapter->lock, flags);
2544 }
2545
2546 /*
2547 * Orphaned vendor comment left intact here:
2548 * <vendor comment>
2549 * If TPD Buffer size equal to 0, PCIE DMAR_TO_INT
2550 * will assert. We do soft reset <0x1400=1> according
2551 * with the SPEC. BUT, it seemes that PCIE or DMA
2552 * state-machine will not be reset. DMAR_TO_INT will
2553 * assert again and again.
2554 * </vendor comment>
2555 */
2556
2557 static int atl1_reset(struct atl1_adapter *adapter)
2558 {
2559 int ret;
2560 ret = atl1_reset_hw(&adapter->hw);
2561 if (ret)
2562 return ret;
2563 return atl1_init_hw(&adapter->hw);
2564 }
2565
2566 static s32 atl1_up(struct atl1_adapter *adapter)
2567 {
2568 struct net_device *netdev = adapter->netdev;
2569 int err;
2570 int irq_flags = 0;
2571
2572 /* hardware has been reset, we need to reload some things */
2573 atlx_set_multi(netdev);
2574 atl1_init_ring_ptrs(adapter);
2575 atlx_restore_vlan(adapter);
2576 err = atl1_alloc_rx_buffers(adapter);
2577 if (unlikely(!err))
2578 /* no RX BUFFER allocated */
2579 return -ENOMEM;
2580
2581 if (unlikely(atl1_configure(adapter))) {
2582 err = -EIO;
2583 goto err_up;
2584 }
2585
2586 err = pci_enable_msi(adapter->pdev);
2587 if (err) {
2588 if (netif_msg_ifup(adapter))
2589 dev_info(&adapter->pdev->dev,
2590 "Unable to enable MSI: %d\n", err);
2591 irq_flags |= IRQF_SHARED;
2592 }
2593
2594 err = request_irq(adapter->pdev->irq, atl1_intr, irq_flags,
2595 netdev->name, netdev);
2596 if (unlikely(err))
2597 goto err_up;
2598
2599 atlx_irq_enable(adapter);
2600 atl1_check_link(adapter);
2601 netif_start_queue(netdev);
2602 return 0;
2603
2604 err_up:
2605 pci_disable_msi(adapter->pdev);
2606 /* free rx_buffers */
2607 atl1_clean_rx_ring(adapter);
2608 return err;
2609 }
2610
2611 static void atl1_down(struct atl1_adapter *adapter)
2612 {
2613 struct net_device *netdev = adapter->netdev;
2614
2615 netif_stop_queue(netdev);
2616 del_timer_sync(&adapter->phy_config_timer);
2617 adapter->phy_timer_pending = false;
2618
2619 atlx_irq_disable(adapter);
2620 free_irq(adapter->pdev->irq, netdev);
2621 pci_disable_msi(adapter->pdev);
2622 atl1_reset_hw(&adapter->hw);
2623 adapter->cmb.cmb->int_stats = 0;
2624
2625 adapter->link_speed = SPEED_0;
2626 adapter->link_duplex = -1;
2627 netif_carrier_off(netdev);
2628
2629 atl1_clean_tx_ring(adapter);
2630 atl1_clean_rx_ring(adapter);
2631 }
2632
2633 static void atl1_reset_dev_task(struct work_struct *work)
2634 {
2635 struct atl1_adapter *adapter =
2636 container_of(work, struct atl1_adapter, reset_dev_task);
2637 struct net_device *netdev = adapter->netdev;
2638
2639 netif_device_detach(netdev);
2640 atl1_down(adapter);
2641 atl1_up(adapter);
2642 netif_device_attach(netdev);
2643 }
2644
2645 /*
2646 * atl1_change_mtu - Change the Maximum Transfer Unit
2647 * @netdev: network interface device structure
2648 * @new_mtu: new value for maximum frame size
2649 *
2650 * Returns 0 on success, negative on failure
2651 */
2652 static int atl1_change_mtu(struct net_device *netdev, int new_mtu)
2653 {
2654 struct atl1_adapter *adapter = netdev_priv(netdev);
2655 int old_mtu = netdev->mtu;
2656 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
2657
2658 if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
2659 (max_frame > MAX_JUMBO_FRAME_SIZE)) {
2660 if (netif_msg_link(adapter))
2661 dev_warn(&adapter->pdev->dev, "invalid MTU setting\n");
2662 return -EINVAL;
2663 }
2664
2665 adapter->hw.max_frame_size = max_frame;
2666 adapter->hw.tx_jumbo_task_th = (max_frame + 7) >> 3;
2667 adapter->rx_buffer_len = (max_frame + 7) & ~7;
2668 adapter->hw.rx_jumbo_th = adapter->rx_buffer_len / 8;
2669
2670 netdev->mtu = new_mtu;
2671 if ((old_mtu != new_mtu) && netif_running(netdev)) {
2672 atl1_down(adapter);
2673 atl1_up(adapter);
2674 }
2675
2676 return 0;
2677 }
2678
2679 /*
2680 * atl1_open - Called when a network interface is made active
2681 * @netdev: network interface device structure
2682 *
2683 * Returns 0 on success, negative value on failure
2684 *
2685 * The open entry point is called when a network interface is made
2686 * active by the system (IFF_UP). At this point all resources needed
2687 * for transmit and receive operations are allocated, the interrupt
2688 * handler is registered with the OS, the watchdog timer is started,
2689 * and the stack is notified that the interface is ready.
2690 */
2691 static int atl1_open(struct net_device *netdev)
2692 {
2693 struct atl1_adapter *adapter = netdev_priv(netdev);
2694 int err;
2695
2696 netif_carrier_off(netdev);
2697
2698 /* allocate transmit descriptors */
2699 err = atl1_setup_ring_resources(adapter);
2700 if (err)
2701 return err;
2702
2703 err = atl1_up(adapter);
2704 if (err)
2705 goto err_up;
2706
2707 return 0;
2708
2709 err_up:
2710 atl1_reset(adapter);
2711 return err;
2712 }
2713
2714 /*
2715 * atl1_close - Disables a network interface
2716 * @netdev: network interface device structure
2717 *
2718 * Returns 0, this is not allowed to fail
2719 *
2720 * The close entry point is called when an interface is de-activated
2721 * by the OS. The hardware is still under the drivers control, but
2722 * needs to be disabled. A global MAC reset is issued to stop the
2723 * hardware, and all transmit and receive resources are freed.
2724 */
2725 static int atl1_close(struct net_device *netdev)
2726 {
2727 struct atl1_adapter *adapter = netdev_priv(netdev);
2728 atl1_down(adapter);
2729 atl1_free_ring_resources(adapter);
2730 return 0;
2731 }
2732
2733 #ifdef CONFIG_PM
2734 static int atl1_suspend(struct device *dev)
2735 {
2736 struct pci_dev *pdev = to_pci_dev(dev);
2737 struct net_device *netdev = pci_get_drvdata(pdev);
2738 struct atl1_adapter *adapter = netdev_priv(netdev);
2739 struct atl1_hw *hw = &adapter->hw;
2740 u32 ctrl = 0;
2741 u32 wufc = adapter->wol;
2742 u32 val;
2743 u16 speed;
2744 u16 duplex;
2745
2746 netif_device_detach(netdev);
2747 if (netif_running(netdev))
2748 atl1_down(adapter);
2749
2750 atl1_read_phy_reg(hw, MII_BMSR, (u16 *) & ctrl);
2751 atl1_read_phy_reg(hw, MII_BMSR, (u16 *) & ctrl);
2752 val = ctrl & BMSR_LSTATUS;
2753 if (val)
2754 wufc &= ~ATLX_WUFC_LNKC;
2755 if (!wufc)
2756 goto disable_wol;
2757
2758 if (val) {
2759 val = atl1_get_speed_and_duplex(hw, &speed, &duplex);
2760 if (val) {
2761 if (netif_msg_ifdown(adapter))
2762 dev_printk(KERN_DEBUG, &pdev->dev,
2763 "error getting speed/duplex\n");
2764 goto disable_wol;
2765 }
2766
2767 ctrl = 0;
2768
2769 /* enable magic packet WOL */
2770 if (wufc & ATLX_WUFC_MAG)
2771 ctrl |= (WOL_MAGIC_EN | WOL_MAGIC_PME_EN);
2772 iowrite32(ctrl, hw->hw_addr + REG_WOL_CTRL);
2773 ioread32(hw->hw_addr + REG_WOL_CTRL);
2774
2775 /* configure the mac */
2776 ctrl = MAC_CTRL_RX_EN;
2777 ctrl |= ((u32)((speed == SPEED_1000) ? MAC_CTRL_SPEED_1000 :
2778 MAC_CTRL_SPEED_10_100) << MAC_CTRL_SPEED_SHIFT);
2779 if (duplex == FULL_DUPLEX)
2780 ctrl |= MAC_CTRL_DUPLX;
2781 ctrl |= (((u32)adapter->hw.preamble_len &
2782 MAC_CTRL_PRMLEN_MASK) << MAC_CTRL_PRMLEN_SHIFT);
2783 __atlx_vlan_mode(netdev->features, &ctrl);
2784 if (wufc & ATLX_WUFC_MAG)
2785 ctrl |= MAC_CTRL_BC_EN;
2786 iowrite32(ctrl, hw->hw_addr + REG_MAC_CTRL);
2787 ioread32(hw->hw_addr + REG_MAC_CTRL);
2788
2789 /* poke the PHY */
2790 ctrl = ioread32(hw->hw_addr + REG_PCIE_PHYMISC);
2791 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
2792 iowrite32(ctrl, hw->hw_addr + REG_PCIE_PHYMISC);
2793 ioread32(hw->hw_addr + REG_PCIE_PHYMISC);
2794 } else {
2795 ctrl |= (WOL_LINK_CHG_EN | WOL_LINK_CHG_PME_EN);
2796 iowrite32(ctrl, hw->hw_addr + REG_WOL_CTRL);
2797 ioread32(hw->hw_addr + REG_WOL_CTRL);
2798 iowrite32(0, hw->hw_addr + REG_MAC_CTRL);
2799 ioread32(hw->hw_addr + REG_MAC_CTRL);
2800 hw->phy_configured = false;
2801 }
2802
2803 return 0;
2804
2805 disable_wol:
2806 iowrite32(0, hw->hw_addr + REG_WOL_CTRL);
2807 ioread32(hw->hw_addr + REG_WOL_CTRL);
2808 ctrl = ioread32(hw->hw_addr + REG_PCIE_PHYMISC);
2809 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
2810 iowrite32(ctrl, hw->hw_addr + REG_PCIE_PHYMISC);
2811 ioread32(hw->hw_addr + REG_PCIE_PHYMISC);
2812 hw->phy_configured = false;
2813
2814 return 0;
2815 }
2816
2817 static int atl1_resume(struct device *dev)
2818 {
2819 struct pci_dev *pdev = to_pci_dev(dev);
2820 struct net_device *netdev = pci_get_drvdata(pdev);
2821 struct atl1_adapter *adapter = netdev_priv(netdev);
2822
2823 iowrite32(0, adapter->hw.hw_addr + REG_WOL_CTRL);
2824
2825 atl1_reset_hw(&adapter->hw);
2826
2827 if (netif_running(netdev)) {
2828 adapter->cmb.cmb->int_stats = 0;
2829 atl1_up(adapter);
2830 }
2831 netif_device_attach(netdev);
2832
2833 return 0;
2834 }
2835
2836 static SIMPLE_DEV_PM_OPS(atl1_pm_ops, atl1_suspend, atl1_resume);
2837 #define ATL1_PM_OPS (&atl1_pm_ops)
2838
2839 #else
2840
2841 static int atl1_suspend(struct device *dev) { return 0; }
2842
2843 #define ATL1_PM_OPS NULL
2844 #endif
2845
2846 static void atl1_shutdown(struct pci_dev *pdev)
2847 {
2848 struct net_device *netdev = pci_get_drvdata(pdev);
2849 struct atl1_adapter *adapter = netdev_priv(netdev);
2850
2851 atl1_suspend(&pdev->dev);
2852 pci_wake_from_d3(pdev, adapter->wol);
2853 pci_set_power_state(pdev, PCI_D3hot);
2854 }
2855
2856 #ifdef CONFIG_NET_POLL_CONTROLLER
2857 static void atl1_poll_controller(struct net_device *netdev)
2858 {
2859 disable_irq(netdev->irq);
2860 atl1_intr(netdev->irq, netdev);
2861 enable_irq(netdev->irq);
2862 }
2863 #endif
2864
2865 static const struct net_device_ops atl1_netdev_ops = {
2866 .ndo_open = atl1_open,
2867 .ndo_stop = atl1_close,
2868 .ndo_start_xmit = atl1_xmit_frame,
2869 .ndo_set_rx_mode = atlx_set_multi,
2870 .ndo_validate_addr = eth_validate_addr,
2871 .ndo_set_mac_address = atl1_set_mac,
2872 .ndo_change_mtu = atl1_change_mtu,
2873 .ndo_fix_features = atlx_fix_features,
2874 .ndo_set_features = atlx_set_features,
2875 .ndo_do_ioctl = atlx_ioctl,
2876 .ndo_tx_timeout = atlx_tx_timeout,
2877 #ifdef CONFIG_NET_POLL_CONTROLLER
2878 .ndo_poll_controller = atl1_poll_controller,
2879 #endif
2880 };
2881
2882 /*
2883 * atl1_probe - Device Initialization Routine
2884 * @pdev: PCI device information struct
2885 * @ent: entry in atl1_pci_tbl
2886 *
2887 * Returns 0 on success, negative on failure
2888 *
2889 * atl1_probe initializes an adapter identified by a pci_dev structure.
2890 * The OS initialization, configuring of the adapter private structure,
2891 * and a hardware reset occur.
2892 */
2893 static int __devinit atl1_probe(struct pci_dev *pdev,
2894 const struct pci_device_id *ent)
2895 {
2896 struct net_device *netdev;
2897 struct atl1_adapter *adapter;
2898 static int cards_found = 0;
2899 int err;
2900
2901 err = pci_enable_device(pdev);
2902 if (err)
2903 return err;
2904
2905 /*
2906 * The atl1 chip can DMA to 64-bit addresses, but it uses a single
2907 * shared register for the high 32 bits, so only a single, aligned,
2908 * 4 GB physical address range can be used at a time.
2909 *
2910 * Supporting 64-bit DMA on this hardware is more trouble than it's
2911 * worth. It is far easier to limit to 32-bit DMA than update
2912 * various kernel subsystems to support the mechanics required by a
2913 * fixed-high-32-bit system.
2914 */
2915 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2916 if (err) {
2917 dev_err(&pdev->dev, "no usable DMA configuration\n");
2918 goto err_dma;
2919 }
2920 /*
2921 * Mark all PCI regions associated with PCI device
2922 * pdev as being reserved by owner atl1_driver_name
2923 */
2924 err = pci_request_regions(pdev, ATLX_DRIVER_NAME);
2925 if (err)
2926 goto err_request_regions;
2927
2928 /*
2929 * Enables bus-mastering on the device and calls
2930 * pcibios_set_master to do the needed arch specific settings
2931 */
2932 pci_set_master(pdev);
2933
2934 netdev = alloc_etherdev(sizeof(struct atl1_adapter));
2935 if (!netdev) {
2936 err = -ENOMEM;
2937 goto err_alloc_etherdev;
2938 }
2939 SET_NETDEV_DEV(netdev, &pdev->dev);
2940
2941 pci_set_drvdata(pdev, netdev);
2942 adapter = netdev_priv(netdev);
2943 adapter->netdev = netdev;
2944 adapter->pdev = pdev;
2945 adapter->hw.back = adapter;
2946 adapter->msg_enable = netif_msg_init(debug, atl1_default_msg);
2947
2948 adapter->hw.hw_addr = pci_iomap(pdev, 0, 0);
2949 if (!adapter->hw.hw_addr) {
2950 err = -EIO;
2951 goto err_pci_iomap;
2952 }
2953 /* get device revision number */
2954 adapter->hw.dev_rev = ioread16(adapter->hw.hw_addr +
2955 (REG_MASTER_CTRL + 2));
2956 if (netif_msg_probe(adapter))
2957 dev_info(&pdev->dev, "version %s\n", ATLX_DRIVER_VERSION);
2958
2959 /* set default ring resource counts */
2960 adapter->rfd_ring.count = adapter->rrd_ring.count = ATL1_DEFAULT_RFD;
2961 adapter->tpd_ring.count = ATL1_DEFAULT_TPD;
2962
2963 adapter->mii.dev = netdev;
2964 adapter->mii.mdio_read = mdio_read;
2965 adapter->mii.mdio_write = mdio_write;
2966 adapter->mii.phy_id_mask = 0x1f;
2967 adapter->mii.reg_num_mask = 0x1f;
2968
2969 netdev->netdev_ops = &atl1_netdev_ops;
2970 netdev->watchdog_timeo = 5 * HZ;
2971
2972 netdev->ethtool_ops = &atl1_ethtool_ops;
2973 adapter->bd_number = cards_found;
2974
2975 /* setup the private structure */
2976 err = atl1_sw_init(adapter);
2977 if (err)
2978 goto err_common;
2979
2980 netdev->features = NETIF_F_HW_CSUM;
2981 netdev->features |= NETIF_F_SG;
2982 netdev->features |= (NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX);
2983
2984 netdev->hw_features = NETIF_F_HW_CSUM | NETIF_F_SG | NETIF_F_TSO |
2985 NETIF_F_HW_VLAN_RX;
2986
2987 /* is this valid? see atl1_setup_mac_ctrl() */
2988 netdev->features |= NETIF_F_RXCSUM;
2989
2990 /*
2991 * patch for some L1 of old version,
2992 * the final version of L1 may not need these
2993 * patches
2994 */
2995 /* atl1_pcie_patch(adapter); */
2996
2997 /* really reset GPHY core */
2998 iowrite16(0, adapter->hw.hw_addr + REG_PHY_ENABLE);
2999
3000 /*
3001 * reset the controller to
3002 * put the device in a known good starting state
3003 */
3004 if (atl1_reset_hw(&adapter->hw)) {
3005 err = -EIO;
3006 goto err_common;
3007 }
3008
3009 /* copy the MAC address out of the EEPROM */
3010 atl1_read_mac_addr(&adapter->hw);
3011 memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len);
3012
3013 if (!is_valid_ether_addr(netdev->dev_addr)) {
3014 err = -EIO;
3015 goto err_common;
3016 }
3017
3018 atl1_check_options(adapter);
3019
3020 /* pre-init the MAC, and setup link */
3021 err = atl1_init_hw(&adapter->hw);
3022 if (err) {
3023 err = -EIO;
3024 goto err_common;
3025 }
3026
3027 atl1_pcie_patch(adapter);
3028 /* assume we have no link for now */
3029 netif_carrier_off(netdev);
3030
3031 setup_timer(&adapter->phy_config_timer, atl1_phy_config,
3032 (unsigned long)adapter);
3033 adapter->phy_timer_pending = false;
3034
3035 INIT_WORK(&adapter->reset_dev_task, atl1_reset_dev_task);
3036
3037 INIT_WORK(&adapter->link_chg_task, atlx_link_chg_task);
3038
3039 err = register_netdev(netdev);
3040 if (err)
3041 goto err_common;
3042
3043 cards_found++;
3044 atl1_via_workaround(adapter);
3045 return 0;
3046
3047 err_common:
3048 pci_iounmap(pdev, adapter->hw.hw_addr);
3049 err_pci_iomap:
3050 free_netdev(netdev);
3051 err_alloc_etherdev:
3052 pci_release_regions(pdev);
3053 err_dma:
3054 err_request_regions:
3055 pci_disable_device(pdev);
3056 return err;
3057 }
3058
3059 /*
3060 * atl1_remove - Device Removal Routine
3061 * @pdev: PCI device information struct
3062 *
3063 * atl1_remove is called by the PCI subsystem to alert the driver
3064 * that it should release a PCI device. The could be caused by a
3065 * Hot-Plug event, or because the driver is going to be removed from
3066 * memory.
3067 */
3068 static void __devexit atl1_remove(struct pci_dev *pdev)
3069 {
3070 struct net_device *netdev = pci_get_drvdata(pdev);
3071 struct atl1_adapter *adapter;
3072 /* Device not available. Return. */
3073 if (!netdev)
3074 return;
3075
3076 adapter = netdev_priv(netdev);
3077
3078 /*
3079 * Some atl1 boards lack persistent storage for their MAC, and get it
3080 * from the BIOS during POST. If we've been messing with the MAC
3081 * address, we need to save the permanent one.
3082 */
3083 if (memcmp(adapter->hw.mac_addr, adapter->hw.perm_mac_addr, ETH_ALEN)) {
3084 memcpy(adapter->hw.mac_addr, adapter->hw.perm_mac_addr,
3085 ETH_ALEN);
3086 atl1_set_mac_addr(&adapter->hw);
3087 }
3088
3089 iowrite16(0, adapter->hw.hw_addr + REG_PHY_ENABLE);
3090 unregister_netdev(netdev);
3091 pci_iounmap(pdev, adapter->hw.hw_addr);
3092 pci_release_regions(pdev);
3093 free_netdev(netdev);
3094 pci_disable_device(pdev);
3095 }
3096
3097 static struct pci_driver atl1_driver = {
3098 .name = ATLX_DRIVER_NAME,
3099 .id_table = atl1_pci_tbl,
3100 .probe = atl1_probe,
3101 .remove = __devexit_p(atl1_remove),
3102 .shutdown = atl1_shutdown,
3103 .driver.pm = ATL1_PM_OPS,
3104 };
3105
3106 /*
3107 * atl1_exit_module - Driver Exit Cleanup Routine
3108 *
3109 * atl1_exit_module is called just before the driver is removed
3110 * from memory.
3111 */
3112 static void __exit atl1_exit_module(void)
3113 {
3114 pci_unregister_driver(&atl1_driver);
3115 }
3116
3117 /*
3118 * atl1_init_module - Driver Registration Routine
3119 *
3120 * atl1_init_module is the first routine called when the driver is
3121 * loaded. All it does is register with the PCI subsystem.
3122 */
3123 static int __init atl1_init_module(void)
3124 {
3125 return pci_register_driver(&atl1_driver);
3126 }
3127
3128 module_init(atl1_init_module);
3129 module_exit(atl1_exit_module);
3130
3131 struct atl1_stats {
3132 char stat_string[ETH_GSTRING_LEN];
3133 int sizeof_stat;
3134 int stat_offset;
3135 };
3136
3137 #define ATL1_STAT(m) \
3138 sizeof(((struct atl1_adapter *)0)->m), offsetof(struct atl1_adapter, m)
3139
3140 static struct atl1_stats atl1_gstrings_stats[] = {
3141 {"rx_packets", ATL1_STAT(soft_stats.rx_packets)},
3142 {"tx_packets", ATL1_STAT(soft_stats.tx_packets)},
3143 {"rx_bytes", ATL1_STAT(soft_stats.rx_bytes)},
3144 {"tx_bytes", ATL1_STAT(soft_stats.tx_bytes)},
3145 {"rx_errors", ATL1_STAT(soft_stats.rx_errors)},
3146 {"tx_errors", ATL1_STAT(soft_stats.tx_errors)},
3147 {"multicast", ATL1_STAT(soft_stats.multicast)},
3148 {"collisions", ATL1_STAT(soft_stats.collisions)},
3149 {"rx_length_errors", ATL1_STAT(soft_stats.rx_length_errors)},
3150 {"rx_over_errors", ATL1_STAT(soft_stats.rx_missed_errors)},
3151 {"rx_crc_errors", ATL1_STAT(soft_stats.rx_crc_errors)},
3152 {"rx_frame_errors", ATL1_STAT(soft_stats.rx_frame_errors)},
3153 {"rx_fifo_errors", ATL1_STAT(soft_stats.rx_fifo_errors)},
3154 {"rx_missed_errors", ATL1_STAT(soft_stats.rx_missed_errors)},
3155 {"tx_aborted_errors", ATL1_STAT(soft_stats.tx_aborted_errors)},
3156 {"tx_carrier_errors", ATL1_STAT(soft_stats.tx_carrier_errors)},
3157 {"tx_fifo_errors", ATL1_STAT(soft_stats.tx_fifo_errors)},
3158 {"tx_window_errors", ATL1_STAT(soft_stats.tx_window_errors)},
3159 {"tx_abort_exce_coll", ATL1_STAT(soft_stats.excecol)},
3160 {"tx_abort_late_coll", ATL1_STAT(soft_stats.latecol)},
3161 {"tx_deferred_ok", ATL1_STAT(soft_stats.deffer)},
3162 {"tx_single_coll_ok", ATL1_STAT(soft_stats.scc)},
3163 {"tx_multi_coll_ok", ATL1_STAT(soft_stats.mcc)},
3164 {"tx_underun", ATL1_STAT(soft_stats.tx_underun)},
3165 {"tx_trunc", ATL1_STAT(soft_stats.tx_trunc)},
3166 {"tx_pause", ATL1_STAT(soft_stats.tx_pause)},
3167 {"rx_pause", ATL1_STAT(soft_stats.rx_pause)},
3168 {"rx_rrd_ov", ATL1_STAT(soft_stats.rx_rrd_ov)},
3169 {"rx_trunc", ATL1_STAT(soft_stats.rx_trunc)}
3170 };
3171
3172 static void atl1_get_ethtool_stats(struct net_device *netdev,
3173 struct ethtool_stats *stats, u64 *data)
3174 {
3175 struct atl1_adapter *adapter = netdev_priv(netdev);
3176 int i;
3177 char *p;
3178
3179 for (i = 0; i < ARRAY_SIZE(atl1_gstrings_stats); i++) {
3180 p = (char *)adapter+atl1_gstrings_stats[i].stat_offset;
3181 data[i] = (atl1_gstrings_stats[i].sizeof_stat ==
3182 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
3183 }
3184
3185 }
3186
3187 static int atl1_get_sset_count(struct net_device *netdev, int sset)
3188 {
3189 switch (sset) {
3190 case ETH_SS_STATS:
3191 return ARRAY_SIZE(atl1_gstrings_stats);
3192 default:
3193 return -EOPNOTSUPP;
3194 }
3195 }
3196
3197 static int atl1_get_settings(struct net_device *netdev,
3198 struct ethtool_cmd *ecmd)
3199 {
3200 struct atl1_adapter *adapter = netdev_priv(netdev);
3201 struct atl1_hw *hw = &adapter->hw;
3202
3203 ecmd->supported = (SUPPORTED_10baseT_Half |
3204 SUPPORTED_10baseT_Full |
3205 SUPPORTED_100baseT_Half |
3206 SUPPORTED_100baseT_Full |
3207 SUPPORTED_1000baseT_Full |
3208 SUPPORTED_Autoneg | SUPPORTED_TP);
3209 ecmd->advertising = ADVERTISED_TP;
3210 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
3211 hw->media_type == MEDIA_TYPE_1000M_FULL) {
3212 ecmd->advertising |= ADVERTISED_Autoneg;
3213 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR) {
3214 ecmd->advertising |= ADVERTISED_Autoneg;
3215 ecmd->advertising |=
3216 (ADVERTISED_10baseT_Half |
3217 ADVERTISED_10baseT_Full |
3218 ADVERTISED_100baseT_Half |
3219 ADVERTISED_100baseT_Full |
3220 ADVERTISED_1000baseT_Full);
3221 } else
3222 ecmd->advertising |= (ADVERTISED_1000baseT_Full);
3223 }
3224 ecmd->port = PORT_TP;
3225 ecmd->phy_address = 0;
3226 ecmd->transceiver = XCVR_INTERNAL;
3227
3228 if (netif_carrier_ok(adapter->netdev)) {
3229 u16 link_speed, link_duplex;
3230 atl1_get_speed_and_duplex(hw, &link_speed, &link_duplex);
3231 ethtool_cmd_speed_set(ecmd, link_speed);
3232 if (link_duplex == FULL_DUPLEX)
3233 ecmd->duplex = DUPLEX_FULL;
3234 else
3235 ecmd->duplex = DUPLEX_HALF;
3236 } else {
3237 ethtool_cmd_speed_set(ecmd, -1);
3238 ecmd->duplex = -1;
3239 }
3240 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
3241 hw->media_type == MEDIA_TYPE_1000M_FULL)
3242 ecmd->autoneg = AUTONEG_ENABLE;
3243 else
3244 ecmd->autoneg = AUTONEG_DISABLE;
3245
3246 return 0;
3247 }
3248
3249 static int atl1_set_settings(struct net_device *netdev,
3250 struct ethtool_cmd *ecmd)
3251 {
3252 struct atl1_adapter *adapter = netdev_priv(netdev);
3253 struct atl1_hw *hw = &adapter->hw;
3254 u16 phy_data;
3255 int ret_val = 0;
3256 u16 old_media_type = hw->media_type;
3257
3258 if (netif_running(adapter->netdev)) {
3259 if (netif_msg_link(adapter))
3260 dev_dbg(&adapter->pdev->dev,
3261 "ethtool shutting down adapter\n");
3262 atl1_down(adapter);
3263 }
3264
3265 if (ecmd->autoneg == AUTONEG_ENABLE)
3266 hw->media_type = MEDIA_TYPE_AUTO_SENSOR;
3267 else {
3268 u32 speed = ethtool_cmd_speed(ecmd);
3269 if (speed == SPEED_1000) {
3270 if (ecmd->duplex != DUPLEX_FULL) {
3271 if (netif_msg_link(adapter))
3272 dev_warn(&adapter->pdev->dev,
3273 "1000M half is invalid\n");
3274 ret_val = -EINVAL;
3275 goto exit_sset;
3276 }
3277 hw->media_type = MEDIA_TYPE_1000M_FULL;
3278 } else if (speed == SPEED_100) {
3279 if (ecmd->duplex == DUPLEX_FULL)
3280 hw->media_type = MEDIA_TYPE_100M_FULL;
3281 else
3282 hw->media_type = MEDIA_TYPE_100M_HALF;
3283 } else {
3284 if (ecmd->duplex == DUPLEX_FULL)
3285 hw->media_type = MEDIA_TYPE_10M_FULL;
3286 else
3287 hw->media_type = MEDIA_TYPE_10M_HALF;
3288 }
3289 }
3290 switch (hw->media_type) {
3291 case MEDIA_TYPE_AUTO_SENSOR:
3292 ecmd->advertising =
3293 ADVERTISED_10baseT_Half |
3294 ADVERTISED_10baseT_Full |
3295 ADVERTISED_100baseT_Half |
3296 ADVERTISED_100baseT_Full |
3297 ADVERTISED_1000baseT_Full |
3298 ADVERTISED_Autoneg | ADVERTISED_TP;
3299 break;
3300 case MEDIA_TYPE_1000M_FULL:
3301 ecmd->advertising =
3302 ADVERTISED_1000baseT_Full |
3303 ADVERTISED_Autoneg | ADVERTISED_TP;
3304 break;
3305 default:
3306 ecmd->advertising = 0;
3307 break;
3308 }
3309 if (atl1_phy_setup_autoneg_adv(hw)) {
3310 ret_val = -EINVAL;
3311 if (netif_msg_link(adapter))
3312 dev_warn(&adapter->pdev->dev,
3313 "invalid ethtool speed/duplex setting\n");
3314 goto exit_sset;
3315 }
3316 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
3317 hw->media_type == MEDIA_TYPE_1000M_FULL)
3318 phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN;
3319 else {
3320 switch (hw->media_type) {
3321 case MEDIA_TYPE_100M_FULL:
3322 phy_data =
3323 MII_CR_FULL_DUPLEX | MII_CR_SPEED_100 |
3324 MII_CR_RESET;
3325 break;
3326 case MEDIA_TYPE_100M_HALF:
3327 phy_data = MII_CR_SPEED_100 | MII_CR_RESET;
3328 break;
3329 case MEDIA_TYPE_10M_FULL:
3330 phy_data =
3331 MII_CR_FULL_DUPLEX | MII_CR_SPEED_10 | MII_CR_RESET;
3332 break;
3333 default:
3334 /* MEDIA_TYPE_10M_HALF: */
3335 phy_data = MII_CR_SPEED_10 | MII_CR_RESET;
3336 break;
3337 }
3338 }
3339 atl1_write_phy_reg(hw, MII_BMCR, phy_data);
3340 exit_sset:
3341 if (ret_val)
3342 hw->media_type = old_media_type;
3343
3344 if (netif_running(adapter->netdev)) {
3345 if (netif_msg_link(adapter))
3346 dev_dbg(&adapter->pdev->dev,
3347 "ethtool starting adapter\n");
3348 atl1_up(adapter);
3349 } else if (!ret_val) {
3350 if (netif_msg_link(adapter))
3351 dev_dbg(&adapter->pdev->dev,
3352 "ethtool resetting adapter\n");
3353 atl1_reset(adapter);
3354 }
3355 return ret_val;
3356 }
3357
3358 static void atl1_get_drvinfo(struct net_device *netdev,
3359 struct ethtool_drvinfo *drvinfo)
3360 {
3361 struct atl1_adapter *adapter = netdev_priv(netdev);
3362
3363 strlcpy(drvinfo->driver, ATLX_DRIVER_NAME, sizeof(drvinfo->driver));
3364 strlcpy(drvinfo->version, ATLX_DRIVER_VERSION,
3365 sizeof(drvinfo->version));
3366 strlcpy(drvinfo->bus_info, pci_name(adapter->pdev),
3367 sizeof(drvinfo->bus_info));
3368 drvinfo->eedump_len = ATL1_EEDUMP_LEN;
3369 }
3370
3371 static void atl1_get_wol(struct net_device *netdev,
3372 struct ethtool_wolinfo *wol)
3373 {
3374 struct atl1_adapter *adapter = netdev_priv(netdev);
3375
3376 wol->supported = WAKE_MAGIC;
3377 wol->wolopts = 0;
3378 if (adapter->wol & ATLX_WUFC_MAG)
3379 wol->wolopts |= WAKE_MAGIC;
3380 }
3381
3382 static int atl1_set_wol(struct net_device *netdev,
3383 struct ethtool_wolinfo *wol)
3384 {
3385 struct atl1_adapter *adapter = netdev_priv(netdev);
3386
3387 if (wol->wolopts & (WAKE_PHY | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST |
3388 WAKE_ARP | WAKE_MAGICSECURE))
3389 return -EOPNOTSUPP;
3390 adapter->wol = 0;
3391 if (wol->wolopts & WAKE_MAGIC)
3392 adapter->wol |= ATLX_WUFC_MAG;
3393
3394 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
3395
3396 return 0;
3397 }
3398
3399 static u32 atl1_get_msglevel(struct net_device *netdev)
3400 {
3401 struct atl1_adapter *adapter = netdev_priv(netdev);
3402 return adapter->msg_enable;
3403 }
3404
3405 static void atl1_set_msglevel(struct net_device *netdev, u32 value)
3406 {
3407 struct atl1_adapter *adapter = netdev_priv(netdev);
3408 adapter->msg_enable = value;
3409 }
3410
3411 static int atl1_get_regs_len(struct net_device *netdev)
3412 {
3413 return ATL1_REG_COUNT * sizeof(u32);
3414 }
3415
3416 static void atl1_get_regs(struct net_device *netdev, struct ethtool_regs *regs,
3417 void *p)
3418 {
3419 struct atl1_adapter *adapter = netdev_priv(netdev);
3420 struct atl1_hw *hw = &adapter->hw;
3421 unsigned int i;
3422 u32 *regbuf = p;
3423
3424 for (i = 0; i < ATL1_REG_COUNT; i++) {
3425 /*
3426 * This switch statement avoids reserved regions
3427 * of register space.
3428 */
3429 switch (i) {
3430 case 6 ... 9:
3431 case 14:
3432 case 29 ... 31:
3433 case 34 ... 63:
3434 case 75 ... 127:
3435 case 136 ... 1023:
3436 case 1027 ... 1087:
3437 case 1091 ... 1151:
3438 case 1194 ... 1195:
3439 case 1200 ... 1201:
3440 case 1206 ... 1213:
3441 case 1216 ... 1279:
3442 case 1290 ... 1311:
3443 case 1323 ... 1343:
3444 case 1358 ... 1359:
3445 case 1368 ... 1375:
3446 case 1378 ... 1383:
3447 case 1388 ... 1391:
3448 case 1393 ... 1395:
3449 case 1402 ... 1403:
3450 case 1410 ... 1471:
3451 case 1522 ... 1535:
3452 /* reserved region; don't read it */
3453 regbuf[i] = 0;
3454 break;
3455 default:
3456 /* unreserved region */
3457 regbuf[i] = ioread32(hw->hw_addr + (i * sizeof(u32)));
3458 }
3459 }
3460 }
3461
3462 static void atl1_get_ringparam(struct net_device *netdev,
3463 struct ethtool_ringparam *ring)
3464 {
3465 struct atl1_adapter *adapter = netdev_priv(netdev);
3466 struct atl1_tpd_ring *txdr = &adapter->tpd_ring;
3467 struct atl1_rfd_ring *rxdr = &adapter->rfd_ring;
3468
3469 ring->rx_max_pending = ATL1_MAX_RFD;
3470 ring->tx_max_pending = ATL1_MAX_TPD;
3471 ring->rx_pending = rxdr->count;
3472 ring->tx_pending = txdr->count;
3473 }
3474
3475 static int atl1_set_ringparam(struct net_device *netdev,
3476 struct ethtool_ringparam *ring)
3477 {
3478 struct atl1_adapter *adapter = netdev_priv(netdev);
3479 struct atl1_tpd_ring *tpdr = &adapter->tpd_ring;
3480 struct atl1_rrd_ring *rrdr = &adapter->rrd_ring;
3481 struct atl1_rfd_ring *rfdr = &adapter->rfd_ring;
3482
3483 struct atl1_tpd_ring tpd_old, tpd_new;
3484 struct atl1_rfd_ring rfd_old, rfd_new;
3485 struct atl1_rrd_ring rrd_old, rrd_new;
3486 struct atl1_ring_header rhdr_old, rhdr_new;
3487 struct atl1_smb smb;
3488 struct atl1_cmb cmb;
3489 int err;
3490
3491 tpd_old = adapter->tpd_ring;
3492 rfd_old = adapter->rfd_ring;
3493 rrd_old = adapter->rrd_ring;
3494 rhdr_old = adapter->ring_header;
3495
3496 if (netif_running(adapter->netdev))
3497 atl1_down(adapter);
3498
3499 rfdr->count = (u16) max(ring->rx_pending, (u32) ATL1_MIN_RFD);
3500 rfdr->count = rfdr->count > ATL1_MAX_RFD ? ATL1_MAX_RFD :
3501 rfdr->count;
3502 rfdr->count = (rfdr->count + 3) & ~3;
3503 rrdr->count = rfdr->count;
3504
3505 tpdr->count = (u16) max(ring->tx_pending, (u32) ATL1_MIN_TPD);
3506 tpdr->count = tpdr->count > ATL1_MAX_TPD ? ATL1_MAX_TPD :
3507 tpdr->count;
3508 tpdr->count = (tpdr->count + 3) & ~3;
3509
3510 if (netif_running(adapter->netdev)) {
3511 /* try to get new resources before deleting old */
3512 err = atl1_setup_ring_resources(adapter);
3513 if (err)
3514 goto err_setup_ring;
3515
3516 /*
3517 * save the new, restore the old in order to free it,
3518 * then restore the new back again
3519 */
3520
3521 rfd_new = adapter->rfd_ring;
3522 rrd_new = adapter->rrd_ring;
3523 tpd_new = adapter->tpd_ring;
3524 rhdr_new = adapter->ring_header;
3525 adapter->rfd_ring = rfd_old;
3526 adapter->rrd_ring = rrd_old;
3527 adapter->tpd_ring = tpd_old;
3528 adapter->ring_header = rhdr_old;
3529 /*
3530 * Save SMB and CMB, since atl1_free_ring_resources
3531 * will clear them.
3532 */
3533 smb = adapter->smb;
3534 cmb = adapter->cmb;
3535 atl1_free_ring_resources(adapter);
3536 adapter->rfd_ring = rfd_new;
3537 adapter->rrd_ring = rrd_new;
3538 adapter->tpd_ring = tpd_new;
3539 adapter->ring_header = rhdr_new;
3540 adapter->smb = smb;
3541 adapter->cmb = cmb;
3542
3543 err = atl1_up(adapter);
3544 if (err)
3545 return err;
3546 }
3547 return 0;
3548
3549 err_setup_ring:
3550 adapter->rfd_ring = rfd_old;
3551 adapter->rrd_ring = rrd_old;
3552 adapter->tpd_ring = tpd_old;
3553 adapter->ring_header = rhdr_old;
3554 atl1_up(adapter);
3555 return err;
3556 }
3557
3558 static void atl1_get_pauseparam(struct net_device *netdev,
3559 struct ethtool_pauseparam *epause)
3560 {
3561 struct atl1_adapter *adapter = netdev_priv(netdev);
3562 struct atl1_hw *hw = &adapter->hw;
3563
3564 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
3565 hw->media_type == MEDIA_TYPE_1000M_FULL) {
3566 epause->autoneg = AUTONEG_ENABLE;
3567 } else {
3568 epause->autoneg = AUTONEG_DISABLE;
3569 }
3570 epause->rx_pause = 1;
3571 epause->tx_pause = 1;
3572 }
3573
3574 static int atl1_set_pauseparam(struct net_device *netdev,
3575 struct ethtool_pauseparam *epause)
3576 {
3577 struct atl1_adapter *adapter = netdev_priv(netdev);
3578 struct atl1_hw *hw = &adapter->hw;
3579
3580 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
3581 hw->media_type == MEDIA_TYPE_1000M_FULL) {
3582 epause->autoneg = AUTONEG_ENABLE;
3583 } else {
3584 epause->autoneg = AUTONEG_DISABLE;
3585 }
3586
3587 epause->rx_pause = 1;
3588 epause->tx_pause = 1;
3589
3590 return 0;
3591 }
3592
3593 static void atl1_get_strings(struct net_device *netdev, u32 stringset,
3594 u8 *data)
3595 {
3596 u8 *p = data;
3597 int i;
3598
3599 switch (stringset) {
3600 case ETH_SS_STATS:
3601 for (i = 0; i < ARRAY_SIZE(atl1_gstrings_stats); i++) {
3602 memcpy(p, atl1_gstrings_stats[i].stat_string,
3603 ETH_GSTRING_LEN);
3604 p += ETH_GSTRING_LEN;
3605 }
3606 break;
3607 }
3608 }
3609
3610 static int atl1_nway_reset(struct net_device *netdev)
3611 {
3612 struct atl1_adapter *adapter = netdev_priv(netdev);
3613 struct atl1_hw *hw = &adapter->hw;
3614
3615 if (netif_running(netdev)) {
3616 u16 phy_data;
3617 atl1_down(adapter);
3618
3619 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
3620 hw->media_type == MEDIA_TYPE_1000M_FULL) {
3621 phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN;
3622 } else {
3623 switch (hw->media_type) {
3624 case MEDIA_TYPE_100M_FULL:
3625 phy_data = MII_CR_FULL_DUPLEX |
3626 MII_CR_SPEED_100 | MII_CR_RESET;
3627 break;
3628 case MEDIA_TYPE_100M_HALF:
3629 phy_data = MII_CR_SPEED_100 | MII_CR_RESET;
3630 break;
3631 case MEDIA_TYPE_10M_FULL:
3632 phy_data = MII_CR_FULL_DUPLEX |
3633 MII_CR_SPEED_10 | MII_CR_RESET;
3634 break;
3635 default:
3636 /* MEDIA_TYPE_10M_HALF */
3637 phy_data = MII_CR_SPEED_10 | MII_CR_RESET;
3638 }
3639 }
3640 atl1_write_phy_reg(hw, MII_BMCR, phy_data);
3641 atl1_up(adapter);
3642 }
3643 return 0;
3644 }
3645
3646 static const struct ethtool_ops atl1_ethtool_ops = {
3647 .get_settings = atl1_get_settings,
3648 .set_settings = atl1_set_settings,
3649 .get_drvinfo = atl1_get_drvinfo,
3650 .get_wol = atl1_get_wol,
3651 .set_wol = atl1_set_wol,
3652 .get_msglevel = atl1_get_msglevel,
3653 .set_msglevel = atl1_set_msglevel,
3654 .get_regs_len = atl1_get_regs_len,
3655 .get_regs = atl1_get_regs,
3656 .get_ringparam = atl1_get_ringparam,
3657 .set_ringparam = atl1_set_ringparam,
3658 .get_pauseparam = atl1_get_pauseparam,
3659 .set_pauseparam = atl1_set_pauseparam,
3660 .get_link = ethtool_op_get_link,
3661 .get_strings = atl1_get_strings,
3662 .nway_reset = atl1_nway_reset,
3663 .get_ethtool_stats = atl1_get_ethtool_stats,
3664 .get_sset_count = atl1_get_sset_count,
3665 };