drivers/net/ethernet/chelsio/cxgb/mv88e1xxx.h

   1 /* $Date: 2005/03/07 23:59:05 $ $RCSfile: mv88e1xxx.h,v $ $Revision: 1.13 $ */
   2 #ifndef CHELSIO_MV8E1XXX_H
   3 #define CHELSIO_MV8E1XXX_H
   4
   5 #ifndef BMCR_SPEED1000
   6 # define BMCR_SPEED1000 0x40
   7 #endif
   8
   9 #ifndef ADVERTISE_PAUSE
  10 # define ADVERTISE_PAUSE 0x400
  11 #endif
  12 #ifndef ADVERTISE_PAUSE_ASYM
  13 # define ADVERTISE_PAUSE_ASYM 0x800
  14 #endif
  15
  16 /* Gigabit MII registers */
  17 #define MII_GBCR 9       /* 1000Base-T control register */
  18 #define MII_GBSR 10      /* 1000Base-T status register */
  19
  20 /* 1000Base-T control register fields */
  21 #define GBCR_ADV_1000HALF         0x100
  22 #define GBCR_ADV_1000FULL         0x200
  23 #define GBCR_PREFER_MASTER        0x400
  24 #define GBCR_MANUAL_AS_MASTER     0x800
  25 #define GBCR_MANUAL_CONFIG_ENABLE 0x1000
  26
  27 /* 1000Base-T status register fields */
  28 #define GBSR_LP_1000HALF  0x400
  29 #define GBSR_LP_1000FULL  0x800
  30 #define GBSR_REMOTE_OK    0x1000
  31 #define GBSR_LOCAL_OK     0x2000
  32 #define GBSR_LOCAL_MASTER 0x4000
  33 #define GBSR_MASTER_FAULT 0x8000
  34
  35 /* Marvell PHY interrupt status bits. */
  36 #define MV88E1XXX_INTR_JABBER          0x0001
  37 #define MV88E1XXX_INTR_POLARITY_CHNG   0x0002
  38 #define MV88E1XXX_INTR_ENG_DETECT_CHNG 0x0010
  39 #define MV88E1XXX_INTR_DOWNSHIFT       0x0020
  40 #define MV88E1XXX_INTR_MDI_XOVER_CHNG  0x0040
  41 #define MV88E1XXX_INTR_FIFO_OVER_UNDER 0x0080
  42 #define MV88E1XXX_INTR_FALSE_CARRIER   0x0100
  43 #define MV88E1XXX_INTR_SYMBOL_ERROR    0x0200
  44 #define MV88E1XXX_INTR_LINK_CHNG       0x0400
  45 #define MV88E1XXX_INTR_AUTONEG_DONE    0x0800
  46 #define MV88E1XXX_INTR_PAGE_RECV       0x1000
  47 #define MV88E1XXX_INTR_DUPLEX_CHNG     0x2000
  48 #define MV88E1XXX_INTR_SPEED_CHNG      0x4000
  49 #define MV88E1XXX_INTR_AUTONEG_ERR     0x8000
  50
  51 /* Marvell PHY specific registers. */
  52 #define MV88E1XXX_SPECIFIC_CNTRL_REGISTER               16
  53 #define MV88E1XXX_SPECIFIC_STATUS_REGISTER              17
  54 #define MV88E1XXX_INTERRUPT_ENABLE_REGISTER             18
  55 #define MV88E1XXX_INTERRUPT_STATUS_REGISTER             19
  56 #define MV88E1XXX_EXT_PHY_SPECIFIC_CNTRL_REGISTER       20
  57 #define MV88E1XXX_RECV_ERR_CNTR_REGISTER                21
  58 #define MV88E1XXX_RES_REGISTER                          22
  59 #define MV88E1XXX_GLOBAL_STATUS_REGISTER                23
  60 #define MV88E1XXX_LED_CONTROL_REGISTER                  24
  61 #define MV88E1XXX_MANUAL_LED_OVERRIDE_REGISTER          25
  62 #define MV88E1XXX_EXT_PHY_SPECIFIC_CNTRL_2_REGISTER     26
  63 #define MV88E1XXX_EXT_PHY_SPECIFIC_STATUS_REGISTER      27
  64 #define MV88E1XXX_VIRTUAL_CABLE_TESTER_REGISTER         28
  65 #define MV88E1XXX_EXTENDED_ADDR_REGISTER                29
  66 #define MV88E1XXX_EXTENDED_REGISTER                     30
  67
  68 /* PHY specific control register fields */
  69 #define S_PSCR_MDI_XOVER_MODE    5
  70 #define M_PSCR_MDI_XOVER_MODE    0x3
  71 #define V_PSCR_MDI_XOVER_MODE(x) ((x) << S_PSCR_MDI_XOVER_MODE)
  72 #define G_PSCR_MDI_XOVER_MODE(x) (((x) >> S_PSCR_MDI_XOVER_MODE) & M_PSCR_MDI_XOVER_MODE)
  73
  74 /* Extended PHY specific control register fields */
  75 #define S_DOWNSHIFT_ENABLE 8
  76 #define V_DOWNSHIFT_ENABLE (1 << S_DOWNSHIFT_ENABLE)
  77
  78 #define S_DOWNSHIFT_CNT    9
  79 #define M_DOWNSHIFT_CNT    0x7
  80 #define V_DOWNSHIFT_CNT(x) ((x) << S_DOWNSHIFT_CNT)
  81 #define G_DOWNSHIFT_CNT(x) (((x) >> S_DOWNSHIFT_CNT) & M_DOWNSHIFT_CNT)
  82
  83 /* PHY specific status register fields */
  84 #define S_PSSR_JABBER 0
  85 #define V_PSSR_JABBER (1 << S_PSSR_JABBER)
  86
  87 #define S_PSSR_POLARITY 1
  88 #define V_PSSR_POLARITY (1 << S_PSSR_POLARITY)
  89
  90 #define S_PSSR_RX_PAUSE 2
  91 #define V_PSSR_RX_PAUSE (1 << S_PSSR_RX_PAUSE)
  92
  93 #define S_PSSR_TX_PAUSE 3
  94 #define V_PSSR_TX_PAUSE (1 << S_PSSR_TX_PAUSE)
  95
  96 #define S_PSSR_ENERGY_DETECT 4
  97 #define V_PSSR_ENERGY_DETECT (1 << S_PSSR_ENERGY_DETECT)
  98
  99 #define S_PSSR_DOWNSHIFT_STATUS 5
 100 #define V_PSSR_DOWNSHIFT_STATUS (1 << S_PSSR_DOWNSHIFT_STATUS)
 101
 102 #define S_PSSR_MDI 6
 103 #define V_PSSR_MDI (1 << S_PSSR_MDI)
 104
 105 #define S_PSSR_CABLE_LEN    7
 106 #define M_PSSR_CABLE_LEN    0x7
 107 #define V_PSSR_CABLE_LEN(x) ((x) << S_PSSR_CABLE_LEN)
 108 #define G_PSSR_CABLE_LEN(x) (((x) >> S_PSSR_CABLE_LEN) & M_PSSR_CABLE_LEN)
 109
 110 #define S_PSSR_LINK 10
 111 #define V_PSSR_LINK (1 << S_PSSR_LINK)
 112
 113 #define S_PSSR_STATUS_RESOLVED 11
 114 #define V_PSSR_STATUS_RESOLVED (1 << S_PSSR_STATUS_RESOLVED)
 115
 116 #define S_PSSR_PAGE_RECEIVED 12
 117 #define V_PSSR_PAGE_RECEIVED (1 << S_PSSR_PAGE_RECEIVED)
 118
 119 #define S_PSSR_DUPLEX 13
 120 #define V_PSSR_DUPLEX (1 << S_PSSR_DUPLEX)
 121
 122 #define S_PSSR_SPEED    14
 123 #define M_PSSR_SPEED    0x3
 124 #define V_PSSR_SPEED(x) ((x) << S_PSSR_SPEED)
 125 #define G_PSSR_SPEED(x) (((x) >> S_PSSR_SPEED) & M_PSSR_SPEED)
 126
 127 #endif