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spi-topcliff-pch: add recovery processing in case wait-event timeout
[zen-stable.git] / drivers / net / ethernet / stmicro / stmmac / stmmac_main.c
blob6ee593a55a64d9eabbf3238bfba28102257b8cc5
1 /*******************************************************************************
2 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
3 ST Ethernet IPs are built around a Synopsys IP Core.
4
5 Copyright(C) 2007-2011 STMicroelectronics Ltd
6
7 This program is free software; you can redistribute it and/or modify it
8 under the terms and conditions of the GNU General Public License,
9 version 2, as published by the Free Software Foundation.
10
11 This program is distributed in the hope it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 more details.
15
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc.,
18 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19
20 The full GNU General Public License is included in this distribution in
21 the file called "COPYING".
22
23 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
24
25 Documentation available at:
26 http://www.stlinux.com
27 Support available at:
28 https://bugzilla.stlinux.com/
29 *******************************************************************************/
30
31 #include <linux/kernel.h>
32 #include <linux/interrupt.h>
33 #include <linux/ip.h>
34 #include <linux/tcp.h>
35 #include <linux/skbuff.h>
36 #include <linux/ethtool.h>
37 #include <linux/if_ether.h>
38 #include <linux/crc32.h>
39 #include <linux/mii.h>
40 #include <linux/if.h>
41 #include <linux/if_vlan.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/slab.h>
44 #include <linux/prefetch.h>
45 #ifdef CONFIG_STMMAC_DEBUG_FS
46 #include <linux/debugfs.h>
47 #include <linux/seq_file.h>
48 #endif
49 #include "stmmac.h"
50
51 #undef STMMAC_DEBUG
52 /*#define STMMAC_DEBUG*/
53 #ifdef STMMAC_DEBUG
54 #define DBG(nlevel, klevel, fmt, args...) \
55 ((void)(netif_msg_##nlevel(priv) && \
56 printk(KERN_##klevel fmt, ## args)))
57 #else
58 #define DBG(nlevel, klevel, fmt, args...) do { } while (0)
59 #endif
60
61 #undef STMMAC_RX_DEBUG
62 /*#define STMMAC_RX_DEBUG*/
63 #ifdef STMMAC_RX_DEBUG
64 #define RX_DBG(fmt, args...) printk(fmt, ## args)
65 #else
66 #define RX_DBG(fmt, args...) do { } while (0)
67 #endif
68
69 #undef STMMAC_XMIT_DEBUG
70 /*#define STMMAC_XMIT_DEBUG*/
71 #ifdef STMMAC_TX_DEBUG
72 #define TX_DBG(fmt, args...) printk(fmt, ## args)
73 #else
74 #define TX_DBG(fmt, args...) do { } while (0)
75 #endif
76
77 #define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x)
78 #define JUMBO_LEN 9000
79
80 /* Module parameters */
81 #define TX_TIMEO 5000 /* default 5 seconds */
82 static int watchdog = TX_TIMEO;
83 module_param(watchdog, int, S_IRUGO | S_IWUSR);
84 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds");
85
86 static int debug = -1; /* -1: default, 0: no output, 16: all */
87 module_param(debug, int, S_IRUGO | S_IWUSR);
88 MODULE_PARM_DESC(debug, "Message Level (0: no output, 16: all)");
89
90 int phyaddr = -1;
91 module_param(phyaddr, int, S_IRUGO);
92 MODULE_PARM_DESC(phyaddr, "Physical device address");
93
94 #define DMA_TX_SIZE 256
95 static int dma_txsize = DMA_TX_SIZE;
96 module_param(dma_txsize, int, S_IRUGO | S_IWUSR);
97 MODULE_PARM_DESC(dma_txsize, "Number of descriptors in the TX list");
98
99 #define DMA_RX_SIZE 256
100 static int dma_rxsize = DMA_RX_SIZE;
101 module_param(dma_rxsize, int, S_IRUGO | S_IWUSR);
102 MODULE_PARM_DESC(dma_rxsize, "Number of descriptors in the RX list");
103
104 static int flow_ctrl = FLOW_OFF;
105 module_param(flow_ctrl, int, S_IRUGO | S_IWUSR);
106 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]");
107
108 static int pause = PAUSE_TIME;
109 module_param(pause, int, S_IRUGO | S_IWUSR);
110 MODULE_PARM_DESC(pause, "Flow Control Pause Time");
111
112 #define TC_DEFAULT 64
113 static int tc = TC_DEFAULT;
114 module_param(tc, int, S_IRUGO | S_IWUSR);
115 MODULE_PARM_DESC(tc, "DMA threshold control value");
116
117 /* Pay attention to tune this parameter; take care of both
118 * hardware capability and network stabitily/performance impact.
119 * Many tests showed that ~4ms latency seems to be good enough. */
120 #ifdef CONFIG_STMMAC_TIMER
121 #define DEFAULT_PERIODIC_RATE 256
122 static int tmrate = DEFAULT_PERIODIC_RATE;
123 module_param(tmrate, int, S_IRUGO | S_IWUSR);
124 MODULE_PARM_DESC(tmrate, "External timer freq. (default: 256Hz)");
125 #endif
126
127 #define DMA_BUFFER_SIZE BUF_SIZE_2KiB
128 static int buf_sz = DMA_BUFFER_SIZE;
129 module_param(buf_sz, int, S_IRUGO | S_IWUSR);
130 MODULE_PARM_DESC(buf_sz, "DMA buffer size");
131
132 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
133 NETIF_MSG_LINK | NETIF_MSG_IFUP |
134 NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
135
136 static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
137
138 #ifdef CONFIG_STMMAC_DEBUG_FS
139 static int stmmac_init_fs(struct net_device *dev);
140 static void stmmac_exit_fs(void);
141 #endif
142
143 /**
144 * stmmac_verify_args - verify the driver parameters.
145 * Description: it verifies if some wrong parameter is passed to the driver.
146 * Note that wrong parameters are replaced with the default values.
147 */
148 static void stmmac_verify_args(void)
149 {
150 if (unlikely(watchdog < 0))
151 watchdog = TX_TIMEO;
152 if (unlikely(dma_rxsize < 0))
153 dma_rxsize = DMA_RX_SIZE;
154 if (unlikely(dma_txsize < 0))
155 dma_txsize = DMA_TX_SIZE;
156 if (unlikely((buf_sz < DMA_BUFFER_SIZE) || (buf_sz > BUF_SIZE_16KiB)))
157 buf_sz = DMA_BUFFER_SIZE;
158 if (unlikely(flow_ctrl > 1))
159 flow_ctrl = FLOW_AUTO;
160 else if (likely(flow_ctrl < 0))
161 flow_ctrl = FLOW_OFF;
162 if (unlikely((pause < 0) || (pause > 0xffff)))
163 pause = PAUSE_TIME;
164 }
165
166 #if defined(STMMAC_XMIT_DEBUG) || defined(STMMAC_RX_DEBUG)
167 static void print_pkt(unsigned char *buf, int len)
168 {
169 int j;
170 pr_info("len = %d byte, buf addr: 0x%p", len, buf);
171 for (j = 0; j < len; j++) {
172 if ((j % 16) == 0)
173 pr_info("\n %03x:", j);
174 pr_info(" %02x", buf[j]);
175 }
176 pr_info("\n");
177 }
178 #endif
179
180 /* minimum number of free TX descriptors required to wake up TX process */
181 #define STMMAC_TX_THRESH(x) (x->dma_tx_size/4)
182
183 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv)
184 {
185 return priv->dirty_tx + priv->dma_tx_size - priv->cur_tx - 1;
186 }
187
188 /* On some ST platforms, some HW system configuraton registers have to be
189 * set according to the link speed negotiated.
190 */
191 static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv *priv)
192 {
193 struct phy_device *phydev = priv->phydev;
194
195 if (likely(priv->plat->fix_mac_speed))
196 priv->plat->fix_mac_speed(priv->plat->bsp_priv,
197 phydev->speed);
198 }
199
200 /**
201 * stmmac_adjust_link
202 * @dev: net device structure
203 * Description: it adjusts the link parameters.
204 */
205 static void stmmac_adjust_link(struct net_device *dev)
206 {
207 struct stmmac_priv *priv = netdev_priv(dev);
208 struct phy_device *phydev = priv->phydev;
209 unsigned long flags;
210 int new_state = 0;
211 unsigned int fc = priv->flow_ctrl, pause_time = priv->pause;
212
213 if (phydev == NULL)
214 return;
215
216 DBG(probe, DEBUG, "stmmac_adjust_link: called. address %d link %d\n",
217 phydev->addr, phydev->link);
218
219 spin_lock_irqsave(&priv->lock, flags);
220 if (phydev->link) {
221 u32 ctrl = readl(priv->ioaddr + MAC_CTRL_REG);
222
223 /* Now we make sure that we can be in full duplex mode.
224 * If not, we operate in half-duplex mode. */
225 if (phydev->duplex != priv->oldduplex) {
226 new_state = 1;
227 if (!(phydev->duplex))
228 ctrl &= ~priv->hw->link.duplex;
229 else
230 ctrl |= priv->hw->link.duplex;
231 priv->oldduplex = phydev->duplex;
232 }
233 /* Flow Control operation */
234 if (phydev->pause)
235 priv->hw->mac->flow_ctrl(priv->ioaddr, phydev->duplex,
236 fc, pause_time);
237
238 if (phydev->speed != priv->speed) {
239 new_state = 1;
240 switch (phydev->speed) {
241 case 1000:
242 if (likely(priv->plat->has_gmac))
243 ctrl &= ~priv->hw->link.port;
244 stmmac_hw_fix_mac_speed(priv);
245 break;
246 case 100:
247 case 10:
248 if (priv->plat->has_gmac) {
249 ctrl |= priv->hw->link.port;
250 if (phydev->speed == SPEED_100) {
251 ctrl |= priv->hw->link.speed;
252 } else {
253 ctrl &= ~(priv->hw->link.speed);
254 }
255 } else {
256 ctrl &= ~priv->hw->link.port;
257 }
258 stmmac_hw_fix_mac_speed(priv);
259 break;
260 default:
261 if (netif_msg_link(priv))
262 pr_warning("%s: Speed (%d) is not 10"
263 " or 100!\n", dev->name, phydev->speed);
264 break;
265 }
266
267 priv->speed = phydev->speed;
268 }
269
270 writel(ctrl, priv->ioaddr + MAC_CTRL_REG);
271
272 if (!priv->oldlink) {
273 new_state = 1;
274 priv->oldlink = 1;
275 }
276 } else if (priv->oldlink) {
277 new_state = 1;
278 priv->oldlink = 0;
279 priv->speed = 0;
280 priv->oldduplex = -1;
281 }
282
283 if (new_state && netif_msg_link(priv))
284 phy_print_status(phydev);
285
286 spin_unlock_irqrestore(&priv->lock, flags);
287
288 DBG(probe, DEBUG, "stmmac_adjust_link: exiting\n");
289 }
290
291 /**
292 * stmmac_init_phy - PHY initialization
293 * @dev: net device structure
294 * Description: it initializes the driver's PHY state, and attaches the PHY
295 * to the mac driver.
296 * Return value:
297 * 0 on success
298 */
299 static int stmmac_init_phy(struct net_device *dev)
300 {
301 struct stmmac_priv *priv = netdev_priv(dev);
302 struct phy_device *phydev;
303 char phy_id[MII_BUS_ID_SIZE + 3];
304 char bus_id[MII_BUS_ID_SIZE];
305 int interface = priv->plat->interface;
306 priv->oldlink = 0;
307 priv->speed = 0;
308 priv->oldduplex = -1;
309
310 snprintf(bus_id, MII_BUS_ID_SIZE, "stmmac-%x", priv->plat->bus_id);
311 snprintf(phy_id, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id,
312 priv->plat->phy_addr);
313 pr_debug("stmmac_init_phy: trying to attach to %s\n", phy_id);
314
315 phydev = phy_connect(dev, phy_id, &stmmac_adjust_link, 0, interface);
316
317 if (IS_ERR(phydev)) {
318 pr_err("%s: Could not attach to PHY\n", dev->name);
319 return PTR_ERR(phydev);
320 }
321
322 /* Stop Advertising 1000BASE Capability if interface is not GMII */
323 if ((interface == PHY_INTERFACE_MODE_MII) ||
324 (interface == PHY_INTERFACE_MODE_RMII))
325 phydev->advertising &= ~(SUPPORTED_1000baseT_Half |
326 SUPPORTED_1000baseT_Full);
327
328 /*
329 * Broken HW is sometimes missing the pull-up resistor on the
330 * MDIO line, which results in reads to non-existent devices returning
331 * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent
332 * device as well.
333 * Note: phydev->phy_id is the result of reading the UID PHY registers.
334 */
335 if (phydev->phy_id == 0) {
336 phy_disconnect(phydev);
337 return -ENODEV;
338 }
339 pr_debug("stmmac_init_phy: %s: attached to PHY (UID 0x%x)"
340 " Link = %d\n", dev->name, phydev->phy_id, phydev->link);
341
342 priv->phydev = phydev;
343
344 return 0;
345 }
346
347 /**
348 * display_ring
349 * @p: pointer to the ring.
350 * @size: size of the ring.
351 * Description: display all the descriptors within the ring.
352 */
353 static void display_ring(struct dma_desc *p, int size)
354 {
355 struct tmp_s {
356 u64 a;
357 unsigned int b;
358 unsigned int c;
359 };
360 int i;
361 for (i = 0; i < size; i++) {
362 struct tmp_s *x = (struct tmp_s *)(p + i);
363 pr_info("\t%d [0x%x]: DES0=0x%x DES1=0x%x BUF1=0x%x BUF2=0x%x",
364 i, (unsigned int)virt_to_phys(&p[i]),
365 (unsigned int)(x->a), (unsigned int)((x->a) >> 32),
366 x->b, x->c);
367 pr_info("\n");
368 }
369 }
370
371 static int stmmac_set_bfsize(int mtu, int bufsize)
372 {
373 int ret = bufsize;
374
375 if (mtu >= BUF_SIZE_4KiB)
376 ret = BUF_SIZE_8KiB;
377 else if (mtu >= BUF_SIZE_2KiB)
378 ret = BUF_SIZE_4KiB;
379 else if (mtu >= DMA_BUFFER_SIZE)
380 ret = BUF_SIZE_2KiB;
381 else
382 ret = DMA_BUFFER_SIZE;
383
384 return ret;
385 }
386
387 /**
388 * init_dma_desc_rings - init the RX/TX descriptor rings
389 * @dev: net device structure
390 * Description: this function initializes the DMA RX/TX descriptors
391 * and allocates the socket buffers. It suppors the chained and ring
392 * modes.
393 */
394 static void init_dma_desc_rings(struct net_device *dev)
395 {
396 int i;
397 struct stmmac_priv *priv = netdev_priv(dev);
398 struct sk_buff *skb;
399 unsigned int txsize = priv->dma_tx_size;
400 unsigned int rxsize = priv->dma_rx_size;
401 unsigned int bfsize;
402 int dis_ic = 0;
403 int des3_as_data_buf = 0;
404
405 /* Set the max buffer size according to the DESC mode
406 * and the MTU. Note that RING mode allows 16KiB bsize. */
407 bfsize = priv->hw->ring->set_16kib_bfsize(dev->mtu);
408
409 if (bfsize == BUF_SIZE_16KiB)
410 des3_as_data_buf = 1;
411 else
412 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz);
413
414 #ifdef CONFIG_STMMAC_TIMER
415 /* Disable interrupts on completion for the reception if timer is on */
416 if (likely(priv->tm->enable))
417 dis_ic = 1;
418 #endif
419
420 DBG(probe, INFO, "stmmac: txsize %d, rxsize %d, bfsize %d\n",
421 txsize, rxsize, bfsize);
422
423 priv->rx_skbuff_dma = kmalloc(rxsize * sizeof(dma_addr_t), GFP_KERNEL);
424 priv->rx_skbuff =
425 kmalloc(sizeof(struct sk_buff *) * rxsize, GFP_KERNEL);
426 priv->dma_rx =
427 (struct dma_desc *)dma_alloc_coherent(priv->device,
428 rxsize *
429 sizeof(struct dma_desc),
430 &priv->dma_rx_phy,
431 GFP_KERNEL);
432 priv->tx_skbuff = kmalloc(sizeof(struct sk_buff *) * txsize,
433 GFP_KERNEL);
434 priv->dma_tx =
435 (struct dma_desc *)dma_alloc_coherent(priv->device,
436 txsize *
437 sizeof(struct dma_desc),
438 &priv->dma_tx_phy,
439 GFP_KERNEL);
440
441 if ((priv->dma_rx == NULL) || (priv->dma_tx == NULL)) {
442 pr_err("%s:ERROR allocating the DMA Tx/Rx desc\n", __func__);
443 return;
444 }
445
446 DBG(probe, INFO, "stmmac (%s) DMA desc: virt addr (Rx %p, "
447 "Tx %p)\n\tDMA phy addr (Rx 0x%08x, Tx 0x%08x)\n",
448 dev->name, priv->dma_rx, priv->dma_tx,
449 (unsigned int)priv->dma_rx_phy, (unsigned int)priv->dma_tx_phy);
450
451 /* RX INITIALIZATION */
452 DBG(probe, INFO, "stmmac: SKB addresses:\n"
453 "skb\t\tskb data\tdma data\n");
454
455 for (i = 0; i < rxsize; i++) {
456 struct dma_desc *p = priv->dma_rx + i;
457
458 skb = __netdev_alloc_skb(dev, bfsize + NET_IP_ALIGN,
459 GFP_KERNEL);
460 if (unlikely(skb == NULL)) {
461 pr_err("%s: Rx init fails; skb is NULL\n", __func__);
462 break;
463 }
464 skb_reserve(skb, NET_IP_ALIGN);
465 priv->rx_skbuff[i] = skb;
466 priv->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data,
467 bfsize, DMA_FROM_DEVICE);
468
469 p->des2 = priv->rx_skbuff_dma[i];
470
471 priv->hw->ring->init_desc3(des3_as_data_buf, p);
472
473 DBG(probe, INFO, "[%p]\t[%p]\t[%x]\n", priv->rx_skbuff[i],
474 priv->rx_skbuff[i]->data, priv->rx_skbuff_dma[i]);
475 }
476 priv->cur_rx = 0;
477 priv->dirty_rx = (unsigned int)(i - rxsize);
478 priv->dma_buf_sz = bfsize;
479 buf_sz = bfsize;
480
481 /* TX INITIALIZATION */
482 for (i = 0; i < txsize; i++) {
483 priv->tx_skbuff[i] = NULL;
484 priv->dma_tx[i].des2 = 0;
485 }
486
487 /* In case of Chained mode this sets the des3 to the next
488 * element in the chain */
489 priv->hw->ring->init_dma_chain(priv->dma_rx, priv->dma_rx_phy, rxsize);
490 priv->hw->ring->init_dma_chain(priv->dma_tx, priv->dma_tx_phy, txsize);
491
492 priv->dirty_tx = 0;
493 priv->cur_tx = 0;
494
495 /* Clear the Rx/Tx descriptors */
496 priv->hw->desc->init_rx_desc(priv->dma_rx, rxsize, dis_ic);
497 priv->hw->desc->init_tx_desc(priv->dma_tx, txsize);
498
499 if (netif_msg_hw(priv)) {
500 pr_info("RX descriptor ring:\n");
501 display_ring(priv->dma_rx, rxsize);
502 pr_info("TX descriptor ring:\n");
503 display_ring(priv->dma_tx, txsize);
504 }
505 }
506
507 static void dma_free_rx_skbufs(struct stmmac_priv *priv)
508 {
509 int i;
510
511 for (i = 0; i < priv->dma_rx_size; i++) {
512 if (priv->rx_skbuff[i]) {
513 dma_unmap_single(priv->device, priv->rx_skbuff_dma[i],
514 priv->dma_buf_sz, DMA_FROM_DEVICE);
515 dev_kfree_skb_any(priv->rx_skbuff[i]);
516 }
517 priv->rx_skbuff[i] = NULL;
518 }
519 }
520
521 static void dma_free_tx_skbufs(struct stmmac_priv *priv)
522 {
523 int i;
524
525 for (i = 0; i < priv->dma_tx_size; i++) {
526 if (priv->tx_skbuff[i] != NULL) {
527 struct dma_desc *p = priv->dma_tx + i;
528 if (p->des2)
529 dma_unmap_single(priv->device, p->des2,
530 priv->hw->desc->get_tx_len(p),
531 DMA_TO_DEVICE);
532 dev_kfree_skb_any(priv->tx_skbuff[i]);
533 priv->tx_skbuff[i] = NULL;
534 }
535 }
536 }
537
538 static void free_dma_desc_resources(struct stmmac_priv *priv)
539 {
540 /* Release the DMA TX/RX socket buffers */
541 dma_free_rx_skbufs(priv);
542 dma_free_tx_skbufs(priv);
543
544 /* Free the region of consistent memory previously allocated for
545 * the DMA */
546 dma_free_coherent(priv->device,
547 priv->dma_tx_size * sizeof(struct dma_desc),
548 priv->dma_tx, priv->dma_tx_phy);
549 dma_free_coherent(priv->device,
550 priv->dma_rx_size * sizeof(struct dma_desc),
551 priv->dma_rx, priv->dma_rx_phy);
552 kfree(priv->rx_skbuff_dma);
553 kfree(priv->rx_skbuff);
554 kfree(priv->tx_skbuff);
555 }
556
557 /**
558 * stmmac_dma_operation_mode - HW DMA operation mode
559 * @priv : pointer to the private device structure.
560 * Description: it sets the DMA operation mode: tx/rx DMA thresholds
561 * or Store-And-Forward capability.
562 */
563 static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
564 {
565 if (likely(priv->plat->force_sf_dma_mode ||
566 ((priv->plat->tx_coe) && (!priv->no_csum_insertion)))) {
567 /*
568 * In case of GMAC, SF mode can be enabled
569 * to perform the TX COE in HW. This depends on:
570 * 1) TX COE if actually supported
571 * 2) There is no bugged Jumbo frame support
572 * that needs to not insert csum in the TDES.
573 */
574 priv->hw->dma->dma_mode(priv->ioaddr,
575 SF_DMA_MODE, SF_DMA_MODE);
576 tc = SF_DMA_MODE;
577 } else
578 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE);
579 }
580
581 /**
582 * stmmac_tx:
583 * @priv: private driver structure
584 * Description: it reclaims resources after transmission completes.
585 */
586 static void stmmac_tx(struct stmmac_priv *priv)
587 {
588 unsigned int txsize = priv->dma_tx_size;
589
590 spin_lock(&priv->tx_lock);
591
592 while (priv->dirty_tx != priv->cur_tx) {
593 int last;
594 unsigned int entry = priv->dirty_tx % txsize;
595 struct sk_buff *skb = priv->tx_skbuff[entry];
596 struct dma_desc *p = priv->dma_tx + entry;
597
598 /* Check if the descriptor is owned by the DMA. */
599 if (priv->hw->desc->get_tx_owner(p))
600 break;
601
602 /* Verify tx error by looking at the last segment */
603 last = priv->hw->desc->get_tx_ls(p);
604 if (likely(last)) {
605 int tx_error =
606 priv->hw->desc->tx_status(&priv->dev->stats,
607 &priv->xstats, p,
608 priv->ioaddr);
609 if (likely(tx_error == 0)) {
610 priv->dev->stats.tx_packets++;
611 priv->xstats.tx_pkt_n++;
612 } else
613 priv->dev->stats.tx_errors++;
614 }
615 TX_DBG("%s: curr %d, dirty %d\n", __func__,
616 priv->cur_tx, priv->dirty_tx);
617
618 if (likely(p->des2))
619 dma_unmap_single(priv->device, p->des2,
620 priv->hw->desc->get_tx_len(p),
621 DMA_TO_DEVICE);
622 priv->hw->ring->clean_desc3(p);
623
624 if (likely(skb != NULL)) {
625 /*
626 * If there's room in the queue (limit it to size)
627 * we add this skb back into the pool,
628 * if it's the right size.
629 */
630 if ((skb_queue_len(&priv->rx_recycle) <
631 priv->dma_rx_size) &&
632 skb_recycle_check(skb, priv->dma_buf_sz))
633 __skb_queue_head(&priv->rx_recycle, skb);
634 else
635 dev_kfree_skb(skb);
636
637 priv->tx_skbuff[entry] = NULL;
638 }
639
640 priv->hw->desc->release_tx_desc(p);
641
642 entry = (++priv->dirty_tx) % txsize;
643 }
644 if (unlikely(netif_queue_stopped(priv->dev) &&
645 stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv))) {
646 netif_tx_lock(priv->dev);
647 if (netif_queue_stopped(priv->dev) &&
648 stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv)) {
649 TX_DBG("%s: restart transmit\n", __func__);
650 netif_wake_queue(priv->dev);
651 }
652 netif_tx_unlock(priv->dev);
653 }
654 spin_unlock(&priv->tx_lock);
655 }
656
657 static inline void stmmac_enable_irq(struct stmmac_priv *priv)
658 {
659 #ifdef CONFIG_STMMAC_TIMER
660 if (likely(priv->tm->enable))
661 priv->tm->timer_start(tmrate);
662 else
663 #endif
664 priv->hw->dma->enable_dma_irq(priv->ioaddr);
665 }
666
667 static inline void stmmac_disable_irq(struct stmmac_priv *priv)
668 {
669 #ifdef CONFIG_STMMAC_TIMER
670 if (likely(priv->tm->enable))
671 priv->tm->timer_stop();
672 else
673 #endif
674 priv->hw->dma->disable_dma_irq(priv->ioaddr);
675 }
676
677 static int stmmac_has_work(struct stmmac_priv *priv)
678 {
679 unsigned int has_work = 0;
680 int rxret, tx_work = 0;
681
682 rxret = priv->hw->desc->get_rx_owner(priv->dma_rx +
683 (priv->cur_rx % priv->dma_rx_size));
684
685 if (priv->dirty_tx != priv->cur_tx)
686 tx_work = 1;
687
688 if (likely(!rxret || tx_work))
689 has_work = 1;
690
691 return has_work;
692 }
693
694 static inline void _stmmac_schedule(struct stmmac_priv *priv)
695 {
696 if (likely(stmmac_has_work(priv))) {
697 stmmac_disable_irq(priv);
698 napi_schedule(&priv->napi);
699 }
700 }
701
702 #ifdef CONFIG_STMMAC_TIMER
703 void stmmac_schedule(struct net_device *dev)
704 {
705 struct stmmac_priv *priv = netdev_priv(dev);
706
707 priv->xstats.sched_timer_n++;
708
709 _stmmac_schedule(priv);
710 }
711
712 static void stmmac_no_timer_started(unsigned int x)
713 {;
714 };
715
716 static void stmmac_no_timer_stopped(void)
717 {;
718 };
719 #endif
720
721 /**
722 * stmmac_tx_err:
723 * @priv: pointer to the private device structure
724 * Description: it cleans the descriptors and restarts the transmission
725 * in case of errors.
726 */
727 static void stmmac_tx_err(struct stmmac_priv *priv)
728 {
729 netif_stop_queue(priv->dev);
730
731 priv->hw->dma->stop_tx(priv->ioaddr);
732 dma_free_tx_skbufs(priv);
733 priv->hw->desc->init_tx_desc(priv->dma_tx, priv->dma_tx_size);
734 priv->dirty_tx = 0;
735 priv->cur_tx = 0;
736 priv->hw->dma->start_tx(priv->ioaddr);
737
738 priv->dev->stats.tx_errors++;
739 netif_wake_queue(priv->dev);
740 }
741
742
743 static void stmmac_dma_interrupt(struct stmmac_priv *priv)
744 {
745 int status;
746
747 status = priv->hw->dma->dma_interrupt(priv->ioaddr, &priv->xstats);
748 if (likely(status == handle_tx_rx))
749 _stmmac_schedule(priv);
750
751 else if (unlikely(status == tx_hard_error_bump_tc)) {
752 /* Try to bump up the dma threshold on this failure */
753 if (unlikely(tc != SF_DMA_MODE) && (tc <= 256)) {
754 tc += 64;
755 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE);
756 priv->xstats.threshold = tc;
757 }
758 } else if (unlikely(status == tx_hard_error))
759 stmmac_tx_err(priv);
760 }
761
762 static void stmmac_mmc_setup(struct stmmac_priv *priv)
763 {
764 unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET |
765 MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET;
766
767 /* Mask MMC irq, counters are managed in SW and registers
768 * are cleared on each READ eventually. */
769 dwmac_mmc_intr_all_mask(priv->ioaddr);
770
771 if (priv->dma_cap.rmon) {
772 dwmac_mmc_ctrl(priv->ioaddr, mode);
773 memset(&priv->mmc, 0, sizeof(struct stmmac_counters));
774 } else
775 pr_info(" No MAC Management Counters available\n");
776 }
777
778 static u32 stmmac_get_synopsys_id(struct stmmac_priv *priv)
779 {
780 u32 hwid = priv->hw->synopsys_uid;
781
782 /* Only check valid Synopsys Id because old MAC chips
783 * have no HW registers where get the ID */
784 if (likely(hwid)) {
785 u32 uid = ((hwid & 0x0000ff00) >> 8);
786 u32 synid = (hwid & 0x000000ff);
787
788 pr_info("stmmac - user ID: 0x%x, Synopsys ID: 0x%x\n",
789 uid, synid);
790
791 return synid;
792 }
793 return 0;
794 }
795
796 /**
797 * stmmac_selec_desc_mode
798 * @dev : device pointer
799 * Description: select the Enhanced/Alternate or Normal descriptors */
800 static void stmmac_selec_desc_mode(struct stmmac_priv *priv)
801 {
802 if (priv->plat->enh_desc) {
803 pr_info(" Enhanced/Alternate descriptors\n");
804 priv->hw->desc = &enh_desc_ops;
805 } else {
806 pr_info(" Normal descriptors\n");
807 priv->hw->desc = &ndesc_ops;
808 }
809 }
810
811 /**
812 * stmmac_get_hw_features
813 * @priv : private device pointer
814 * Description:
815 * new GMAC chip generations have a new register to indicate the
816 * presence of the optional feature/functions.
817 * This can be also used to override the value passed through the
818 * platform and necessary for old MAC10/100 and GMAC chips.
819 */
820 static int stmmac_get_hw_features(struct stmmac_priv *priv)
821 {
822 u32 hw_cap = 0;
823
824 if (priv->hw->dma->get_hw_feature) {
825 hw_cap = priv->hw->dma->get_hw_feature(priv->ioaddr);
826
827 priv->dma_cap.mbps_10_100 = (hw_cap & DMA_HW_FEAT_MIISEL);
828 priv->dma_cap.mbps_1000 = (hw_cap & DMA_HW_FEAT_GMIISEL) >> 1;
829 priv->dma_cap.half_duplex = (hw_cap & DMA_HW_FEAT_HDSEL) >> 2;
830 priv->dma_cap.hash_filter = (hw_cap & DMA_HW_FEAT_HASHSEL) >> 4;
831 priv->dma_cap.multi_addr =
832 (hw_cap & DMA_HW_FEAT_ADDMACADRSEL) >> 5;
833 priv->dma_cap.pcs = (hw_cap & DMA_HW_FEAT_PCSSEL) >> 6;
834 priv->dma_cap.sma_mdio = (hw_cap & DMA_HW_FEAT_SMASEL) >> 8;
835 priv->dma_cap.pmt_remote_wake_up =
836 (hw_cap & DMA_HW_FEAT_RWKSEL) >> 9;
837 priv->dma_cap.pmt_magic_frame =
838 (hw_cap & DMA_HW_FEAT_MGKSEL) >> 10;
839 /* MMC */
840 priv->dma_cap.rmon = (hw_cap & DMA_HW_FEAT_MMCSEL) >> 11;
841 /* IEEE 1588-2002*/
842 priv->dma_cap.time_stamp =
843 (hw_cap & DMA_HW_FEAT_TSVER1SEL) >> 12;
844 /* IEEE 1588-2008*/
845 priv->dma_cap.atime_stamp =
846 (hw_cap & DMA_HW_FEAT_TSVER2SEL) >> 13;
847 /* 802.3az - Energy-Efficient Ethernet (EEE) */
848 priv->dma_cap.eee = (hw_cap & DMA_HW_FEAT_EEESEL) >> 14;
849 priv->dma_cap.av = (hw_cap & DMA_HW_FEAT_AVSEL) >> 15;
850 /* TX and RX csum */
851 priv->dma_cap.tx_coe = (hw_cap & DMA_HW_FEAT_TXCOESEL) >> 16;
852 priv->dma_cap.rx_coe_type1 =
853 (hw_cap & DMA_HW_FEAT_RXTYP1COE) >> 17;
854 priv->dma_cap.rx_coe_type2 =
855 (hw_cap & DMA_HW_FEAT_RXTYP2COE) >> 18;
856 priv->dma_cap.rxfifo_over_2048 =
857 (hw_cap & DMA_HW_FEAT_RXFIFOSIZE) >> 19;
858 /* TX and RX number of channels */
859 priv->dma_cap.number_rx_channel =
860 (hw_cap & DMA_HW_FEAT_RXCHCNT) >> 20;
861 priv->dma_cap.number_tx_channel =
862 (hw_cap & DMA_HW_FEAT_TXCHCNT) >> 22;
863 /* Alternate (enhanced) DESC mode*/
864 priv->dma_cap.enh_desc =
865 (hw_cap & DMA_HW_FEAT_ENHDESSEL) >> 24;
866
867 }
868
869 return hw_cap;
870 }
871
872 static void stmmac_check_ether_addr(struct stmmac_priv *priv)
873 {
874 /* verify if the MAC address is valid, in case of failures it
875 * generates a random MAC address */
876 if (!is_valid_ether_addr(priv->dev->dev_addr)) {
877 priv->hw->mac->get_umac_addr((void __iomem *)
878 priv->dev->base_addr,
879 priv->dev->dev_addr, 0);
880 if (!is_valid_ether_addr(priv->dev->dev_addr))
881 random_ether_addr(priv->dev->dev_addr);
882 }
883 pr_warning("%s: device MAC address %pM\n", priv->dev->name,
884 priv->dev->dev_addr);
885 }
886
887 /**
888 * stmmac_open - open entry point of the driver
889 * @dev : pointer to the device structure.
890 * Description:
891 * This function is the open entry point of the driver.
892 * Return value:
893 * 0 on success and an appropriate (-)ve integer as defined in errno.h
894 * file on failure.
895 */
896 static int stmmac_open(struct net_device *dev)
897 {
898 struct stmmac_priv *priv = netdev_priv(dev);
899 int ret;
900
901 stmmac_check_ether_addr(priv);
902
903 /* MDIO bus Registration */
904 ret = stmmac_mdio_register(dev);
905 if (ret < 0) {
906 pr_debug("%s: MDIO bus (id: %d) registration failed",
907 __func__, priv->plat->bus_id);
908 return ret;
909 }
910
911 #ifdef CONFIG_STMMAC_TIMER
912 priv->tm = kzalloc(sizeof(struct stmmac_timer *), GFP_KERNEL);
913 if (unlikely(priv->tm == NULL)) {
914 pr_err("%s: ERROR: timer memory alloc failed\n", __func__);
915 return -ENOMEM;
916 }
917 priv->tm->freq = tmrate;
918
919 /* Test if the external timer can be actually used.
920 * In case of failure continue without timer. */
921 if (unlikely((stmmac_open_ext_timer(dev, priv->tm)) < 0)) {
922 pr_warning("stmmaceth: cannot attach the external timer.\n");
923 priv->tm->freq = 0;
924 priv->tm->timer_start = stmmac_no_timer_started;
925 priv->tm->timer_stop = stmmac_no_timer_stopped;
926 } else
927 priv->tm->enable = 1;
928 #endif
929 ret = stmmac_init_phy(dev);
930 if (unlikely(ret)) {
931 pr_err("%s: Cannot attach to PHY (error: %d)\n", __func__, ret);
932 goto open_error;
933 }
934
935 /* Create and initialize the TX/RX descriptors chains. */
936 priv->dma_tx_size = STMMAC_ALIGN(dma_txsize);
937 priv->dma_rx_size = STMMAC_ALIGN(dma_rxsize);
938 priv->dma_buf_sz = STMMAC_ALIGN(buf_sz);
939 init_dma_desc_rings(dev);
940
941 /* DMA initialization and SW reset */
942 ret = priv->hw->dma->init(priv->ioaddr, priv->plat->pbl,
943 priv->dma_tx_phy, priv->dma_rx_phy);
944 if (ret < 0) {
945 pr_err("%s: DMA initialization failed\n", __func__);
946 goto open_error;
947 }
948
949 /* Copy the MAC addr into the HW */
950 priv->hw->mac->set_umac_addr(priv->ioaddr, dev->dev_addr, 0);
951
952 /* If required, perform hw setup of the bus. */
953 if (priv->plat->bus_setup)
954 priv->plat->bus_setup(priv->ioaddr);
955
956 /* Initialize the MAC Core */
957 priv->hw->mac->core_init(priv->ioaddr);
958
959 /* Request the IRQ lines */
960 ret = request_irq(dev->irq, stmmac_interrupt,
961 IRQF_SHARED, dev->name, dev);
962 if (unlikely(ret < 0)) {
963 pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n",
964 __func__, dev->irq, ret);
965 goto open_error;
966 }
967
968 /* Request the Wake IRQ in case of another line is used for WoL */
969 if (priv->wol_irq != dev->irq) {
970 ret = request_irq(priv->wol_irq, stmmac_interrupt,
971 IRQF_SHARED, dev->name, dev);
972 if (unlikely(ret < 0)) {
973 pr_err("%s: ERROR: allocating the ext WoL IRQ %d "
974 "(error: %d)\n", __func__, priv->wol_irq, ret);
975 goto open_error_wolirq;
976 }
977 }
978
979 /* Enable the MAC Rx/Tx */
980 stmmac_set_mac(priv->ioaddr, true);
981
982 /* Set the HW DMA mode and the COE */
983 stmmac_dma_operation_mode(priv);
984
985 /* Extra statistics */
986 memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
987 priv->xstats.threshold = tc;
988
989 stmmac_mmc_setup(priv);
990
991 #ifdef CONFIG_STMMAC_DEBUG_FS
992 ret = stmmac_init_fs(dev);
993 if (ret < 0)
994 pr_warning("%s: failed debugFS registration\n", __func__);
995 #endif
996 /* Start the ball rolling... */
997 DBG(probe, DEBUG, "%s: DMA RX/TX processes started...\n", dev->name);
998 priv->hw->dma->start_tx(priv->ioaddr);
999 priv->hw->dma->start_rx(priv->ioaddr);
1000
1001 #ifdef CONFIG_STMMAC_TIMER
1002 priv->tm->timer_start(tmrate);
1003 #endif
1004
1005 /* Dump DMA/MAC registers */
1006 if (netif_msg_hw(priv)) {
1007 priv->hw->mac->dump_regs(priv->ioaddr);
1008 priv->hw->dma->dump_regs(priv->ioaddr);
1009 }
1010
1011 if (priv->phydev)
1012 phy_start(priv->phydev);
1013
1014 napi_enable(&priv->napi);
1015 skb_queue_head_init(&priv->rx_recycle);
1016 netif_start_queue(dev);
1017
1018 return 0;
1019
1020 open_error_wolirq:
1021 free_irq(dev->irq, dev);
1022
1023 open_error:
1024 #ifdef CONFIG_STMMAC_TIMER
1025 kfree(priv->tm);
1026 #endif
1027 if (priv->phydev)
1028 phy_disconnect(priv->phydev);
1029
1030 return ret;
1031 }
1032
1033 /**
1034 * stmmac_release - close entry point of the driver
1035 * @dev : device pointer.
1036 * Description:
1037 * This is the stop entry point of the driver.
1038 */
1039 static int stmmac_release(struct net_device *dev)
1040 {
1041 struct stmmac_priv *priv = netdev_priv(dev);
1042
1043 /* Stop and disconnect the PHY */
1044 if (priv->phydev) {
1045 phy_stop(priv->phydev);
1046 phy_disconnect(priv->phydev);
1047 priv->phydev = NULL;
1048 }
1049
1050 netif_stop_queue(dev);
1051
1052 #ifdef CONFIG_STMMAC_TIMER
1053 /* Stop and release the timer */
1054 stmmac_close_ext_timer();
1055 if (priv->tm != NULL)
1056 kfree(priv->tm);
1057 #endif
1058 napi_disable(&priv->napi);
1059 skb_queue_purge(&priv->rx_recycle);
1060
1061 /* Free the IRQ lines */
1062 free_irq(dev->irq, dev);
1063 if (priv->wol_irq != dev->irq)
1064 free_irq(priv->wol_irq, dev);
1065
1066 /* Stop TX/RX DMA and clear the descriptors */
1067 priv->hw->dma->stop_tx(priv->ioaddr);
1068 priv->hw->dma->stop_rx(priv->ioaddr);
1069
1070 /* Release and free the Rx/Tx resources */
1071 free_dma_desc_resources(priv);
1072
1073 /* Disable the MAC Rx/Tx */
1074 stmmac_set_mac(priv->ioaddr, false);
1075
1076 netif_carrier_off(dev);
1077
1078 #ifdef CONFIG_STMMAC_DEBUG_FS
1079 stmmac_exit_fs();
1080 #endif
1081 stmmac_mdio_unregister(dev);
1082
1083 return 0;
1084 }
1085
1086 /**
1087 * stmmac_xmit:
1088 * @skb : the socket buffer
1089 * @dev : device pointer
1090 * Description : Tx entry point of the driver.
1091 */
1092 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
1093 {
1094 struct stmmac_priv *priv = netdev_priv(dev);
1095 unsigned int txsize = priv->dma_tx_size;
1096 unsigned int entry;
1097 int i, csum_insertion = 0;
1098 int nfrags = skb_shinfo(skb)->nr_frags;
1099 struct dma_desc *desc, *first;
1100 unsigned int nopaged_len = skb_headlen(skb);
1101
1102 if (unlikely(stmmac_tx_avail(priv) < nfrags + 1)) {
1103 if (!netif_queue_stopped(dev)) {
1104 netif_stop_queue(dev);
1105 /* This is a hard error, log it. */
1106 pr_err("%s: BUG! Tx Ring full when queue awake\n",
1107 __func__);
1108 }
1109 return NETDEV_TX_BUSY;
1110 }
1111
1112 spin_lock(&priv->tx_lock);
1113
1114 entry = priv->cur_tx % txsize;
1115
1116 #ifdef STMMAC_XMIT_DEBUG
1117 if ((skb->len > ETH_FRAME_LEN) || nfrags)
1118 pr_info("stmmac xmit:\n"
1119 "\tskb addr %p - len: %d - nopaged_len: %d\n"
1120 "\tn_frags: %d - ip_summed: %d - %s gso\n",
1121 skb, skb->len, nopaged_len, nfrags, skb->ip_summed,
1122 !skb_is_gso(skb) ? "isn't" : "is");
1123 #endif
1124
1125 csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL);
1126
1127 desc = priv->dma_tx + entry;
1128 first = desc;
1129
1130 #ifdef STMMAC_XMIT_DEBUG
1131 if ((nfrags > 0) || (skb->len > ETH_FRAME_LEN))
1132 pr_debug("stmmac xmit: skb len: %d, nopaged_len: %d,\n"
1133 "\t\tn_frags: %d, ip_summed: %d\n",
1134 skb->len, nopaged_len, nfrags, skb->ip_summed);
1135 #endif
1136 priv->tx_skbuff[entry] = skb;
1137
1138 if (priv->hw->ring->is_jumbo_frm(skb->len, priv->plat->enh_desc)) {
1139 entry = priv->hw->ring->jumbo_frm(priv, skb, csum_insertion);
1140 desc = priv->dma_tx + entry;
1141 } else {
1142 desc->des2 = dma_map_single(priv->device, skb->data,
1143 nopaged_len, DMA_TO_DEVICE);
1144 priv->hw->desc->prepare_tx_desc(desc, 1, nopaged_len,
1145 csum_insertion);
1146 }
1147
1148 for (i = 0; i < nfrags; i++) {
1149 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1150 int len = skb_frag_size(frag);
1151
1152 entry = (++priv->cur_tx) % txsize;
1153 desc = priv->dma_tx + entry;
1154
1155 TX_DBG("\t[entry %d] segment len: %d\n", entry, len);
1156 desc->des2 = skb_frag_dma_map(priv->device, frag, 0, len,
1157 DMA_TO_DEVICE);
1158 priv->tx_skbuff[entry] = NULL;
1159 priv->hw->desc->prepare_tx_desc(desc, 0, len, csum_insertion);
1160 wmb();
1161 priv->hw->desc->set_tx_owner(desc);
1162 }
1163
1164 /* Interrupt on completition only for the latest segment */
1165 priv->hw->desc->close_tx_desc(desc);
1166
1167 #ifdef CONFIG_STMMAC_TIMER
1168 /* Clean IC while using timer */
1169 if (likely(priv->tm->enable))
1170 priv->hw->desc->clear_tx_ic(desc);
1171 #endif
1172
1173 wmb();
1174
1175 /* To avoid raise condition */
1176 priv->hw->desc->set_tx_owner(first);
1177
1178 priv->cur_tx++;
1179
1180 #ifdef STMMAC_XMIT_DEBUG
1181 if (netif_msg_pktdata(priv)) {
1182 pr_info("stmmac xmit: current=%d, dirty=%d, entry=%d, "
1183 "first=%p, nfrags=%d\n",
1184 (priv->cur_tx % txsize), (priv->dirty_tx % txsize),
1185 entry, first, nfrags);
1186 display_ring(priv->dma_tx, txsize);
1187 pr_info(">>> frame to be transmitted: ");
1188 print_pkt(skb->data, skb->len);
1189 }
1190 #endif
1191 if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) {
1192 TX_DBG("%s: stop transmitted packets\n", __func__);
1193 netif_stop_queue(dev);
1194 }
1195
1196 dev->stats.tx_bytes += skb->len;
1197
1198 skb_tx_timestamp(skb);
1199
1200 priv->hw->dma->enable_dma_transmission(priv->ioaddr);
1201
1202 spin_unlock(&priv->tx_lock);
1203
1204 return NETDEV_TX_OK;
1205 }
1206
1207 static inline void stmmac_rx_refill(struct stmmac_priv *priv)
1208 {
1209 unsigned int rxsize = priv->dma_rx_size;
1210 int bfsize = priv->dma_buf_sz;
1211 struct dma_desc *p = priv->dma_rx;
1212
1213 for (; priv->cur_rx - priv->dirty_rx > 0; priv->dirty_rx++) {
1214 unsigned int entry = priv->dirty_rx % rxsize;
1215 if (likely(priv->rx_skbuff[entry] == NULL)) {
1216 struct sk_buff *skb;
1217
1218 skb = __skb_dequeue(&priv->rx_recycle);
1219 if (skb == NULL)
1220 skb = netdev_alloc_skb_ip_align(priv->dev,
1221 bfsize);
1222
1223 if (unlikely(skb == NULL))
1224 break;
1225
1226 priv->rx_skbuff[entry] = skb;
1227 priv->rx_skbuff_dma[entry] =
1228 dma_map_single(priv->device, skb->data, bfsize,
1229 DMA_FROM_DEVICE);
1230
1231 (p + entry)->des2 = priv->rx_skbuff_dma[entry];
1232
1233 if (unlikely(priv->plat->has_gmac))
1234 priv->hw->ring->refill_desc3(bfsize, p + entry);
1235
1236 RX_DBG(KERN_INFO "\trefill entry #%d\n", entry);
1237 }
1238 wmb();
1239 priv->hw->desc->set_rx_owner(p + entry);
1240 }
1241 }
1242
1243 static int stmmac_rx(struct stmmac_priv *priv, int limit)
1244 {
1245 unsigned int rxsize = priv->dma_rx_size;
1246 unsigned int entry = priv->cur_rx % rxsize;
1247 unsigned int next_entry;
1248 unsigned int count = 0;
1249 struct dma_desc *p = priv->dma_rx + entry;
1250 struct dma_desc *p_next;
1251
1252 #ifdef STMMAC_RX_DEBUG
1253 if (netif_msg_hw(priv)) {
1254 pr_debug(">>> stmmac_rx: descriptor ring:\n");
1255 display_ring(priv->dma_rx, rxsize);
1256 }
1257 #endif
1258 count = 0;
1259 while (!priv->hw->desc->get_rx_owner(p)) {
1260 int status;
1261
1262 if (count >= limit)
1263 break;
1264
1265 count++;
1266
1267 next_entry = (++priv->cur_rx) % rxsize;
1268 p_next = priv->dma_rx + next_entry;
1269 prefetch(p_next);
1270
1271 /* read the status of the incoming frame */
1272 status = (priv->hw->desc->rx_status(&priv->dev->stats,
1273 &priv->xstats, p));
1274 if (unlikely(status == discard_frame))
1275 priv->dev->stats.rx_errors++;
1276 else {
1277 struct sk_buff *skb;
1278 int frame_len;
1279
1280 frame_len = priv->hw->desc->get_rx_frame_len(p);
1281 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
1282 * Type frames (LLC/LLC-SNAP) */
1283 if (unlikely(status != llc_snap))
1284 frame_len -= ETH_FCS_LEN;
1285 #ifdef STMMAC_RX_DEBUG
1286 if (frame_len > ETH_FRAME_LEN)
1287 pr_debug("\tRX frame size %d, COE status: %d\n",
1288 frame_len, status);
1289
1290 if (netif_msg_hw(priv))
1291 pr_debug("\tdesc: %p [entry %d] buff=0x%x\n",
1292 p, entry, p->des2);
1293 #endif
1294 skb = priv->rx_skbuff[entry];
1295 if (unlikely(!skb)) {
1296 pr_err("%s: Inconsistent Rx descriptor chain\n",
1297 priv->dev->name);
1298 priv->dev->stats.rx_dropped++;
1299 break;
1300 }
1301 prefetch(skb->data - NET_IP_ALIGN);
1302 priv->rx_skbuff[entry] = NULL;
1303
1304 skb_put(skb, frame_len);
1305 dma_unmap_single(priv->device,
1306 priv->rx_skbuff_dma[entry],
1307 priv->dma_buf_sz, DMA_FROM_DEVICE);
1308 #ifdef STMMAC_RX_DEBUG
1309 if (netif_msg_pktdata(priv)) {
1310 pr_info(" frame received (%dbytes)", frame_len);
1311 print_pkt(skb->data, frame_len);
1312 }
1313 #endif
1314 skb->protocol = eth_type_trans(skb, priv->dev);
1315
1316 if (unlikely(!priv->rx_coe)) {
1317 /* No RX COE for old mac10/100 devices */
1318 skb_checksum_none_assert(skb);
1319 netif_receive_skb(skb);
1320 } else {
1321 skb->ip_summed = CHECKSUM_UNNECESSARY;
1322 napi_gro_receive(&priv->napi, skb);
1323 }
1324
1325 priv->dev->stats.rx_packets++;
1326 priv->dev->stats.rx_bytes += frame_len;
1327 }
1328 entry = next_entry;
1329 p = p_next; /* use prefetched values */
1330 }
1331
1332 stmmac_rx_refill(priv);
1333
1334 priv->xstats.rx_pkt_n += count;
1335
1336 return count;
1337 }
1338
1339 /**
1340 * stmmac_poll - stmmac poll method (NAPI)
1341 * @napi : pointer to the napi structure.
1342 * @budget : maximum number of packets that the current CPU can receive from
1343 * all interfaces.
1344 * Description :
1345 * This function implements the the reception process.
1346 * Also it runs the TX completion thread
1347 */
1348 static int stmmac_poll(struct napi_struct *napi, int budget)
1349 {
1350 struct stmmac_priv *priv = container_of(napi, struct stmmac_priv, napi);
1351 int work_done = 0;
1352
1353 priv->xstats.poll_n++;
1354 stmmac_tx(priv);
1355 work_done = stmmac_rx(priv, budget);
1356
1357 if (work_done < budget) {
1358 napi_complete(napi);
1359 stmmac_enable_irq(priv);
1360 }
1361 return work_done;
1362 }
1363
1364 /**
1365 * stmmac_tx_timeout
1366 * @dev : Pointer to net device structure
1367 * Description: this function is called when a packet transmission fails to
1368 * complete within a reasonable tmrate. The driver will mark the error in the
1369 * netdev structure and arrange for the device to be reset to a sane state
1370 * in order to transmit a new packet.
1371 */
1372 static void stmmac_tx_timeout(struct net_device *dev)
1373 {
1374 struct stmmac_priv *priv = netdev_priv(dev);
1375
1376 /* Clear Tx resources and restart transmitting again */
1377 stmmac_tx_err(priv);
1378 }
1379
1380 /* Configuration changes (passed on by ifconfig) */
1381 static int stmmac_config(struct net_device *dev, struct ifmap *map)
1382 {
1383 if (dev->flags & IFF_UP) /* can't act on a running interface */
1384 return -EBUSY;
1385
1386 /* Don't allow changing the I/O address */
1387 if (map->base_addr != dev->base_addr) {
1388 pr_warning("%s: can't change I/O address\n", dev->name);
1389 return -EOPNOTSUPP;
1390 }
1391
1392 /* Don't allow changing the IRQ */
1393 if (map->irq != dev->irq) {
1394 pr_warning("%s: can't change IRQ number %d\n",
1395 dev->name, dev->irq);
1396 return -EOPNOTSUPP;
1397 }
1398
1399 /* ignore other fields */
1400 return 0;
1401 }
1402
1403 /**
1404 * stmmac_set_rx_mode - entry point for multicast addressing
1405 * @dev : pointer to the device structure
1406 * Description:
1407 * This function is a driver entry point which gets called by the kernel
1408 * whenever multicast addresses must be enabled/disabled.
1409 * Return value:
1410 * void.
1411 */
1412 static void stmmac_set_rx_mode(struct net_device *dev)
1413 {
1414 struct stmmac_priv *priv = netdev_priv(dev);
1415
1416 spin_lock(&priv->lock);
1417 priv->hw->mac->set_filter(dev);
1418 spin_unlock(&priv->lock);
1419 }
1420
1421 /**
1422 * stmmac_change_mtu - entry point to change MTU size for the device.
1423 * @dev : device pointer.
1424 * @new_mtu : the new MTU size for the device.
1425 * Description: the Maximum Transfer Unit (MTU) is used by the network layer
1426 * to drive packet transmission. Ethernet has an MTU of 1500 octets
1427 * (ETH_DATA_LEN). This value can be changed with ifconfig.
1428 * Return value:
1429 * 0 on success and an appropriate (-)ve integer as defined in errno.h
1430 * file on failure.
1431 */
1432 static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
1433 {
1434 struct stmmac_priv *priv = netdev_priv(dev);
1435 int max_mtu;
1436
1437 if (netif_running(dev)) {
1438 pr_err("%s: must be stopped to change its MTU\n", dev->name);
1439 return -EBUSY;
1440 }
1441
1442 if (priv->plat->enh_desc)
1443 max_mtu = JUMBO_LEN;
1444 else
1445 max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN);
1446
1447 if ((new_mtu < 46) || (new_mtu > max_mtu)) {
1448 pr_err("%s: invalid MTU, max MTU is: %d\n", dev->name, max_mtu);
1449 return -EINVAL;
1450 }
1451
1452 dev->mtu = new_mtu;
1453 netdev_update_features(dev);
1454
1455 return 0;
1456 }
1457
1458 static netdev_features_t stmmac_fix_features(struct net_device *dev,
1459 netdev_features_t features)
1460 {
1461 struct stmmac_priv *priv = netdev_priv(dev);
1462
1463 if (!priv->rx_coe)
1464 features &= ~NETIF_F_RXCSUM;
1465 if (!priv->plat->tx_coe)
1466 features &= ~NETIF_F_ALL_CSUM;
1467
1468 /* Some GMAC devices have a bugged Jumbo frame support that
1469 * needs to have the Tx COE disabled for oversized frames
1470 * (due to limited buffer sizes). In this case we disable
1471 * the TX csum insertionin the TDES and not use SF. */
1472 if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN))
1473 features &= ~NETIF_F_ALL_CSUM;
1474
1475 return features;
1476 }
1477
1478 static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
1479 {
1480 struct net_device *dev = (struct net_device *)dev_id;
1481 struct stmmac_priv *priv = netdev_priv(dev);
1482
1483 if (unlikely(!dev)) {
1484 pr_err("%s: invalid dev pointer\n", __func__);
1485 return IRQ_NONE;
1486 }
1487
1488 if (priv->plat->has_gmac)
1489 /* To handle GMAC own interrupts */
1490 priv->hw->mac->host_irq_status((void __iomem *) dev->base_addr);
1491
1492 stmmac_dma_interrupt(priv);
1493
1494 return IRQ_HANDLED;
1495 }
1496
1497 #ifdef CONFIG_NET_POLL_CONTROLLER
1498 /* Polling receive - used by NETCONSOLE and other diagnostic tools
1499 * to allow network I/O with interrupts disabled. */
1500 static void stmmac_poll_controller(struct net_device *dev)
1501 {
1502 disable_irq(dev->irq);
1503 stmmac_interrupt(dev->irq, dev);
1504 enable_irq(dev->irq);
1505 }
1506 #endif
1507
1508 /**
1509 * stmmac_ioctl - Entry point for the Ioctl
1510 * @dev: Device pointer.
1511 * @rq: An IOCTL specefic structure, that can contain a pointer to
1512 * a proprietary structure used to pass information to the driver.
1513 * @cmd: IOCTL command
1514 * Description:
1515 * Currently there are no special functionality supported in IOCTL, just the
1516 * phy_mii_ioctl(...) can be invoked.
1517 */
1518 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1519 {
1520 struct stmmac_priv *priv = netdev_priv(dev);
1521 int ret;
1522
1523 if (!netif_running(dev))
1524 return -EINVAL;
1525
1526 if (!priv->phydev)
1527 return -EINVAL;
1528
1529 ret = phy_mii_ioctl(priv->phydev, rq, cmd);
1530
1531 return ret;
1532 }
1533
1534 #ifdef CONFIG_STMMAC_DEBUG_FS
1535 static struct dentry *stmmac_fs_dir;
1536 static struct dentry *stmmac_rings_status;
1537 static struct dentry *stmmac_dma_cap;
1538
1539 static int stmmac_sysfs_ring_read(struct seq_file *seq, void *v)
1540 {
1541 struct tmp_s {
1542 u64 a;
1543 unsigned int b;
1544 unsigned int c;
1545 };
1546 int i;
1547 struct net_device *dev = seq->private;
1548 struct stmmac_priv *priv = netdev_priv(dev);
1549
1550 seq_printf(seq, "=======================\n");
1551 seq_printf(seq, " RX descriptor ring\n");
1552 seq_printf(seq, "=======================\n");
1553
1554 for (i = 0; i < priv->dma_rx_size; i++) {
1555 struct tmp_s *x = (struct tmp_s *)(priv->dma_rx + i);
1556 seq_printf(seq, "[%d] DES0=0x%x DES1=0x%x BUF1=0x%x BUF2=0x%x",
1557 i, (unsigned int)(x->a),
1558 (unsigned int)((x->a) >> 32), x->b, x->c);
1559 seq_printf(seq, "\n");
1560 }
1561
1562 seq_printf(seq, "\n");
1563 seq_printf(seq, "=======================\n");
1564 seq_printf(seq, " TX descriptor ring\n");
1565 seq_printf(seq, "=======================\n");
1566
1567 for (i = 0; i < priv->dma_tx_size; i++) {
1568 struct tmp_s *x = (struct tmp_s *)(priv->dma_tx + i);
1569 seq_printf(seq, "[%d] DES0=0x%x DES1=0x%x BUF1=0x%x BUF2=0x%x",
1570 i, (unsigned int)(x->a),
1571 (unsigned int)((x->a) >> 32), x->b, x->c);
1572 seq_printf(seq, "\n");
1573 }
1574
1575 return 0;
1576 }
1577
1578 static int stmmac_sysfs_ring_open(struct inode *inode, struct file *file)
1579 {
1580 return single_open(file, stmmac_sysfs_ring_read, inode->i_private);
1581 }
1582
1583 static const struct file_operations stmmac_rings_status_fops = {
1584 .owner = THIS_MODULE,
1585 .open = stmmac_sysfs_ring_open,
1586 .read = seq_read,
1587 .llseek = seq_lseek,
1588 .release = seq_release,
1589 };
1590
1591 static int stmmac_sysfs_dma_cap_read(struct seq_file *seq, void *v)
1592 {
1593 struct net_device *dev = seq->private;
1594 struct stmmac_priv *priv = netdev_priv(dev);
1595
1596 if (!priv->hw_cap_support) {
1597 seq_printf(seq, "DMA HW features not supported\n");
1598 return 0;
1599 }
1600
1601 seq_printf(seq, "==============================\n");
1602 seq_printf(seq, "\tDMA HW features\n");
1603 seq_printf(seq, "==============================\n");
1604
1605 seq_printf(seq, "\t10/100 Mbps %s\n",
1606 (priv->dma_cap.mbps_10_100) ? "Y" : "N");
1607 seq_printf(seq, "\t1000 Mbps %s\n",
1608 (priv->dma_cap.mbps_1000) ? "Y" : "N");
1609 seq_printf(seq, "\tHalf duple %s\n",
1610 (priv->dma_cap.half_duplex) ? "Y" : "N");
1611 seq_printf(seq, "\tHash Filter: %s\n",
1612 (priv->dma_cap.hash_filter) ? "Y" : "N");
1613 seq_printf(seq, "\tMultiple MAC address registers: %s\n",
1614 (priv->dma_cap.multi_addr) ? "Y" : "N");
1615 seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfatces): %s\n",
1616 (priv->dma_cap.pcs) ? "Y" : "N");
1617 seq_printf(seq, "\tSMA (MDIO) Interface: %s\n",
1618 (priv->dma_cap.sma_mdio) ? "Y" : "N");
1619 seq_printf(seq, "\tPMT Remote wake up: %s\n",
1620 (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N");
1621 seq_printf(seq, "\tPMT Magic Frame: %s\n",
1622 (priv->dma_cap.pmt_magic_frame) ? "Y" : "N");
1623 seq_printf(seq, "\tRMON module: %s\n",
1624 (priv->dma_cap.rmon) ? "Y" : "N");
1625 seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n",
1626 (priv->dma_cap.time_stamp) ? "Y" : "N");
1627 seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp:%s\n",
1628 (priv->dma_cap.atime_stamp) ? "Y" : "N");
1629 seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE) %s\n",
1630 (priv->dma_cap.eee) ? "Y" : "N");
1631 seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N");
1632 seq_printf(seq, "\tChecksum Offload in TX: %s\n",
1633 (priv->dma_cap.tx_coe) ? "Y" : "N");
1634 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n",
1635 (priv->dma_cap.rx_coe_type1) ? "Y" : "N");
1636 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n",
1637 (priv->dma_cap.rx_coe_type2) ? "Y" : "N");
1638 seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n",
1639 (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N");
1640 seq_printf(seq, "\tNumber of Additional RX channel: %d\n",
1641 priv->dma_cap.number_rx_channel);
1642 seq_printf(seq, "\tNumber of Additional TX channel: %d\n",
1643 priv->dma_cap.number_tx_channel);
1644 seq_printf(seq, "\tEnhanced descriptors: %s\n",
1645 (priv->dma_cap.enh_desc) ? "Y" : "N");
1646
1647 return 0;
1648 }
1649
1650 static int stmmac_sysfs_dma_cap_open(struct inode *inode, struct file *file)
1651 {
1652 return single_open(file, stmmac_sysfs_dma_cap_read, inode->i_private);
1653 }
1654
1655 static const struct file_operations stmmac_dma_cap_fops = {
1656 .owner = THIS_MODULE,
1657 .open = stmmac_sysfs_dma_cap_open,
1658 .read = seq_read,
1659 .llseek = seq_lseek,
1660 .release = seq_release,
1661 };
1662
1663 static int stmmac_init_fs(struct net_device *dev)
1664 {
1665 /* Create debugfs entries */
1666 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL);
1667
1668 if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) {
1669 pr_err("ERROR %s, debugfs create directory failed\n",
1670 STMMAC_RESOURCE_NAME);
1671
1672 return -ENOMEM;
1673 }
1674
1675 /* Entry to report DMA RX/TX rings */
1676 stmmac_rings_status = debugfs_create_file("descriptors_status",
1677 S_IRUGO, stmmac_fs_dir, dev,
1678 &stmmac_rings_status_fops);
1679
1680 if (!stmmac_rings_status || IS_ERR(stmmac_rings_status)) {
1681 pr_info("ERROR creating stmmac ring debugfs file\n");
1682 debugfs_remove(stmmac_fs_dir);
1683
1684 return -ENOMEM;
1685 }
1686
1687 /* Entry to report the DMA HW features */
1688 stmmac_dma_cap = debugfs_create_file("dma_cap", S_IRUGO, stmmac_fs_dir,
1689 dev, &stmmac_dma_cap_fops);
1690
1691 if (!stmmac_dma_cap || IS_ERR(stmmac_dma_cap)) {
1692 pr_info("ERROR creating stmmac MMC debugfs file\n");
1693 debugfs_remove(stmmac_rings_status);
1694 debugfs_remove(stmmac_fs_dir);
1695
1696 return -ENOMEM;
1697 }
1698
1699 return 0;
1700 }
1701
1702 static void stmmac_exit_fs(void)
1703 {
1704 debugfs_remove(stmmac_rings_status);
1705 debugfs_remove(stmmac_dma_cap);
1706 debugfs_remove(stmmac_fs_dir);
1707 }
1708 #endif /* CONFIG_STMMAC_DEBUG_FS */
1709
1710 static const struct net_device_ops stmmac_netdev_ops = {
1711 .ndo_open = stmmac_open,
1712 .ndo_start_xmit = stmmac_xmit,
1713 .ndo_stop = stmmac_release,
1714 .ndo_change_mtu = stmmac_change_mtu,
1715 .ndo_fix_features = stmmac_fix_features,
1716 .ndo_set_rx_mode = stmmac_set_rx_mode,
1717 .ndo_tx_timeout = stmmac_tx_timeout,
1718 .ndo_do_ioctl = stmmac_ioctl,
1719 .ndo_set_config = stmmac_config,
1720 #ifdef CONFIG_NET_POLL_CONTROLLER
1721 .ndo_poll_controller = stmmac_poll_controller,
1722 #endif
1723 .ndo_set_mac_address = eth_mac_addr,
1724 };
1725
1726 /**
1727 * stmmac_hw_init - Init the MAC device
1728 * @priv : pointer to the private device structure.
1729 * Description: this function detects which MAC device
1730 * (GMAC/MAC10-100) has to attached, checks the HW capability
1731 * (if supported) and sets the driver's features (for example
1732 * to use the ring or chaine mode or support the normal/enh
1733 * descriptor structure).
1734 */
1735 static int stmmac_hw_init(struct stmmac_priv *priv)
1736 {
1737 int ret = 0;
1738 struct mac_device_info *mac;
1739
1740 /* Identify the MAC HW device */
1741 if (priv->plat->has_gmac)
1742 mac = dwmac1000_setup(priv->ioaddr);
1743 else
1744 mac = dwmac100_setup(priv->ioaddr);
1745 if (!mac)
1746 return -ENOMEM;
1747
1748 priv->hw = mac;
1749
1750 /* To use the chained or ring mode */
1751 priv->hw->ring = &ring_mode_ops;
1752
1753 /* Get and dump the chip ID */
1754 stmmac_get_synopsys_id(priv);
1755
1756 /* Get the HW capability (new GMAC newer than 3.50a) */
1757 priv->hw_cap_support = stmmac_get_hw_features(priv);
1758 if (priv->hw_cap_support) {
1759 pr_info(" DMA HW capability register supported");
1760
1761 /* We can override some gmac/dma configuration fields: e.g.
1762 * enh_desc, tx_coe (e.g. that are passed through the
1763 * platform) with the values from the HW capability
1764 * register (if supported).
1765 */
1766 priv->plat->enh_desc = priv->dma_cap.enh_desc;
1767 priv->plat->tx_coe = priv->dma_cap.tx_coe;
1768 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up;
1769 } else
1770 pr_info(" No HW DMA feature register supported");
1771
1772 /* Select the enhnaced/normal descriptor structures */
1773 stmmac_selec_desc_mode(priv);
1774
1775 priv->rx_coe = priv->hw->mac->rx_coe(priv->ioaddr);
1776 if (priv->rx_coe)
1777 pr_info(" RX Checksum Offload Engine supported\n");
1778 if (priv->plat->tx_coe)
1779 pr_info(" TX Checksum insertion supported\n");
1780
1781 if (priv->plat->pmt) {
1782 pr_info(" Wake-Up On Lan supported\n");
1783 device_set_wakeup_capable(priv->device, 1);
1784 }
1785
1786 return ret;
1787 }
1788
1789 /**
1790 * stmmac_dvr_probe
1791 * @device: device pointer
1792 * Description: this is the main probe function used to
1793 * call the alloc_etherdev, allocate the priv structure.
1794 */
1795 struct stmmac_priv *stmmac_dvr_probe(struct device *device,
1796 struct plat_stmmacenet_data *plat_dat,
1797 void __iomem *addr)
1798 {
1799 int ret = 0;
1800 struct net_device *ndev = NULL;
1801 struct stmmac_priv *priv;
1802
1803 ndev = alloc_etherdev(sizeof(struct stmmac_priv));
1804 if (!ndev) {
1805 pr_err("%s: ERROR: allocating the device\n", __func__);
1806 return NULL;
1807 }
1808
1809 SET_NETDEV_DEV(ndev, device);
1810
1811 priv = netdev_priv(ndev);
1812 priv->device = device;
1813 priv->dev = ndev;
1814
1815 ether_setup(ndev);
1816
1817 stmmac_set_ethtool_ops(ndev);
1818 priv->pause = pause;
1819 priv->plat = plat_dat;
1820 priv->ioaddr = addr;
1821 priv->dev->base_addr = (unsigned long)addr;
1822
1823 /* Verify driver arguments */
1824 stmmac_verify_args();
1825
1826 /* Override with kernel parameters if supplied XXX CRS XXX
1827 * this needs to have multiple instances */
1828 if ((phyaddr >= 0) && (phyaddr <= 31))
1829 priv->plat->phy_addr = phyaddr;
1830
1831 /* Init MAC and get the capabilities */
1832 stmmac_hw_init(priv);
1833
1834 ndev->netdev_ops = &stmmac_netdev_ops;
1835
1836 ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
1837 NETIF_F_RXCSUM;
1838 ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
1839 ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
1840 #ifdef STMMAC_VLAN_TAG_USED
1841 /* Both mac100 and gmac support receive VLAN tag detection */
1842 ndev->features |= NETIF_F_HW_VLAN_RX;
1843 #endif
1844 priv->msg_enable = netif_msg_init(debug, default_msg_level);
1845
1846 if (flow_ctrl)
1847 priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */
1848
1849 netif_napi_add(ndev, &priv->napi, stmmac_poll, 64);
1850
1851 spin_lock_init(&priv->lock);
1852 spin_lock_init(&priv->tx_lock);
1853
1854 ret = register_netdev(ndev);
1855 if (ret) {
1856 pr_err("%s: ERROR %i registering the device\n", __func__, ret);
1857 goto error;
1858 }
1859
1860 return priv;
1861
1862 error:
1863 netif_napi_del(&priv->napi);
1864
1865 unregister_netdev(ndev);
1866 free_netdev(ndev);
1867
1868 return NULL;
1869 }
1870
1871 /**
1872 * stmmac_dvr_remove
1873 * @ndev: net device pointer
1874 * Description: this function resets the TX/RX processes, disables the MAC RX/TX
1875 * changes the link status, releases the DMA descriptor rings.
1876 */
1877 int stmmac_dvr_remove(struct net_device *ndev)
1878 {
1879 struct stmmac_priv *priv = netdev_priv(ndev);
1880
1881 pr_info("%s:\n\tremoving driver", __func__);
1882
1883 priv->hw->dma->stop_rx(priv->ioaddr);
1884 priv->hw->dma->stop_tx(priv->ioaddr);
1885
1886 stmmac_set_mac(priv->ioaddr, false);
1887 netif_carrier_off(ndev);
1888 unregister_netdev(ndev);
1889 free_netdev(ndev);
1890
1891 return 0;
1892 }
1893
1894 #ifdef CONFIG_PM
1895 int stmmac_suspend(struct net_device *ndev)
1896 {
1897 struct stmmac_priv *priv = netdev_priv(ndev);
1898 int dis_ic = 0;
1899
1900 if (!ndev || !netif_running(ndev))
1901 return 0;
1902
1903 if (priv->phydev)
1904 phy_stop(priv->phydev);
1905
1906 spin_lock(&priv->lock);
1907
1908 netif_device_detach(ndev);
1909 netif_stop_queue(ndev);
1910
1911 #ifdef CONFIG_STMMAC_TIMER
1912 priv->tm->timer_stop();
1913 if (likely(priv->tm->enable))
1914 dis_ic = 1;
1915 #endif
1916 napi_disable(&priv->napi);
1917
1918 /* Stop TX/RX DMA */
1919 priv->hw->dma->stop_tx(priv->ioaddr);
1920 priv->hw->dma->stop_rx(priv->ioaddr);
1921 /* Clear the Rx/Tx descriptors */
1922 priv->hw->desc->init_rx_desc(priv->dma_rx, priv->dma_rx_size,
1923 dis_ic);
1924 priv->hw->desc->init_tx_desc(priv->dma_tx, priv->dma_tx_size);
1925
1926 /* Enable Power down mode by programming the PMT regs */
1927 if (device_may_wakeup(priv->device))
1928 priv->hw->mac->pmt(priv->ioaddr, priv->wolopts);
1929 else
1930 stmmac_set_mac(priv->ioaddr, false);
1931
1932 spin_unlock(&priv->lock);
1933 return 0;
1934 }
1935
1936 int stmmac_resume(struct net_device *ndev)
1937 {
1938 struct stmmac_priv *priv = netdev_priv(ndev);
1939
1940 if (!netif_running(ndev))
1941 return 0;
1942
1943 spin_lock(&priv->lock);
1944
1945 /* Power Down bit, into the PM register, is cleared
1946 * automatically as soon as a magic packet or a Wake-up frame
1947 * is received. Anyway, it's better to manually clear
1948 * this bit because it can generate problems while resuming
1949 * from another devices (e.g. serial console). */
1950 if (device_may_wakeup(priv->device))
1951 priv->hw->mac->pmt(priv->ioaddr, 0);
1952
1953 netif_device_attach(ndev);
1954
1955 /* Enable the MAC and DMA */
1956 stmmac_set_mac(priv->ioaddr, true);
1957 priv->hw->dma->start_tx(priv->ioaddr);
1958 priv->hw->dma->start_rx(priv->ioaddr);
1959
1960 #ifdef CONFIG_STMMAC_TIMER
1961 if (likely(priv->tm->enable))
1962 priv->tm->timer_start(tmrate);
1963 #endif
1964 napi_enable(&priv->napi);
1965
1966 netif_start_queue(ndev);
1967
1968 spin_unlock(&priv->lock);
1969
1970 if (priv->phydev)
1971 phy_start(priv->phydev);
1972
1973 return 0;
1974 }
1975
1976 int stmmac_freeze(struct net_device *ndev)
1977 {
1978 if (!ndev || !netif_running(ndev))
1979 return 0;
1980
1981 return stmmac_release(ndev);
1982 }
1983
1984 int stmmac_restore(struct net_device *ndev)
1985 {
1986 if (!ndev || !netif_running(ndev))
1987 return 0;
1988
1989 return stmmac_open(ndev);
1990 }
1991 #endif /* CONFIG_PM */
1992
1993 #ifndef MODULE
1994 static int __init stmmac_cmdline_opt(char *str)
1995 {
1996 char *opt;
1997
1998 if (!str || !*str)
1999 return -EINVAL;
2000 while ((opt = strsep(&str, ",")) != NULL) {
2001 if (!strncmp(opt, "debug:", 6)) {
2002 if (strict_strtoul(opt + 6, 0, (unsigned long *)&debug))
2003 goto err;
2004 } else if (!strncmp(opt, "phyaddr:", 8)) {
2005 if (strict_strtoul(opt + 8, 0,
2006 (unsigned long *)&phyaddr))
2007 goto err;
2008 } else if (!strncmp(opt, "dma_txsize:", 11)) {
2009 if (strict_strtoul(opt + 11, 0,
2010 (unsigned long *)&dma_txsize))
2011 goto err;
2012 } else if (!strncmp(opt, "dma_rxsize:", 11)) {
2013 if (strict_strtoul(opt + 11, 0,
2014 (unsigned long *)&dma_rxsize))
2015 goto err;
2016 } else if (!strncmp(opt, "buf_sz:", 7)) {
2017 if (strict_strtoul(opt + 7, 0,
2018 (unsigned long *)&buf_sz))
2019 goto err;
2020 } else if (!strncmp(opt, "tc:", 3)) {
2021 if (strict_strtoul(opt + 3, 0, (unsigned long *)&tc))
2022 goto err;
2023 } else if (!strncmp(opt, "watchdog:", 9)) {
2024 if (strict_strtoul(opt + 9, 0,
2025 (unsigned long *)&watchdog))
2026 goto err;
2027 } else if (!strncmp(opt, "flow_ctrl:", 10)) {
2028 if (strict_strtoul(opt + 10, 0,
2029 (unsigned long *)&flow_ctrl))
2030 goto err;
2031 } else if (!strncmp(opt, "pause:", 6)) {
2032 if (strict_strtoul(opt + 6, 0, (unsigned long *)&pause))
2033 goto err;
2034 #ifdef CONFIG_STMMAC_TIMER
2035 } else if (!strncmp(opt, "tmrate:", 7)) {
2036 if (strict_strtoul(opt + 7, 0,
2037 (unsigned long *)&tmrate))
2038 goto err;
2039 #endif
2040 }
2041 }
2042 return 0;
2043
2044 err:
2045 pr_err("%s: ERROR broken module parameter conversion", __func__);
2046 return -EINVAL;
2047 }
2048
2049 __setup("stmmaceth=", stmmac_cmdline_opt);
2050 #endif
2051
2052 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver");
2053 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
2054 MODULE_LICENSE("GPL");