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spi-topcliff-pch: add recovery processing in case wait-event timeout
[zen-stable.git] / drivers / net / wireless / ath / ath9k / ar5008_phy.c
blob86a891f93fc9dc70939088e70080af874343f4b4
1 /*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include "hw.h"
18 #include "hw-ops.h"
19 #include "../regd.h"
20 #include "ar9002_phy.h"
21
22 /* All code below is for AR5008, AR9001, AR9002 */
23
24 static const int firstep_table[] =
25 /* level: 0 1 2 3 4 5 6 7 8 */
26 { -4, -2, 0, 2, 4, 6, 8, 10, 12 }; /* lvl 0-8, default 2 */
27
28 static const int cycpwrThr1_table[] =
29 /* level: 0 1 2 3 4 5 6 7 8 */
30 { -6, -4, -2, 0, 2, 4, 6, 8 }; /* lvl 0-7, default 3 */
31
32 /*
33 * register values to turn OFDM weak signal detection OFF
34 */
35 static const int m1ThreshLow_off = 127;
36 static const int m2ThreshLow_off = 127;
37 static const int m1Thresh_off = 127;
38 static const int m2Thresh_off = 127;
39 static const int m2CountThr_off = 31;
40 static const int m2CountThrLow_off = 63;
41 static const int m1ThreshLowExt_off = 127;
42 static const int m2ThreshLowExt_off = 127;
43 static const int m1ThreshExt_off = 127;
44 static const int m2ThreshExt_off = 127;
45
46
47 static void ar5008_rf_bank_setup(u32 *bank, struct ar5416IniArray *array,
48 int col)
49 {
50 int i;
51
52 for (i = 0; i < array->ia_rows; i++)
53 bank[i] = INI_RA(array, i, col);
54 }
55
56
57 #define REG_WRITE_RF_ARRAY(iniarray, regData, regWr) \
58 ar5008_write_rf_array(ah, iniarray, regData, &(regWr))
59
60 static void ar5008_write_rf_array(struct ath_hw *ah, struct ar5416IniArray *array,
61 u32 *data, unsigned int *writecnt)
62 {
63 int r;
64
65 ENABLE_REGWRITE_BUFFER(ah);
66
67 for (r = 0; r < array->ia_rows; r++) {
68 REG_WRITE(ah, INI_RA(array, r, 0), data[r]);
69 DO_DELAY(*writecnt);
70 }
71
72 REGWRITE_BUFFER_FLUSH(ah);
73 }
74
75 /**
76 * ar5008_hw_phy_modify_rx_buffer() - perform analog swizzling of parameters
77 * @rfbuf:
78 * @reg32:
79 * @numBits:
80 * @firstBit:
81 * @column:
82 *
83 * Performs analog "swizzling" of parameters into their location.
84 * Used on external AR2133/AR5133 radios.
85 */
86 static void ar5008_hw_phy_modify_rx_buffer(u32 *rfBuf, u32 reg32,
87 u32 numBits, u32 firstBit,
88 u32 column)
89 {
90 u32 tmp32, mask, arrayEntry, lastBit;
91 int32_t bitPosition, bitsLeft;
92
93 tmp32 = ath9k_hw_reverse_bits(reg32, numBits);
94 arrayEntry = (firstBit - 1) / 8;
95 bitPosition = (firstBit - 1) % 8;
96 bitsLeft = numBits;
97 while (bitsLeft > 0) {
98 lastBit = (bitPosition + bitsLeft > 8) ?
99 8 : bitPosition + bitsLeft;
100 mask = (((1 << lastBit) - 1) ^ ((1 << bitPosition) - 1)) <<
101 (column * 8);
102 rfBuf[arrayEntry] &= ~mask;
103 rfBuf[arrayEntry] |= ((tmp32 << bitPosition) <<
104 (column * 8)) & mask;
105 bitsLeft -= 8 - bitPosition;
106 tmp32 = tmp32 >> (8 - bitPosition);
107 bitPosition = 0;
108 arrayEntry++;
109 }
110 }
111
112 /*
113 * Fix on 2.4 GHz band for orientation sensitivity issue by increasing
114 * rf_pwd_icsyndiv.
115 *
116 * Theoretical Rules:
117 * if 2 GHz band
118 * if forceBiasAuto
119 * if synth_freq < 2412
120 * bias = 0
121 * else if 2412 <= synth_freq <= 2422
122 * bias = 1
123 * else // synth_freq > 2422
124 * bias = 2
125 * else if forceBias > 0
126 * bias = forceBias & 7
127 * else
128 * no change, use value from ini file
129 * else
130 * no change, invalid band
131 *
132 * 1st Mod:
133 * 2422 also uses value of 2
134 * <approved>
135 *
136 * 2nd Mod:
137 * Less than 2412 uses value of 0, 2412 and above uses value of 2
138 */
139 static void ar5008_hw_force_bias(struct ath_hw *ah, u16 synth_freq)
140 {
141 struct ath_common *common = ath9k_hw_common(ah);
142 u32 tmp_reg;
143 int reg_writes = 0;
144 u32 new_bias = 0;
145
146 if (!AR_SREV_5416(ah) || synth_freq >= 3000)
147 return;
148
149 BUG_ON(AR_SREV_9280_20_OR_LATER(ah));
150
151 if (synth_freq < 2412)
152 new_bias = 0;
153 else if (synth_freq < 2422)
154 new_bias = 1;
155 else
156 new_bias = 2;
157
158 /* pre-reverse this field */
159 tmp_reg = ath9k_hw_reverse_bits(new_bias, 3);
160
161 ath_dbg(common, CONFIG, "Force rf_pwd_icsyndiv to %1d on %4d\n",
162 new_bias, synth_freq);
163
164 /* swizzle rf_pwd_icsyndiv */
165 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, tmp_reg, 3, 181, 3);
166
167 /* write Bank 6 with new params */
168 REG_WRITE_RF_ARRAY(&ah->iniBank6, ah->analogBank6Data, reg_writes);
169 }
170
171 /**
172 * ar5008_hw_set_channel - tune to a channel on the external AR2133/AR5133 radios
173 * @ah: atheros hardware structure
174 * @chan:
175 *
176 * For the external AR2133/AR5133 radios, takes the MHz channel value and set
177 * the channel value. Assumes writes enabled to analog bus and bank6 register
178 * cache in ah->analogBank6Data.
179 */
180 static int ar5008_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
181 {
182 struct ath_common *common = ath9k_hw_common(ah);
183 u32 channelSel = 0;
184 u32 bModeSynth = 0;
185 u32 aModeRefSel = 0;
186 u32 reg32 = 0;
187 u16 freq;
188 struct chan_centers centers;
189
190 ath9k_hw_get_channel_centers(ah, chan, &centers);
191 freq = centers.synth_center;
192
193 if (freq < 4800) {
194 u32 txctl;
195
196 if (((freq - 2192) % 5) == 0) {
197 channelSel = ((freq - 672) * 2 - 3040) / 10;
198 bModeSynth = 0;
199 } else if (((freq - 2224) % 5) == 0) {
200 channelSel = ((freq - 704) * 2 - 3040) / 10;
201 bModeSynth = 1;
202 } else {
203 ath_err(common, "Invalid channel %u MHz\n", freq);
204 return -EINVAL;
205 }
206
207 channelSel = (channelSel << 2) & 0xff;
208 channelSel = ath9k_hw_reverse_bits(channelSel, 8);
209
210 txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL);
211 if (freq == 2484) {
212
213 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
214 txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
215 } else {
216 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
217 txctl & ~AR_PHY_CCK_TX_CTRL_JAPAN);
218 }
219
220 } else if ((freq % 20) == 0 && freq >= 5120) {
221 channelSel =
222 ath9k_hw_reverse_bits(((freq - 4800) / 20 << 2), 8);
223 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
224 } else if ((freq % 10) == 0) {
225 channelSel =
226 ath9k_hw_reverse_bits(((freq - 4800) / 10 << 1), 8);
227 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah))
228 aModeRefSel = ath9k_hw_reverse_bits(2, 2);
229 else
230 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
231 } else if ((freq % 5) == 0) {
232 channelSel = ath9k_hw_reverse_bits((freq - 4800) / 5, 8);
233 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
234 } else {
235 ath_err(common, "Invalid channel %u MHz\n", freq);
236 return -EINVAL;
237 }
238
239 ar5008_hw_force_bias(ah, freq);
240
241 reg32 =
242 (channelSel << 8) | (aModeRefSel << 2) | (bModeSynth << 1) |
243 (1 << 5) | 0x1;
244
245 REG_WRITE(ah, AR_PHY(0x37), reg32);
246
247 ah->curchan = chan;
248 ah->curchan_rad_index = -1;
249
250 return 0;
251 }
252
253 /**
254 * ar5008_hw_spur_mitigate - convert baseband spur frequency for external radios
255 * @ah: atheros hardware structure
256 * @chan:
257 *
258 * For non single-chip solutions. Converts to baseband spur frequency given the
259 * input channel frequency and compute register settings below.
260 */
261 static void ar5008_hw_spur_mitigate(struct ath_hw *ah,
262 struct ath9k_channel *chan)
263 {
264 int bb_spur = AR_NO_SPUR;
265 int bin, cur_bin;
266 int spur_freq_sd;
267 int spur_delta_phase;
268 int denominator;
269 int upper, lower, cur_vit_mask;
270 int tmp, new;
271 int i;
272 static int pilot_mask_reg[4] = {
273 AR_PHY_TIMING7, AR_PHY_TIMING8,
274 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
275 };
276 static int chan_mask_reg[4] = {
277 AR_PHY_TIMING9, AR_PHY_TIMING10,
278 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
279 };
280 static int inc[4] = { 0, 100, 0, 0 };
281
282 int8_t mask_m[123];
283 int8_t mask_p[123];
284 int8_t mask_amt;
285 int tmp_mask;
286 int cur_bb_spur;
287 bool is2GHz = IS_CHAN_2GHZ(chan);
288
289 memset(&mask_m, 0, sizeof(int8_t) * 123);
290 memset(&mask_p, 0, sizeof(int8_t) * 123);
291
292 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
293 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
294 if (AR_NO_SPUR == cur_bb_spur)
295 break;
296 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
297 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
298 bb_spur = cur_bb_spur;
299 break;
300 }
301 }
302
303 if (AR_NO_SPUR == bb_spur)
304 return;
305
306 bin = bb_spur * 32;
307
308 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
309 new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
310 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
311 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
312 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
313
314 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
315
316 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
317 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
318 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
319 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
320 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
321 REG_WRITE(ah, AR_PHY_SPUR_REG, new);
322
323 spur_delta_phase = ((bb_spur * 524288) / 100) &
324 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
325
326 denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
327 spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
328
329 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
330 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
331 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
332 REG_WRITE(ah, AR_PHY_TIMING11, new);
333
334 cur_bin = -6000;
335 upper = bin + 100;
336 lower = bin - 100;
337
338 for (i = 0; i < 4; i++) {
339 int pilot_mask = 0;
340 int chan_mask = 0;
341 int bp = 0;
342 for (bp = 0; bp < 30; bp++) {
343 if ((cur_bin > lower) && (cur_bin < upper)) {
344 pilot_mask = pilot_mask | 0x1 << bp;
345 chan_mask = chan_mask | 0x1 << bp;
346 }
347 cur_bin += 100;
348 }
349 cur_bin += inc[i];
350 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
351 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
352 }
353
354 cur_vit_mask = 6100;
355 upper = bin + 120;
356 lower = bin - 120;
357
358 for (i = 0; i < 123; i++) {
359 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
360
361 /* workaround for gcc bug #37014 */
362 volatile int tmp_v = abs(cur_vit_mask - bin);
363
364 if (tmp_v < 75)
365 mask_amt = 1;
366 else
367 mask_amt = 0;
368 if (cur_vit_mask < 0)
369 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
370 else
371 mask_p[cur_vit_mask / 100] = mask_amt;
372 }
373 cur_vit_mask -= 100;
374 }
375
376 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
377 | (mask_m[48] << 26) | (mask_m[49] << 24)
378 | (mask_m[50] << 22) | (mask_m[51] << 20)
379 | (mask_m[52] << 18) | (mask_m[53] << 16)
380 | (mask_m[54] << 14) | (mask_m[55] << 12)
381 | (mask_m[56] << 10) | (mask_m[57] << 8)
382 | (mask_m[58] << 6) | (mask_m[59] << 4)
383 | (mask_m[60] << 2) | (mask_m[61] << 0);
384 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
385 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
386
387 tmp_mask = (mask_m[31] << 28)
388 | (mask_m[32] << 26) | (mask_m[33] << 24)
389 | (mask_m[34] << 22) | (mask_m[35] << 20)
390 | (mask_m[36] << 18) | (mask_m[37] << 16)
391 | (mask_m[48] << 14) | (mask_m[39] << 12)
392 | (mask_m[40] << 10) | (mask_m[41] << 8)
393 | (mask_m[42] << 6) | (mask_m[43] << 4)
394 | (mask_m[44] << 2) | (mask_m[45] << 0);
395 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
396 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
397
398 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
399 | (mask_m[18] << 26) | (mask_m[18] << 24)
400 | (mask_m[20] << 22) | (mask_m[20] << 20)
401 | (mask_m[22] << 18) | (mask_m[22] << 16)
402 | (mask_m[24] << 14) | (mask_m[24] << 12)
403 | (mask_m[25] << 10) | (mask_m[26] << 8)
404 | (mask_m[27] << 6) | (mask_m[28] << 4)
405 | (mask_m[29] << 2) | (mask_m[30] << 0);
406 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
407 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
408
409 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
410 | (mask_m[2] << 26) | (mask_m[3] << 24)
411 | (mask_m[4] << 22) | (mask_m[5] << 20)
412 | (mask_m[6] << 18) | (mask_m[7] << 16)
413 | (mask_m[8] << 14) | (mask_m[9] << 12)
414 | (mask_m[10] << 10) | (mask_m[11] << 8)
415 | (mask_m[12] << 6) | (mask_m[13] << 4)
416 | (mask_m[14] << 2) | (mask_m[15] << 0);
417 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
418 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
419
420 tmp_mask = (mask_p[15] << 28)
421 | (mask_p[14] << 26) | (mask_p[13] << 24)
422 | (mask_p[12] << 22) | (mask_p[11] << 20)
423 | (mask_p[10] << 18) | (mask_p[9] << 16)
424 | (mask_p[8] << 14) | (mask_p[7] << 12)
425 | (mask_p[6] << 10) | (mask_p[5] << 8)
426 | (mask_p[4] << 6) | (mask_p[3] << 4)
427 | (mask_p[2] << 2) | (mask_p[1] << 0);
428 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
429 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
430
431 tmp_mask = (mask_p[30] << 28)
432 | (mask_p[29] << 26) | (mask_p[28] << 24)
433 | (mask_p[27] << 22) | (mask_p[26] << 20)
434 | (mask_p[25] << 18) | (mask_p[24] << 16)
435 | (mask_p[23] << 14) | (mask_p[22] << 12)
436 | (mask_p[21] << 10) | (mask_p[20] << 8)
437 | (mask_p[19] << 6) | (mask_p[18] << 4)
438 | (mask_p[17] << 2) | (mask_p[16] << 0);
439 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
440 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
441
442 tmp_mask = (mask_p[45] << 28)
443 | (mask_p[44] << 26) | (mask_p[43] << 24)
444 | (mask_p[42] << 22) | (mask_p[41] << 20)
445 | (mask_p[40] << 18) | (mask_p[39] << 16)
446 | (mask_p[38] << 14) | (mask_p[37] << 12)
447 | (mask_p[36] << 10) | (mask_p[35] << 8)
448 | (mask_p[34] << 6) | (mask_p[33] << 4)
449 | (mask_p[32] << 2) | (mask_p[31] << 0);
450 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
451 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
452
453 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
454 | (mask_p[59] << 26) | (mask_p[58] << 24)
455 | (mask_p[57] << 22) | (mask_p[56] << 20)
456 | (mask_p[55] << 18) | (mask_p[54] << 16)
457 | (mask_p[53] << 14) | (mask_p[52] << 12)
458 | (mask_p[51] << 10) | (mask_p[50] << 8)
459 | (mask_p[49] << 6) | (mask_p[48] << 4)
460 | (mask_p[47] << 2) | (mask_p[46] << 0);
461 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
462 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
463 }
464
465 /**
466 * ar5008_hw_rf_alloc_ext_banks - allocates banks for external radio programming
467 * @ah: atheros hardware structure
468 *
469 * Only required for older devices with external AR2133/AR5133 radios.
470 */
471 static int ar5008_hw_rf_alloc_ext_banks(struct ath_hw *ah)
472 {
473 #define ATH_ALLOC_BANK(bank, size) do { \
474 bank = kzalloc((sizeof(u32) * size), GFP_KERNEL); \
475 if (!bank) { \
476 ath_err(common, "Cannot allocate RF banks\n"); \
477 return -ENOMEM; \
478 } \
479 } while (0);
480
481 struct ath_common *common = ath9k_hw_common(ah);
482
483 BUG_ON(AR_SREV_9280_20_OR_LATER(ah));
484
485 ATH_ALLOC_BANK(ah->analogBank0Data, ah->iniBank0.ia_rows);
486 ATH_ALLOC_BANK(ah->analogBank1Data, ah->iniBank1.ia_rows);
487 ATH_ALLOC_BANK(ah->analogBank2Data, ah->iniBank2.ia_rows);
488 ATH_ALLOC_BANK(ah->analogBank3Data, ah->iniBank3.ia_rows);
489 ATH_ALLOC_BANK(ah->analogBank6Data, ah->iniBank6.ia_rows);
490 ATH_ALLOC_BANK(ah->analogBank6TPCData, ah->iniBank6TPC.ia_rows);
491 ATH_ALLOC_BANK(ah->analogBank7Data, ah->iniBank7.ia_rows);
492 ATH_ALLOC_BANK(ah->bank6Temp, ah->iniBank6.ia_rows);
493
494 return 0;
495 #undef ATH_ALLOC_BANK
496 }
497
498
499 /**
500 * ar5008_hw_rf_free_ext_banks - Free memory for analog bank scratch buffers
501 * @ah: atheros hardware struture
502 * For the external AR2133/AR5133 radios banks.
503 */
504 static void ar5008_hw_rf_free_ext_banks(struct ath_hw *ah)
505 {
506 #define ATH_FREE_BANK(bank) do { \
507 kfree(bank); \
508 bank = NULL; \
509 } while (0);
510
511 BUG_ON(AR_SREV_9280_20_OR_LATER(ah));
512
513 ATH_FREE_BANK(ah->analogBank0Data);
514 ATH_FREE_BANK(ah->analogBank1Data);
515 ATH_FREE_BANK(ah->analogBank2Data);
516 ATH_FREE_BANK(ah->analogBank3Data);
517 ATH_FREE_BANK(ah->analogBank6Data);
518 ATH_FREE_BANK(ah->analogBank6TPCData);
519 ATH_FREE_BANK(ah->analogBank7Data);
520 ATH_FREE_BANK(ah->bank6Temp);
521
522 #undef ATH_FREE_BANK
523 }
524
525 /* *
526 * ar5008_hw_set_rf_regs - programs rf registers based on EEPROM
527 * @ah: atheros hardware structure
528 * @chan:
529 * @modesIndex:
530 *
531 * Used for the external AR2133/AR5133 radios.
532 *
533 * Reads the EEPROM header info from the device structure and programs
534 * all rf registers. This routine requires access to the analog
535 * rf device. This is not required for single-chip devices.
536 */
537 static bool ar5008_hw_set_rf_regs(struct ath_hw *ah,
538 struct ath9k_channel *chan,
539 u16 modesIndex)
540 {
541 u32 eepMinorRev;
542 u32 ob5GHz = 0, db5GHz = 0;
543 u32 ob2GHz = 0, db2GHz = 0;
544 int regWrites = 0;
545
546 /*
547 * Software does not need to program bank data
548 * for single chip devices, that is AR9280 or anything
549 * after that.
550 */
551 if (AR_SREV_9280_20_OR_LATER(ah))
552 return true;
553
554 /* Setup rf parameters */
555 eepMinorRev = ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV);
556
557 /* Setup Bank 0 Write */
558 ar5008_rf_bank_setup(ah->analogBank0Data, &ah->iniBank0, 1);
559
560 /* Setup Bank 1 Write */
561 ar5008_rf_bank_setup(ah->analogBank1Data, &ah->iniBank1, 1);
562
563 /* Setup Bank 2 Write */
564 ar5008_rf_bank_setup(ah->analogBank2Data, &ah->iniBank2, 1);
565
566 /* Setup Bank 6 Write */
567 ar5008_rf_bank_setup(ah->analogBank3Data, &ah->iniBank3,
568 modesIndex);
569 {
570 int i;
571 for (i = 0; i < ah->iniBank6TPC.ia_rows; i++) {
572 ah->analogBank6Data[i] =
573 INI_RA(&ah->iniBank6TPC, i, modesIndex);
574 }
575 }
576
577 /* Only the 5 or 2 GHz OB/DB need to be set for a mode */
578 if (eepMinorRev >= 2) {
579 if (IS_CHAN_2GHZ(chan)) {
580 ob2GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_2);
581 db2GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_2);
582 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
583 ob2GHz, 3, 197, 0);
584 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
585 db2GHz, 3, 194, 0);
586 } else {
587 ob5GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_5);
588 db5GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_5);
589 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
590 ob5GHz, 3, 203, 0);
591 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
592 db5GHz, 3, 200, 0);
593 }
594 }
595
596 /* Setup Bank 7 Setup */
597 ar5008_rf_bank_setup(ah->analogBank7Data, &ah->iniBank7, 1);
598
599 /* Write Analog registers */
600 REG_WRITE_RF_ARRAY(&ah->iniBank0, ah->analogBank0Data,
601 regWrites);
602 REG_WRITE_RF_ARRAY(&ah->iniBank1, ah->analogBank1Data,
603 regWrites);
604 REG_WRITE_RF_ARRAY(&ah->iniBank2, ah->analogBank2Data,
605 regWrites);
606 REG_WRITE_RF_ARRAY(&ah->iniBank3, ah->analogBank3Data,
607 regWrites);
608 REG_WRITE_RF_ARRAY(&ah->iniBank6TPC, ah->analogBank6Data,
609 regWrites);
610 REG_WRITE_RF_ARRAY(&ah->iniBank7, ah->analogBank7Data,
611 regWrites);
612
613 return true;
614 }
615
616 static void ar5008_hw_init_bb(struct ath_hw *ah,
617 struct ath9k_channel *chan)
618 {
619 u32 synthDelay;
620
621 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
622 if (IS_CHAN_B(chan))
623 synthDelay = (4 * synthDelay) / 22;
624 else
625 synthDelay /= 10;
626
627 if (IS_CHAN_HALF_RATE(chan))
628 synthDelay *= 2;
629 else if (IS_CHAN_QUARTER_RATE(chan))
630 synthDelay *= 4;
631
632 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
633
634 udelay(synthDelay + BASE_ACTIVATE_DELAY);
635 }
636
637 static void ar5008_hw_init_chain_masks(struct ath_hw *ah)
638 {
639 int rx_chainmask, tx_chainmask;
640
641 rx_chainmask = ah->rxchainmask;
642 tx_chainmask = ah->txchainmask;
643
644
645 switch (rx_chainmask) {
646 case 0x5:
647 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
648 AR_PHY_SWAP_ALT_CHAIN);
649 case 0x3:
650 if (ah->hw_version.macVersion == AR_SREV_REVISION_5416_10) {
651 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
652 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
653 break;
654 }
655 case 0x1:
656 case 0x2:
657 case 0x7:
658 ENABLE_REGWRITE_BUFFER(ah);
659 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
660 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
661 break;
662 default:
663 ENABLE_REGWRITE_BUFFER(ah);
664 break;
665 }
666
667 REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
668
669 REGWRITE_BUFFER_FLUSH(ah);
670
671 if (tx_chainmask == 0x5) {
672 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
673 AR_PHY_SWAP_ALT_CHAIN);
674 }
675 if (AR_SREV_9100(ah))
676 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
677 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
678 }
679
680 static void ar5008_hw_override_ini(struct ath_hw *ah,
681 struct ath9k_channel *chan)
682 {
683 u32 val;
684
685 /*
686 * Set the RX_ABORT and RX_DIS and clear if off only after
687 * RXE is set for MAC. This prevents frames with corrupted
688 * descriptor status.
689 */
690 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
691
692 if (AR_SREV_9280_20_OR_LATER(ah)) {
693 val = REG_READ(ah, AR_PCU_MISC_MODE2);
694
695 if (!AR_SREV_9271(ah))
696 val &= ~AR_PCU_MISC_MODE2_HWWAR1;
697
698 if (AR_SREV_9287_11_OR_LATER(ah))
699 val = val & (~AR_PCU_MISC_MODE2_HWWAR2);
700
701 REG_WRITE(ah, AR_PCU_MISC_MODE2, val);
702 }
703
704 REG_SET_BIT(ah, AR_PHY_CCK_DETECT,
705 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV);
706
707 if (AR_SREV_9280_20_OR_LATER(ah))
708 return;
709 /*
710 * Disable BB clock gating
711 * Necessary to avoid issues on AR5416 2.0
712 */
713 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
714
715 /*
716 * Disable RIFS search on some chips to avoid baseband
717 * hang issues.
718 */
719 if (AR_SREV_9100(ah) || AR_SREV_9160(ah)) {
720 val = REG_READ(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS);
721 val &= ~AR_PHY_RIFS_INIT_DELAY;
722 REG_WRITE(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS, val);
723 }
724 }
725
726 static void ar5008_hw_set_channel_regs(struct ath_hw *ah,
727 struct ath9k_channel *chan)
728 {
729 u32 phymode;
730 u32 enableDacFifo = 0;
731
732 if (AR_SREV_9285_12_OR_LATER(ah))
733 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
734 AR_PHY_FC_ENABLE_DAC_FIFO);
735
736 phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
737 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
738
739 if (IS_CHAN_HT40(chan)) {
740 phymode |= AR_PHY_FC_DYN2040_EN;
741
742 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
743 (chan->chanmode == CHANNEL_G_HT40PLUS))
744 phymode |= AR_PHY_FC_DYN2040_PRI_CH;
745
746 }
747 REG_WRITE(ah, AR_PHY_TURBO, phymode);
748
749 ath9k_hw_set11nmac2040(ah);
750
751 ENABLE_REGWRITE_BUFFER(ah);
752
753 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
754 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
755
756 REGWRITE_BUFFER_FLUSH(ah);
757 }
758
759
760 static int ar5008_hw_process_ini(struct ath_hw *ah,
761 struct ath9k_channel *chan)
762 {
763 struct ath_common *common = ath9k_hw_common(ah);
764 int i, regWrites = 0;
765 u32 modesIndex, freqIndex;
766
767 switch (chan->chanmode) {
768 case CHANNEL_A:
769 case CHANNEL_A_HT20:
770 modesIndex = 1;
771 freqIndex = 1;
772 break;
773 case CHANNEL_A_HT40PLUS:
774 case CHANNEL_A_HT40MINUS:
775 modesIndex = 2;
776 freqIndex = 1;
777 break;
778 case CHANNEL_G:
779 case CHANNEL_G_HT20:
780 case CHANNEL_B:
781 modesIndex = 4;
782 freqIndex = 2;
783 break;
784 case CHANNEL_G_HT40PLUS:
785 case CHANNEL_G_HT40MINUS:
786 modesIndex = 3;
787 freqIndex = 2;
788 break;
789
790 default:
791 return -EINVAL;
792 }
793
794 /*
795 * Set correct baseband to analog shift setting to
796 * access analog chips.
797 */
798 REG_WRITE(ah, AR_PHY(0), 0x00000007);
799
800 /* Write ADDAC shifts */
801 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
802 if (ah->eep_ops->set_addac)
803 ah->eep_ops->set_addac(ah, chan);
804
805 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
806 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
807
808 ENABLE_REGWRITE_BUFFER(ah);
809
810 for (i = 0; i < ah->iniModes.ia_rows; i++) {
811 u32 reg = INI_RA(&ah->iniModes, i, 0);
812 u32 val = INI_RA(&ah->iniModes, i, modesIndex);
813
814 if (reg == AR_AN_TOP2 && ah->need_an_top2_fixup)
815 val &= ~AR_AN_TOP2_PWDCLKIND;
816
817 REG_WRITE(ah, reg, val);
818
819 if (reg >= 0x7800 && reg < 0x78a0
820 && ah->config.analog_shiftreg
821 && (common->bus_ops->ath_bus_type != ATH_USB)) {
822 udelay(100);
823 }
824
825 DO_DELAY(regWrites);
826 }
827
828 REGWRITE_BUFFER_FLUSH(ah);
829
830 if (AR_SREV_9280(ah) || AR_SREV_9287_11_OR_LATER(ah))
831 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
832
833 if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) ||
834 AR_SREV_9287_11_OR_LATER(ah))
835 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
836
837 if (AR_SREV_9271_10(ah))
838 REG_WRITE_ARRAY(&ah->iniModes_9271_1_0_only,
839 modesIndex, regWrites);
840
841 ENABLE_REGWRITE_BUFFER(ah);
842
843 /* Write common array parameters */
844 for (i = 0; i < ah->iniCommon.ia_rows; i++) {
845 u32 reg = INI_RA(&ah->iniCommon, i, 0);
846 u32 val = INI_RA(&ah->iniCommon, i, 1);
847
848 REG_WRITE(ah, reg, val);
849
850 if (reg >= 0x7800 && reg < 0x78a0
851 && ah->config.analog_shiftreg
852 && (common->bus_ops->ath_bus_type != ATH_USB)) {
853 udelay(100);
854 }
855
856 DO_DELAY(regWrites);
857 }
858
859 REGWRITE_BUFFER_FLUSH(ah);
860
861 if (AR_SREV_9271(ah)) {
862 if (ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE) == 1)
863 REG_WRITE_ARRAY(&ah->iniModes_high_power_tx_gain_9271,
864 modesIndex, regWrites);
865 else
866 REG_WRITE_ARRAY(&ah->iniModes_normal_power_tx_gain_9271,
867 modesIndex, regWrites);
868 }
869
870 REG_WRITE_ARRAY(&ah->iniBB_RfGain, freqIndex, regWrites);
871
872 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) {
873 REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
874 regWrites);
875 }
876
877 ar5008_hw_override_ini(ah, chan);
878 ar5008_hw_set_channel_regs(ah, chan);
879 ar5008_hw_init_chain_masks(ah);
880 ath9k_olc_init(ah);
881 ath9k_hw_apply_txpower(ah, chan);
882
883 /* Write analog registers */
884 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
885 ath_err(ath9k_hw_common(ah), "ar5416SetRfRegs failed\n");
886 return -EIO;
887 }
888
889 return 0;
890 }
891
892 static void ar5008_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
893 {
894 u32 rfMode = 0;
895
896 if (chan == NULL)
897 return;
898
899 rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
900 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
901
902 if (!AR_SREV_9280_20_OR_LATER(ah))
903 rfMode |= (IS_CHAN_5GHZ(chan)) ?
904 AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
905
906 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
907 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
908
909 REG_WRITE(ah, AR_PHY_MODE, rfMode);
910 }
911
912 static void ar5008_hw_mark_phy_inactive(struct ath_hw *ah)
913 {
914 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
915 }
916
917 static void ar5008_hw_set_delta_slope(struct ath_hw *ah,
918 struct ath9k_channel *chan)
919 {
920 u32 coef_scaled, ds_coef_exp, ds_coef_man;
921 u32 clockMhzScaled = 0x64000000;
922 struct chan_centers centers;
923
924 if (IS_CHAN_HALF_RATE(chan))
925 clockMhzScaled = clockMhzScaled >> 1;
926 else if (IS_CHAN_QUARTER_RATE(chan))
927 clockMhzScaled = clockMhzScaled >> 2;
928
929 ath9k_hw_get_channel_centers(ah, chan, &centers);
930 coef_scaled = clockMhzScaled / centers.synth_center;
931
932 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
933 &ds_coef_exp);
934
935 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
936 AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
937 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
938 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
939
940 coef_scaled = (9 * coef_scaled) / 10;
941
942 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
943 &ds_coef_exp);
944
945 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
946 AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
947 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
948 AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
949 }
950
951 static bool ar5008_hw_rfbus_req(struct ath_hw *ah)
952 {
953 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
954 return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
955 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT);
956 }
957
958 static void ar5008_hw_rfbus_done(struct ath_hw *ah)
959 {
960 u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
961 if (IS_CHAN_B(ah->curchan))
962 synthDelay = (4 * synthDelay) / 22;
963 else
964 synthDelay /= 10;
965
966 udelay(synthDelay + BASE_ACTIVATE_DELAY);
967
968 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
969 }
970
971 static void ar5008_restore_chainmask(struct ath_hw *ah)
972 {
973 int rx_chainmask = ah->rxchainmask;
974
975 if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
976 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
977 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
978 }
979 }
980
981 static u32 ar9160_hw_compute_pll_control(struct ath_hw *ah,
982 struct ath9k_channel *chan)
983 {
984 u32 pll;
985
986 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
987
988 if (chan && IS_CHAN_HALF_RATE(chan))
989 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
990 else if (chan && IS_CHAN_QUARTER_RATE(chan))
991 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
992
993 if (chan && IS_CHAN_5GHZ(chan))
994 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
995 else
996 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
997
998 return pll;
999 }
1000
1001 static u32 ar5008_hw_compute_pll_control(struct ath_hw *ah,
1002 struct ath9k_channel *chan)
1003 {
1004 u32 pll;
1005
1006 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
1007
1008 if (chan && IS_CHAN_HALF_RATE(chan))
1009 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
1010 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1011 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
1012
1013 if (chan && IS_CHAN_5GHZ(chan))
1014 pll |= SM(0xa, AR_RTC_PLL_DIV);
1015 else
1016 pll |= SM(0xb, AR_RTC_PLL_DIV);
1017
1018 return pll;
1019 }
1020
1021 static bool ar5008_hw_ani_control_old(struct ath_hw *ah,
1022 enum ath9k_ani_cmd cmd,
1023 int param)
1024 {
1025 struct ar5416AniState *aniState = &ah->curchan->ani;
1026 struct ath_common *common = ath9k_hw_common(ah);
1027
1028 switch (cmd & ah->ani_function) {
1029 case ATH9K_ANI_NOISE_IMMUNITY_LEVEL:{
1030 u32 level = param;
1031
1032 if (level >= ARRAY_SIZE(ah->totalSizeDesired)) {
1033 ath_dbg(common, ANI, "level out of range (%u > %zu)\n",
1034 level, ARRAY_SIZE(ah->totalSizeDesired));
1035 return false;
1036 }
1037
1038 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
1039 AR_PHY_DESIRED_SZ_TOT_DES,
1040 ah->totalSizeDesired[level]);
1041 REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
1042 AR_PHY_AGC_CTL1_COARSE_LOW,
1043 ah->coarse_low[level]);
1044 REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
1045 AR_PHY_AGC_CTL1_COARSE_HIGH,
1046 ah->coarse_high[level]);
1047 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
1048 AR_PHY_FIND_SIG_FIRPWR,
1049 ah->firpwr[level]);
1050
1051 if (level > aniState->noiseImmunityLevel)
1052 ah->stats.ast_ani_niup++;
1053 else if (level < aniState->noiseImmunityLevel)
1054 ah->stats.ast_ani_nidown++;
1055 aniState->noiseImmunityLevel = level;
1056 break;
1057 }
1058 case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
1059 static const int m1ThreshLow[] = { 127, 50 };
1060 static const int m2ThreshLow[] = { 127, 40 };
1061 static const int m1Thresh[] = { 127, 0x4d };
1062 static const int m2Thresh[] = { 127, 0x40 };
1063 static const int m2CountThr[] = { 31, 16 };
1064 static const int m2CountThrLow[] = { 63, 48 };
1065 u32 on = param ? 1 : 0;
1066
1067 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
1068 AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
1069 m1ThreshLow[on]);
1070 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
1071 AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
1072 m2ThreshLow[on]);
1073 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
1074 AR_PHY_SFCORR_M1_THRESH,
1075 m1Thresh[on]);
1076 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
1077 AR_PHY_SFCORR_M2_THRESH,
1078 m2Thresh[on]);
1079 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
1080 AR_PHY_SFCORR_M2COUNT_THR,
1081 m2CountThr[on]);
1082 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
1083 AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW,
1084 m2CountThrLow[on]);
1085
1086 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1087 AR_PHY_SFCORR_EXT_M1_THRESH_LOW,
1088 m1ThreshLow[on]);
1089 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1090 AR_PHY_SFCORR_EXT_M2_THRESH_LOW,
1091 m2ThreshLow[on]);
1092 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1093 AR_PHY_SFCORR_EXT_M1_THRESH,
1094 m1Thresh[on]);
1095 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1096 AR_PHY_SFCORR_EXT_M2_THRESH,
1097 m2Thresh[on]);
1098
1099 if (on)
1100 REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
1101 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
1102 else
1103 REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
1104 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
1105
1106 if (!on != aniState->ofdmWeakSigDetectOff) {
1107 if (on)
1108 ah->stats.ast_ani_ofdmon++;
1109 else
1110 ah->stats.ast_ani_ofdmoff++;
1111 aniState->ofdmWeakSigDetectOff = !on;
1112 }
1113 break;
1114 }
1115 case ATH9K_ANI_CCK_WEAK_SIGNAL_THR:{
1116 static const int weakSigThrCck[] = { 8, 6 };
1117 u32 high = param ? 1 : 0;
1118
1119 REG_RMW_FIELD(ah, AR_PHY_CCK_DETECT,
1120 AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK,
1121 weakSigThrCck[high]);
1122 if (high != aniState->cckWeakSigThreshold) {
1123 if (high)
1124 ah->stats.ast_ani_cckhigh++;
1125 else
1126 ah->stats.ast_ani_ccklow++;
1127 aniState->cckWeakSigThreshold = high;
1128 }
1129 break;
1130 }
1131 case ATH9K_ANI_FIRSTEP_LEVEL:{
1132 static const int firstep[] = { 0, 4, 8 };
1133 u32 level = param;
1134
1135 if (level >= ARRAY_SIZE(firstep)) {
1136 ath_dbg(common, ANI, "level out of range (%u > %zu)\n",
1137 level, ARRAY_SIZE(firstep));
1138 return false;
1139 }
1140 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
1141 AR_PHY_FIND_SIG_FIRSTEP,
1142 firstep[level]);
1143 if (level > aniState->firstepLevel)
1144 ah->stats.ast_ani_stepup++;
1145 else if (level < aniState->firstepLevel)
1146 ah->stats.ast_ani_stepdown++;
1147 aniState->firstepLevel = level;
1148 break;
1149 }
1150 case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
1151 static const int cycpwrThr1[] = { 2, 4, 6, 8, 10, 12, 14, 16 };
1152 u32 level = param;
1153
1154 if (level >= ARRAY_SIZE(cycpwrThr1)) {
1155 ath_dbg(common, ANI, "level out of range (%u > %zu)\n",
1156 level, ARRAY_SIZE(cycpwrThr1));
1157 return false;
1158 }
1159 REG_RMW_FIELD(ah, AR_PHY_TIMING5,
1160 AR_PHY_TIMING5_CYCPWR_THR1,
1161 cycpwrThr1[level]);
1162 if (level > aniState->spurImmunityLevel)
1163 ah->stats.ast_ani_spurup++;
1164 else if (level < aniState->spurImmunityLevel)
1165 ah->stats.ast_ani_spurdown++;
1166 aniState->spurImmunityLevel = level;
1167 break;
1168 }
1169 case ATH9K_ANI_PRESENT:
1170 break;
1171 default:
1172 ath_dbg(common, ANI, "invalid cmd %u\n", cmd);
1173 return false;
1174 }
1175
1176 ath_dbg(common, ANI, "ANI parameters:\n");
1177 ath_dbg(common, ANI,
1178 "noiseImmunityLevel=%d, spurImmunityLevel=%d, ofdmWeakSigDetectOff=%d\n",
1179 aniState->noiseImmunityLevel,
1180 aniState->spurImmunityLevel,
1181 !aniState->ofdmWeakSigDetectOff);
1182 ath_dbg(common, ANI,
1183 "cckWeakSigThreshold=%d, firstepLevel=%d, listenTime=%d\n",
1184 aniState->cckWeakSigThreshold,
1185 aniState->firstepLevel,
1186 aniState->listenTime);
1187 ath_dbg(common, ANI, "ofdmPhyErrCount=%d, cckPhyErrCount=%d\n\n",
1188 aniState->ofdmPhyErrCount,
1189 aniState->cckPhyErrCount);
1190
1191 return true;
1192 }
1193
1194 static bool ar5008_hw_ani_control_new(struct ath_hw *ah,
1195 enum ath9k_ani_cmd cmd,
1196 int param)
1197 {
1198 struct ath_common *common = ath9k_hw_common(ah);
1199 struct ath9k_channel *chan = ah->curchan;
1200 struct ar5416AniState *aniState = &chan->ani;
1201 s32 value, value2;
1202
1203 switch (cmd & ah->ani_function) {
1204 case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
1205 /*
1206 * on == 1 means ofdm weak signal detection is ON
1207 * on == 1 is the default, for less noise immunity
1208 *
1209 * on == 0 means ofdm weak signal detection is OFF
1210 * on == 0 means more noise imm
1211 */
1212 u32 on = param ? 1 : 0;
1213 /*
1214 * make register setting for default
1215 * (weak sig detect ON) come from INI file
1216 */
1217 int m1ThreshLow = on ?
1218 aniState->iniDef.m1ThreshLow : m1ThreshLow_off;
1219 int m2ThreshLow = on ?
1220 aniState->iniDef.m2ThreshLow : m2ThreshLow_off;
1221 int m1Thresh = on ?
1222 aniState->iniDef.m1Thresh : m1Thresh_off;
1223 int m2Thresh = on ?
1224 aniState->iniDef.m2Thresh : m2Thresh_off;
1225 int m2CountThr = on ?
1226 aniState->iniDef.m2CountThr : m2CountThr_off;
1227 int m2CountThrLow = on ?
1228 aniState->iniDef.m2CountThrLow : m2CountThrLow_off;
1229 int m1ThreshLowExt = on ?
1230 aniState->iniDef.m1ThreshLowExt : m1ThreshLowExt_off;
1231 int m2ThreshLowExt = on ?
1232 aniState->iniDef.m2ThreshLowExt : m2ThreshLowExt_off;
1233 int m1ThreshExt = on ?
1234 aniState->iniDef.m1ThreshExt : m1ThreshExt_off;
1235 int m2ThreshExt = on ?
1236 aniState->iniDef.m2ThreshExt : m2ThreshExt_off;
1237
1238 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
1239 AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
1240 m1ThreshLow);
1241 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
1242 AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
1243 m2ThreshLow);
1244 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
1245 AR_PHY_SFCORR_M1_THRESH, m1Thresh);
1246 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
1247 AR_PHY_SFCORR_M2_THRESH, m2Thresh);
1248 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
1249 AR_PHY_SFCORR_M2COUNT_THR, m2CountThr);
1250 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
1251 AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW,
1252 m2CountThrLow);
1253
1254 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1255 AR_PHY_SFCORR_EXT_M1_THRESH_LOW, m1ThreshLowExt);
1256 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1257 AR_PHY_SFCORR_EXT_M2_THRESH_LOW, m2ThreshLowExt);
1258 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1259 AR_PHY_SFCORR_EXT_M1_THRESH, m1ThreshExt);
1260 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1261 AR_PHY_SFCORR_EXT_M2_THRESH, m2ThreshExt);
1262
1263 if (on)
1264 REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
1265 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
1266 else
1267 REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
1268 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
1269
1270 if (!on != aniState->ofdmWeakSigDetectOff) {
1271 ath_dbg(common, ANI,
1272 "** ch %d: ofdm weak signal: %s=>%s\n",
1273 chan->channel,
1274 !aniState->ofdmWeakSigDetectOff ?
1275 "on" : "off",
1276 on ? "on" : "off");
1277 if (on)
1278 ah->stats.ast_ani_ofdmon++;
1279 else
1280 ah->stats.ast_ani_ofdmoff++;
1281 aniState->ofdmWeakSigDetectOff = !on;
1282 }
1283 break;
1284 }
1285 case ATH9K_ANI_FIRSTEP_LEVEL:{
1286 u32 level = param;
1287
1288 if (level >= ARRAY_SIZE(firstep_table)) {
1289 ath_dbg(common, ANI,
1290 "ATH9K_ANI_FIRSTEP_LEVEL: level out of range (%u > %zu)\n",
1291 level, ARRAY_SIZE(firstep_table));
1292 return false;
1293 }
1294
1295 /*
1296 * make register setting relative to default
1297 * from INI file & cap value
1298 */
1299 value = firstep_table[level] -
1300 firstep_table[ATH9K_ANI_FIRSTEP_LVL_NEW] +
1301 aniState->iniDef.firstep;
1302 if (value < ATH9K_SIG_FIRSTEP_SETTING_MIN)
1303 value = ATH9K_SIG_FIRSTEP_SETTING_MIN;
1304 if (value > ATH9K_SIG_FIRSTEP_SETTING_MAX)
1305 value = ATH9K_SIG_FIRSTEP_SETTING_MAX;
1306 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
1307 AR_PHY_FIND_SIG_FIRSTEP,
1308 value);
1309 /*
1310 * we need to set first step low register too
1311 * make register setting relative to default
1312 * from INI file & cap value
1313 */
1314 value2 = firstep_table[level] -
1315 firstep_table[ATH9K_ANI_FIRSTEP_LVL_NEW] +
1316 aniState->iniDef.firstepLow;
1317 if (value2 < ATH9K_SIG_FIRSTEP_SETTING_MIN)
1318 value2 = ATH9K_SIG_FIRSTEP_SETTING_MIN;
1319 if (value2 > ATH9K_SIG_FIRSTEP_SETTING_MAX)
1320 value2 = ATH9K_SIG_FIRSTEP_SETTING_MAX;
1321
1322 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW,
1323 AR_PHY_FIND_SIG_FIRSTEP_LOW, value2);
1324
1325 if (level != aniState->firstepLevel) {
1326 ath_dbg(common, ANI,
1327 "** ch %d: level %d=>%d[def:%d] firstep[level]=%d ini=%d\n",
1328 chan->channel,
1329 aniState->firstepLevel,
1330 level,
1331 ATH9K_ANI_FIRSTEP_LVL_NEW,
1332 value,
1333 aniState->iniDef.firstep);
1334 ath_dbg(common, ANI,
1335 "** ch %d: level %d=>%d[def:%d] firstep_low[level]=%d ini=%d\n",
1336 chan->channel,
1337 aniState->firstepLevel,
1338 level,
1339 ATH9K_ANI_FIRSTEP_LVL_NEW,
1340 value2,
1341 aniState->iniDef.firstepLow);
1342 if (level > aniState->firstepLevel)
1343 ah->stats.ast_ani_stepup++;
1344 else if (level < aniState->firstepLevel)
1345 ah->stats.ast_ani_stepdown++;
1346 aniState->firstepLevel = level;
1347 }
1348 break;
1349 }
1350 case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
1351 u32 level = param;
1352
1353 if (level >= ARRAY_SIZE(cycpwrThr1_table)) {
1354 ath_dbg(common, ANI,
1355 "ATH9K_ANI_SPUR_IMMUNITY_LEVEL: level out of range (%u > %zu)\n",
1356 level, ARRAY_SIZE(cycpwrThr1_table));
1357 return false;
1358 }
1359 /*
1360 * make register setting relative to default
1361 * from INI file & cap value
1362 */
1363 value = cycpwrThr1_table[level] -
1364 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL_NEW] +
1365 aniState->iniDef.cycpwrThr1;
1366 if (value < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
1367 value = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
1368 if (value > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
1369 value = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
1370 REG_RMW_FIELD(ah, AR_PHY_TIMING5,
1371 AR_PHY_TIMING5_CYCPWR_THR1,
1372 value);
1373
1374 /*
1375 * set AR_PHY_EXT_CCA for extension channel
1376 * make register setting relative to default
1377 * from INI file & cap value
1378 */
1379 value2 = cycpwrThr1_table[level] -
1380 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL_NEW] +
1381 aniState->iniDef.cycpwrThr1Ext;
1382 if (value2 < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
1383 value2 = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
1384 if (value2 > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
1385 value2 = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
1386 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
1387 AR_PHY_EXT_TIMING5_CYCPWR_THR1, value2);
1388
1389 if (level != aniState->spurImmunityLevel) {
1390 ath_dbg(common, ANI,
1391 "** ch %d: level %d=>%d[def:%d] cycpwrThr1[level]=%d ini=%d\n",
1392 chan->channel,
1393 aniState->spurImmunityLevel,
1394 level,
1395 ATH9K_ANI_SPUR_IMMUNE_LVL_NEW,
1396 value,
1397 aniState->iniDef.cycpwrThr1);
1398 ath_dbg(common, ANI,
1399 "** ch %d: level %d=>%d[def:%d] cycpwrThr1Ext[level]=%d ini=%d\n",
1400 chan->channel,
1401 aniState->spurImmunityLevel,
1402 level,
1403 ATH9K_ANI_SPUR_IMMUNE_LVL_NEW,
1404 value2,
1405 aniState->iniDef.cycpwrThr1Ext);
1406 if (level > aniState->spurImmunityLevel)
1407 ah->stats.ast_ani_spurup++;
1408 else if (level < aniState->spurImmunityLevel)
1409 ah->stats.ast_ani_spurdown++;
1410 aniState->spurImmunityLevel = level;
1411 }
1412 break;
1413 }
1414 case ATH9K_ANI_MRC_CCK:
1415 /*
1416 * You should not see this as AR5008, AR9001, AR9002
1417 * does not have hardware support for MRC CCK.
1418 */
1419 WARN_ON(1);
1420 break;
1421 case ATH9K_ANI_PRESENT:
1422 break;
1423 default:
1424 ath_dbg(common, ANI, "invalid cmd %u\n", cmd);
1425 return false;
1426 }
1427
1428 ath_dbg(common, ANI,
1429 "ANI parameters: SI=%d, ofdmWS=%s FS=%d MRCcck=%s listenTime=%d ofdmErrs=%d cckErrs=%d\n",
1430 aniState->spurImmunityLevel,
1431 !aniState->ofdmWeakSigDetectOff ? "on" : "off",
1432 aniState->firstepLevel,
1433 !aniState->mrcCCKOff ? "on" : "off",
1434 aniState->listenTime,
1435 aniState->ofdmPhyErrCount,
1436 aniState->cckPhyErrCount);
1437 return true;
1438 }
1439
1440 static void ar5008_hw_do_getnf(struct ath_hw *ah,
1441 int16_t nfarray[NUM_NF_READINGS])
1442 {
1443 int16_t nf;
1444
1445 nf = MS(REG_READ(ah, AR_PHY_CCA), AR_PHY_MINCCA_PWR);
1446 nfarray[0] = sign_extend32(nf, 8);
1447
1448 nf = MS(REG_READ(ah, AR_PHY_CH1_CCA), AR_PHY_CH1_MINCCA_PWR);
1449 nfarray[1] = sign_extend32(nf, 8);
1450
1451 nf = MS(REG_READ(ah, AR_PHY_CH2_CCA), AR_PHY_CH2_MINCCA_PWR);
1452 nfarray[2] = sign_extend32(nf, 8);
1453
1454 if (!IS_CHAN_HT40(ah->curchan))
1455 return;
1456
1457 nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), AR_PHY_EXT_MINCCA_PWR);
1458 nfarray[3] = sign_extend32(nf, 8);
1459
1460 nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR_PHY_CH1_EXT_MINCCA_PWR);
1461 nfarray[4] = sign_extend32(nf, 8);
1462
1463 nf = MS(REG_READ(ah, AR_PHY_CH2_EXT_CCA), AR_PHY_CH2_EXT_MINCCA_PWR);
1464 nfarray[5] = sign_extend32(nf, 8);
1465 }
1466
1467 /*
1468 * Initialize the ANI register values with default (ini) values.
1469 * This routine is called during a (full) hardware reset after
1470 * all the registers are initialised from the INI.
1471 */
1472 static void ar5008_hw_ani_cache_ini_regs(struct ath_hw *ah)
1473 {
1474 struct ath_common *common = ath9k_hw_common(ah);
1475 struct ath9k_channel *chan = ah->curchan;
1476 struct ar5416AniState *aniState = &chan->ani;
1477 struct ath9k_ani_default *iniDef;
1478 u32 val;
1479
1480 iniDef = &aniState->iniDef;
1481
1482 ath_dbg(common, ANI, "ver %d.%d opmode %u chan %d Mhz/0x%x\n",
1483 ah->hw_version.macVersion,
1484 ah->hw_version.macRev,
1485 ah->opmode,
1486 chan->channel,
1487 chan->channelFlags);
1488
1489 val = REG_READ(ah, AR_PHY_SFCORR);
1490 iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH);
1491 iniDef->m2Thresh = MS(val, AR_PHY_SFCORR_M2_THRESH);
1492 iniDef->m2CountThr = MS(val, AR_PHY_SFCORR_M2COUNT_THR);
1493
1494 val = REG_READ(ah, AR_PHY_SFCORR_LOW);
1495 iniDef->m1ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M1_THRESH_LOW);
1496 iniDef->m2ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M2_THRESH_LOW);
1497 iniDef->m2CountThrLow = MS(val, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW);
1498
1499 val = REG_READ(ah, AR_PHY_SFCORR_EXT);
1500 iniDef->m1ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH);
1501 iniDef->m2ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH);
1502 iniDef->m1ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH_LOW);
1503 iniDef->m2ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH_LOW);
1504 iniDef->firstep = REG_READ_FIELD(ah,
1505 AR_PHY_FIND_SIG,
1506 AR_PHY_FIND_SIG_FIRSTEP);
1507 iniDef->firstepLow = REG_READ_FIELD(ah,
1508 AR_PHY_FIND_SIG_LOW,
1509 AR_PHY_FIND_SIG_FIRSTEP_LOW);
1510 iniDef->cycpwrThr1 = REG_READ_FIELD(ah,
1511 AR_PHY_TIMING5,
1512 AR_PHY_TIMING5_CYCPWR_THR1);
1513 iniDef->cycpwrThr1Ext = REG_READ_FIELD(ah,
1514 AR_PHY_EXT_CCA,
1515 AR_PHY_EXT_TIMING5_CYCPWR_THR1);
1516
1517 /* these levels just got reset to defaults by the INI */
1518 aniState->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL_NEW;
1519 aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL_NEW;
1520 aniState->ofdmWeakSigDetectOff = !ATH9K_ANI_USE_OFDM_WEAK_SIG;
1521 aniState->mrcCCKOff = true; /* not available on pre AR9003 */
1522 }
1523
1524 static void ar5008_hw_set_nf_limits(struct ath_hw *ah)
1525 {
1526 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_2GHZ;
1527 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_2GHZ;
1528 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_5416_2GHZ;
1529 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_5GHZ;
1530 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_5GHZ;
1531 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_5416_5GHZ;
1532 }
1533
1534 static void ar5008_hw_set_radar_params(struct ath_hw *ah,
1535 struct ath_hw_radar_conf *conf)
1536 {
1537 u32 radar_0 = 0, radar_1 = 0;
1538
1539 if (!conf) {
1540 REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA);
1541 return;
1542 }
1543
1544 radar_0 |= AR_PHY_RADAR_0_ENA | AR_PHY_RADAR_0_FFT_ENA;
1545 radar_0 |= SM(conf->fir_power, AR_PHY_RADAR_0_FIRPWR);
1546 radar_0 |= SM(conf->radar_rssi, AR_PHY_RADAR_0_RRSSI);
1547 radar_0 |= SM(conf->pulse_height, AR_PHY_RADAR_0_HEIGHT);
1548 radar_0 |= SM(conf->pulse_rssi, AR_PHY_RADAR_0_PRSSI);
1549 radar_0 |= SM(conf->pulse_inband, AR_PHY_RADAR_0_INBAND);
1550
1551 radar_1 |= AR_PHY_RADAR_1_MAX_RRSSI;
1552 radar_1 |= AR_PHY_RADAR_1_BLOCK_CHECK;
1553 radar_1 |= SM(conf->pulse_maxlen, AR_PHY_RADAR_1_MAXLEN);
1554 radar_1 |= SM(conf->pulse_inband_step, AR_PHY_RADAR_1_RELSTEP_THRESH);
1555 radar_1 |= SM(conf->radar_inband, AR_PHY_RADAR_1_RELPWR_THRESH);
1556
1557 REG_WRITE(ah, AR_PHY_RADAR_0, radar_0);
1558 REG_WRITE(ah, AR_PHY_RADAR_1, radar_1);
1559 if (conf->ext_channel)
1560 REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1561 else
1562 REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1563 }
1564
1565 static void ar5008_hw_set_radar_conf(struct ath_hw *ah)
1566 {
1567 struct ath_hw_radar_conf *conf = &ah->radar_conf;
1568
1569 conf->fir_power = -33;
1570 conf->radar_rssi = 20;
1571 conf->pulse_height = 10;
1572 conf->pulse_rssi = 24;
1573 conf->pulse_inband = 15;
1574 conf->pulse_maxlen = 255;
1575 conf->pulse_inband_step = 12;
1576 conf->radar_inband = 8;
1577 }
1578
1579 void ar5008_hw_attach_phy_ops(struct ath_hw *ah)
1580 {
1581 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
1582 static const u32 ar5416_cca_regs[6] = {
1583 AR_PHY_CCA,
1584 AR_PHY_CH1_CCA,
1585 AR_PHY_CH2_CCA,
1586 AR_PHY_EXT_CCA,
1587 AR_PHY_CH1_EXT_CCA,
1588 AR_PHY_CH2_EXT_CCA
1589 };
1590
1591 priv_ops->rf_set_freq = ar5008_hw_set_channel;
1592 priv_ops->spur_mitigate_freq = ar5008_hw_spur_mitigate;
1593
1594 priv_ops->rf_alloc_ext_banks = ar5008_hw_rf_alloc_ext_banks;
1595 priv_ops->rf_free_ext_banks = ar5008_hw_rf_free_ext_banks;
1596 priv_ops->set_rf_regs = ar5008_hw_set_rf_regs;
1597 priv_ops->set_channel_regs = ar5008_hw_set_channel_regs;
1598 priv_ops->init_bb = ar5008_hw_init_bb;
1599 priv_ops->process_ini = ar5008_hw_process_ini;
1600 priv_ops->set_rfmode = ar5008_hw_set_rfmode;
1601 priv_ops->mark_phy_inactive = ar5008_hw_mark_phy_inactive;
1602 priv_ops->set_delta_slope = ar5008_hw_set_delta_slope;
1603 priv_ops->rfbus_req = ar5008_hw_rfbus_req;
1604 priv_ops->rfbus_done = ar5008_hw_rfbus_done;
1605 priv_ops->restore_chainmask = ar5008_restore_chainmask;
1606 priv_ops->do_getnf = ar5008_hw_do_getnf;
1607 priv_ops->set_radar_params = ar5008_hw_set_radar_params;
1608
1609 if (modparam_force_new_ani) {
1610 priv_ops->ani_control = ar5008_hw_ani_control_new;
1611 priv_ops->ani_cache_ini_regs = ar5008_hw_ani_cache_ini_regs;
1612 } else
1613 priv_ops->ani_control = ar5008_hw_ani_control_old;
1614
1615 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah))
1616 priv_ops->compute_pll_control = ar9160_hw_compute_pll_control;
1617 else
1618 priv_ops->compute_pll_control = ar5008_hw_compute_pll_control;
1619
1620 ar5008_hw_set_nf_limits(ah);
1621 ar5008_hw_set_radar_conf(ah);
1622 memcpy(ah->nf_regs, ar5416_cca_regs, sizeof(ah->nf_regs));
1623 }