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spi-topcliff-pch: add recovery processing in case wait-event timeout
[zen-stable.git] / drivers / net / wireless / ath / ath9k / ar9003_calib.c
blob8e70f0bc073e2d12a554428701e67184f538a3c5
1 /*
2 * Copyright (c) 2010-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include "hw.h"
18 #include "hw-ops.h"
19 #include "ar9003_phy.h"
20 #include "ar9003_rtt.h"
21 #include "ar9003_mci.h"
22
23 #define MAX_MEASUREMENT MAX_IQCAL_MEASUREMENT
24 #define MAX_MAG_DELTA 11
25 #define MAX_PHS_DELTA 10
26
27 struct coeff {
28 int mag_coeff[AR9300_MAX_CHAINS][MAX_MEASUREMENT];
29 int phs_coeff[AR9300_MAX_CHAINS][MAX_MEASUREMENT];
30 int iqc_coeff[2];
31 };
32
33 enum ar9003_cal_types {
34 IQ_MISMATCH_CAL = BIT(0),
35 TEMP_COMP_CAL = BIT(1),
36 };
37
38 static void ar9003_hw_setup_calibration(struct ath_hw *ah,
39 struct ath9k_cal_list *currCal)
40 {
41 struct ath_common *common = ath9k_hw_common(ah);
42
43 /* Select calibration to run */
44 switch (currCal->calData->calType) {
45 case IQ_MISMATCH_CAL:
46 /*
47 * Start calibration with
48 * 2^(INIT_IQCAL_LOG_COUNT_MAX+1) samples
49 */
50 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
51 AR_PHY_TIMING4_IQCAL_LOG_COUNT_MAX,
52 currCal->calData->calCountMax);
53 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ);
54
55 ath_dbg(common, CALIBRATE,
56 "starting IQ Mismatch Calibration\n");
57
58 /* Kick-off cal */
59 REG_SET_BIT(ah, AR_PHY_TIMING4, AR_PHY_TIMING4_DO_CAL);
60 break;
61 case TEMP_COMP_CAL:
62 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_THERM,
63 AR_PHY_65NM_CH0_THERM_LOCAL, 1);
64 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_THERM,
65 AR_PHY_65NM_CH0_THERM_START, 1);
66
67 ath_dbg(common, CALIBRATE,
68 "starting Temperature Compensation Calibration\n");
69 break;
70 }
71 }
72
73 /*
74 * Generic calibration routine.
75 * Recalibrate the lower PHY chips to account for temperature/environment
76 * changes.
77 */
78 static bool ar9003_hw_per_calibration(struct ath_hw *ah,
79 struct ath9k_channel *ichan,
80 u8 rxchainmask,
81 struct ath9k_cal_list *currCal)
82 {
83 struct ath9k_hw_cal_data *caldata = ah->caldata;
84 /* Cal is assumed not done until explicitly set below */
85 bool iscaldone = false;
86
87 /* Calibration in progress. */
88 if (currCal->calState == CAL_RUNNING) {
89 /* Check to see if it has finished. */
90 if (!(REG_READ(ah, AR_PHY_TIMING4) & AR_PHY_TIMING4_DO_CAL)) {
91 /*
92 * Accumulate cal measures for active chains
93 */
94 currCal->calData->calCollect(ah);
95 ah->cal_samples++;
96
97 if (ah->cal_samples >=
98 currCal->calData->calNumSamples) {
99 unsigned int i, numChains = 0;
100 for (i = 0; i < AR9300_MAX_CHAINS; i++) {
101 if (rxchainmask & (1 << i))
102 numChains++;
103 }
104
105 /*
106 * Process accumulated data
107 */
108 currCal->calData->calPostProc(ah, numChains);
109
110 /* Calibration has finished. */
111 caldata->CalValid |= currCal->calData->calType;
112 currCal->calState = CAL_DONE;
113 iscaldone = true;
114 } else {
115 /*
116 * Set-up collection of another sub-sample until we
117 * get desired number
118 */
119 ar9003_hw_setup_calibration(ah, currCal);
120 }
121 }
122 } else if (!(caldata->CalValid & currCal->calData->calType)) {
123 /* If current cal is marked invalid in channel, kick it off */
124 ath9k_hw_reset_calibration(ah, currCal);
125 }
126
127 return iscaldone;
128 }
129
130 static bool ar9003_hw_calibrate(struct ath_hw *ah,
131 struct ath9k_channel *chan,
132 u8 rxchainmask,
133 bool longcal)
134 {
135 bool iscaldone = true;
136 struct ath9k_cal_list *currCal = ah->cal_list_curr;
137
138 /*
139 * For given calibration:
140 * 1. Call generic cal routine
141 * 2. When this cal is done (isCalDone) if we have more cals waiting
142 * (eg after reset), mask this to upper layers by not propagating
143 * isCalDone if it is set to TRUE.
144 * Instead, change isCalDone to FALSE and setup the waiting cal(s)
145 * to be run.
146 */
147 if (currCal &&
148 (currCal->calState == CAL_RUNNING ||
149 currCal->calState == CAL_WAITING)) {
150 iscaldone = ar9003_hw_per_calibration(ah, chan,
151 rxchainmask, currCal);
152 if (iscaldone) {
153 ah->cal_list_curr = currCal = currCal->calNext;
154
155 if (currCal->calState == CAL_WAITING) {
156 iscaldone = false;
157 ath9k_hw_reset_calibration(ah, currCal);
158 }
159 }
160 }
161
162 /* Do NF cal only at longer intervals */
163 if (longcal) {
164 /*
165 * Get the value from the previous NF cal and update
166 * history buffer.
167 */
168 ath9k_hw_getnf(ah, chan);
169
170 /*
171 * Load the NF from history buffer of the current channel.
172 * NF is slow time-variant, so it is OK to use a historical
173 * value.
174 */
175 ath9k_hw_loadnf(ah, ah->curchan);
176
177 /* start NF calibration, without updating BB NF register */
178 ath9k_hw_start_nfcal(ah, false);
179 }
180
181 return iscaldone;
182 }
183
184 static void ar9003_hw_iqcal_collect(struct ath_hw *ah)
185 {
186 int i;
187
188 /* Accumulate IQ cal measures for active chains */
189 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
190 if (ah->txchainmask & BIT(i)) {
191 ah->totalPowerMeasI[i] +=
192 REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
193 ah->totalPowerMeasQ[i] +=
194 REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
195 ah->totalIqCorrMeas[i] +=
196 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
197 ath_dbg(ath9k_hw_common(ah), CALIBRATE,
198 "%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n",
199 ah->cal_samples, i, ah->totalPowerMeasI[i],
200 ah->totalPowerMeasQ[i],
201 ah->totalIqCorrMeas[i]);
202 }
203 }
204 }
205
206 static void ar9003_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
207 {
208 struct ath_common *common = ath9k_hw_common(ah);
209 u32 powerMeasQ, powerMeasI, iqCorrMeas;
210 u32 qCoffDenom, iCoffDenom;
211 int32_t qCoff, iCoff;
212 int iqCorrNeg, i;
213 static const u_int32_t offset_array[3] = {
214 AR_PHY_RX_IQCAL_CORR_B0,
215 AR_PHY_RX_IQCAL_CORR_B1,
216 AR_PHY_RX_IQCAL_CORR_B2,
217 };
218
219 for (i = 0; i < numChains; i++) {
220 powerMeasI = ah->totalPowerMeasI[i];
221 powerMeasQ = ah->totalPowerMeasQ[i];
222 iqCorrMeas = ah->totalIqCorrMeas[i];
223
224 ath_dbg(common, CALIBRATE,
225 "Starting IQ Cal and Correction for Chain %d\n", i);
226
227 ath_dbg(common, CALIBRATE,
228 "Original: Chn %d iq_corr_meas = 0x%08x\n",
229 i, ah->totalIqCorrMeas[i]);
230
231 iqCorrNeg = 0;
232
233 if (iqCorrMeas > 0x80000000) {
234 iqCorrMeas = (0xffffffff - iqCorrMeas) + 1;
235 iqCorrNeg = 1;
236 }
237
238 ath_dbg(common, CALIBRATE, "Chn %d pwr_meas_i = 0x%08x\n",
239 i, powerMeasI);
240 ath_dbg(common, CALIBRATE, "Chn %d pwr_meas_q = 0x%08x\n",
241 i, powerMeasQ);
242 ath_dbg(common, CALIBRATE, "iqCorrNeg is 0x%08x\n", iqCorrNeg);
243
244 iCoffDenom = (powerMeasI / 2 + powerMeasQ / 2) / 256;
245 qCoffDenom = powerMeasQ / 64;
246
247 if ((iCoffDenom != 0) && (qCoffDenom != 0)) {
248 iCoff = iqCorrMeas / iCoffDenom;
249 qCoff = powerMeasI / qCoffDenom - 64;
250 ath_dbg(common, CALIBRATE, "Chn %d iCoff = 0x%08x\n",
251 i, iCoff);
252 ath_dbg(common, CALIBRATE, "Chn %d qCoff = 0x%08x\n",
253 i, qCoff);
254
255 /* Force bounds on iCoff */
256 if (iCoff >= 63)
257 iCoff = 63;
258 else if (iCoff <= -63)
259 iCoff = -63;
260
261 /* Negate iCoff if iqCorrNeg == 0 */
262 if (iqCorrNeg == 0x0)
263 iCoff = -iCoff;
264
265 /* Force bounds on qCoff */
266 if (qCoff >= 63)
267 qCoff = 63;
268 else if (qCoff <= -63)
269 qCoff = -63;
270
271 iCoff = iCoff & 0x7f;
272 qCoff = qCoff & 0x7f;
273
274 ath_dbg(common, CALIBRATE,
275 "Chn %d : iCoff = 0x%x qCoff = 0x%x\n",
276 i, iCoff, qCoff);
277 ath_dbg(common, CALIBRATE,
278 "Register offset (0x%04x) before update = 0x%x\n",
279 offset_array[i],
280 REG_READ(ah, offset_array[i]));
281
282 REG_RMW_FIELD(ah, offset_array[i],
283 AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF,
284 iCoff);
285 REG_RMW_FIELD(ah, offset_array[i],
286 AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF,
287 qCoff);
288 ath_dbg(common, CALIBRATE,
289 "Register offset (0x%04x) QI COFF (bitfields 0x%08x) after update = 0x%x\n",
290 offset_array[i],
291 AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF,
292 REG_READ(ah, offset_array[i]));
293 ath_dbg(common, CALIBRATE,
294 "Register offset (0x%04x) QQ COFF (bitfields 0x%08x) after update = 0x%x\n",
295 offset_array[i],
296 AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF,
297 REG_READ(ah, offset_array[i]));
298
299 ath_dbg(common, CALIBRATE,
300 "IQ Cal and Correction done for Chain %d\n", i);
301 }
302 }
303
304 REG_SET_BIT(ah, AR_PHY_RX_IQCAL_CORR_B0,
305 AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE);
306 ath_dbg(common, CALIBRATE,
307 "IQ Cal and Correction (offset 0x%04x) enabled (bit position 0x%08x). New Value 0x%08x\n",
308 (unsigned) (AR_PHY_RX_IQCAL_CORR_B0),
309 AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE,
310 REG_READ(ah, AR_PHY_RX_IQCAL_CORR_B0));
311 }
312
313 static const struct ath9k_percal_data iq_cal_single_sample = {
314 IQ_MISMATCH_CAL,
315 MIN_CAL_SAMPLES,
316 PER_MAX_LOG_COUNT,
317 ar9003_hw_iqcal_collect,
318 ar9003_hw_iqcalibrate
319 };
320
321 static void ar9003_hw_init_cal_settings(struct ath_hw *ah)
322 {
323 ah->iq_caldata.calData = &iq_cal_single_sample;
324 }
325
326 /*
327 * solve 4x4 linear equation used in loopback iq cal.
328 */
329 static bool ar9003_hw_solve_iq_cal(struct ath_hw *ah,
330 s32 sin_2phi_1,
331 s32 cos_2phi_1,
332 s32 sin_2phi_2,
333 s32 cos_2phi_2,
334 s32 mag_a0_d0,
335 s32 phs_a0_d0,
336 s32 mag_a1_d0,
337 s32 phs_a1_d0,
338 s32 solved_eq[])
339 {
340 s32 f1 = cos_2phi_1 - cos_2phi_2,
341 f3 = sin_2phi_1 - sin_2phi_2,
342 f2;
343 s32 mag_tx, phs_tx, mag_rx, phs_rx;
344 const s32 result_shift = 1 << 15;
345 struct ath_common *common = ath9k_hw_common(ah);
346
347 f2 = (f1 * f1 + f3 * f3) / result_shift;
348
349 if (!f2) {
350 ath_dbg(common, CALIBRATE, "Divide by 0\n");
351 return false;
352 }
353
354 /* mag mismatch, tx */
355 mag_tx = f1 * (mag_a0_d0 - mag_a1_d0) + f3 * (phs_a0_d0 - phs_a1_d0);
356 /* phs mismatch, tx */
357 phs_tx = f3 * (-mag_a0_d0 + mag_a1_d0) + f1 * (phs_a0_d0 - phs_a1_d0);
358
359 mag_tx = (mag_tx / f2);
360 phs_tx = (phs_tx / f2);
361
362 /* mag mismatch, rx */
363 mag_rx = mag_a0_d0 - (cos_2phi_1 * mag_tx + sin_2phi_1 * phs_tx) /
364 result_shift;
365 /* phs mismatch, rx */
366 phs_rx = phs_a0_d0 + (sin_2phi_1 * mag_tx - cos_2phi_1 * phs_tx) /
367 result_shift;
368
369 solved_eq[0] = mag_tx;
370 solved_eq[1] = phs_tx;
371 solved_eq[2] = mag_rx;
372 solved_eq[3] = phs_rx;
373
374 return true;
375 }
376
377 static s32 ar9003_hw_find_mag_approx(struct ath_hw *ah, s32 in_re, s32 in_im)
378 {
379 s32 abs_i = abs(in_re),
380 abs_q = abs(in_im),
381 max_abs, min_abs;
382
383 if (abs_i > abs_q) {
384 max_abs = abs_i;
385 min_abs = abs_q;
386 } else {
387 max_abs = abs_q;
388 min_abs = abs_i;
389 }
390
391 return max_abs - (max_abs / 32) + (min_abs / 8) + (min_abs / 4);
392 }
393
394 #define DELPT 32
395
396 static bool ar9003_hw_calc_iq_corr(struct ath_hw *ah,
397 s32 chain_idx,
398 const s32 iq_res[],
399 s32 iqc_coeff[])
400 {
401 s32 i2_m_q2_a0_d0, i2_p_q2_a0_d0, iq_corr_a0_d0,
402 i2_m_q2_a0_d1, i2_p_q2_a0_d1, iq_corr_a0_d1,
403 i2_m_q2_a1_d0, i2_p_q2_a1_d0, iq_corr_a1_d0,
404 i2_m_q2_a1_d1, i2_p_q2_a1_d1, iq_corr_a1_d1;
405 s32 mag_a0_d0, mag_a1_d0, mag_a0_d1, mag_a1_d1,
406 phs_a0_d0, phs_a1_d0, phs_a0_d1, phs_a1_d1,
407 sin_2phi_1, cos_2phi_1,
408 sin_2phi_2, cos_2phi_2;
409 s32 mag_tx, phs_tx, mag_rx, phs_rx;
410 s32 solved_eq[4], mag_corr_tx, phs_corr_tx, mag_corr_rx, phs_corr_rx,
411 q_q_coff, q_i_coff;
412 const s32 res_scale = 1 << 15;
413 const s32 delpt_shift = 1 << 8;
414 s32 mag1, mag2;
415 struct ath_common *common = ath9k_hw_common(ah);
416
417 i2_m_q2_a0_d0 = iq_res[0] & 0xfff;
418 i2_p_q2_a0_d0 = (iq_res[0] >> 12) & 0xfff;
419 iq_corr_a0_d0 = ((iq_res[0] >> 24) & 0xff) + ((iq_res[1] & 0xf) << 8);
420
421 if (i2_m_q2_a0_d0 > 0x800)
422 i2_m_q2_a0_d0 = -((0xfff - i2_m_q2_a0_d0) + 1);
423
424 if (i2_p_q2_a0_d0 > 0x800)
425 i2_p_q2_a0_d0 = -((0xfff - i2_p_q2_a0_d0) + 1);
426
427 if (iq_corr_a0_d0 > 0x800)
428 iq_corr_a0_d0 = -((0xfff - iq_corr_a0_d0) + 1);
429
430 i2_m_q2_a0_d1 = (iq_res[1] >> 4) & 0xfff;
431 i2_p_q2_a0_d1 = (iq_res[2] & 0xfff);
432 iq_corr_a0_d1 = (iq_res[2] >> 12) & 0xfff;
433
434 if (i2_m_q2_a0_d1 > 0x800)
435 i2_m_q2_a0_d1 = -((0xfff - i2_m_q2_a0_d1) + 1);
436
437 if (i2_p_q2_a0_d1 > 0x800)
438 i2_p_q2_a0_d1 = -((0xfff - i2_p_q2_a0_d1) + 1);
439
440 if (iq_corr_a0_d1 > 0x800)
441 iq_corr_a0_d1 = -((0xfff - iq_corr_a0_d1) + 1);
442
443 i2_m_q2_a1_d0 = ((iq_res[2] >> 24) & 0xff) + ((iq_res[3] & 0xf) << 8);
444 i2_p_q2_a1_d0 = (iq_res[3] >> 4) & 0xfff;
445 iq_corr_a1_d0 = iq_res[4] & 0xfff;
446
447 if (i2_m_q2_a1_d0 > 0x800)
448 i2_m_q2_a1_d0 = -((0xfff - i2_m_q2_a1_d0) + 1);
449
450 if (i2_p_q2_a1_d0 > 0x800)
451 i2_p_q2_a1_d0 = -((0xfff - i2_p_q2_a1_d0) + 1);
452
453 if (iq_corr_a1_d0 > 0x800)
454 iq_corr_a1_d0 = -((0xfff - iq_corr_a1_d0) + 1);
455
456 i2_m_q2_a1_d1 = (iq_res[4] >> 12) & 0xfff;
457 i2_p_q2_a1_d1 = ((iq_res[4] >> 24) & 0xff) + ((iq_res[5] & 0xf) << 8);
458 iq_corr_a1_d1 = (iq_res[5] >> 4) & 0xfff;
459
460 if (i2_m_q2_a1_d1 > 0x800)
461 i2_m_q2_a1_d1 = -((0xfff - i2_m_q2_a1_d1) + 1);
462
463 if (i2_p_q2_a1_d1 > 0x800)
464 i2_p_q2_a1_d1 = -((0xfff - i2_p_q2_a1_d1) + 1);
465
466 if (iq_corr_a1_d1 > 0x800)
467 iq_corr_a1_d1 = -((0xfff - iq_corr_a1_d1) + 1);
468
469 if ((i2_p_q2_a0_d0 == 0) || (i2_p_q2_a0_d1 == 0) ||
470 (i2_p_q2_a1_d0 == 0) || (i2_p_q2_a1_d1 == 0)) {
471 ath_dbg(common, CALIBRATE,
472 "Divide by 0:\n"
473 "a0_d0=%d\n"
474 "a0_d1=%d\n"
475 "a2_d0=%d\n"
476 "a1_d1=%d\n",
477 i2_p_q2_a0_d0, i2_p_q2_a0_d1,
478 i2_p_q2_a1_d0, i2_p_q2_a1_d1);
479 return false;
480 }
481
482 mag_a0_d0 = (i2_m_q2_a0_d0 * res_scale) / i2_p_q2_a0_d0;
483 phs_a0_d0 = (iq_corr_a0_d0 * res_scale) / i2_p_q2_a0_d0;
484
485 mag_a0_d1 = (i2_m_q2_a0_d1 * res_scale) / i2_p_q2_a0_d1;
486 phs_a0_d1 = (iq_corr_a0_d1 * res_scale) / i2_p_q2_a0_d1;
487
488 mag_a1_d0 = (i2_m_q2_a1_d0 * res_scale) / i2_p_q2_a1_d0;
489 phs_a1_d0 = (iq_corr_a1_d0 * res_scale) / i2_p_q2_a1_d0;
490
491 mag_a1_d1 = (i2_m_q2_a1_d1 * res_scale) / i2_p_q2_a1_d1;
492 phs_a1_d1 = (iq_corr_a1_d1 * res_scale) / i2_p_q2_a1_d1;
493
494 /* w/o analog phase shift */
495 sin_2phi_1 = (((mag_a0_d0 - mag_a0_d1) * delpt_shift) / DELPT);
496 /* w/o analog phase shift */
497 cos_2phi_1 = (((phs_a0_d1 - phs_a0_d0) * delpt_shift) / DELPT);
498 /* w/ analog phase shift */
499 sin_2phi_2 = (((mag_a1_d0 - mag_a1_d1) * delpt_shift) / DELPT);
500 /* w/ analog phase shift */
501 cos_2phi_2 = (((phs_a1_d1 - phs_a1_d0) * delpt_shift) / DELPT);
502
503 /*
504 * force sin^2 + cos^2 = 1;
505 * find magnitude by approximation
506 */
507 mag1 = ar9003_hw_find_mag_approx(ah, cos_2phi_1, sin_2phi_1);
508 mag2 = ar9003_hw_find_mag_approx(ah, cos_2phi_2, sin_2phi_2);
509
510 if ((mag1 == 0) || (mag2 == 0)) {
511 ath_dbg(common, CALIBRATE, "Divide by 0: mag1=%d, mag2=%d\n",
512 mag1, mag2);
513 return false;
514 }
515
516 /* normalization sin and cos by mag */
517 sin_2phi_1 = (sin_2phi_1 * res_scale / mag1);
518 cos_2phi_1 = (cos_2phi_1 * res_scale / mag1);
519 sin_2phi_2 = (sin_2phi_2 * res_scale / mag2);
520 cos_2phi_2 = (cos_2phi_2 * res_scale / mag2);
521
522 /* calculate IQ mismatch */
523 if (!ar9003_hw_solve_iq_cal(ah,
524 sin_2phi_1, cos_2phi_1,
525 sin_2phi_2, cos_2phi_2,
526 mag_a0_d0, phs_a0_d0,
527 mag_a1_d0,
528 phs_a1_d0, solved_eq)) {
529 ath_dbg(common, CALIBRATE,
530 "Call to ar9003_hw_solve_iq_cal() failed\n");
531 return false;
532 }
533
534 mag_tx = solved_eq[0];
535 phs_tx = solved_eq[1];
536 mag_rx = solved_eq[2];
537 phs_rx = solved_eq[3];
538
539 ath_dbg(common, CALIBRATE,
540 "chain %d: mag mismatch=%d phase mismatch=%d\n",
541 chain_idx, mag_tx/res_scale, phs_tx/res_scale);
542
543 if (res_scale == mag_tx) {
544 ath_dbg(common, CALIBRATE,
545 "Divide by 0: mag_tx=%d, res_scale=%d\n",
546 mag_tx, res_scale);
547 return false;
548 }
549
550 /* calculate and quantize Tx IQ correction factor */
551 mag_corr_tx = (mag_tx * res_scale) / (res_scale - mag_tx);
552 phs_corr_tx = -phs_tx;
553
554 q_q_coff = (mag_corr_tx * 128 / res_scale);
555 q_i_coff = (phs_corr_tx * 256 / res_scale);
556
557 ath_dbg(common, CALIBRATE, "tx chain %d: mag corr=%d phase corr=%d\n",
558 chain_idx, q_q_coff, q_i_coff);
559
560 if (q_i_coff < -63)
561 q_i_coff = -63;
562 if (q_i_coff > 63)
563 q_i_coff = 63;
564 if (q_q_coff < -63)
565 q_q_coff = -63;
566 if (q_q_coff > 63)
567 q_q_coff = 63;
568
569 iqc_coeff[0] = (q_q_coff * 128) + q_i_coff;
570
571 ath_dbg(common, CALIBRATE, "tx chain %d: iq corr coeff=%x\n",
572 chain_idx, iqc_coeff[0]);
573
574 if (-mag_rx == res_scale) {
575 ath_dbg(common, CALIBRATE,
576 "Divide by 0: mag_rx=%d, res_scale=%d\n",
577 mag_rx, res_scale);
578 return false;
579 }
580
581 /* calculate and quantize Rx IQ correction factors */
582 mag_corr_rx = (-mag_rx * res_scale) / (res_scale + mag_rx);
583 phs_corr_rx = -phs_rx;
584
585 q_q_coff = (mag_corr_rx * 128 / res_scale);
586 q_i_coff = (phs_corr_rx * 256 / res_scale);
587
588 ath_dbg(common, CALIBRATE, "rx chain %d: mag corr=%d phase corr=%d\n",
589 chain_idx, q_q_coff, q_i_coff);
590
591 if (q_i_coff < -63)
592 q_i_coff = -63;
593 if (q_i_coff > 63)
594 q_i_coff = 63;
595 if (q_q_coff < -63)
596 q_q_coff = -63;
597 if (q_q_coff > 63)
598 q_q_coff = 63;
599
600 iqc_coeff[1] = (q_q_coff * 128) + q_i_coff;
601
602 ath_dbg(common, CALIBRATE, "rx chain %d: iq corr coeff=%x\n",
603 chain_idx, iqc_coeff[1]);
604
605 return true;
606 }
607
608 static void ar9003_hw_detect_outlier(int *mp_coeff, int nmeasurement,
609 int max_delta)
610 {
611 int mp_max = -64, max_idx = 0;
612 int mp_min = 63, min_idx = 0;
613 int mp_avg = 0, i, outlier_idx = 0, mp_count = 0;
614
615 /* find min/max mismatch across all calibrated gains */
616 for (i = 0; i < nmeasurement; i++) {
617 if (mp_coeff[i] > mp_max) {
618 mp_max = mp_coeff[i];
619 max_idx = i;
620 } else if (mp_coeff[i] < mp_min) {
621 mp_min = mp_coeff[i];
622 min_idx = i;
623 }
624 }
625
626 /* find average (exclude max abs value) */
627 for (i = 0; i < nmeasurement; i++) {
628 if ((abs(mp_coeff[i]) < abs(mp_max)) ||
629 (abs(mp_coeff[i]) < abs(mp_min))) {
630 mp_avg += mp_coeff[i];
631 mp_count++;
632 }
633 }
634
635 /*
636 * finding mean magnitude/phase if possible, otherwise
637 * just use the last value as the mean
638 */
639 if (mp_count)
640 mp_avg /= mp_count;
641 else
642 mp_avg = mp_coeff[nmeasurement - 1];
643
644 /* detect outlier */
645 if (abs(mp_max - mp_min) > max_delta) {
646 if (abs(mp_max - mp_avg) > abs(mp_min - mp_avg))
647 outlier_idx = max_idx;
648 else
649 outlier_idx = min_idx;
650
651 mp_coeff[outlier_idx] = mp_avg;
652 }
653 }
654
655 static void ar9003_hw_tx_iqcal_load_avg_2_passes(struct ath_hw *ah,
656 u8 num_chains,
657 struct coeff *coeff,
658 bool is_reusable)
659 {
660 int i, im, nmeasurement;
661 u32 tx_corr_coeff[MAX_MEASUREMENT][AR9300_MAX_CHAINS];
662 struct ath9k_hw_cal_data *caldata = ah->caldata;
663
664 memset(tx_corr_coeff, 0, sizeof(tx_corr_coeff));
665 for (i = 0; i < MAX_MEASUREMENT / 2; i++) {
666 tx_corr_coeff[i * 2][0] = tx_corr_coeff[(i * 2) + 1][0] =
667 AR_PHY_TX_IQCAL_CORR_COEFF_B0(i);
668 if (!AR_SREV_9485(ah)) {
669 tx_corr_coeff[i * 2][1] =
670 tx_corr_coeff[(i * 2) + 1][1] =
671 AR_PHY_TX_IQCAL_CORR_COEFF_B1(i);
672
673 tx_corr_coeff[i * 2][2] =
674 tx_corr_coeff[(i * 2) + 1][2] =
675 AR_PHY_TX_IQCAL_CORR_COEFF_B2(i);
676 }
677 }
678
679 /* Load the average of 2 passes */
680 for (i = 0; i < num_chains; i++) {
681 nmeasurement = REG_READ_FIELD(ah,
682 AR_PHY_TX_IQCAL_STATUS_B0,
683 AR_PHY_CALIBRATED_GAINS_0);
684
685 if (nmeasurement > MAX_MEASUREMENT)
686 nmeasurement = MAX_MEASUREMENT;
687
688 /* detect outlier only if nmeasurement > 1 */
689 if (nmeasurement > 1) {
690 /* Detect magnitude outlier */
691 ar9003_hw_detect_outlier(coeff->mag_coeff[i],
692 nmeasurement, MAX_MAG_DELTA);
693
694 /* Detect phase outlier */
695 ar9003_hw_detect_outlier(coeff->phs_coeff[i],
696 nmeasurement, MAX_PHS_DELTA);
697 }
698
699 for (im = 0; im < nmeasurement; im++) {
700
701 coeff->iqc_coeff[0] = (coeff->mag_coeff[i][im] & 0x7f) |
702 ((coeff->phs_coeff[i][im] & 0x7f) << 7);
703
704 if ((im % 2) == 0)
705 REG_RMW_FIELD(ah, tx_corr_coeff[im][i],
706 AR_PHY_TX_IQCAL_CORR_COEFF_00_COEFF_TABLE,
707 coeff->iqc_coeff[0]);
708 else
709 REG_RMW_FIELD(ah, tx_corr_coeff[im][i],
710 AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE,
711 coeff->iqc_coeff[0]);
712
713 if (caldata)
714 caldata->tx_corr_coeff[im][i] =
715 coeff->iqc_coeff[0];
716 }
717 if (caldata)
718 caldata->num_measures[i] = nmeasurement;
719 }
720
721 REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_3,
722 AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN, 0x1);
723 REG_RMW_FIELD(ah, AR_PHY_RX_IQCAL_CORR_B0,
724 AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN, 0x1);
725
726 if (caldata)
727 caldata->done_txiqcal_once = is_reusable;
728
729 return;
730 }
731
732 static bool ar9003_hw_tx_iq_cal_run(struct ath_hw *ah)
733 {
734 struct ath_common *common = ath9k_hw_common(ah);
735 u8 tx_gain_forced;
736
737 tx_gain_forced = REG_READ_FIELD(ah, AR_PHY_TX_FORCED_GAIN,
738 AR_PHY_TXGAIN_FORCE);
739 if (tx_gain_forced)
740 REG_RMW_FIELD(ah, AR_PHY_TX_FORCED_GAIN,
741 AR_PHY_TXGAIN_FORCE, 0);
742
743 REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_START,
744 AR_PHY_TX_IQCAL_START_DO_CAL, 1);
745
746 if (!ath9k_hw_wait(ah, AR_PHY_TX_IQCAL_START,
747 AR_PHY_TX_IQCAL_START_DO_CAL, 0,
748 AH_WAIT_TIMEOUT)) {
749 ath_dbg(common, CALIBRATE, "Tx IQ Cal is not completed\n");
750 return false;
751 }
752 return true;
753 }
754
755 static void ar9003_hw_tx_iq_cal_post_proc(struct ath_hw *ah, bool is_reusable)
756 {
757 struct ath_common *common = ath9k_hw_common(ah);
758 const u32 txiqcal_status[AR9300_MAX_CHAINS] = {
759 AR_PHY_TX_IQCAL_STATUS_B0,
760 AR_PHY_TX_IQCAL_STATUS_B1,
761 AR_PHY_TX_IQCAL_STATUS_B2,
762 };
763 const u_int32_t chan_info_tab[] = {
764 AR_PHY_CHAN_INFO_TAB_0,
765 AR_PHY_CHAN_INFO_TAB_1,
766 AR_PHY_CHAN_INFO_TAB_2,
767 };
768 struct coeff coeff;
769 s32 iq_res[6];
770 u8 num_chains = 0;
771 int i, im, j;
772 int nmeasurement;
773
774 for (i = 0; i < AR9300_MAX_CHAINS; i++) {
775 if (ah->txchainmask & (1 << i))
776 num_chains++;
777 }
778
779 for (i = 0; i < num_chains; i++) {
780 nmeasurement = REG_READ_FIELD(ah,
781 AR_PHY_TX_IQCAL_STATUS_B0,
782 AR_PHY_CALIBRATED_GAINS_0);
783 if (nmeasurement > MAX_MEASUREMENT)
784 nmeasurement = MAX_MEASUREMENT;
785
786 for (im = 0; im < nmeasurement; im++) {
787 ath_dbg(common, CALIBRATE,
788 "Doing Tx IQ Cal for chain %d\n", i);
789
790 if (REG_READ(ah, txiqcal_status[i]) &
791 AR_PHY_TX_IQCAL_STATUS_FAILED) {
792 ath_dbg(common, CALIBRATE,
793 "Tx IQ Cal failed for chain %d\n", i);
794 goto tx_iqcal_fail;
795 }
796
797 for (j = 0; j < 3; j++) {
798 u32 idx = 2 * j, offset = 4 * (3 * im + j);
799
800 REG_RMW_FIELD(ah,
801 AR_PHY_CHAN_INFO_MEMORY,
802 AR_PHY_CHAN_INFO_TAB_S2_READ,
803 0);
804
805 /* 32 bits */
806 iq_res[idx] = REG_READ(ah,
807 chan_info_tab[i] +
808 offset);
809
810 REG_RMW_FIELD(ah,
811 AR_PHY_CHAN_INFO_MEMORY,
812 AR_PHY_CHAN_INFO_TAB_S2_READ,
813 1);
814
815 /* 16 bits */
816 iq_res[idx + 1] = 0xffff & REG_READ(ah,
817 chan_info_tab[i] + offset);
818
819 ath_dbg(common, CALIBRATE,
820 "IQ_RES[%d]=0x%x IQ_RES[%d]=0x%x\n",
821 idx, iq_res[idx], idx + 1,
822 iq_res[idx + 1]);
823 }
824
825 if (!ar9003_hw_calc_iq_corr(ah, i, iq_res,
826 coeff.iqc_coeff)) {
827 ath_dbg(common, CALIBRATE,
828 "Failed in calculation of IQ correction\n");
829 goto tx_iqcal_fail;
830 }
831
832 coeff.mag_coeff[i][im] = coeff.iqc_coeff[0] & 0x7f;
833 coeff.phs_coeff[i][im] =
834 (coeff.iqc_coeff[0] >> 7) & 0x7f;
835
836 if (coeff.mag_coeff[i][im] > 63)
837 coeff.mag_coeff[i][im] -= 128;
838 if (coeff.phs_coeff[i][im] > 63)
839 coeff.phs_coeff[i][im] -= 128;
840 }
841 }
842 ar9003_hw_tx_iqcal_load_avg_2_passes(ah, num_chains,
843 &coeff, is_reusable);
844
845 return;
846
847 tx_iqcal_fail:
848 ath_dbg(common, CALIBRATE, "Tx IQ Cal failed\n");
849 return;
850 }
851
852 static void ar9003_hw_tx_iq_cal_reload(struct ath_hw *ah)
853 {
854 struct ath9k_hw_cal_data *caldata = ah->caldata;
855 u32 tx_corr_coeff[MAX_MEASUREMENT][AR9300_MAX_CHAINS];
856 int i, im;
857
858 memset(tx_corr_coeff, 0, sizeof(tx_corr_coeff));
859 for (i = 0; i < MAX_MEASUREMENT / 2; i++) {
860 tx_corr_coeff[i * 2][0] = tx_corr_coeff[(i * 2) + 1][0] =
861 AR_PHY_TX_IQCAL_CORR_COEFF_B0(i);
862 if (!AR_SREV_9485(ah)) {
863 tx_corr_coeff[i * 2][1] =
864 tx_corr_coeff[(i * 2) + 1][1] =
865 AR_PHY_TX_IQCAL_CORR_COEFF_B1(i);
866
867 tx_corr_coeff[i * 2][2] =
868 tx_corr_coeff[(i * 2) + 1][2] =
869 AR_PHY_TX_IQCAL_CORR_COEFF_B2(i);
870 }
871 }
872
873 for (i = 0; i < AR9300_MAX_CHAINS; i++) {
874 if (!(ah->txchainmask & (1 << i)))
875 continue;
876
877 for (im = 0; im < caldata->num_measures[i]; im++) {
878 if ((im % 2) == 0)
879 REG_RMW_FIELD(ah, tx_corr_coeff[im][i],
880 AR_PHY_TX_IQCAL_CORR_COEFF_00_COEFF_TABLE,
881 caldata->tx_corr_coeff[im][i]);
882 else
883 REG_RMW_FIELD(ah, tx_corr_coeff[im][i],
884 AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE,
885 caldata->tx_corr_coeff[im][i]);
886 }
887 }
888
889 REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_3,
890 AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN, 0x1);
891 REG_RMW_FIELD(ah, AR_PHY_RX_IQCAL_CORR_B0,
892 AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN, 0x1);
893 }
894
895 static bool ar9003_hw_rtt_restore(struct ath_hw *ah, struct ath9k_channel *chan)
896 {
897 struct ath9k_rtt_hist *hist;
898 u32 *table;
899 int i;
900 bool restore;
901
902 if (!ah->caldata)
903 return false;
904
905 hist = &ah->caldata->rtt_hist;
906 if (!hist->num_readings)
907 return false;
908
909 ar9003_hw_rtt_enable(ah);
910 ar9003_hw_rtt_set_mask(ah, 0x00);
911 for (i = 0; i < AR9300_MAX_CHAINS; i++) {
912 if (!(ah->rxchainmask & (1 << i)))
913 continue;
914 table = &hist->table[i][hist->num_readings][0];
915 ar9003_hw_rtt_load_hist(ah, i, table);
916 }
917 restore = ar9003_hw_rtt_force_restore(ah);
918 ar9003_hw_rtt_disable(ah);
919
920 return restore;
921 }
922
923 static bool ar9003_hw_init_cal(struct ath_hw *ah,
924 struct ath9k_channel *chan)
925 {
926 struct ath_common *common = ath9k_hw_common(ah);
927 struct ath9k_hw_cal_data *caldata = ah->caldata;
928 struct ath9k_hw_mci *mci_hw = &ah->btcoex_hw.mci;
929 bool txiqcal_done = false, txclcal_done = false;
930 bool is_reusable = true, status = true;
931 bool run_rtt_cal = false, run_agc_cal;
932 bool rtt = !!(ah->caps.hw_caps & ATH9K_HW_CAP_RTT);
933 bool mci = !!(ah->caps.hw_caps & ATH9K_HW_CAP_MCI);
934 u32 agc_ctrl = 0, agc_supp_cals = AR_PHY_AGC_CONTROL_OFFSET_CAL |
935 AR_PHY_AGC_CONTROL_FLTR_CAL |
936 AR_PHY_AGC_CONTROL_PKDET_CAL;
937 int i, j;
938 u32 cl_idx[AR9300_MAX_CHAINS] = { AR_PHY_CL_TAB_0,
939 AR_PHY_CL_TAB_1,
940 AR_PHY_CL_TAB_2 };
941
942 if (rtt) {
943 if (!ar9003_hw_rtt_restore(ah, chan))
944 run_rtt_cal = true;
945
946 ath_dbg(common, CALIBRATE, "RTT restore %s\n",
947 run_rtt_cal ? "failed" : "succeed");
948 }
949 run_agc_cal = run_rtt_cal;
950
951 if (run_rtt_cal) {
952 ar9003_hw_rtt_enable(ah);
953 ar9003_hw_rtt_set_mask(ah, 0x00);
954 ar9003_hw_rtt_clear_hist(ah);
955 }
956
957 if (rtt && !run_rtt_cal) {
958 agc_ctrl = REG_READ(ah, AR_PHY_AGC_CONTROL);
959 agc_supp_cals &= agc_ctrl;
960 agc_ctrl &= ~(AR_PHY_AGC_CONTROL_OFFSET_CAL |
961 AR_PHY_AGC_CONTROL_FLTR_CAL |
962 AR_PHY_AGC_CONTROL_PKDET_CAL);
963 REG_WRITE(ah, AR_PHY_AGC_CONTROL, agc_ctrl);
964 }
965
966 if (ah->enabled_cals & TX_CL_CAL) {
967 if (caldata && caldata->done_txclcal_once)
968 REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL,
969 AR_PHY_CL_CAL_ENABLE);
970 else {
971 REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL,
972 AR_PHY_CL_CAL_ENABLE);
973 run_agc_cal = true;
974 }
975 }
976
977 if (!(ah->enabled_cals & TX_IQ_CAL))
978 goto skip_tx_iqcal;
979
980 /* Do Tx IQ Calibration */
981 REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_1,
982 AR_PHY_TX_IQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT,
983 DELPT);
984
985 /*
986 * For AR9485 or later chips, TxIQ cal runs as part of
987 * AGC calibration
988 */
989 if (ah->enabled_cals & TX_IQ_ON_AGC_CAL) {
990 if (caldata && !caldata->done_txiqcal_once)
991 REG_SET_BIT(ah, AR_PHY_TX_IQCAL_CONTROL_0,
992 AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL);
993 else
994 REG_CLR_BIT(ah, AR_PHY_TX_IQCAL_CONTROL_0,
995 AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL);
996 txiqcal_done = run_agc_cal = true;
997 goto skip_tx_iqcal;
998 } else if (caldata && !caldata->done_txiqcal_once)
999 run_agc_cal = true;
1000
1001 if (mci && IS_CHAN_2GHZ(chan) &&
1002 (mci_hw->bt_state == MCI_BT_AWAKE) &&
1003 run_agc_cal &&
1004 !(mci_hw->config & ATH_MCI_CONFIG_DISABLE_MCI_CAL)) {
1005
1006 u32 pld[4] = {0, 0, 0, 0};
1007
1008 /* send CAL_REQ only when BT is AWAKE. */
1009 ath_dbg(common, MCI, "MCI send WLAN_CAL_REQ 0x%x\n",
1010 mci_hw->wlan_cal_seq);
1011 MCI_GPM_SET_CAL_TYPE(pld, MCI_GPM_WLAN_CAL_REQ);
1012 pld[MCI_GPM_WLAN_CAL_W_SEQUENCE] = mci_hw->wlan_cal_seq++;
1013 ar9003_mci_send_message(ah, MCI_GPM, 0, pld, 16, true, false);
1014
1015 /* Wait BT_CAL_GRANT for 50ms */
1016 ath_dbg(common, MCI, "MCI wait for BT_CAL_GRANT\n");
1017
1018 if (ar9003_mci_wait_for_gpm(ah, MCI_GPM_BT_CAL_GRANT, 0, 50000))
1019 ath_dbg(common, MCI, "MCI got BT_CAL_GRANT\n");
1020 else {
1021 is_reusable = false;
1022 ath_dbg(common, MCI, "\nMCI BT is not responding\n");
1023 }
1024 }
1025
1026 txiqcal_done = ar9003_hw_tx_iq_cal_run(ah);
1027 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1028 udelay(5);
1029 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
1030
1031 skip_tx_iqcal:
1032 if (run_agc_cal || !(ah->ah_flags & AH_FASTCC)) {
1033 /* Calibrate the AGC */
1034 REG_WRITE(ah, AR_PHY_AGC_CONTROL,
1035 REG_READ(ah, AR_PHY_AGC_CONTROL) |
1036 AR_PHY_AGC_CONTROL_CAL);
1037
1038 /* Poll for offset calibration complete */
1039 status = ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL,
1040 AR_PHY_AGC_CONTROL_CAL,
1041 0, AH_WAIT_TIMEOUT);
1042 }
1043
1044 if (mci && IS_CHAN_2GHZ(chan) &&
1045 (mci_hw->bt_state == MCI_BT_AWAKE) &&
1046 run_agc_cal &&
1047 !(mci_hw->config & ATH_MCI_CONFIG_DISABLE_MCI_CAL)) {
1048
1049 u32 pld[4] = {0, 0, 0, 0};
1050
1051 ath_dbg(common, MCI, "MCI Send WLAN_CAL_DONE 0x%x\n",
1052 mci_hw->wlan_cal_done);
1053 MCI_GPM_SET_CAL_TYPE(pld, MCI_GPM_WLAN_CAL_DONE);
1054 pld[MCI_GPM_WLAN_CAL_W_SEQUENCE] = mci_hw->wlan_cal_done++;
1055 ar9003_mci_send_message(ah, MCI_GPM, 0, pld, 16, true, false);
1056 }
1057
1058 if (rtt && !run_rtt_cal) {
1059 agc_ctrl |= agc_supp_cals;
1060 REG_WRITE(ah, AR_PHY_AGC_CONTROL, agc_ctrl);
1061 }
1062
1063 if (!status) {
1064 if (run_rtt_cal)
1065 ar9003_hw_rtt_disable(ah);
1066
1067 ath_dbg(common, CALIBRATE,
1068 "offset calibration failed to complete in 1ms; noisy environment?\n");
1069 return false;
1070 }
1071
1072 if (txiqcal_done)
1073 ar9003_hw_tx_iq_cal_post_proc(ah, is_reusable);
1074 else if (caldata && caldata->done_txiqcal_once)
1075 ar9003_hw_tx_iq_cal_reload(ah);
1076
1077 #define CL_TAB_ENTRY(reg_base) (reg_base + (4 * j))
1078 if (caldata && (ah->enabled_cals & TX_CL_CAL)) {
1079 txclcal_done = !!(REG_READ(ah, AR_PHY_AGC_CONTROL) &
1080 AR_PHY_AGC_CONTROL_CLC_SUCCESS);
1081 if (caldata->done_txclcal_once) {
1082 for (i = 0; i < AR9300_MAX_CHAINS; i++) {
1083 if (!(ah->txchainmask & (1 << i)))
1084 continue;
1085 for (j = 0; j < MAX_CL_TAB_ENTRY; j++)
1086 REG_WRITE(ah, CL_TAB_ENTRY(cl_idx[i]),
1087 caldata->tx_clcal[i][j]);
1088 }
1089 } else if (is_reusable && txclcal_done) {
1090 for (i = 0; i < AR9300_MAX_CHAINS; i++) {
1091 if (!(ah->txchainmask & (1 << i)))
1092 continue;
1093 for (j = 0; j < MAX_CL_TAB_ENTRY; j++)
1094 caldata->tx_clcal[i][j] =
1095 REG_READ(ah,
1096 CL_TAB_ENTRY(cl_idx[i]));
1097 }
1098 caldata->done_txclcal_once = true;
1099 }
1100 }
1101 #undef CL_TAB_ENTRY
1102
1103 if (run_rtt_cal && caldata) {
1104 struct ath9k_rtt_hist *hist = &caldata->rtt_hist;
1105 if (is_reusable && (hist->num_readings < RTT_HIST_MAX)) {
1106 u32 *table;
1107
1108 hist->num_readings++;
1109 for (i = 0; i < AR9300_MAX_CHAINS; i++) {
1110 if (!(ah->rxchainmask & (1 << i)))
1111 continue;
1112 table = &hist->table[i][hist->num_readings][0];
1113 ar9003_hw_rtt_fill_hist(ah, i, table);
1114 }
1115 }
1116
1117 ar9003_hw_rtt_disable(ah);
1118 }
1119
1120 /* Initialize list pointers */
1121 ah->cal_list = ah->cal_list_last = ah->cal_list_curr = NULL;
1122 ah->supp_cals = IQ_MISMATCH_CAL;
1123
1124 if (ah->supp_cals & IQ_MISMATCH_CAL) {
1125 INIT_CAL(&ah->iq_caldata);
1126 INSERT_CAL(ah, &ah->iq_caldata);
1127 ath_dbg(common, CALIBRATE, "enabling IQ Calibration\n");
1128 }
1129
1130 if (ah->supp_cals & TEMP_COMP_CAL) {
1131 INIT_CAL(&ah->tempCompCalData);
1132 INSERT_CAL(ah, &ah->tempCompCalData);
1133 ath_dbg(common, CALIBRATE,
1134 "enabling Temperature Compensation Calibration\n");
1135 }
1136
1137 /* Initialize current pointer to first element in list */
1138 ah->cal_list_curr = ah->cal_list;
1139
1140 if (ah->cal_list_curr)
1141 ath9k_hw_reset_calibration(ah, ah->cal_list_curr);
1142
1143 if (caldata)
1144 caldata->CalValid = 0;
1145
1146 return true;
1147 }
1148
1149 void ar9003_hw_attach_calib_ops(struct ath_hw *ah)
1150 {
1151 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
1152 struct ath_hw_ops *ops = ath9k_hw_ops(ah);
1153
1154 priv_ops->init_cal_settings = ar9003_hw_init_cal_settings;
1155 priv_ops->init_cal = ar9003_hw_init_cal;
1156 priv_ops->setup_calibration = ar9003_hw_setup_calibration;
1157
1158 ops->calibrate = ar9003_hw_calibrate;
1159 }