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spi-topcliff-pch: add recovery processing in case wait-event timeout
[zen-stable.git] / drivers / net / wireless / ath / ath9k / ar9003_mac.c
blob09b8c9dbf78f5e3267ebfadc2d4bed15f9562487
1 /*
2 * Copyright (c) 2010-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16 #include <linux/export.h>
17 #include "hw.h"
18 #include "ar9003_mac.h"
19
20 static void ar9003_hw_rx_enable(struct ath_hw *hw)
21 {
22 REG_WRITE(hw, AR_CR, 0);
23 }
24
25 static void
26 ar9003_set_txdesc(struct ath_hw *ah, void *ds, struct ath_tx_info *i)
27 {
28 struct ar9003_txc *ads = ds;
29 int checksum = 0;
30 u32 val, ctl12, ctl17;
31
32 val = (ATHEROS_VENDOR_ID << AR_DescId_S) |
33 (1 << AR_TxRxDesc_S) |
34 (1 << AR_CtrlStat_S) |
35 (i->qcu << AR_TxQcuNum_S) | 0x17;
36
37 checksum += val;
38 ACCESS_ONCE(ads->info) = val;
39
40 checksum += i->link;
41 ACCESS_ONCE(ads->link) = i->link;
42
43 checksum += i->buf_addr[0];
44 ACCESS_ONCE(ads->data0) = i->buf_addr[0];
45 checksum += i->buf_addr[1];
46 ACCESS_ONCE(ads->data1) = i->buf_addr[1];
47 checksum += i->buf_addr[2];
48 ACCESS_ONCE(ads->data2) = i->buf_addr[2];
49 checksum += i->buf_addr[3];
50 ACCESS_ONCE(ads->data3) = i->buf_addr[3];
51
52 checksum += (val = (i->buf_len[0] << AR_BufLen_S) & AR_BufLen);
53 ACCESS_ONCE(ads->ctl3) = val;
54 checksum += (val = (i->buf_len[1] << AR_BufLen_S) & AR_BufLen);
55 ACCESS_ONCE(ads->ctl5) = val;
56 checksum += (val = (i->buf_len[2] << AR_BufLen_S) & AR_BufLen);
57 ACCESS_ONCE(ads->ctl7) = val;
58 checksum += (val = (i->buf_len[3] << AR_BufLen_S) & AR_BufLen);
59 ACCESS_ONCE(ads->ctl9) = val;
60
61 checksum = (u16) (((checksum & 0xffff) + (checksum >> 16)) & 0xffff);
62 ACCESS_ONCE(ads->ctl10) = checksum;
63
64 if (i->is_first || i->is_last) {
65 ACCESS_ONCE(ads->ctl13) = set11nTries(i->rates, 0)
66 | set11nTries(i->rates, 1)
67 | set11nTries(i->rates, 2)
68 | set11nTries(i->rates, 3)
69 | (i->dur_update ? AR_DurUpdateEna : 0)
70 | SM(0, AR_BurstDur);
71
72 ACCESS_ONCE(ads->ctl14) = set11nRate(i->rates, 0)
73 | set11nRate(i->rates, 1)
74 | set11nRate(i->rates, 2)
75 | set11nRate(i->rates, 3);
76 } else {
77 ACCESS_ONCE(ads->ctl13) = 0;
78 ACCESS_ONCE(ads->ctl14) = 0;
79 }
80
81 ads->ctl20 = 0;
82 ads->ctl21 = 0;
83 ads->ctl22 = 0;
84
85 ctl17 = SM(i->keytype, AR_EncrType);
86 if (!i->is_first) {
87 ACCESS_ONCE(ads->ctl11) = 0;
88 ACCESS_ONCE(ads->ctl12) = i->is_last ? 0 : AR_TxMore;
89 ACCESS_ONCE(ads->ctl15) = 0;
90 ACCESS_ONCE(ads->ctl16) = 0;
91 ACCESS_ONCE(ads->ctl17) = ctl17;
92 ACCESS_ONCE(ads->ctl18) = 0;
93 ACCESS_ONCE(ads->ctl19) = 0;
94 return;
95 }
96
97 ACCESS_ONCE(ads->ctl11) = (i->pkt_len & AR_FrameLen)
98 | (i->flags & ATH9K_TXDESC_VMF ? AR_VirtMoreFrag : 0)
99 | SM(i->txpower, AR_XmitPower)
100 | (i->flags & ATH9K_TXDESC_VEOL ? AR_VEOL : 0)
101 | (i->keyix != ATH9K_TXKEYIX_INVALID ? AR_DestIdxValid : 0)
102 | (i->flags & ATH9K_TXDESC_LOWRXCHAIN ? AR_LowRxChain : 0)
103 | (i->flags & ATH9K_TXDESC_CLRDMASK ? AR_ClrDestMask : 0)
104 | (i->flags & ATH9K_TXDESC_RTSENA ? AR_RTSEnable :
105 (i->flags & ATH9K_TXDESC_CTSENA ? AR_CTSEnable : 0));
106
107 ctl12 = (i->keyix != ATH9K_TXKEYIX_INVALID ?
108 SM(i->keyix, AR_DestIdx) : 0)
109 | SM(i->type, AR_FrameType)
110 | (i->flags & ATH9K_TXDESC_NOACK ? AR_NoAck : 0)
111 | (i->flags & ATH9K_TXDESC_EXT_ONLY ? AR_ExtOnly : 0)
112 | (i->flags & ATH9K_TXDESC_EXT_AND_CTL ? AR_ExtAndCtl : 0);
113
114 ctl17 |= (i->flags & ATH9K_TXDESC_LDPC ? AR_LDPC : 0);
115 switch (i->aggr) {
116 case AGGR_BUF_FIRST:
117 ctl17 |= SM(i->aggr_len, AR_AggrLen);
118 /* fall through */
119 case AGGR_BUF_MIDDLE:
120 ctl12 |= AR_IsAggr | AR_MoreAggr;
121 ctl17 |= SM(i->ndelim, AR_PadDelim);
122 break;
123 case AGGR_BUF_LAST:
124 ctl12 |= AR_IsAggr;
125 break;
126 case AGGR_BUF_NONE:
127 break;
128 }
129
130 val = (i->flags & ATH9K_TXDESC_PAPRD) >> ATH9K_TXDESC_PAPRD_S;
131 ctl12 |= SM(val, AR_PAPRDChainMask);
132
133 ACCESS_ONCE(ads->ctl12) = ctl12;
134 ACCESS_ONCE(ads->ctl17) = ctl17;
135
136 ACCESS_ONCE(ads->ctl15) = set11nPktDurRTSCTS(i->rates, 0)
137 | set11nPktDurRTSCTS(i->rates, 1);
138
139 ACCESS_ONCE(ads->ctl16) = set11nPktDurRTSCTS(i->rates, 2)
140 | set11nPktDurRTSCTS(i->rates, 3);
141
142 ACCESS_ONCE(ads->ctl18) = set11nRateFlags(i->rates, 0)
143 | set11nRateFlags(i->rates, 1)
144 | set11nRateFlags(i->rates, 2)
145 | set11nRateFlags(i->rates, 3)
146 | SM(i->rtscts_rate, AR_RTSCTSRate);
147
148 ACCESS_ONCE(ads->ctl19) = AR_Not_Sounding;
149 }
150
151 static u16 ar9003_calc_ptr_chksum(struct ar9003_txc *ads)
152 {
153 int checksum;
154
155 checksum = ads->info + ads->link
156 + ads->data0 + ads->ctl3
157 + ads->data1 + ads->ctl5
158 + ads->data2 + ads->ctl7
159 + ads->data3 + ads->ctl9;
160
161 return ((checksum & 0xffff) + (checksum >> 16)) & AR_TxPtrChkSum;
162 }
163
164 static void ar9003_hw_set_desc_link(void *ds, u32 ds_link)
165 {
166 struct ar9003_txc *ads = ds;
167
168 ads->link = ds_link;
169 ads->ctl10 &= ~AR_TxPtrChkSum;
170 ads->ctl10 |= ar9003_calc_ptr_chksum(ads);
171 }
172
173 static bool ar9003_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked)
174 {
175 u32 isr = 0;
176 u32 mask2 = 0;
177 struct ath9k_hw_capabilities *pCap = &ah->caps;
178 struct ath_common *common = ath9k_hw_common(ah);
179 struct ath9k_hw_mci *mci = &ah->btcoex_hw.mci;
180 u32 sync_cause = 0, async_cause;
181
182 async_cause = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
183
184 if (async_cause & (AR_INTR_MAC_IRQ | AR_INTR_ASYNC_MASK_MCI)) {
185 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
186 == AR_RTC_STATUS_ON)
187 isr = REG_READ(ah, AR_ISR);
188 }
189
190
191 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) & AR_INTR_SYNC_DEFAULT;
192
193 *masked = 0;
194
195 if (!isr && !sync_cause && !async_cause)
196 return false;
197
198 if (isr) {
199 if (isr & AR_ISR_BCNMISC) {
200 u32 isr2;
201 isr2 = REG_READ(ah, AR_ISR_S2);
202
203 mask2 |= ((isr2 & AR_ISR_S2_TIM) >>
204 MAP_ISR_S2_TIM);
205 mask2 |= ((isr2 & AR_ISR_S2_DTIM) >>
206 MAP_ISR_S2_DTIM);
207 mask2 |= ((isr2 & AR_ISR_S2_DTIMSYNC) >>
208 MAP_ISR_S2_DTIMSYNC);
209 mask2 |= ((isr2 & AR_ISR_S2_CABEND) >>
210 MAP_ISR_S2_CABEND);
211 mask2 |= ((isr2 & AR_ISR_S2_GTT) <<
212 MAP_ISR_S2_GTT);
213 mask2 |= ((isr2 & AR_ISR_S2_CST) <<
214 MAP_ISR_S2_CST);
215 mask2 |= ((isr2 & AR_ISR_S2_TSFOOR) >>
216 MAP_ISR_S2_TSFOOR);
217 mask2 |= ((isr2 & AR_ISR_S2_BB_WATCHDOG) >>
218 MAP_ISR_S2_BB_WATCHDOG);
219
220 if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) {
221 REG_WRITE(ah, AR_ISR_S2, isr2);
222 isr &= ~AR_ISR_BCNMISC;
223 }
224 }
225
226 if ((pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED))
227 isr = REG_READ(ah, AR_ISR_RAC);
228
229 if (isr == 0xffffffff) {
230 *masked = 0;
231 return false;
232 }
233
234 *masked = isr & ATH9K_INT_COMMON;
235
236 if (ah->config.rx_intr_mitigation)
237 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
238 *masked |= ATH9K_INT_RXLP;
239
240 if (ah->config.tx_intr_mitigation)
241 if (isr & (AR_ISR_TXMINTR | AR_ISR_TXINTM))
242 *masked |= ATH9K_INT_TX;
243
244 if (isr & (AR_ISR_LP_RXOK | AR_ISR_RXERR))
245 *masked |= ATH9K_INT_RXLP;
246
247 if (isr & AR_ISR_HP_RXOK)
248 *masked |= ATH9K_INT_RXHP;
249
250 if (isr & (AR_ISR_TXOK | AR_ISR_TXERR | AR_ISR_TXEOL)) {
251 *masked |= ATH9K_INT_TX;
252
253 if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) {
254 u32 s0, s1;
255 s0 = REG_READ(ah, AR_ISR_S0);
256 REG_WRITE(ah, AR_ISR_S0, s0);
257 s1 = REG_READ(ah, AR_ISR_S1);
258 REG_WRITE(ah, AR_ISR_S1, s1);
259
260 isr &= ~(AR_ISR_TXOK | AR_ISR_TXERR |
261 AR_ISR_TXEOL);
262 }
263 }
264
265 if (isr & AR_ISR_GENTMR) {
266 u32 s5;
267
268 if (pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)
269 s5 = REG_READ(ah, AR_ISR_S5_S);
270 else
271 s5 = REG_READ(ah, AR_ISR_S5);
272
273 ah->intr_gen_timer_trigger =
274 MS(s5, AR_ISR_S5_GENTIMER_TRIG);
275
276 ah->intr_gen_timer_thresh =
277 MS(s5, AR_ISR_S5_GENTIMER_THRESH);
278
279 if (ah->intr_gen_timer_trigger)
280 *masked |= ATH9K_INT_GENTIMER;
281
282 if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) {
283 REG_WRITE(ah, AR_ISR_S5, s5);
284 isr &= ~AR_ISR_GENTMR;
285 }
286
287 }
288
289 *masked |= mask2;
290
291 if (!(pCap->hw_caps & ATH9K_HW_CAP_RAC_SUPPORTED)) {
292 REG_WRITE(ah, AR_ISR, isr);
293
294 (void) REG_READ(ah, AR_ISR);
295 }
296
297 if (*masked & ATH9K_INT_BB_WATCHDOG)
298 ar9003_hw_bb_watchdog_read(ah);
299 }
300
301 if (async_cause & AR_INTR_ASYNC_MASK_MCI) {
302 u32 raw_intr, rx_msg_intr;
303
304 rx_msg_intr = REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_RAW);
305 raw_intr = REG_READ(ah, AR_MCI_INTERRUPT_RAW);
306
307 if ((raw_intr == 0xdeadbeef) || (rx_msg_intr == 0xdeadbeef))
308 ath_dbg(common, MCI,
309 "MCI gets 0xdeadbeef during MCI int processing new raw_intr=0x%08x, new rx_msg_raw=0x%08x, raw_intr=0x%08x, rx_msg_raw=0x%08x\n",
310 raw_intr, rx_msg_intr, mci->raw_intr,
311 mci->rx_msg_intr);
312 else {
313 mci->rx_msg_intr |= rx_msg_intr;
314 mci->raw_intr |= raw_intr;
315 *masked |= ATH9K_INT_MCI;
316
317 if (rx_msg_intr & AR_MCI_INTERRUPT_RX_MSG_CONT_INFO)
318 mci->cont_status =
319 REG_READ(ah, AR_MCI_CONT_STATUS);
320
321 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_RAW, rx_msg_intr);
322 REG_WRITE(ah, AR_MCI_INTERRUPT_RAW, raw_intr);
323 ath_dbg(common, MCI, "AR_INTR_SYNC_MCI\n");
324
325 }
326 }
327
328 if (sync_cause) {
329 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
330 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
331 REG_WRITE(ah, AR_RC, 0);
332 *masked |= ATH9K_INT_FATAL;
333 }
334
335 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT)
336 ath_dbg(common, INTERRUPT,
337 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
338
339 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
340 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
341
342 }
343 return true;
344 }
345
346 static int ar9003_hw_proc_txdesc(struct ath_hw *ah, void *ds,
347 struct ath_tx_status *ts)
348 {
349 struct ar9003_txc *txc = (struct ar9003_txc *) ds;
350 struct ar9003_txs *ads;
351 u32 status;
352
353 ads = &ah->ts_ring[ah->ts_tail];
354
355 status = ACCESS_ONCE(ads->status8);
356 if ((status & AR_TxDone) == 0)
357 return -EINPROGRESS;
358
359 ts->qid = MS(ads->ds_info, AR_TxQcuNum);
360 if (!txc || (MS(txc->info, AR_TxQcuNum) == ts->qid))
361 ah->ts_tail = (ah->ts_tail + 1) % ah->ts_size;
362 else
363 return -ENOENT;
364
365 if ((MS(ads->ds_info, AR_DescId) != ATHEROS_VENDOR_ID) ||
366 (MS(ads->ds_info, AR_TxRxDesc) != 1)) {
367 ath_dbg(ath9k_hw_common(ah), XMIT,
368 "Tx Descriptor error %x\n", ads->ds_info);
369 memset(ads, 0, sizeof(*ads));
370 return -EIO;
371 }
372
373 ts->ts_rateindex = MS(status, AR_FinalTxIdx);
374 ts->ts_seqnum = MS(status, AR_SeqNum);
375 ts->tid = MS(status, AR_TxTid);
376
377 ts->desc_id = MS(ads->status1, AR_TxDescId);
378 ts->ts_tstamp = ads->status4;
379 ts->ts_status = 0;
380 ts->ts_flags = 0;
381
382 if (status & AR_TxOpExceeded)
383 ts->ts_status |= ATH9K_TXERR_XTXOP;
384 status = ACCESS_ONCE(ads->status2);
385 ts->ts_rssi_ctl0 = MS(status, AR_TxRSSIAnt00);
386 ts->ts_rssi_ctl1 = MS(status, AR_TxRSSIAnt01);
387 ts->ts_rssi_ctl2 = MS(status, AR_TxRSSIAnt02);
388 if (status & AR_TxBaStatus) {
389 ts->ts_flags |= ATH9K_TX_BA;
390 ts->ba_low = ads->status5;
391 ts->ba_high = ads->status6;
392 }
393
394 status = ACCESS_ONCE(ads->status3);
395 if (status & AR_ExcessiveRetries)
396 ts->ts_status |= ATH9K_TXERR_XRETRY;
397 if (status & AR_Filtered)
398 ts->ts_status |= ATH9K_TXERR_FILT;
399 if (status & AR_FIFOUnderrun) {
400 ts->ts_status |= ATH9K_TXERR_FIFO;
401 ath9k_hw_updatetxtriglevel(ah, true);
402 }
403 if (status & AR_TxTimerExpired)
404 ts->ts_status |= ATH9K_TXERR_TIMER_EXPIRED;
405 if (status & AR_DescCfgErr)
406 ts->ts_flags |= ATH9K_TX_DESC_CFG_ERR;
407 if (status & AR_TxDataUnderrun) {
408 ts->ts_flags |= ATH9K_TX_DATA_UNDERRUN;
409 ath9k_hw_updatetxtriglevel(ah, true);
410 }
411 if (status & AR_TxDelimUnderrun) {
412 ts->ts_flags |= ATH9K_TX_DELIM_UNDERRUN;
413 ath9k_hw_updatetxtriglevel(ah, true);
414 }
415 ts->ts_shortretry = MS(status, AR_RTSFailCnt);
416 ts->ts_longretry = MS(status, AR_DataFailCnt);
417 ts->ts_virtcol = MS(status, AR_VirtRetryCnt);
418
419 status = ACCESS_ONCE(ads->status7);
420 ts->ts_rssi = MS(status, AR_TxRSSICombined);
421 ts->ts_rssi_ext0 = MS(status, AR_TxRSSIAnt10);
422 ts->ts_rssi_ext1 = MS(status, AR_TxRSSIAnt11);
423 ts->ts_rssi_ext2 = MS(status, AR_TxRSSIAnt12);
424
425 memset(ads, 0, sizeof(*ads));
426
427 return 0;
428 }
429
430 void ar9003_hw_attach_mac_ops(struct ath_hw *hw)
431 {
432 struct ath_hw_ops *ops = ath9k_hw_ops(hw);
433
434 ops->rx_enable = ar9003_hw_rx_enable;
435 ops->set_desc_link = ar9003_hw_set_desc_link;
436 ops->get_isr = ar9003_hw_get_isr;
437 ops->set_txdesc = ar9003_set_txdesc;
438 ops->proc_txdesc = ar9003_hw_proc_txdesc;
439 }
440
441 void ath9k_hw_set_rx_bufsize(struct ath_hw *ah, u16 buf_size)
442 {
443 REG_WRITE(ah, AR_DATABUF_SIZE, buf_size & AR_DATABUF_SIZE_MASK);
444 }
445 EXPORT_SYMBOL(ath9k_hw_set_rx_bufsize);
446
447 void ath9k_hw_addrxbuf_edma(struct ath_hw *ah, u32 rxdp,
448 enum ath9k_rx_qtype qtype)
449 {
450 if (qtype == ATH9K_RX_QUEUE_HP)
451 REG_WRITE(ah, AR_HP_RXDP, rxdp);
452 else
453 REG_WRITE(ah, AR_LP_RXDP, rxdp);
454 }
455 EXPORT_SYMBOL(ath9k_hw_addrxbuf_edma);
456
457 int ath9k_hw_process_rxdesc_edma(struct ath_hw *ah, struct ath_rx_status *rxs,
458 void *buf_addr)
459 {
460 struct ar9003_rxs *rxsp = (struct ar9003_rxs *) buf_addr;
461 unsigned int phyerr;
462
463 /* TODO: byte swap on big endian for ar9300_10 */
464
465 if (!rxs) {
466 if ((rxsp->status11 & AR_RxDone) == 0)
467 return -EINPROGRESS;
468
469 if (MS(rxsp->ds_info, AR_DescId) != 0x168c)
470 return -EINVAL;
471
472 if ((rxsp->ds_info & (AR_TxRxDesc | AR_CtrlStat)) != 0)
473 return -EINPROGRESS;
474
475 return 0;
476 }
477
478 rxs->rs_status = 0;
479 rxs->rs_flags = 0;
480
481 rxs->rs_datalen = rxsp->status2 & AR_DataLen;
482 rxs->rs_tstamp = rxsp->status3;
483
484 /* XXX: Keycache */
485 rxs->rs_rssi = MS(rxsp->status5, AR_RxRSSICombined);
486 rxs->rs_rssi_ctl0 = MS(rxsp->status1, AR_RxRSSIAnt00);
487 rxs->rs_rssi_ctl1 = MS(rxsp->status1, AR_RxRSSIAnt01);
488 rxs->rs_rssi_ctl2 = MS(rxsp->status1, AR_RxRSSIAnt02);
489 rxs->rs_rssi_ext0 = MS(rxsp->status5, AR_RxRSSIAnt10);
490 rxs->rs_rssi_ext1 = MS(rxsp->status5, AR_RxRSSIAnt11);
491 rxs->rs_rssi_ext2 = MS(rxsp->status5, AR_RxRSSIAnt12);
492
493 if (rxsp->status11 & AR_RxKeyIdxValid)
494 rxs->rs_keyix = MS(rxsp->status11, AR_KeyIdx);
495 else
496 rxs->rs_keyix = ATH9K_RXKEYIX_INVALID;
497
498 rxs->rs_rate = MS(rxsp->status1, AR_RxRate);
499 rxs->rs_more = (rxsp->status2 & AR_RxMore) ? 1 : 0;
500
501 rxs->rs_isaggr = (rxsp->status11 & AR_RxAggr) ? 1 : 0;
502 rxs->rs_moreaggr = (rxsp->status11 & AR_RxMoreAggr) ? 1 : 0;
503 rxs->rs_antenna = (MS(rxsp->status4, AR_RxAntenna) & 0x7);
504 rxs->rs_flags = (rxsp->status4 & AR_GI) ? ATH9K_RX_GI : 0;
505 rxs->rs_flags |= (rxsp->status4 & AR_2040) ? ATH9K_RX_2040 : 0;
506
507 rxs->evm0 = rxsp->status6;
508 rxs->evm1 = rxsp->status7;
509 rxs->evm2 = rxsp->status8;
510 rxs->evm3 = rxsp->status9;
511 rxs->evm4 = (rxsp->status10 & 0xffff);
512
513 if (rxsp->status11 & AR_PreDelimCRCErr)
514 rxs->rs_flags |= ATH9K_RX_DELIM_CRC_PRE;
515
516 if (rxsp->status11 & AR_PostDelimCRCErr)
517 rxs->rs_flags |= ATH9K_RX_DELIM_CRC_POST;
518
519 if (rxsp->status11 & AR_DecryptBusyErr)
520 rxs->rs_flags |= ATH9K_RX_DECRYPT_BUSY;
521
522 if ((rxsp->status11 & AR_RxFrameOK) == 0) {
523 /*
524 * AR_CRCErr will bet set to true if we're on the last
525 * subframe and the AR_PostDelimCRCErr is caught.
526 * In a way this also gives us a guarantee that when
527 * (!(AR_CRCErr) && (AR_PostDelimCRCErr)) we cannot
528 * possibly be reviewing the last subframe. AR_CRCErr
529 * is the CRC of the actual data.
530 */
531 if (rxsp->status11 & AR_CRCErr)
532 rxs->rs_status |= ATH9K_RXERR_CRC;
533 else if (rxsp->status11 & AR_PHYErr) {
534 phyerr = MS(rxsp->status11, AR_PHYErrCode);
535 /*
536 * If we reach a point here where AR_PostDelimCRCErr is
537 * true it implies we're *not* on the last subframe. In
538 * in that case that we know already that the CRC of
539 * the frame was OK, and MAC would send an ACK for that
540 * subframe, even if we did get a phy error of type
541 * ATH9K_PHYERR_OFDM_RESTART. This is only applicable
542 * to frame that are prior to the last subframe.
543 * The AR_PostDelimCRCErr is the CRC for the MPDU
544 * delimiter, which contains the 4 reserved bits,
545 * the MPDU length (12 bits), and follows the MPDU
546 * delimiter for an A-MPDU subframe (0x4E = 'N' ASCII).
547 */
548 if ((phyerr == ATH9K_PHYERR_OFDM_RESTART) &&
549 (rxsp->status11 & AR_PostDelimCRCErr)) {
550 rxs->rs_phyerr = 0;
551 } else {
552 rxs->rs_status |= ATH9K_RXERR_PHY;
553 rxs->rs_phyerr = phyerr;
554 }
555
556 } else if (rxsp->status11 & AR_DecryptCRCErr)
557 rxs->rs_status |= ATH9K_RXERR_DECRYPT;
558 else if (rxsp->status11 & AR_MichaelErr)
559 rxs->rs_status |= ATH9K_RXERR_MIC;
560 }
561
562 if (rxsp->status11 & AR_KeyMiss)
563 rxs->rs_status |= ATH9K_RXERR_KEYMISS;
564
565 return 0;
566 }
567 EXPORT_SYMBOL(ath9k_hw_process_rxdesc_edma);
568
569 void ath9k_hw_reset_txstatus_ring(struct ath_hw *ah)
570 {
571 ah->ts_tail = 0;
572
573 memset((void *) ah->ts_ring, 0,
574 ah->ts_size * sizeof(struct ar9003_txs));
575
576 ath_dbg(ath9k_hw_common(ah), XMIT,
577 "TS Start 0x%x End 0x%x Virt %p, Size %d\n",
578 ah->ts_paddr_start, ah->ts_paddr_end,
579 ah->ts_ring, ah->ts_size);
580
581 REG_WRITE(ah, AR_Q_STATUS_RING_START, ah->ts_paddr_start);
582 REG_WRITE(ah, AR_Q_STATUS_RING_END, ah->ts_paddr_end);
583 }
584
585 void ath9k_hw_setup_statusring(struct ath_hw *ah, void *ts_start,
586 u32 ts_paddr_start,
587 u16 size)
588 {
589
590 ah->ts_paddr_start = ts_paddr_start;
591 ah->ts_paddr_end = ts_paddr_start + (size * sizeof(struct ar9003_txs));
592 ah->ts_size = size;
593 ah->ts_ring = (struct ar9003_txs *) ts_start;
594
595 ath9k_hw_reset_txstatus_ring(ah);
596 }
597 EXPORT_SYMBOL(ath9k_hw_setup_statusring);