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spi-topcliff-pch: add recovery processing in case wait-event timeout
[zen-stable.git] / drivers / net / wireless / rtlwifi / rtl8192c / dm_common.c
bloba004ad75d568f3ddea0da1b7323a0d51922edb82
1 /******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30 #include <linux/export.h>
31 #include "dm_common.h"
32 #include "phy_common.h"
33 #include "../pci.h"
34 #include "../base.h"
35
36 struct dig_t dm_digtable;
37 static struct ps_t dm_pstable;
38
39 #define BT_RSSI_STATE_NORMAL_POWER BIT_OFFSET_LEN_MASK_32(0, 1)
40 #define BT_RSSI_STATE_AMDPU_OFF BIT_OFFSET_LEN_MASK_32(1, 1)
41 #define BT_RSSI_STATE_SPECIAL_LOW BIT_OFFSET_LEN_MASK_32(2, 1)
42 #define BT_RSSI_STATE_BG_EDCA_LOW BIT_OFFSET_LEN_MASK_32(3, 1)
43 #define BT_RSSI_STATE_TXPOWER_LOW BIT_OFFSET_LEN_MASK_32(4, 1)
44
45 #define RTLPRIV (struct rtl_priv *)
46 #define GET_UNDECORATED_AVERAGE_RSSI(_priv) \
47 ((RTLPRIV(_priv))->mac80211.opmode == \
48 NL80211_IFTYPE_ADHOC) ? \
49 ((RTLPRIV(_priv))->dm.entry_min_undecoratedsmoothed_pwdb) : \
50 ((RTLPRIV(_priv))->dm.undecorated_smoothed_pwdb)
51
52 static const u32 ofdmswing_table[OFDM_TABLE_SIZE] = {
53 0x7f8001fe,
54 0x788001e2,
55 0x71c001c7,
56 0x6b8001ae,
57 0x65400195,
58 0x5fc0017f,
59 0x5a400169,
60 0x55400155,
61 0x50800142,
62 0x4c000130,
63 0x47c0011f,
64 0x43c0010f,
65 0x40000100,
66 0x3c8000f2,
67 0x390000e4,
68 0x35c000d7,
69 0x32c000cb,
70 0x300000c0,
71 0x2d4000b5,
72 0x2ac000ab,
73 0x288000a2,
74 0x26000098,
75 0x24000090,
76 0x22000088,
77 0x20000080,
78 0x1e400079,
79 0x1c800072,
80 0x1b00006c,
81 0x19800066,
82 0x18000060,
83 0x16c0005b,
84 0x15800056,
85 0x14400051,
86 0x1300004c,
87 0x12000048,
88 0x11000044,
89 0x10000040,
90 };
91
92 static const u8 cckswing_table_ch1ch13[CCK_TABLE_SIZE][8] = {
93 {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04},
94 {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04},
95 {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03},
96 {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03},
97 {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03},
98 {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03},
99 {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03},
100 {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03},
101 {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02},
102 {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02},
103 {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02},
104 {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02},
105 {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02},
106 {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02},
107 {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02},
108 {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02},
109 {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01},
110 {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02},
111 {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01},
112 {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},
113 {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},
114 {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01},
115 {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01},
116 {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01},
117 {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01},
118 {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01},
119 {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01},
120 {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01},
121 {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01},
122 {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01},
123 {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01},
124 {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01},
125 {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}
126 };
127
128 static const u8 cckswing_table_ch14[CCK_TABLE_SIZE][8] = {
129 {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00},
130 {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00},
131 {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00},
132 {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00},
133 {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00},
134 {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00},
135 {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00},
136 {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00},
137 {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00},
138 {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00},
139 {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00},
140 {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00},
141 {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00},
142 {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00},
143 {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00},
144 {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00},
145 {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00},
146 {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00},
147 {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00},
148 {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},
149 {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},
150 {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00},
151 {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00},
152 {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},
153 {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},
154 {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00},
155 {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},
156 {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},
157 {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},
158 {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},
159 {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},
160 {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},
161 {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00}
162 };
163
164 static void rtl92c_dm_diginit(struct ieee80211_hw *hw)
165 {
166 dm_digtable.dig_enable_flag = true;
167 dm_digtable.dig_ext_port_stage = DIG_EXT_PORT_STAGE_MAX;
168 dm_digtable.cur_igvalue = 0x20;
169 dm_digtable.pre_igvalue = 0x0;
170 dm_digtable.cursta_connectctate = DIG_STA_DISCONNECT;
171 dm_digtable.presta_connectstate = DIG_STA_DISCONNECT;
172 dm_digtable.curmultista_connectstate = DIG_MULTISTA_DISCONNECT;
173 dm_digtable.rssi_lowthresh = DM_DIG_THRESH_LOW;
174 dm_digtable.rssi_highthresh = DM_DIG_THRESH_HIGH;
175 dm_digtable.fa_lowthresh = DM_FALSEALARM_THRESH_LOW;
176 dm_digtable.fa_highthresh = DM_FALSEALARM_THRESH_HIGH;
177 dm_digtable.rx_gain_range_max = DM_DIG_MAX;
178 dm_digtable.rx_gain_range_min = DM_DIG_MIN;
179 dm_digtable.backoff_val = DM_DIG_BACKOFF_DEFAULT;
180 dm_digtable.backoff_val_range_max = DM_DIG_BACKOFF_MAX;
181 dm_digtable.backoff_val_range_min = DM_DIG_BACKOFF_MIN;
182 dm_digtable.pre_cck_pd_state = CCK_PD_STAGE_MAX;
183 dm_digtable.cur_cck_pd_state = CCK_PD_STAGE_MAX;
184 }
185
186 static u8 rtl92c_dm_initial_gain_min_pwdb(struct ieee80211_hw *hw)
187 {
188 struct rtl_priv *rtlpriv = rtl_priv(hw);
189 long rssi_val_min = 0;
190
191 if ((dm_digtable.curmultista_connectstate == DIG_MULTISTA_CONNECT) &&
192 (dm_digtable.cursta_connectctate == DIG_STA_CONNECT)) {
193 if (rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb != 0)
194 rssi_val_min =
195 (rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb >
196 rtlpriv->dm.undecorated_smoothed_pwdb) ?
197 rtlpriv->dm.undecorated_smoothed_pwdb :
198 rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
199 else
200 rssi_val_min = rtlpriv->dm.undecorated_smoothed_pwdb;
201 } else if (dm_digtable.cursta_connectctate == DIG_STA_CONNECT ||
202 dm_digtable.cursta_connectctate == DIG_STA_BEFORE_CONNECT) {
203 rssi_val_min = rtlpriv->dm.undecorated_smoothed_pwdb;
204 } else if (dm_digtable.curmultista_connectstate ==
205 DIG_MULTISTA_CONNECT) {
206 rssi_val_min = rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
207 }
208
209 return (u8) rssi_val_min;
210 }
211
212 static void rtl92c_dm_false_alarm_counter_statistics(struct ieee80211_hw *hw)
213 {
214 u32 ret_value;
215 struct rtl_priv *rtlpriv = rtl_priv(hw);
216 struct false_alarm_statistics *falsealm_cnt = &(rtlpriv->falsealm_cnt);
217
218 ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER1, MASKDWORD);
219 falsealm_cnt->cnt_parity_fail = ((ret_value & 0xffff0000) >> 16);
220
221 ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER2, MASKDWORD);
222 falsealm_cnt->cnt_rate_illegal = (ret_value & 0xffff);
223 falsealm_cnt->cnt_crc8_fail = ((ret_value & 0xffff0000) >> 16);
224
225 ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER3, MASKDWORD);
226 falsealm_cnt->cnt_mcs_fail = (ret_value & 0xffff);
227 falsealm_cnt->cnt_ofdm_fail = falsealm_cnt->cnt_parity_fail +
228 falsealm_cnt->cnt_rate_illegal +
229 falsealm_cnt->cnt_crc8_fail + falsealm_cnt->cnt_mcs_fail;
230
231 rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, BIT(14), 1);
232 ret_value = rtl_get_bbreg(hw, RCCK0_FACOUNTERLOWER, MASKBYTE0);
233 falsealm_cnt->cnt_cck_fail = ret_value;
234
235 ret_value = rtl_get_bbreg(hw, RCCK0_FACOUNTERUPPER, MASKBYTE3);
236 falsealm_cnt->cnt_cck_fail += (ret_value & 0xff) << 8;
237 falsealm_cnt->cnt_all = (falsealm_cnt->cnt_parity_fail +
238 falsealm_cnt->cnt_rate_illegal +
239 falsealm_cnt->cnt_crc8_fail +
240 falsealm_cnt->cnt_mcs_fail +
241 falsealm_cnt->cnt_cck_fail);
242
243 rtl_set_bbreg(hw, ROFDM1_LSTF, 0x08000000, 1);
244 rtl_set_bbreg(hw, ROFDM1_LSTF, 0x08000000, 0);
245 rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, 0x0000c000, 0);
246 rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, 0x0000c000, 2);
247
248 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
249 ("cnt_parity_fail = %d, cnt_rate_illegal = %d, "
250 "cnt_crc8_fail = %d, cnt_mcs_fail = %d\n",
251 falsealm_cnt->cnt_parity_fail,
252 falsealm_cnt->cnt_rate_illegal,
253 falsealm_cnt->cnt_crc8_fail, falsealm_cnt->cnt_mcs_fail));
254
255 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
256 ("cnt_ofdm_fail = %x, cnt_cck_fail = %x, cnt_all = %x\n",
257 falsealm_cnt->cnt_ofdm_fail,
258 falsealm_cnt->cnt_cck_fail, falsealm_cnt->cnt_all));
259 }
260
261 static void rtl92c_dm_ctrl_initgain_by_fa(struct ieee80211_hw *hw)
262 {
263 struct rtl_priv *rtlpriv = rtl_priv(hw);
264 u8 value_igi = dm_digtable.cur_igvalue;
265
266 if (rtlpriv->falsealm_cnt.cnt_all < DM_DIG_FA_TH0)
267 value_igi--;
268 else if (rtlpriv->falsealm_cnt.cnt_all < DM_DIG_FA_TH1)
269 value_igi += 0;
270 else if (rtlpriv->falsealm_cnt.cnt_all < DM_DIG_FA_TH2)
271 value_igi++;
272 else if (rtlpriv->falsealm_cnt.cnt_all >= DM_DIG_FA_TH2)
273 value_igi += 2;
274 if (value_igi > DM_DIG_FA_UPPER)
275 value_igi = DM_DIG_FA_UPPER;
276 else if (value_igi < DM_DIG_FA_LOWER)
277 value_igi = DM_DIG_FA_LOWER;
278 if (rtlpriv->falsealm_cnt.cnt_all > 10000)
279 value_igi = 0x32;
280
281 dm_digtable.cur_igvalue = value_igi;
282 rtl92c_dm_write_dig(hw);
283 }
284
285 static void rtl92c_dm_ctrl_initgain_by_rssi(struct ieee80211_hw *hw)
286 {
287 struct rtl_priv *rtlpriv = rtl_priv(hw);
288
289 if (rtlpriv->falsealm_cnt.cnt_all > dm_digtable.fa_highthresh) {
290 if ((dm_digtable.backoff_val - 2) <
291 dm_digtable.backoff_val_range_min)
292 dm_digtable.backoff_val =
293 dm_digtable.backoff_val_range_min;
294 else
295 dm_digtable.backoff_val -= 2;
296 } else if (rtlpriv->falsealm_cnt.cnt_all < dm_digtable.fa_lowthresh) {
297 if ((dm_digtable.backoff_val + 2) >
298 dm_digtable.backoff_val_range_max)
299 dm_digtable.backoff_val =
300 dm_digtable.backoff_val_range_max;
301 else
302 dm_digtable.backoff_val += 2;
303 }
304
305 if ((dm_digtable.rssi_val_min + 10 - dm_digtable.backoff_val) >
306 dm_digtable.rx_gain_range_max)
307 dm_digtable.cur_igvalue = dm_digtable.rx_gain_range_max;
308 else if ((dm_digtable.rssi_val_min + 10 -
309 dm_digtable.backoff_val) < dm_digtable.rx_gain_range_min)
310 dm_digtable.cur_igvalue = dm_digtable.rx_gain_range_min;
311 else
312 dm_digtable.cur_igvalue = dm_digtable.rssi_val_min + 10 -
313 dm_digtable.backoff_val;
314
315 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
316 ("rssi_val_min = %x backoff_val %x\n",
317 dm_digtable.rssi_val_min, dm_digtable.backoff_val));
318
319 rtl92c_dm_write_dig(hw);
320 }
321
322 static void rtl92c_dm_initial_gain_multi_sta(struct ieee80211_hw *hw)
323 {
324 static u8 initialized; /* initialized to false */
325 struct rtl_priv *rtlpriv = rtl_priv(hw);
326 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
327 long rssi_strength = rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
328 bool multi_sta = false;
329
330 if (mac->opmode == NL80211_IFTYPE_ADHOC)
331 multi_sta = true;
332
333 if ((multi_sta == false) || (dm_digtable.cursta_connectctate !=
334 DIG_STA_DISCONNECT)) {
335 initialized = false;
336 dm_digtable.dig_ext_port_stage = DIG_EXT_PORT_STAGE_MAX;
337 return;
338 } else if (initialized == false) {
339 initialized = true;
340 dm_digtable.dig_ext_port_stage = DIG_EXT_PORT_STAGE_0;
341 dm_digtable.cur_igvalue = 0x20;
342 rtl92c_dm_write_dig(hw);
343 }
344
345 if (dm_digtable.curmultista_connectstate == DIG_MULTISTA_CONNECT) {
346 if ((rssi_strength < dm_digtable.rssi_lowthresh) &&
347 (dm_digtable.dig_ext_port_stage != DIG_EXT_PORT_STAGE_1)) {
348
349 if (dm_digtable.dig_ext_port_stage ==
350 DIG_EXT_PORT_STAGE_2) {
351 dm_digtable.cur_igvalue = 0x20;
352 rtl92c_dm_write_dig(hw);
353 }
354
355 dm_digtable.dig_ext_port_stage = DIG_EXT_PORT_STAGE_1;
356 } else if (rssi_strength > dm_digtable.rssi_highthresh) {
357 dm_digtable.dig_ext_port_stage = DIG_EXT_PORT_STAGE_2;
358 rtl92c_dm_ctrl_initgain_by_fa(hw);
359 }
360 } else if (dm_digtable.dig_ext_port_stage != DIG_EXT_PORT_STAGE_0) {
361 dm_digtable.dig_ext_port_stage = DIG_EXT_PORT_STAGE_0;
362 dm_digtable.cur_igvalue = 0x20;
363 rtl92c_dm_write_dig(hw);
364 }
365
366 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
367 ("curmultista_connectstate = "
368 "%x dig_ext_port_stage %x\n",
369 dm_digtable.curmultista_connectstate,
370 dm_digtable.dig_ext_port_stage));
371 }
372
373 static void rtl92c_dm_initial_gain_sta(struct ieee80211_hw *hw)
374 {
375 struct rtl_priv *rtlpriv = rtl_priv(hw);
376
377 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
378 ("presta_connectstate = %x,"
379 " cursta_connectctate = %x\n",
380 dm_digtable.presta_connectstate,
381 dm_digtable.cursta_connectctate));
382
383 if (dm_digtable.presta_connectstate == dm_digtable.cursta_connectctate
384 || dm_digtable.cursta_connectctate == DIG_STA_BEFORE_CONNECT
385 || dm_digtable.cursta_connectctate == DIG_STA_CONNECT) {
386
387 if (dm_digtable.cursta_connectctate != DIG_STA_DISCONNECT) {
388 dm_digtable.rssi_val_min =
389 rtl92c_dm_initial_gain_min_pwdb(hw);
390 rtl92c_dm_ctrl_initgain_by_rssi(hw);
391 }
392 } else {
393 dm_digtable.rssi_val_min = 0;
394 dm_digtable.dig_ext_port_stage = DIG_EXT_PORT_STAGE_MAX;
395 dm_digtable.backoff_val = DM_DIG_BACKOFF_DEFAULT;
396 dm_digtable.cur_igvalue = 0x20;
397 dm_digtable.pre_igvalue = 0;
398 rtl92c_dm_write_dig(hw);
399 }
400 }
401
402 static void rtl92c_dm_cck_packet_detection_thresh(struct ieee80211_hw *hw)
403 {
404 struct rtl_priv *rtlpriv = rtl_priv(hw);
405 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
406
407 if (dm_digtable.cursta_connectctate == DIG_STA_CONNECT) {
408 dm_digtable.rssi_val_min = rtl92c_dm_initial_gain_min_pwdb(hw);
409
410 if (dm_digtable.pre_cck_pd_state == CCK_PD_STAGE_LowRssi) {
411 if (dm_digtable.rssi_val_min <= 25)
412 dm_digtable.cur_cck_pd_state =
413 CCK_PD_STAGE_LowRssi;
414 else
415 dm_digtable.cur_cck_pd_state =
416 CCK_PD_STAGE_HighRssi;
417 } else {
418 if (dm_digtable.rssi_val_min <= 20)
419 dm_digtable.cur_cck_pd_state =
420 CCK_PD_STAGE_LowRssi;
421 else
422 dm_digtable.cur_cck_pd_state =
423 CCK_PD_STAGE_HighRssi;
424 }
425 } else {
426 dm_digtable.cur_cck_pd_state = CCK_PD_STAGE_MAX;
427 }
428
429 if (dm_digtable.pre_cck_pd_state != dm_digtable.cur_cck_pd_state) {
430 if (dm_digtable.cur_cck_pd_state == CCK_PD_STAGE_LowRssi) {
431 if (rtlpriv->falsealm_cnt.cnt_cck_fail > 800)
432 dm_digtable.cur_cck_fa_state =
433 CCK_FA_STAGE_High;
434 else
435 dm_digtable.cur_cck_fa_state = CCK_FA_STAGE_Low;
436
437 if (dm_digtable.pre_cck_fa_state !=
438 dm_digtable.cur_cck_fa_state) {
439 if (dm_digtable.cur_cck_fa_state ==
440 CCK_FA_STAGE_Low)
441 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2,
442 0x83);
443 else
444 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2,
445 0xcd);
446
447 dm_digtable.pre_cck_fa_state =
448 dm_digtable.cur_cck_fa_state;
449 }
450
451 rtl_set_bbreg(hw, RCCK0_SYSTEM, MASKBYTE1, 0x40);
452
453 if (IS_92C_SERIAL(rtlhal->version))
454 rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT,
455 MASKBYTE2, 0xd7);
456 } else {
457 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0xcd);
458 rtl_set_bbreg(hw, RCCK0_SYSTEM, MASKBYTE1, 0x47);
459
460 if (IS_92C_SERIAL(rtlhal->version))
461 rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT,
462 MASKBYTE2, 0xd3);
463 }
464 dm_digtable.pre_cck_pd_state = dm_digtable.cur_cck_pd_state;
465 }
466
467 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
468 ("CCKPDStage=%x\n", dm_digtable.cur_cck_pd_state));
469
470 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
471 ("is92C=%x\n", IS_92C_SERIAL(rtlhal->version)));
472 }
473
474 static void rtl92c_dm_ctrl_initgain_by_twoport(struct ieee80211_hw *hw)
475 {
476 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
477
478 if (mac->act_scanning)
479 return;
480
481 if (mac->link_state >= MAC80211_LINKED)
482 dm_digtable.cursta_connectctate = DIG_STA_CONNECT;
483 else
484 dm_digtable.cursta_connectctate = DIG_STA_DISCONNECT;
485
486 rtl92c_dm_initial_gain_sta(hw);
487 rtl92c_dm_initial_gain_multi_sta(hw);
488 rtl92c_dm_cck_packet_detection_thresh(hw);
489
490 dm_digtable.presta_connectstate = dm_digtable.cursta_connectctate;
491
492 }
493
494 static void rtl92c_dm_dig(struct ieee80211_hw *hw)
495 {
496 struct rtl_priv *rtlpriv = rtl_priv(hw);
497
498 if (rtlpriv->dm.dm_initialgain_enable == false)
499 return;
500 if (dm_digtable.dig_enable_flag == false)
501 return;
502
503 rtl92c_dm_ctrl_initgain_by_twoport(hw);
504
505 }
506
507 static void rtl92c_dm_init_dynamic_txpower(struct ieee80211_hw *hw)
508 {
509 struct rtl_priv *rtlpriv = rtl_priv(hw);
510
511 rtlpriv->dm.dynamic_txpower_enable = false;
512
513 rtlpriv->dm.last_dtp_lvl = TXHIGHPWRLEVEL_NORMAL;
514 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
515 }
516
517 void rtl92c_dm_write_dig(struct ieee80211_hw *hw)
518 {
519 struct rtl_priv *rtlpriv = rtl_priv(hw);
520
521 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD,
522 ("cur_igvalue = 0x%x, "
523 "pre_igvalue = 0x%x, backoff_val = %d\n",
524 dm_digtable.cur_igvalue, dm_digtable.pre_igvalue,
525 dm_digtable.backoff_val));
526
527 dm_digtable.cur_igvalue += 2;
528 if (dm_digtable.cur_igvalue > 0x3f)
529 dm_digtable.cur_igvalue = 0x3f;
530
531 if (dm_digtable.pre_igvalue != dm_digtable.cur_igvalue) {
532 rtl_set_bbreg(hw, ROFDM0_XAAGCCORE1, 0x7f,
533 dm_digtable.cur_igvalue);
534 rtl_set_bbreg(hw, ROFDM0_XBAGCCORE1, 0x7f,
535 dm_digtable.cur_igvalue);
536
537 dm_digtable.pre_igvalue = dm_digtable.cur_igvalue;
538 }
539 }
540 EXPORT_SYMBOL(rtl92c_dm_write_dig);
541
542 static void rtl92c_dm_pwdb_monitor(struct ieee80211_hw *hw)
543 {
544 struct rtl_priv *rtlpriv = rtl_priv(hw);
545 long tmpentry_max_pwdb = 0, tmpentry_min_pwdb = 0xff;
546
547 u8 h2c_parameter[3] = { 0 };
548
549 return;
550
551 if (tmpentry_max_pwdb != 0) {
552 rtlpriv->dm.entry_max_undecoratedsmoothed_pwdb =
553 tmpentry_max_pwdb;
554 } else {
555 rtlpriv->dm.entry_max_undecoratedsmoothed_pwdb = 0;
556 }
557
558 if (tmpentry_min_pwdb != 0xff) {
559 rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb =
560 tmpentry_min_pwdb;
561 } else {
562 rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb = 0;
563 }
564
565 h2c_parameter[2] = (u8) (rtlpriv->dm.undecorated_smoothed_pwdb & 0xFF);
566 h2c_parameter[0] = 0;
567
568 rtl92c_fill_h2c_cmd(hw, H2C_RSSI_REPORT, 3, h2c_parameter);
569 }
570
571 void rtl92c_dm_init_edca_turbo(struct ieee80211_hw *hw)
572 {
573 struct rtl_priv *rtlpriv = rtl_priv(hw);
574 rtlpriv->dm.current_turbo_edca = false;
575 rtlpriv->dm.is_any_nonbepkts = false;
576 rtlpriv->dm.is_cur_rdlstate = false;
577 }
578 EXPORT_SYMBOL(rtl92c_dm_init_edca_turbo);
579
580 static void rtl92c_dm_check_edca_turbo(struct ieee80211_hw *hw)
581 {
582 struct rtl_priv *rtlpriv = rtl_priv(hw);
583 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
584 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
585
586 static u64 last_txok_cnt;
587 static u64 last_rxok_cnt;
588 static u32 last_bt_edca_ul;
589 static u32 last_bt_edca_dl;
590 u64 cur_txok_cnt = 0;
591 u64 cur_rxok_cnt = 0;
592 u32 edca_be_ul = 0x5ea42b;
593 u32 edca_be_dl = 0x5ea42b;
594 bool bt_change_edca = false;
595
596 if ((last_bt_edca_ul != rtlpcipriv->bt_coexist.bt_edca_ul) ||
597 (last_bt_edca_dl != rtlpcipriv->bt_coexist.bt_edca_dl)) {
598 rtlpriv->dm.current_turbo_edca = false;
599 last_bt_edca_ul = rtlpcipriv->bt_coexist.bt_edca_ul;
600 last_bt_edca_dl = rtlpcipriv->bt_coexist.bt_edca_dl;
601 }
602
603 if (rtlpcipriv->bt_coexist.bt_edca_ul != 0) {
604 edca_be_ul = rtlpcipriv->bt_coexist.bt_edca_ul;
605 bt_change_edca = true;
606 }
607
608 if (rtlpcipriv->bt_coexist.bt_edca_dl != 0) {
609 edca_be_ul = rtlpcipriv->bt_coexist.bt_edca_dl;
610 bt_change_edca = true;
611 }
612
613 if (mac->link_state != MAC80211_LINKED) {
614 rtlpriv->dm.current_turbo_edca = false;
615 return;
616 }
617
618 if ((!mac->ht_enable) && (!rtlpcipriv->bt_coexist.bt_coexistence)) {
619 if (!(edca_be_ul & 0xffff0000))
620 edca_be_ul |= 0x005e0000;
621
622 if (!(edca_be_dl & 0xffff0000))
623 edca_be_dl |= 0x005e0000;
624 }
625
626 if ((bt_change_edca) || ((!rtlpriv->dm.is_any_nonbepkts) &&
627 (!rtlpriv->dm.disable_framebursting))) {
628
629 cur_txok_cnt = rtlpriv->stats.txbytesunicast - last_txok_cnt;
630 cur_rxok_cnt = rtlpriv->stats.rxbytesunicast - last_rxok_cnt;
631
632 if (cur_rxok_cnt > 4 * cur_txok_cnt) {
633 if (!rtlpriv->dm.is_cur_rdlstate ||
634 !rtlpriv->dm.current_turbo_edca) {
635 rtl_write_dword(rtlpriv,
636 REG_EDCA_BE_PARAM,
637 edca_be_dl);
638 rtlpriv->dm.is_cur_rdlstate = true;
639 }
640 } else {
641 if (rtlpriv->dm.is_cur_rdlstate ||
642 !rtlpriv->dm.current_turbo_edca) {
643 rtl_write_dword(rtlpriv,
644 REG_EDCA_BE_PARAM,
645 edca_be_ul);
646 rtlpriv->dm.is_cur_rdlstate = false;
647 }
648 }
649 rtlpriv->dm.current_turbo_edca = true;
650 } else {
651 if (rtlpriv->dm.current_turbo_edca) {
652 u8 tmp = AC0_BE;
653 rtlpriv->cfg->ops->set_hw_reg(hw,
654 HW_VAR_AC_PARAM,
655 (u8 *) (&tmp));
656 rtlpriv->dm.current_turbo_edca = false;
657 }
658 }
659
660 rtlpriv->dm.is_any_nonbepkts = false;
661 last_txok_cnt = rtlpriv->stats.txbytesunicast;
662 last_rxok_cnt = rtlpriv->stats.rxbytesunicast;
663 }
664
665 static void rtl92c_dm_txpower_tracking_callback_thermalmeter(struct ieee80211_hw
666 *hw)
667 {
668 struct rtl_priv *rtlpriv = rtl_priv(hw);
669 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
670 struct rtl_phy *rtlphy = &(rtlpriv->phy);
671 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
672 u8 thermalvalue, delta, delta_lck, delta_iqk;
673 long ele_a, ele_d, temp_cck, val_x, value32;
674 long val_y, ele_c = 0;
675 u8 ofdm_index[2], cck_index = 0, ofdm_index_old[2], cck_index_old = 0;
676 int i;
677 bool is2t = IS_92C_SERIAL(rtlhal->version);
678 s8 txpwr_level[2] = {0, 0};
679 u8 ofdm_min_index = 6, rf;
680
681 rtlpriv->dm.txpower_trackinginit = true;
682 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
683 ("rtl92c_dm_txpower_tracking_callback_thermalmeter\n"));
684
685 thermalvalue = (u8) rtl_get_rfreg(hw, RF90_PATH_A, RF_T_METER, 0x1f);
686
687 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
688 ("Readback Thermal Meter = 0x%x pre thermal meter 0x%x "
689 "eeprom_thermalmeter 0x%x\n",
690 thermalvalue, rtlpriv->dm.thermalvalue,
691 rtlefuse->eeprom_thermalmeter));
692
693 rtl92c_phy_ap_calibrate(hw, (thermalvalue -
694 rtlefuse->eeprom_thermalmeter));
695 if (is2t)
696 rf = 2;
697 else
698 rf = 1;
699
700 if (thermalvalue) {
701 ele_d = rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
702 MASKDWORD) & MASKOFDM_D;
703
704 for (i = 0; i < OFDM_TABLE_LENGTH; i++) {
705 if (ele_d == (ofdmswing_table[i] & MASKOFDM_D)) {
706 ofdm_index_old[0] = (u8) i;
707
708 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
709 ("Initial pathA ele_d reg0x%x = 0x%lx, "
710 "ofdm_index=0x%x\n",
711 ROFDM0_XATXIQIMBALANCE,
712 ele_d, ofdm_index_old[0]));
713 break;
714 }
715 }
716
717 if (is2t) {
718 ele_d = rtl_get_bbreg(hw, ROFDM0_XBTXIQIMBALANCE,
719 MASKDWORD) & MASKOFDM_D;
720
721 for (i = 0; i < OFDM_TABLE_LENGTH; i++) {
722 if (ele_d == (ofdmswing_table[i] &
723 MASKOFDM_D)) {
724
725 RT_TRACE(rtlpriv, COMP_POWER_TRACKING,
726 DBG_LOUD,
727 ("Initial pathB ele_d reg0x%x = "
728 "0x%lx, ofdm_index=0x%x\n",
729 ROFDM0_XBTXIQIMBALANCE, ele_d,
730 ofdm_index_old[1]));
731 break;
732 }
733 }
734 }
735
736 temp_cck =
737 rtl_get_bbreg(hw, RCCK0_TXFILTER2, MASKDWORD) & MASKCCK;
738
739 for (i = 0; i < CCK_TABLE_LENGTH; i++) {
740 if (rtlpriv->dm.cck_inch14) {
741 if (memcmp((void *)&temp_cck,
742 (void *)&cckswing_table_ch14[i][2],
743 4) == 0) {
744 cck_index_old = (u8) i;
745
746 RT_TRACE(rtlpriv, COMP_POWER_TRACKING,
747 DBG_LOUD,
748 ("Initial reg0x%x = 0x%lx, "
749 "cck_index=0x%x, ch 14 %d\n",
750 RCCK0_TXFILTER2, temp_cck,
751 cck_index_old,
752 rtlpriv->dm.cck_inch14));
753 break;
754 }
755 } else {
756 if (memcmp((void *)&temp_cck,
757 (void *)
758 &cckswing_table_ch1ch13[i][2],
759 4) == 0) {
760 cck_index_old = (u8) i;
761
762 RT_TRACE(rtlpriv, COMP_POWER_TRACKING,
763 DBG_LOUD,
764 ("Initial reg0x%x = 0x%lx, "
765 "cck_index=0x%x, ch14 %d\n",
766 RCCK0_TXFILTER2, temp_cck,
767 cck_index_old,
768 rtlpriv->dm.cck_inch14));
769 break;
770 }
771 }
772 }
773
774 if (!rtlpriv->dm.thermalvalue) {
775 rtlpriv->dm.thermalvalue =
776 rtlefuse->eeprom_thermalmeter;
777 rtlpriv->dm.thermalvalue_lck = thermalvalue;
778 rtlpriv->dm.thermalvalue_iqk = thermalvalue;
779 for (i = 0; i < rf; i++)
780 rtlpriv->dm.ofdm_index[i] = ofdm_index_old[i];
781 rtlpriv->dm.cck_index = cck_index_old;
782 }
783
784 delta = (thermalvalue > rtlpriv->dm.thermalvalue) ?
785 (thermalvalue - rtlpriv->dm.thermalvalue) :
786 (rtlpriv->dm.thermalvalue - thermalvalue);
787
788 delta_lck = (thermalvalue > rtlpriv->dm.thermalvalue_lck) ?
789 (thermalvalue - rtlpriv->dm.thermalvalue_lck) :
790 (rtlpriv->dm.thermalvalue_lck - thermalvalue);
791
792 delta_iqk = (thermalvalue > rtlpriv->dm.thermalvalue_iqk) ?
793 (thermalvalue - rtlpriv->dm.thermalvalue_iqk) :
794 (rtlpriv->dm.thermalvalue_iqk - thermalvalue);
795
796 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
797 ("Readback Thermal Meter = 0x%x pre thermal meter 0x%x "
798 "eeprom_thermalmeter 0x%x delta 0x%x "
799 "delta_lck 0x%x delta_iqk 0x%x\n",
800 thermalvalue, rtlpriv->dm.thermalvalue,
801 rtlefuse->eeprom_thermalmeter, delta, delta_lck,
802 delta_iqk));
803
804 if (delta_lck > 1) {
805 rtlpriv->dm.thermalvalue_lck = thermalvalue;
806 rtl92c_phy_lc_calibrate(hw);
807 }
808
809 if (delta > 0 && rtlpriv->dm.txpower_track_control) {
810 if (thermalvalue > rtlpriv->dm.thermalvalue) {
811 for (i = 0; i < rf; i++)
812 rtlpriv->dm.ofdm_index[i] -= delta;
813 rtlpriv->dm.cck_index -= delta;
814 } else {
815 for (i = 0; i < rf; i++)
816 rtlpriv->dm.ofdm_index[i] += delta;
817 rtlpriv->dm.cck_index += delta;
818 }
819
820 if (is2t) {
821 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
822 ("temp OFDM_A_index=0x%x, "
823 "OFDM_B_index=0x%x,"
824 "cck_index=0x%x\n",
825 rtlpriv->dm.ofdm_index[0],
826 rtlpriv->dm.ofdm_index[1],
827 rtlpriv->dm.cck_index));
828 } else {
829 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
830 ("temp OFDM_A_index=0x%x,"
831 "cck_index=0x%x\n",
832 rtlpriv->dm.ofdm_index[0],
833 rtlpriv->dm.cck_index));
834 }
835
836 if (thermalvalue > rtlefuse->eeprom_thermalmeter) {
837 for (i = 0; i < rf; i++)
838 ofdm_index[i] =
839 rtlpriv->dm.ofdm_index[i]
840 + 1;
841 cck_index = rtlpriv->dm.cck_index + 1;
842 } else {
843 for (i = 0; i < rf; i++)
844 ofdm_index[i] =
845 rtlpriv->dm.ofdm_index[i];
846 cck_index = rtlpriv->dm.cck_index;
847 }
848
849 for (i = 0; i < rf; i++) {
850 if (txpwr_level[i] >= 0 &&
851 txpwr_level[i] <= 26) {
852 if (thermalvalue >
853 rtlefuse->eeprom_thermalmeter) {
854 if (delta < 5)
855 ofdm_index[i] -= 1;
856
857 else
858 ofdm_index[i] -= 2;
859 } else if (delta > 5 && thermalvalue <
860 rtlefuse->
861 eeprom_thermalmeter) {
862 ofdm_index[i] += 1;
863 }
864 } else if (txpwr_level[i] >= 27 &&
865 txpwr_level[i] <= 32
866 && thermalvalue >
867 rtlefuse->eeprom_thermalmeter) {
868 if (delta < 5)
869 ofdm_index[i] -= 1;
870
871 else
872 ofdm_index[i] -= 2;
873 } else if (txpwr_level[i] >= 32 &&
874 txpwr_level[i] <= 38 &&
875 thermalvalue >
876 rtlefuse->eeprom_thermalmeter
877 && delta > 5) {
878 ofdm_index[i] -= 1;
879 }
880 }
881
882 if (txpwr_level[i] >= 0 && txpwr_level[i] <= 26) {
883 if (thermalvalue >
884 rtlefuse->eeprom_thermalmeter) {
885 if (delta < 5)
886 cck_index -= 1;
887
888 else
889 cck_index -= 2;
890 } else if (delta > 5 && thermalvalue <
891 rtlefuse->eeprom_thermalmeter) {
892 cck_index += 1;
893 }
894 } else if (txpwr_level[i] >= 27 &&
895 txpwr_level[i] <= 32 &&
896 thermalvalue >
897 rtlefuse->eeprom_thermalmeter) {
898 if (delta < 5)
899 cck_index -= 1;
900
901 else
902 cck_index -= 2;
903 } else if (txpwr_level[i] >= 32 &&
904 txpwr_level[i] <= 38 &&
905 thermalvalue > rtlefuse->eeprom_thermalmeter
906 && delta > 5) {
907 cck_index -= 1;
908 }
909
910 for (i = 0; i < rf; i++) {
911 if (ofdm_index[i] > OFDM_TABLE_SIZE - 1)
912 ofdm_index[i] = OFDM_TABLE_SIZE - 1;
913
914 else if (ofdm_index[i] < ofdm_min_index)
915 ofdm_index[i] = ofdm_min_index;
916 }
917
918 if (cck_index > CCK_TABLE_SIZE - 1)
919 cck_index = CCK_TABLE_SIZE - 1;
920 else if (cck_index < 0)
921 cck_index = 0;
922
923 if (is2t) {
924 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
925 ("new OFDM_A_index=0x%x, "
926 "OFDM_B_index=0x%x,"
927 "cck_index=0x%x\n",
928 ofdm_index[0], ofdm_index[1],
929 cck_index));
930 } else {
931 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
932 ("new OFDM_A_index=0x%x,"
933 "cck_index=0x%x\n",
934 ofdm_index[0], cck_index));
935 }
936 }
937
938 if (rtlpriv->dm.txpower_track_control && delta != 0) {
939 ele_d =
940 (ofdmswing_table[ofdm_index[0]] & 0xFFC00000) >> 22;
941 val_x = rtlphy->reg_e94;
942 val_y = rtlphy->reg_e9c;
943
944 if (val_x != 0) {
945 if ((val_x & 0x00000200) != 0)
946 val_x = val_x | 0xFFFFFC00;
947 ele_a = ((val_x * ele_d) >> 8) & 0x000003FF;
948
949 if ((val_y & 0x00000200) != 0)
950 val_y = val_y | 0xFFFFFC00;
951 ele_c = ((val_y * ele_d) >> 8) & 0x000003FF;
952
953 value32 = (ele_d << 22) |
954 ((ele_c & 0x3F) << 16) | ele_a;
955
956 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
957 MASKDWORD, value32);
958
959 value32 = (ele_c & 0x000003C0) >> 6;
960 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, MASKH4BITS,
961 value32);
962
963 value32 = ((val_x * ele_d) >> 7) & 0x01;
964 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
965 BIT(31), value32);
966
967 value32 = ((val_y * ele_d) >> 7) & 0x01;
968 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
969 BIT(29), value32);
970 } else {
971 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
972 MASKDWORD,
973 ofdmswing_table[ofdm_index[0]]);
974
975 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, MASKH4BITS,
976 0x00);
977 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
978 BIT(31) | BIT(29), 0x00);
979 }
980
981 if (!rtlpriv->dm.cck_inch14) {
982 rtl_write_byte(rtlpriv, 0xa22,
983 cckswing_table_ch1ch13[cck_index]
984 [0]);
985 rtl_write_byte(rtlpriv, 0xa23,
986 cckswing_table_ch1ch13[cck_index]
987 [1]);
988 rtl_write_byte(rtlpriv, 0xa24,
989 cckswing_table_ch1ch13[cck_index]
990 [2]);
991 rtl_write_byte(rtlpriv, 0xa25,
992 cckswing_table_ch1ch13[cck_index]
993 [3]);
994 rtl_write_byte(rtlpriv, 0xa26,
995 cckswing_table_ch1ch13[cck_index]
996 [4]);
997 rtl_write_byte(rtlpriv, 0xa27,
998 cckswing_table_ch1ch13[cck_index]
999 [5]);
1000 rtl_write_byte(rtlpriv, 0xa28,
1001 cckswing_table_ch1ch13[cck_index]
1002 [6]);
1003 rtl_write_byte(rtlpriv, 0xa29,
1004 cckswing_table_ch1ch13[cck_index]
1005 [7]);
1006 } else {
1007 rtl_write_byte(rtlpriv, 0xa22,
1008 cckswing_table_ch14[cck_index]
1009 [0]);
1010 rtl_write_byte(rtlpriv, 0xa23,
1011 cckswing_table_ch14[cck_index]
1012 [1]);
1013 rtl_write_byte(rtlpriv, 0xa24,
1014 cckswing_table_ch14[cck_index]
1015 [2]);
1016 rtl_write_byte(rtlpriv, 0xa25,
1017 cckswing_table_ch14[cck_index]
1018 [3]);
1019 rtl_write_byte(rtlpriv, 0xa26,
1020 cckswing_table_ch14[cck_index]
1021 [4]);
1022 rtl_write_byte(rtlpriv, 0xa27,
1023 cckswing_table_ch14[cck_index]
1024 [5]);
1025 rtl_write_byte(rtlpriv, 0xa28,
1026 cckswing_table_ch14[cck_index]
1027 [6]);
1028 rtl_write_byte(rtlpriv, 0xa29,
1029 cckswing_table_ch14[cck_index]
1030 [7]);
1031 }
1032
1033 if (is2t) {
1034 ele_d = (ofdmswing_table[ofdm_index[1]] &
1035 0xFFC00000) >> 22;
1036
1037 val_x = rtlphy->reg_eb4;
1038 val_y = rtlphy->reg_ebc;
1039
1040 if (val_x != 0) {
1041 if ((val_x & 0x00000200) != 0)
1042 val_x = val_x | 0xFFFFFC00;
1043 ele_a = ((val_x * ele_d) >> 8) &
1044 0x000003FF;
1045
1046 if ((val_y & 0x00000200) != 0)
1047 val_y = val_y | 0xFFFFFC00;
1048 ele_c = ((val_y * ele_d) >> 8) &
1049 0x00003FF;
1050
1051 value32 = (ele_d << 22) |
1052 ((ele_c & 0x3F) << 16) | ele_a;
1053 rtl_set_bbreg(hw,
1054 ROFDM0_XBTXIQIMBALANCE,
1055 MASKDWORD, value32);
1056
1057 value32 = (ele_c & 0x000003C0) >> 6;
1058 rtl_set_bbreg(hw, ROFDM0_XDTXAFE,
1059 MASKH4BITS, value32);
1060
1061 value32 = ((val_x * ele_d) >> 7) & 0x01;
1062 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
1063 BIT(27), value32);
1064
1065 value32 = ((val_y * ele_d) >> 7) & 0x01;
1066 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
1067 BIT(25), value32);
1068 } else {
1069 rtl_set_bbreg(hw,
1070 ROFDM0_XBTXIQIMBALANCE,
1071 MASKDWORD,
1072 ofdmswing_table[ofdm_index
1073 [1]]);
1074 rtl_set_bbreg(hw, ROFDM0_XDTXAFE,
1075 MASKH4BITS, 0x00);
1076 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
1077 BIT(27) | BIT(25), 0x00);
1078 }
1079
1080 }
1081 }
1082
1083 if (delta_iqk > 3) {
1084 rtlpriv->dm.thermalvalue_iqk = thermalvalue;
1085 rtl92c_phy_iq_calibrate(hw, false);
1086 }
1087
1088 if (rtlpriv->dm.txpower_track_control)
1089 rtlpriv->dm.thermalvalue = thermalvalue;
1090 }
1091
1092 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, ("<===\n"));
1093
1094 }
1095
1096 static void rtl92c_dm_initialize_txpower_tracking_thermalmeter(
1097 struct ieee80211_hw *hw)
1098 {
1099 struct rtl_priv *rtlpriv = rtl_priv(hw);
1100
1101 rtlpriv->dm.txpower_tracking = true;
1102 rtlpriv->dm.txpower_trackinginit = false;
1103
1104 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1105 ("pMgntInfo->txpower_tracking = %d\n",
1106 rtlpriv->dm.txpower_tracking));
1107 }
1108
1109 static void rtl92c_dm_initialize_txpower_tracking(struct ieee80211_hw *hw)
1110 {
1111 rtl92c_dm_initialize_txpower_tracking_thermalmeter(hw);
1112 }
1113
1114 static void rtl92c_dm_txpower_tracking_directcall(struct ieee80211_hw *hw)
1115 {
1116 rtl92c_dm_txpower_tracking_callback_thermalmeter(hw);
1117 }
1118
1119 static void rtl92c_dm_check_txpower_tracking_thermal_meter(
1120 struct ieee80211_hw *hw)
1121 {
1122 struct rtl_priv *rtlpriv = rtl_priv(hw);
1123 static u8 tm_trigger;
1124
1125 if (!rtlpriv->dm.txpower_tracking)
1126 return;
1127
1128 if (!tm_trigger) {
1129 rtl_set_rfreg(hw, RF90_PATH_A, RF_T_METER, RFREG_OFFSET_MASK,
1130 0x60);
1131 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1132 ("Trigger 92S Thermal Meter!!\n"));
1133 tm_trigger = 1;
1134 return;
1135 } else {
1136 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1137 ("Schedule TxPowerTracking direct call!!\n"));
1138 rtl92c_dm_txpower_tracking_directcall(hw);
1139 tm_trigger = 0;
1140 }
1141 }
1142
1143 void rtl92c_dm_check_txpower_tracking(struct ieee80211_hw *hw)
1144 {
1145 rtl92c_dm_check_txpower_tracking_thermal_meter(hw);
1146 }
1147 EXPORT_SYMBOL(rtl92c_dm_check_txpower_tracking);
1148
1149 void rtl92c_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw)
1150 {
1151 struct rtl_priv *rtlpriv = rtl_priv(hw);
1152 struct rate_adaptive *p_ra = &(rtlpriv->ra);
1153
1154 p_ra->ratr_state = DM_RATR_STA_INIT;
1155 p_ra->pre_ratr_state = DM_RATR_STA_INIT;
1156
1157 if (rtlpriv->dm.dm_type == DM_TYPE_BYDRIVER)
1158 rtlpriv->dm.useramask = true;
1159 else
1160 rtlpriv->dm.useramask = false;
1161
1162 }
1163 EXPORT_SYMBOL(rtl92c_dm_init_rate_adaptive_mask);
1164
1165 static void rtl92c_dm_refresh_rate_adaptive_mask(struct ieee80211_hw *hw)
1166 {
1167 struct rtl_priv *rtlpriv = rtl_priv(hw);
1168 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1169 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1170 struct rate_adaptive *p_ra = &(rtlpriv->ra);
1171 u32 low_rssithresh_for_ra, high_rssithresh_for_ra;
1172 struct ieee80211_sta *sta = NULL;
1173
1174 if (is_hal_stop(rtlhal)) {
1175 RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
1176 ("<---- driver is going to unload\n"));
1177 return;
1178 }
1179
1180 if (!rtlpriv->dm.useramask) {
1181 RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
1182 ("<---- driver does not control rate adaptive mask\n"));
1183 return;
1184 }
1185
1186 if (mac->link_state == MAC80211_LINKED &&
1187 mac->opmode == NL80211_IFTYPE_STATION) {
1188 switch (p_ra->pre_ratr_state) {
1189 case DM_RATR_STA_HIGH:
1190 high_rssithresh_for_ra = 50;
1191 low_rssithresh_for_ra = 20;
1192 break;
1193 case DM_RATR_STA_MIDDLE:
1194 high_rssithresh_for_ra = 55;
1195 low_rssithresh_for_ra = 20;
1196 break;
1197 case DM_RATR_STA_LOW:
1198 high_rssithresh_for_ra = 50;
1199 low_rssithresh_for_ra = 25;
1200 break;
1201 default:
1202 high_rssithresh_for_ra = 50;
1203 low_rssithresh_for_ra = 20;
1204 break;
1205 }
1206
1207 if (rtlpriv->dm.undecorated_smoothed_pwdb >
1208 (long)high_rssithresh_for_ra)
1209 p_ra->ratr_state = DM_RATR_STA_HIGH;
1210 else if (rtlpriv->dm.undecorated_smoothed_pwdb >
1211 (long)low_rssithresh_for_ra)
1212 p_ra->ratr_state = DM_RATR_STA_MIDDLE;
1213 else
1214 p_ra->ratr_state = DM_RATR_STA_LOW;
1215
1216 if (p_ra->pre_ratr_state != p_ra->ratr_state) {
1217 RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
1218 ("RSSI = %ld\n",
1219 rtlpriv->dm.undecorated_smoothed_pwdb));
1220 RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
1221 ("RSSI_LEVEL = %d\n", p_ra->ratr_state));
1222 RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
1223 ("PreState = %d, CurState = %d\n",
1224 p_ra->pre_ratr_state, p_ra->ratr_state));
1225
1226 /* Only the PCI card uses sta in the update rate table
1227 * callback routine */
1228 if (rtlhal->interface == INTF_PCI) {
1229 rcu_read_lock();
1230 sta = ieee80211_find_sta(mac->vif, mac->bssid);
1231 }
1232 rtlpriv->cfg->ops->update_rate_tbl(hw, sta,
1233 p_ra->ratr_state);
1234
1235 p_ra->pre_ratr_state = p_ra->ratr_state;
1236 if (rtlhal->interface == INTF_PCI)
1237 rcu_read_unlock();
1238 }
1239 }
1240 }
1241
1242 static void rtl92c_dm_init_dynamic_bb_powersaving(struct ieee80211_hw *hw)
1243 {
1244 dm_pstable.pre_ccastate = CCA_MAX;
1245 dm_pstable.cur_ccasate = CCA_MAX;
1246 dm_pstable.pre_rfstate = RF_MAX;
1247 dm_pstable.cur_rfstate = RF_MAX;
1248 dm_pstable.rssi_val_min = 0;
1249 }
1250
1251 void rtl92c_dm_rf_saving(struct ieee80211_hw *hw, u8 bforce_in_normal)
1252 {
1253 static u8 initialize;
1254 static u32 reg_874, reg_c70, reg_85c, reg_a74;
1255
1256 if (initialize == 0) {
1257 reg_874 = (rtl_get_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
1258 MASKDWORD) & 0x1CC000) >> 14;
1259
1260 reg_c70 = (rtl_get_bbreg(hw, ROFDM0_AGCPARAMETER1,
1261 MASKDWORD) & BIT(3)) >> 3;
1262
1263 reg_85c = (rtl_get_bbreg(hw, RFPGA0_XCD_SWITCHCONTROL,
1264 MASKDWORD) & 0xFF000000) >> 24;
1265
1266 reg_a74 = (rtl_get_bbreg(hw, 0xa74, MASKDWORD) & 0xF000) >> 12;
1267
1268 initialize = 1;
1269 }
1270
1271 if (!bforce_in_normal) {
1272 if (dm_pstable.rssi_val_min != 0) {
1273 if (dm_pstable.pre_rfstate == RF_NORMAL) {
1274 if (dm_pstable.rssi_val_min >= 30)
1275 dm_pstable.cur_rfstate = RF_SAVE;
1276 else
1277 dm_pstable.cur_rfstate = RF_NORMAL;
1278 } else {
1279 if (dm_pstable.rssi_val_min <= 25)
1280 dm_pstable.cur_rfstate = RF_NORMAL;
1281 else
1282 dm_pstable.cur_rfstate = RF_SAVE;
1283 }
1284 } else {
1285 dm_pstable.cur_rfstate = RF_MAX;
1286 }
1287 } else {
1288 dm_pstable.cur_rfstate = RF_NORMAL;
1289 }
1290
1291 if (dm_pstable.pre_rfstate != dm_pstable.cur_rfstate) {
1292 if (dm_pstable.cur_rfstate == RF_SAVE) {
1293 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
1294 0x1C0000, 0x2);
1295 rtl_set_bbreg(hw, ROFDM0_AGCPARAMETER1, BIT(3), 0);
1296 rtl_set_bbreg(hw, RFPGA0_XCD_SWITCHCONTROL,
1297 0xFF000000, 0x63);
1298 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
1299 0xC000, 0x2);
1300 rtl_set_bbreg(hw, 0xa74, 0xF000, 0x3);
1301 rtl_set_bbreg(hw, 0x818, BIT(28), 0x0);
1302 rtl_set_bbreg(hw, 0x818, BIT(28), 0x1);
1303 } else {
1304 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
1305 0x1CC000, reg_874);
1306 rtl_set_bbreg(hw, ROFDM0_AGCPARAMETER1, BIT(3),
1307 reg_c70);
1308 rtl_set_bbreg(hw, RFPGA0_XCD_SWITCHCONTROL, 0xFF000000,
1309 reg_85c);
1310 rtl_set_bbreg(hw, 0xa74, 0xF000, reg_a74);
1311 rtl_set_bbreg(hw, 0x818, BIT(28), 0x0);
1312 }
1313
1314 dm_pstable.pre_rfstate = dm_pstable.cur_rfstate;
1315 }
1316 }
1317 EXPORT_SYMBOL(rtl92c_dm_rf_saving);
1318
1319 static void rtl92c_dm_dynamic_bb_powersaving(struct ieee80211_hw *hw)
1320 {
1321 struct rtl_priv *rtlpriv = rtl_priv(hw);
1322 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1323 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1324
1325 if (((mac->link_state == MAC80211_NOLINK)) &&
1326 (rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb == 0)) {
1327 dm_pstable.rssi_val_min = 0;
1328 RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD,
1329 ("Not connected to any\n"));
1330 }
1331
1332 if (mac->link_state == MAC80211_LINKED) {
1333 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
1334 dm_pstable.rssi_val_min =
1335 rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
1336 RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD,
1337 ("AP Client PWDB = 0x%lx\n",
1338 dm_pstable.rssi_val_min));
1339 } else {
1340 dm_pstable.rssi_val_min =
1341 rtlpriv->dm.undecorated_smoothed_pwdb;
1342 RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD,
1343 ("STA Default Port PWDB = 0x%lx\n",
1344 dm_pstable.rssi_val_min));
1345 }
1346 } else {
1347 dm_pstable.rssi_val_min =
1348 rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
1349
1350 RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD,
1351 ("AP Ext Port PWDB = 0x%lx\n",
1352 dm_pstable.rssi_val_min));
1353 }
1354
1355 if (IS_92C_SERIAL(rtlhal->version))
1356 ;/* rtl92c_dm_1r_cca(hw); */
1357 else
1358 rtl92c_dm_rf_saving(hw, false);
1359 }
1360
1361 void rtl92c_dm_init(struct ieee80211_hw *hw)
1362 {
1363 struct rtl_priv *rtlpriv = rtl_priv(hw);
1364
1365 rtlpriv->dm.dm_type = DM_TYPE_BYDRIVER;
1366 rtl92c_dm_diginit(hw);
1367 rtl92c_dm_init_dynamic_txpower(hw);
1368 rtl92c_dm_init_edca_turbo(hw);
1369 rtl92c_dm_init_rate_adaptive_mask(hw);
1370 rtl92c_dm_initialize_txpower_tracking(hw);
1371 rtl92c_dm_init_dynamic_bb_powersaving(hw);
1372 }
1373 EXPORT_SYMBOL(rtl92c_dm_init);
1374
1375 void rtl92c_dm_dynamic_txpower(struct ieee80211_hw *hw)
1376 {
1377 struct rtl_priv *rtlpriv = rtl_priv(hw);
1378 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1379 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1380 long undecorated_smoothed_pwdb;
1381
1382 if (!rtlpriv->dm.dynamic_txpower_enable)
1383 return;
1384
1385 if (rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) {
1386 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
1387 return;
1388 }
1389
1390 if ((mac->link_state < MAC80211_LINKED) &&
1391 (rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb == 0)) {
1392 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
1393 ("Not connected to any\n"));
1394
1395 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
1396
1397 rtlpriv->dm.last_dtp_lvl = TXHIGHPWRLEVEL_NORMAL;
1398 return;
1399 }
1400
1401 if (mac->link_state >= MAC80211_LINKED) {
1402 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
1403 undecorated_smoothed_pwdb =
1404 rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
1405 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
1406 ("AP Client PWDB = 0x%lx\n",
1407 undecorated_smoothed_pwdb));
1408 } else {
1409 undecorated_smoothed_pwdb =
1410 rtlpriv->dm.undecorated_smoothed_pwdb;
1411 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
1412 ("STA Default Port PWDB = 0x%lx\n",
1413 undecorated_smoothed_pwdb));
1414 }
1415 } else {
1416 undecorated_smoothed_pwdb =
1417 rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
1418
1419 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
1420 ("AP Ext Port PWDB = 0x%lx\n",
1421 undecorated_smoothed_pwdb));
1422 }
1423
1424 if (undecorated_smoothed_pwdb >= TX_POWER_NEAR_FIELD_THRESH_LVL2) {
1425 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_LEVEL1;
1426 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
1427 ("TXHIGHPWRLEVEL_LEVEL1 (TxPwr=0x0)\n"));
1428 } else if ((undecorated_smoothed_pwdb <
1429 (TX_POWER_NEAR_FIELD_THRESH_LVL2 - 3)) &&
1430 (undecorated_smoothed_pwdb >=
1431 TX_POWER_NEAR_FIELD_THRESH_LVL1)) {
1432
1433 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_LEVEL1;
1434 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
1435 ("TXHIGHPWRLEVEL_LEVEL1 (TxPwr=0x10)\n"));
1436 } else if (undecorated_smoothed_pwdb <
1437 (TX_POWER_NEAR_FIELD_THRESH_LVL1 - 5)) {
1438 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
1439 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
1440 ("TXHIGHPWRLEVEL_NORMAL\n"));
1441 }
1442
1443 if ((rtlpriv->dm.dynamic_txhighpower_lvl != rtlpriv->dm.last_dtp_lvl)) {
1444 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
1445 ("PHY_SetTxPowerLevel8192S() Channel = %d\n",
1446 rtlphy->current_channel));
1447 rtl92c_phy_set_txpower_level(hw, rtlphy->current_channel);
1448 }
1449
1450 rtlpriv->dm.last_dtp_lvl = rtlpriv->dm.dynamic_txhighpower_lvl;
1451 }
1452
1453 void rtl92c_dm_watchdog(struct ieee80211_hw *hw)
1454 {
1455 struct rtl_priv *rtlpriv = rtl_priv(hw);
1456 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1457 bool fw_current_inpsmode = false;
1458 bool fw_ps_awake = true;
1459
1460 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
1461 (u8 *) (&fw_current_inpsmode));
1462 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FWLPS_RF_ON,
1463 (u8 *) (&fw_ps_awake));
1464
1465 if ((ppsc->rfpwr_state == ERFON) && ((!fw_current_inpsmode) &&
1466 fw_ps_awake)
1467 && (!ppsc->rfchange_inprogress)) {
1468 rtl92c_dm_pwdb_monitor(hw);
1469 rtl92c_dm_dig(hw);
1470 rtl92c_dm_false_alarm_counter_statistics(hw);
1471 rtl92c_dm_dynamic_bb_powersaving(hw);
1472 rtl92c_dm_dynamic_txpower(hw);
1473 rtl92c_dm_check_txpower_tracking(hw);
1474 rtl92c_dm_refresh_rate_adaptive_mask(hw);
1475 rtl92c_dm_bt_coexist(hw);
1476 rtl92c_dm_check_edca_turbo(hw);
1477 }
1478 }
1479 EXPORT_SYMBOL(rtl92c_dm_watchdog);
1480
1481 u8 rtl92c_bt_rssi_state_change(struct ieee80211_hw *hw)
1482 {
1483 struct rtl_priv *rtlpriv = rtl_priv(hw);
1484 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
1485 long undecorated_smoothed_pwdb;
1486 u8 curr_bt_rssi_state = 0x00;
1487
1488 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1489 undecorated_smoothed_pwdb =
1490 GET_UNDECORATED_AVERAGE_RSSI(rtlpriv);
1491 } else {
1492 if (rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb == 0)
1493 undecorated_smoothed_pwdb = 100;
1494 else
1495 undecorated_smoothed_pwdb =
1496 rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
1497 }
1498
1499 /* Check RSSI to determine HighPower/NormalPower state for
1500 * BT coexistence. */
1501 if (undecorated_smoothed_pwdb >= 67)
1502 curr_bt_rssi_state &= (~BT_RSSI_STATE_NORMAL_POWER);
1503 else if (undecorated_smoothed_pwdb < 62)
1504 curr_bt_rssi_state |= BT_RSSI_STATE_NORMAL_POWER;
1505
1506 /* Check RSSI to determine AMPDU setting for BT coexistence. */
1507 if (undecorated_smoothed_pwdb >= 40)
1508 curr_bt_rssi_state &= (~BT_RSSI_STATE_AMDPU_OFF);
1509 else if (undecorated_smoothed_pwdb <= 32)
1510 curr_bt_rssi_state |= BT_RSSI_STATE_AMDPU_OFF;
1511
1512 /* Marked RSSI state. It will be used to determine BT coexistence
1513 * setting later. */
1514 if (undecorated_smoothed_pwdb < 35)
1515 curr_bt_rssi_state |= BT_RSSI_STATE_SPECIAL_LOW;
1516 else
1517 curr_bt_rssi_state &= (~BT_RSSI_STATE_SPECIAL_LOW);
1518
1519 /* Set Tx Power according to BT status. */
1520 if (undecorated_smoothed_pwdb >= 30)
1521 curr_bt_rssi_state |= BT_RSSI_STATE_TXPOWER_LOW;
1522 else if (undecorated_smoothed_pwdb < 25)
1523 curr_bt_rssi_state &= (~BT_RSSI_STATE_TXPOWER_LOW);
1524
1525 /* Check BT state related to BT_Idle in B/G mode. */
1526 if (undecorated_smoothed_pwdb < 15)
1527 curr_bt_rssi_state |= BT_RSSI_STATE_BG_EDCA_LOW;
1528 else
1529 curr_bt_rssi_state &= (~BT_RSSI_STATE_BG_EDCA_LOW);
1530
1531 if (curr_bt_rssi_state != rtlpcipriv->bt_coexist.bt_rssi_state) {
1532 rtlpcipriv->bt_coexist.bt_rssi_state = curr_bt_rssi_state;
1533 return true;
1534 } else {
1535 return false;
1536 }
1537 }
1538 EXPORT_SYMBOL(rtl92c_bt_rssi_state_change);
1539
1540 static bool rtl92c_bt_state_change(struct ieee80211_hw *hw)
1541 {
1542 struct rtl_priv *rtlpriv = rtl_priv(hw);
1543 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
1544
1545 u32 polling, ratio_tx, ratio_pri;
1546 u32 bt_tx, bt_pri;
1547 u8 bt_state;
1548 u8 cur_service_type;
1549
1550 if (rtlpriv->mac80211.link_state < MAC80211_LINKED)
1551 return false;
1552
1553 bt_state = rtl_read_byte(rtlpriv, 0x4fd);
1554 bt_tx = rtl_read_dword(rtlpriv, 0x488);
1555 bt_tx = bt_tx & 0x00ffffff;
1556 bt_pri = rtl_read_dword(rtlpriv, 0x48c);
1557 bt_pri = bt_pri & 0x00ffffff;
1558 polling = rtl_read_dword(rtlpriv, 0x490);
1559
1560 if (bt_tx == 0xffffffff && bt_pri == 0xffffffff &&
1561 polling == 0xffffffff && bt_state == 0xff)
1562 return false;
1563
1564 bt_state &= BIT_OFFSET_LEN_MASK_32(0, 1);
1565 if (bt_state != rtlpcipriv->bt_coexist.bt_cur_state) {
1566 rtlpcipriv->bt_coexist.bt_cur_state = bt_state;
1567
1568 if (rtlpcipriv->bt_coexist.reg_bt_sco == 3) {
1569 rtlpcipriv->bt_coexist.bt_service = BT_IDLE;
1570
1571 bt_state = bt_state |
1572 ((rtlpcipriv->bt_coexist.bt_ant_isolation == 1) ?
1573 0 : BIT_OFFSET_LEN_MASK_32(1, 1)) |
1574 BIT_OFFSET_LEN_MASK_32(2, 1);
1575 rtl_write_byte(rtlpriv, 0x4fd, bt_state);
1576 }
1577 return true;
1578 }
1579
1580 ratio_tx = bt_tx * 1000 / polling;
1581 ratio_pri = bt_pri * 1000 / polling;
1582 rtlpcipriv->bt_coexist.ratio_tx = ratio_tx;
1583 rtlpcipriv->bt_coexist.ratio_pri = ratio_pri;
1584
1585 if (bt_state && rtlpcipriv->bt_coexist.reg_bt_sco == 3) {
1586
1587 if ((ratio_tx < 30) && (ratio_pri < 30))
1588 cur_service_type = BT_IDLE;
1589 else if ((ratio_pri > 110) && (ratio_pri < 250))
1590 cur_service_type = BT_SCO;
1591 else if ((ratio_tx >= 200) && (ratio_pri >= 200))
1592 cur_service_type = BT_BUSY;
1593 else if ((ratio_tx >= 350) && (ratio_tx < 500))
1594 cur_service_type = BT_OTHERBUSY;
1595 else if (ratio_tx >= 500)
1596 cur_service_type = BT_PAN;
1597 else
1598 cur_service_type = BT_OTHER_ACTION;
1599
1600 if (cur_service_type != rtlpcipriv->bt_coexist.bt_service) {
1601 rtlpcipriv->bt_coexist.bt_service = cur_service_type;
1602 bt_state = bt_state |
1603 ((rtlpcipriv->bt_coexist.bt_ant_isolation == 1) ?
1604 0 : BIT_OFFSET_LEN_MASK_32(1, 1)) |
1605 ((rtlpcipriv->bt_coexist.bt_service != BT_IDLE) ?
1606 0 : BIT_OFFSET_LEN_MASK_32(2, 1));
1607
1608 /* Add interrupt migration when bt is not ini
1609 * idle state (no traffic). */
1610 if (rtlpcipriv->bt_coexist.bt_service != BT_IDLE) {
1611 rtl_write_word(rtlpriv, 0x504, 0x0ccc);
1612 rtl_write_byte(rtlpriv, 0x506, 0x54);
1613 rtl_write_byte(rtlpriv, 0x507, 0x54);
1614 } else {
1615 rtl_write_byte(rtlpriv, 0x506, 0x00);
1616 rtl_write_byte(rtlpriv, 0x507, 0x00);
1617 }
1618
1619 rtl_write_byte(rtlpriv, 0x4fd, bt_state);
1620 return true;
1621 }
1622 }
1623
1624 return false;
1625
1626 }
1627
1628 static bool rtl92c_bt_wifi_connect_change(struct ieee80211_hw *hw)
1629 {
1630 struct rtl_priv *rtlpriv = rtl_priv(hw);
1631 static bool media_connect;
1632
1633 if (rtlpriv->mac80211.link_state < MAC80211_LINKED) {
1634 media_connect = false;
1635 } else {
1636 if (!media_connect) {
1637 media_connect = true;
1638 return true;
1639 }
1640 media_connect = true;
1641 }
1642
1643 return false;
1644 }
1645
1646 static void rtl92c_bt_set_normal(struct ieee80211_hw *hw)
1647 {
1648 struct rtl_priv *rtlpriv = rtl_priv(hw);
1649 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
1650
1651
1652 if (rtlpcipriv->bt_coexist.bt_service == BT_OTHERBUSY) {
1653 rtlpcipriv->bt_coexist.bt_edca_ul = 0x5ea72b;
1654 rtlpcipriv->bt_coexist.bt_edca_dl = 0x5ea72b;
1655 } else if (rtlpcipriv->bt_coexist.bt_service == BT_BUSY) {
1656 rtlpcipriv->bt_coexist.bt_edca_ul = 0x5eb82f;
1657 rtlpcipriv->bt_coexist.bt_edca_dl = 0x5eb82f;
1658 } else if (rtlpcipriv->bt_coexist.bt_service == BT_SCO) {
1659 if (rtlpcipriv->bt_coexist.ratio_tx > 160) {
1660 rtlpcipriv->bt_coexist.bt_edca_ul = 0x5ea72f;
1661 rtlpcipriv->bt_coexist.bt_edca_dl = 0x5ea72f;
1662 } else {
1663 rtlpcipriv->bt_coexist.bt_edca_ul = 0x5ea32b;
1664 rtlpcipriv->bt_coexist.bt_edca_dl = 0x5ea42b;
1665 }
1666 } else {
1667 rtlpcipriv->bt_coexist.bt_edca_ul = 0;
1668 rtlpcipriv->bt_coexist.bt_edca_dl = 0;
1669 }
1670
1671 if ((rtlpcipriv->bt_coexist.bt_service != BT_IDLE) &&
1672 (rtlpriv->mac80211.mode == WIRELESS_MODE_G ||
1673 (rtlpriv->mac80211.mode == (WIRELESS_MODE_G | WIRELESS_MODE_B))) &&
1674 (rtlpcipriv->bt_coexist.bt_rssi_state &
1675 BT_RSSI_STATE_BG_EDCA_LOW)) {
1676 rtlpcipriv->bt_coexist.bt_edca_ul = 0x5eb82b;
1677 rtlpcipriv->bt_coexist.bt_edca_dl = 0x5eb82b;
1678 }
1679 }
1680
1681 static void rtl92c_bt_ant_isolation(struct ieee80211_hw *hw)
1682 {
1683 struct rtl_priv *rtlpriv = rtl_priv(hw);
1684 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
1685
1686
1687 /* Only enable HW BT coexist when BT in "Busy" state. */
1688 if (rtlpriv->mac80211.vendor == PEER_CISCO &&
1689 rtlpcipriv->bt_coexist.bt_service == BT_OTHER_ACTION) {
1690 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0xa0);
1691 } else {
1692 if ((rtlpcipriv->bt_coexist.bt_service == BT_BUSY) &&
1693 (rtlpcipriv->bt_coexist.bt_rssi_state &
1694 BT_RSSI_STATE_NORMAL_POWER)) {
1695 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0xa0);
1696 } else if ((rtlpcipriv->bt_coexist.bt_service ==
1697 BT_OTHER_ACTION) && (rtlpriv->mac80211.mode <
1698 WIRELESS_MODE_N_24G) &&
1699 (rtlpcipriv->bt_coexist.bt_rssi_state &
1700 BT_RSSI_STATE_SPECIAL_LOW)) {
1701 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0xa0);
1702 } else if (rtlpcipriv->bt_coexist.bt_service == BT_PAN) {
1703 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0x00);
1704 } else {
1705 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0x00);
1706 }
1707 }
1708
1709 if (rtlpcipriv->bt_coexist.bt_service == BT_PAN)
1710 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x10100);
1711 else
1712 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x0);
1713
1714 if (rtlpcipriv->bt_coexist.bt_rssi_state &
1715 BT_RSSI_STATE_NORMAL_POWER) {
1716 rtl92c_bt_set_normal(hw);
1717 } else {
1718 rtlpcipriv->bt_coexist.bt_edca_ul = 0;
1719 rtlpcipriv->bt_coexist.bt_edca_dl = 0;
1720 }
1721
1722 if (rtlpcipriv->bt_coexist.bt_service != BT_IDLE) {
1723 rtlpriv->cfg->ops->set_rfreg(hw,
1724 RF90_PATH_A,
1725 0x1e,
1726 0xf0, 0xf);
1727 } else {
1728 rtlpriv->cfg->ops->set_rfreg(hw,
1729 RF90_PATH_A, 0x1e, 0xf0,
1730 rtlpcipriv->bt_coexist.bt_rfreg_origin_1e);
1731 }
1732
1733 if (!rtlpriv->dm.dynamic_txpower_enable) {
1734 if (rtlpcipriv->bt_coexist.bt_service != BT_IDLE) {
1735 if (rtlpcipriv->bt_coexist.bt_rssi_state &
1736 BT_RSSI_STATE_TXPOWER_LOW) {
1737 rtlpriv->dm.dynamic_txhighpower_lvl =
1738 TXHIGHPWRLEVEL_BT2;
1739 } else {
1740 rtlpriv->dm.dynamic_txhighpower_lvl =
1741 TXHIGHPWRLEVEL_BT1;
1742 }
1743 } else {
1744 rtlpriv->dm.dynamic_txhighpower_lvl =
1745 TXHIGHPWRLEVEL_NORMAL;
1746 }
1747 rtl92c_phy_set_txpower_level(hw,
1748 rtlpriv->phy.current_channel);
1749 }
1750 }
1751
1752 static void rtl92c_check_bt_change(struct ieee80211_hw *hw)
1753 {
1754 struct rtl_priv *rtlpriv = rtl_priv(hw);
1755 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
1756
1757 if (rtlpcipriv->bt_coexist.bt_cur_state) {
1758 if (rtlpcipriv->bt_coexist.bt_ant_isolation)
1759 rtl92c_bt_ant_isolation(hw);
1760 } else {
1761 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0x00);
1762 rtlpriv->cfg->ops->set_rfreg(hw, RF90_PATH_A, 0x1e, 0xf0,
1763 rtlpcipriv->bt_coexist.bt_rfreg_origin_1e);
1764
1765 rtlpcipriv->bt_coexist.bt_edca_ul = 0;
1766 rtlpcipriv->bt_coexist.bt_edca_dl = 0;
1767 }
1768 }
1769
1770 void rtl92c_dm_bt_coexist(struct ieee80211_hw *hw)
1771 {
1772 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
1773
1774 bool wifi_connect_change;
1775 bool bt_state_change;
1776 bool rssi_state_change;
1777
1778 if ((rtlpcipriv->bt_coexist.bt_coexistence) &&
1779 (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4)) {
1780
1781 wifi_connect_change = rtl92c_bt_wifi_connect_change(hw);
1782 bt_state_change = rtl92c_bt_state_change(hw);
1783 rssi_state_change = rtl92c_bt_rssi_state_change(hw);
1784
1785 if (wifi_connect_change || bt_state_change || rssi_state_change)
1786 rtl92c_check_bt_change(hw);
1787 }
1788 }
1789 EXPORT_SYMBOL(rtl92c_dm_bt_coexist);