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spi-topcliff-pch: add recovery processing in case wait-event timeout
[zen-stable.git] / drivers / net / wireless / rtlwifi / rtl8192de / phy.c
blob2cf4c5f25cf0c709a04f8bb8039dc8932ac58317
1 /******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30 #include "../wifi.h"
31 #include "../pci.h"
32 #include "../ps.h"
33 #include "reg.h"
34 #include "def.h"
35 #include "phy.h"
36 #include "rf.h"
37 #include "dm.h"
38 #include "table.h"
39 #include "sw.h"
40 #include "hw.h"
41
42 #define MAX_RF_IMR_INDEX 12
43 #define MAX_RF_IMR_INDEX_NORMAL 13
44 #define RF_REG_NUM_FOR_C_CUT_5G 6
45 #define RF_REG_NUM_FOR_C_CUT_5G_INTERNALPA 7
46 #define RF_REG_NUM_FOR_C_CUT_2G 5
47 #define RF_CHNL_NUM_5G 19
48 #define RF_CHNL_NUM_5G_40M 17
49 #define TARGET_CHNL_NUM_5G 221
50 #define TARGET_CHNL_NUM_2G 14
51 #define CV_CURVE_CNT 64
52
53 static u32 rf_reg_for_5g_swchnl_normal[MAX_RF_IMR_INDEX_NORMAL] = {
54 0, 0x2f, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x0
55 };
56
57 static u8 rf_reg_for_c_cut_5g[RF_REG_NUM_FOR_C_CUT_5G] = {
58 RF_SYN_G1, RF_SYN_G2, RF_SYN_G3, RF_SYN_G4, RF_SYN_G5, RF_SYN_G6
59 };
60
61 static u8 rf_reg_for_c_cut_2g[RF_REG_NUM_FOR_C_CUT_2G] = {
62 RF_SYN_G1, RF_SYN_G2, RF_SYN_G3, RF_SYN_G7, RF_SYN_G8
63 };
64
65 static u8 rf_for_c_cut_5g_internal_pa[RF_REG_NUM_FOR_C_CUT_5G_INTERNALPA] = {
66 0x0B, 0x48, 0x49, 0x4B, 0x03, 0x04, 0x0E
67 };
68
69 static u32 rf_reg_mask_for_c_cut_2g[RF_REG_NUM_FOR_C_CUT_2G] = {
70 BIT(19) | BIT(18) | BIT(17) | BIT(14) | BIT(1),
71 BIT(10) | BIT(9),
72 BIT(18) | BIT(17) | BIT(16) | BIT(1),
73 BIT(2) | BIT(1),
74 BIT(15) | BIT(14) | BIT(13) | BIT(12) | BIT(11)
75 };
76
77 static u8 rf_chnl_5g[RF_CHNL_NUM_5G] = {
78 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108,
79 112, 116, 120, 124, 128, 132, 136, 140
80 };
81
82 static u8 rf_chnl_5g_40m[RF_CHNL_NUM_5G_40M] = {
83 38, 42, 46, 50, 54, 58, 62, 102, 106, 110, 114,
84 118, 122, 126, 130, 134, 138
85 };
86 static u32 rf_reg_pram_c_5g[5][RF_REG_NUM_FOR_C_CUT_5G] = {
87 {0xE43BE, 0xFC638, 0x77C0A, 0xDE471, 0xd7110, 0x8EB04},
88 {0xE43BE, 0xFC078, 0xF7C1A, 0xE0C71, 0xD7550, 0xAEB04},
89 {0xE43BF, 0xFF038, 0xF7C0A, 0xDE471, 0xE5550, 0xAEB04},
90 {0xE43BF, 0xFF079, 0xF7C1A, 0xDE471, 0xE5550, 0xAEB04},
91 {0xE43BF, 0xFF038, 0xF7C1A, 0xDE471, 0xd7550, 0xAEB04}
92 };
93
94 static u32 rf_reg_param_for_c_cut_2g[3][RF_REG_NUM_FOR_C_CUT_2G] = {
95 {0x643BC, 0xFC038, 0x77C1A, 0x41289, 0x01840},
96 {0x643BC, 0xFC038, 0x07C1A, 0x41289, 0x01840},
97 {0x243BC, 0xFC438, 0x07C1A, 0x4128B, 0x0FC41}
98 };
99
100 static u32 rf_syn_g4_for_c_cut_2g = 0xD1C31 & 0x7FF;
101
102 static u32 rf_pram_c_5g_int_pa[3][RF_REG_NUM_FOR_C_CUT_5G_INTERNALPA] = {
103 {0x01a00, 0x40443, 0x00eb5, 0x89bec, 0x94a12, 0x94a12, 0x94a12},
104 {0x01800, 0xc0443, 0x00730, 0x896ee, 0x94a52, 0x94a52, 0x94a52},
105 {0x01800, 0xc0443, 0x00730, 0x896ee, 0x94a12, 0x94a12, 0x94a12}
106 };
107
108 /* [mode][patha+b][reg] */
109 static u32 rf_imr_param_normal[1][3][MAX_RF_IMR_INDEX_NORMAL] = {
110 {
111 /* channel 1-14. */
112 {
113 0x70000, 0x00ff0, 0x4400f, 0x00ff0, 0x0, 0x0, 0x0,
114 0x0, 0x0, 0x64888, 0xe266c, 0x00090, 0x22fff
115 },
116 /* path 36-64 */
117 {
118 0x70000, 0x22880, 0x4470f, 0x55880, 0x00070, 0x88000,
119 0x0, 0x88080, 0x70000, 0x64a82, 0xe466c, 0x00090,
120 0x32c9a
121 },
122 /* 100 -165 */
123 {
124 0x70000, 0x44880, 0x4477f, 0x77880, 0x00070, 0x88000,
125 0x0, 0x880b0, 0x0, 0x64b82, 0xe466c, 0x00090, 0x32c9a
126 }
127 }
128 };
129
130 static u32 curveindex_5g[TARGET_CHNL_NUM_5G] = {0};
131
132 static u32 curveindex_2g[TARGET_CHNL_NUM_2G] = {0};
133
134 static u32 targetchnl_5g[TARGET_CHNL_NUM_5G] = {
135 25141, 25116, 25091, 25066, 25041,
136 25016, 24991, 24966, 24941, 24917,
137 24892, 24867, 24843, 24818, 24794,
138 24770, 24765, 24721, 24697, 24672,
139 24648, 24624, 24600, 24576, 24552,
140 24528, 24504, 24480, 24457, 24433,
141 24409, 24385, 24362, 24338, 24315,
142 24291, 24268, 24245, 24221, 24198,
143 24175, 24151, 24128, 24105, 24082,
144 24059, 24036, 24013, 23990, 23967,
145 23945, 23922, 23899, 23876, 23854,
146 23831, 23809, 23786, 23764, 23741,
147 23719, 23697, 23674, 23652, 23630,
148 23608, 23586, 23564, 23541, 23519,
149 23498, 23476, 23454, 23432, 23410,
150 23388, 23367, 23345, 23323, 23302,
151 23280, 23259, 23237, 23216, 23194,
152 23173, 23152, 23130, 23109, 23088,
153 23067, 23046, 23025, 23003, 22982,
154 22962, 22941, 22920, 22899, 22878,
155 22857, 22837, 22816, 22795, 22775,
156 22754, 22733, 22713, 22692, 22672,
157 22652, 22631, 22611, 22591, 22570,
158 22550, 22530, 22510, 22490, 22469,
159 22449, 22429, 22409, 22390, 22370,
160 22350, 22336, 22310, 22290, 22271,
161 22251, 22231, 22212, 22192, 22173,
162 22153, 22134, 22114, 22095, 22075,
163 22056, 22037, 22017, 21998, 21979,
164 21960, 21941, 21921, 21902, 21883,
165 21864, 21845, 21826, 21807, 21789,
166 21770, 21751, 21732, 21713, 21695,
167 21676, 21657, 21639, 21620, 21602,
168 21583, 21565, 21546, 21528, 21509,
169 21491, 21473, 21454, 21436, 21418,
170 21400, 21381, 21363, 21345, 21327,
171 21309, 21291, 21273, 21255, 21237,
172 21219, 21201, 21183, 21166, 21148,
173 21130, 21112, 21095, 21077, 21059,
174 21042, 21024, 21007, 20989, 20972,
175 25679, 25653, 25627, 25601, 25575,
176 25549, 25523, 25497, 25471, 25446,
177 25420, 25394, 25369, 25343, 25318,
178 25292, 25267, 25242, 25216, 25191,
179 25166
180 };
181
182 /* channel 1~14 */
183 static u32 targetchnl_2g[TARGET_CHNL_NUM_2G] = {
184 26084, 26030, 25976, 25923, 25869, 25816, 25764,
185 25711, 25658, 25606, 25554, 25502, 25451, 25328
186 };
187
188 static u32 _rtl92d_phy_calculate_bit_shift(u32 bitmask)
189 {
190 u32 i;
191
192 for (i = 0; i <= 31; i++) {
193 if (((bitmask >> i) & 0x1) == 1)
194 break;
195 }
196
197 return i;
198 }
199
200 u32 rtl92d_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask)
201 {
202 struct rtl_priv *rtlpriv = rtl_priv(hw);
203 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
204 u32 returnvalue, originalvalue, bitshift;
205 u8 dbi_direct;
206
207 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("regaddr(%#x), "
208 "bitmask(%#x)\n", regaddr, bitmask));
209 if (rtlhal->during_mac1init_radioa || rtlhal->during_mac0init_radiob) {
210 /* mac1 use phy0 read radio_b. */
211 /* mac0 use phy1 read radio_b. */
212 if (rtlhal->during_mac1init_radioa)
213 dbi_direct = BIT(3);
214 else if (rtlhal->during_mac0init_radiob)
215 dbi_direct = BIT(3) | BIT(2);
216 originalvalue = rtl92de_read_dword_dbi(hw, (u16)regaddr,
217 dbi_direct);
218 } else {
219 originalvalue = rtl_read_dword(rtlpriv, regaddr);
220 }
221 bitshift = _rtl92d_phy_calculate_bit_shift(bitmask);
222 returnvalue = (originalvalue & bitmask) >> bitshift;
223 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("BBR MASK=0x%x "
224 "Addr[0x%x]=0x%x\n", bitmask, regaddr, originalvalue));
225 return returnvalue;
226 }
227
228 void rtl92d_phy_set_bb_reg(struct ieee80211_hw *hw,
229 u32 regaddr, u32 bitmask, u32 data)
230 {
231 struct rtl_priv *rtlpriv = rtl_priv(hw);
232 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
233 u8 dbi_direct = 0;
234 u32 originalvalue, bitshift;
235
236 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("regaddr(%#x), bitmask(%#x),"
237 " data(%#x)\n", regaddr, bitmask, data));
238 if (rtlhal->during_mac1init_radioa)
239 dbi_direct = BIT(3);
240 else if (rtlhal->during_mac0init_radiob)
241 /* mac0 use phy1 write radio_b. */
242 dbi_direct = BIT(3) | BIT(2);
243 if (bitmask != BMASKDWORD) {
244 if (rtlhal->during_mac1init_radioa ||
245 rtlhal->during_mac0init_radiob)
246 originalvalue = rtl92de_read_dword_dbi(hw,
247 (u16) regaddr,
248 dbi_direct);
249 else
250 originalvalue = rtl_read_dword(rtlpriv, regaddr);
251 bitshift = _rtl92d_phy_calculate_bit_shift(bitmask);
252 data = ((originalvalue & (~bitmask)) | (data << bitshift));
253 }
254 if (rtlhal->during_mac1init_radioa || rtlhal->during_mac0init_radiob)
255 rtl92de_write_dword_dbi(hw, (u16) regaddr, data, dbi_direct);
256 else
257 rtl_write_dword(rtlpriv, regaddr, data);
258 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("regaddr(%#x), bitmask(%#x),"
259 " data(%#x)\n", regaddr, bitmask, data));
260 }
261
262 static u32 _rtl92d_phy_rf_serial_read(struct ieee80211_hw *hw,
263 enum radio_path rfpath, u32 offset)
264 {
265
266 struct rtl_priv *rtlpriv = rtl_priv(hw);
267 struct rtl_phy *rtlphy = &(rtlpriv->phy);
268 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
269 u32 newoffset;
270 u32 tmplong, tmplong2;
271 u8 rfpi_enable = 0;
272 u32 retvalue;
273
274 newoffset = offset;
275 tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, BMASKDWORD);
276 if (rfpath == RF90_PATH_A)
277 tmplong2 = tmplong;
278 else
279 tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, BMASKDWORD);
280 tmplong2 = (tmplong2 & (~BLSSIREADADDRESS)) |
281 (newoffset << 23) | BLSSIREADEDGE;
282 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, BMASKDWORD,
283 tmplong & (~BLSSIREADEDGE));
284 udelay(10);
285 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, BMASKDWORD, tmplong2);
286 udelay(50);
287 udelay(50);
288 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, BMASKDWORD,
289 tmplong | BLSSIREADEDGE);
290 udelay(10);
291 if (rfpath == RF90_PATH_A)
292 rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1,
293 BIT(8));
294 else if (rfpath == RF90_PATH_B)
295 rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XB_HSSIPARAMETER1,
296 BIT(8));
297 if (rfpi_enable)
298 retvalue = rtl_get_bbreg(hw, pphyreg->rflssi_readbackpi,
299 BLSSIREADBACKDATA);
300 else
301 retvalue = rtl_get_bbreg(hw, pphyreg->rflssi_readback,
302 BLSSIREADBACKDATA);
303 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("RFR-%d Addr[0x%x] = 0x%x\n",
304 rfpath, pphyreg->rflssi_readback, retvalue));
305 return retvalue;
306 }
307
308 static void _rtl92d_phy_rf_serial_write(struct ieee80211_hw *hw,
309 enum radio_path rfpath,
310 u32 offset, u32 data)
311 {
312 u32 data_and_addr;
313 u32 newoffset;
314 struct rtl_priv *rtlpriv = rtl_priv(hw);
315 struct rtl_phy *rtlphy = &(rtlpriv->phy);
316 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
317
318 newoffset = offset;
319 /* T65 RF */
320 data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff;
321 rtl_set_bbreg(hw, pphyreg->rf3wire_offset, BMASKDWORD, data_and_addr);
322 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("RFW-%d Addr[0x%x]=0x%x\n",
323 rfpath, pphyreg->rf3wire_offset, data_and_addr));
324 }
325
326 u32 rtl92d_phy_query_rf_reg(struct ieee80211_hw *hw,
327 enum radio_path rfpath, u32 regaddr, u32 bitmask)
328 {
329 struct rtl_priv *rtlpriv = rtl_priv(hw);
330 u32 original_value, readback_value, bitshift;
331 unsigned long flags;
332
333 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("regaddr(%#x), "
334 "rfpath(%#x), bitmask(%#x)\n",
335 regaddr, rfpath, bitmask));
336 spin_lock_irqsave(&rtlpriv->locks.rf_lock, flags);
337 original_value = _rtl92d_phy_rf_serial_read(hw, rfpath, regaddr);
338 bitshift = _rtl92d_phy_calculate_bit_shift(bitmask);
339 readback_value = (original_value & bitmask) >> bitshift;
340 spin_unlock_irqrestore(&rtlpriv->locks.rf_lock, flags);
341 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("regaddr(%#x), rfpath(%#x), "
342 "bitmask(%#x), original_value(%#x)\n",
343 regaddr, rfpath, bitmask, original_value));
344 return readback_value;
345 }
346
347 void rtl92d_phy_set_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath,
348 u32 regaddr, u32 bitmask, u32 data)
349 {
350 struct rtl_priv *rtlpriv = rtl_priv(hw);
351 struct rtl_phy *rtlphy = &(rtlpriv->phy);
352 u32 original_value, bitshift;
353 unsigned long flags;
354
355 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
356 ("regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
357 regaddr, bitmask, data, rfpath));
358 if (bitmask == 0)
359 return;
360 spin_lock_irqsave(&rtlpriv->locks.rf_lock, flags);
361 if (rtlphy->rf_mode != RF_OP_BY_FW) {
362 if (bitmask != BRFREGOFFSETMASK) {
363 original_value = _rtl92d_phy_rf_serial_read(hw,
364 rfpath, regaddr);
365 bitshift = _rtl92d_phy_calculate_bit_shift(bitmask);
366 data = ((original_value & (~bitmask)) |
367 (data << bitshift));
368 }
369 _rtl92d_phy_rf_serial_write(hw, rfpath, regaddr, data);
370 }
371 spin_unlock_irqrestore(&rtlpriv->locks.rf_lock, flags);
372 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("regaddr(%#x), "
373 "bitmask(%#x), data(%#x), rfpath(%#x)\n",
374 regaddr, bitmask, data, rfpath));
375 }
376
377 bool rtl92d_phy_mac_config(struct ieee80211_hw *hw)
378 {
379 struct rtl_priv *rtlpriv = rtl_priv(hw);
380 u32 i;
381 u32 arraylength;
382 u32 *ptrarray;
383
384 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, ("Read Rtl819XMACPHY_Array\n"));
385 arraylength = MAC_2T_ARRAYLENGTH;
386 ptrarray = rtl8192de_mac_2tarray;
387 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, ("Img:Rtl819XMAC_Array\n"));
388 for (i = 0; i < arraylength; i = i + 2)
389 rtl_write_byte(rtlpriv, ptrarray[i], (u8) ptrarray[i + 1]);
390 if (rtlpriv->rtlhal.macphymode == SINGLEMAC_SINGLEPHY) {
391 /* improve 2-stream TX EVM */
392 /* rtl_write_byte(rtlpriv, 0x14,0x71); */
393 /* AMPDU aggregation number 9 */
394 /* rtl_write_word(rtlpriv, REG_MAX_AGGR_NUM, MAX_AGGR_NUM); */
395 rtl_write_byte(rtlpriv, REG_MAX_AGGR_NUM, 0x0B);
396 } else {
397 /* 92D need to test to decide the num. */
398 rtl_write_byte(rtlpriv, REG_MAX_AGGR_NUM, 0x07);
399 }
400 return true;
401 }
402
403 static void _rtl92d_phy_init_bb_rf_register_definition(struct ieee80211_hw *hw)
404 {
405 struct rtl_priv *rtlpriv = rtl_priv(hw);
406 struct rtl_phy *rtlphy = &(rtlpriv->phy);
407
408 /* RF Interface Sowrtware Control */
409 /* 16 LSBs if read 32-bit from 0x870 */
410 rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW;
411 /* 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872) */
412 rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW;
413 /* 16 LSBs if read 32-bit from 0x874 */
414 rtlphy->phyreg_def[RF90_PATH_C].rfintfs = RFPGA0_XCD_RFINTERFACESW;
415 /* 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876) */
416
417 rtlphy->phyreg_def[RF90_PATH_D].rfintfs = RFPGA0_XCD_RFINTERFACESW;
418 /* RF Interface Readback Value */
419 /* 16 LSBs if read 32-bit from 0x8E0 */
420 rtlphy->phyreg_def[RF90_PATH_A].rfintfi = RFPGA0_XAB_RFINTERFACERB;
421 /* 16 MSBs if read 32-bit from 0x8E0 (16-bit for 0x8E2) */
422 rtlphy->phyreg_def[RF90_PATH_B].rfintfi = RFPGA0_XAB_RFINTERFACERB;
423 /* 16 LSBs if read 32-bit from 0x8E4 */
424 rtlphy->phyreg_def[RF90_PATH_C].rfintfi = RFPGA0_XCD_RFINTERFACERB;
425 /* 16 MSBs if read 32-bit from 0x8E4 (16-bit for 0x8E6) */
426 rtlphy->phyreg_def[RF90_PATH_D].rfintfi = RFPGA0_XCD_RFINTERFACERB;
427
428 /* RF Interface Output (and Enable) */
429 /* 16 LSBs if read 32-bit from 0x860 */
430 rtlphy->phyreg_def[RF90_PATH_A].rfintfo = RFPGA0_XA_RFINTERFACEOE;
431 /* 16 LSBs if read 32-bit from 0x864 */
432 rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE;
433
434 /* RF Interface (Output and) Enable */
435 /* 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862) */
436 rtlphy->phyreg_def[RF90_PATH_A].rfintfe = RFPGA0_XA_RFINTERFACEOE;
437 /* 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866) */
438 rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE;
439
440 /* Addr of LSSI. Wirte RF register by driver */
441 /* LSSI Parameter */
442 rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset =
443 RFPGA0_XA_LSSIPARAMETER;
444 rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset =
445 RFPGA0_XB_LSSIPARAMETER;
446
447 /* RF parameter */
448 /* BB Band Select */
449 rtlphy->phyreg_def[RF90_PATH_A].rflssi_select = RFPGA0_XAB_RFPARAMETER;
450 rtlphy->phyreg_def[RF90_PATH_B].rflssi_select = RFPGA0_XAB_RFPARAMETER;
451 rtlphy->phyreg_def[RF90_PATH_C].rflssi_select = RFPGA0_XCD_RFPARAMETER;
452 rtlphy->phyreg_def[RF90_PATH_D].rflssi_select = RFPGA0_XCD_RFPARAMETER;
453
454 /* Tx AGC Gain Stage (same for all path. Should we remove this?) */
455 /* Tx gain stage */
456 rtlphy->phyreg_def[RF90_PATH_A].rftxgain_stage = RFPGA0_TXGAINSTAGE;
457 /* Tx gain stage */
458 rtlphy->phyreg_def[RF90_PATH_B].rftxgain_stage = RFPGA0_TXGAINSTAGE;
459 /* Tx gain stage */
460 rtlphy->phyreg_def[RF90_PATH_C].rftxgain_stage = RFPGA0_TXGAINSTAGE;
461 /* Tx gain stage */
462 rtlphy->phyreg_def[RF90_PATH_D].rftxgain_stage = RFPGA0_TXGAINSTAGE;
463
464 /* Tranceiver A~D HSSI Parameter-1 */
465 /* wire control parameter1 */
466 rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para1 = RFPGA0_XA_HSSIPARAMETER1;
467 /* wire control parameter1 */
468 rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para1 = RFPGA0_XB_HSSIPARAMETER1;
469
470 /* Tranceiver A~D HSSI Parameter-2 */
471 /* wire control parameter2 */
472 rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para2 = RFPGA0_XA_HSSIPARAMETER2;
473 /* wire control parameter2 */
474 rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RFPGA0_XB_HSSIPARAMETER2;
475
476 /* RF switch Control */
477 /* TR/Ant switch control */
478 rtlphy->phyreg_def[RF90_PATH_A].rfswitch_control =
479 RFPGA0_XAB_SWITCHCONTROL;
480 rtlphy->phyreg_def[RF90_PATH_B].rfswitch_control =
481 RFPGA0_XAB_SWITCHCONTROL;
482 rtlphy->phyreg_def[RF90_PATH_C].rfswitch_control =
483 RFPGA0_XCD_SWITCHCONTROL;
484 rtlphy->phyreg_def[RF90_PATH_D].rfswitch_control =
485 RFPGA0_XCD_SWITCHCONTROL;
486
487 /* AGC control 1 */
488 rtlphy->phyreg_def[RF90_PATH_A].rfagc_control1 = ROFDM0_XAAGCCORE1;
489 rtlphy->phyreg_def[RF90_PATH_B].rfagc_control1 = ROFDM0_XBAGCCORE1;
490 rtlphy->phyreg_def[RF90_PATH_C].rfagc_control1 = ROFDM0_XCAGCCORE1;
491 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control1 = ROFDM0_XDAGCCORE1;
492
493 /* AGC control 2 */
494 rtlphy->phyreg_def[RF90_PATH_A].rfagc_control2 = ROFDM0_XAAGCCORE2;
495 rtlphy->phyreg_def[RF90_PATH_B].rfagc_control2 = ROFDM0_XBAGCCORE2;
496 rtlphy->phyreg_def[RF90_PATH_C].rfagc_control2 = ROFDM0_XCAGCCORE2;
497 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control2 = ROFDM0_XDAGCCORE2;
498
499 /* RX AFE control 1 */
500 rtlphy->phyreg_def[RF90_PATH_A].rfrxiq_imbalance =
501 ROFDM0_XARXIQIMBALANCE;
502 rtlphy->phyreg_def[RF90_PATH_B].rfrxiq_imbalance =
503 ROFDM0_XBRXIQIMBALANCE;
504 rtlphy->phyreg_def[RF90_PATH_C].rfrxiq_imbalance =
505 ROFDM0_XCRXIQIMBALANCE;
506 rtlphy->phyreg_def[RF90_PATH_D].rfrxiq_imbalance =
507 ROFDM0_XDRXIQIMBALANCE;
508
509 /*RX AFE control 1 */
510 rtlphy->phyreg_def[RF90_PATH_A].rfrx_afe = ROFDM0_XARXAFE;
511 rtlphy->phyreg_def[RF90_PATH_B].rfrx_afe = ROFDM0_XBRXAFE;
512 rtlphy->phyreg_def[RF90_PATH_C].rfrx_afe = ROFDM0_XCRXAFE;
513 rtlphy->phyreg_def[RF90_PATH_D].rfrx_afe = ROFDM0_XDRXAFE;
514
515 /* Tx AFE control 1 */
516 rtlphy->phyreg_def[RF90_PATH_A].rftxiq_imbalance =
517 ROFDM0_XATxIQIMBALANCE;
518 rtlphy->phyreg_def[RF90_PATH_B].rftxiq_imbalance =
519 ROFDM0_XBTxIQIMBALANCE;
520 rtlphy->phyreg_def[RF90_PATH_C].rftxiq_imbalance =
521 ROFDM0_XCTxIQIMBALANCE;
522 rtlphy->phyreg_def[RF90_PATH_D].rftxiq_imbalance =
523 ROFDM0_XDTxIQIMBALANCE;
524
525 /* Tx AFE control 2 */
526 rtlphy->phyreg_def[RF90_PATH_A].rftx_afe = ROFDM0_XATxAFE;
527 rtlphy->phyreg_def[RF90_PATH_B].rftx_afe = ROFDM0_XBTxAFE;
528 rtlphy->phyreg_def[RF90_PATH_C].rftx_afe = ROFDM0_XCTxAFE;
529 rtlphy->phyreg_def[RF90_PATH_D].rftx_afe = ROFDM0_XDTxAFE;
530
531 /* Tranceiver LSSI Readback SI mode */
532 rtlphy->phyreg_def[RF90_PATH_A].rflssi_readback =
533 RFPGA0_XA_LSSIREADBACK;
534 rtlphy->phyreg_def[RF90_PATH_B].rflssi_readback =
535 RFPGA0_XB_LSSIREADBACK;
536 rtlphy->phyreg_def[RF90_PATH_C].rflssi_readback =
537 RFPGA0_XC_LSSIREADBACK;
538 rtlphy->phyreg_def[RF90_PATH_D].rflssi_readback =
539 RFPGA0_XD_LSSIREADBACK;
540
541 /* Tranceiver LSSI Readback PI mode */
542 rtlphy->phyreg_def[RF90_PATH_A].rflssi_readbackpi =
543 TRANSCEIVERA_HSPI_READBACK;
544 rtlphy->phyreg_def[RF90_PATH_B].rflssi_readbackpi =
545 TRANSCEIVERB_HSPI_READBACK;
546 }
547
548 static bool _rtl92d_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
549 u8 configtype)
550 {
551 int i;
552 u32 *phy_regarray_table;
553 u32 *agctab_array_table = NULL;
554 u32 *agctab_5garray_table;
555 u16 phy_reg_arraylen, agctab_arraylen = 0, agctab_5garraylen;
556 struct rtl_priv *rtlpriv = rtl_priv(hw);
557 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
558
559 /* Normal chip,Mac0 use AGC_TAB.txt for 2G and 5G band. */
560 if (rtlhal->interfaceindex == 0) {
561 agctab_arraylen = AGCTAB_ARRAYLENGTH;
562 agctab_array_table = rtl8192de_agctab_array;
563 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
564 (" ===> phy:MAC0, Rtl819XAGCTAB_Array\n"));
565 } else {
566 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
567 agctab_arraylen = AGCTAB_2G_ARRAYLENGTH;
568 agctab_array_table = rtl8192de_agctab_2garray;
569 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
570 (" ===> phy:MAC1, Rtl819XAGCTAB_2GArray\n"));
571 } else {
572 agctab_5garraylen = AGCTAB_5G_ARRAYLENGTH;
573 agctab_5garray_table = rtl8192de_agctab_5garray;
574 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
575 (" ===> phy:MAC1, Rtl819XAGCTAB_5GArray\n"));
576
577 }
578 }
579 phy_reg_arraylen = PHY_REG_2T_ARRAYLENGTH;
580 phy_regarray_table = rtl8192de_phy_reg_2tarray;
581 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
582 (" ===> phy:Rtl819XPHY_REG_Array_PG\n"));
583 if (configtype == BASEBAND_CONFIG_PHY_REG) {
584 for (i = 0; i < phy_reg_arraylen; i = i + 2) {
585 if (phy_regarray_table[i] == 0xfe)
586 mdelay(50);
587 else if (phy_regarray_table[i] == 0xfd)
588 mdelay(5);
589 else if (phy_regarray_table[i] == 0xfc)
590 mdelay(1);
591 else if (phy_regarray_table[i] == 0xfb)
592 udelay(50);
593 else if (phy_regarray_table[i] == 0xfa)
594 udelay(5);
595 else if (phy_regarray_table[i] == 0xf9)
596 udelay(1);
597 rtl_set_bbreg(hw, phy_regarray_table[i], BMASKDWORD,
598 phy_regarray_table[i + 1]);
599 udelay(1);
600 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
601 ("The phy_regarray_table[0] is %x"
602 " Rtl819XPHY_REGArray[1] is %x\n",
603 phy_regarray_table[i],
604 phy_regarray_table[i + 1]));
605 }
606 } else if (configtype == BASEBAND_CONFIG_AGC_TAB) {
607 if (rtlhal->interfaceindex == 0) {
608 for (i = 0; i < agctab_arraylen; i = i + 2) {
609 rtl_set_bbreg(hw, agctab_array_table[i],
610 BMASKDWORD,
611 agctab_array_table[i + 1]);
612 /* Add 1us delay between BB/RF register
613 * setting. */
614 udelay(1);
615 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
616 ("The Rtl819XAGCTAB_Array_"
617 "Table[0] is %ul "
618 "Rtl819XPHY_REGArray[1] is %ul\n",
619 agctab_array_table[i],
620 agctab_array_table[i + 1]));
621 }
622 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
623 ("Normal Chip, MAC0, load "
624 "Rtl819XAGCTAB_Array\n"));
625 } else {
626 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
627 for (i = 0; i < agctab_arraylen; i = i + 2) {
628 rtl_set_bbreg(hw, agctab_array_table[i],
629 BMASKDWORD,
630 agctab_array_table[i + 1]);
631 /* Add 1us delay between BB/RF register
632 * setting. */
633 udelay(1);
634 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
635 ("The Rtl819XAGCTAB_Array_"
636 "Table[0] is %ul Rtl819XPHY_"
637 "REGArray[1] is %ul\n",
638 agctab_array_table[i],
639 agctab_array_table[i + 1]));
640 }
641 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
642 ("Load Rtl819XAGCTAB_2GArray\n"));
643 } else {
644 for (i = 0; i < agctab_5garraylen; i = i + 2) {
645 rtl_set_bbreg(hw,
646 agctab_5garray_table[i],
647 BMASKDWORD,
648 agctab_5garray_table[i + 1]);
649 /* Add 1us delay between BB/RF registeri
650 * setting. */
651 udelay(1);
652 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
653 ("The Rtl819XAGCTAB_5GArray_"
654 "Table[0] is %ul Rtl819XPHY_"
655 "REGArray[1] is %ul\n",
656 agctab_5garray_table[i],
657 agctab_5garray_table[i + 1]));
658 }
659 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
660 ("Load Rtl819XAGCTAB_5GArray\n"));
661 }
662 }
663 }
664 return true;
665 }
666
667 static void _rtl92d_store_pwrindex_diffrate_offset(struct ieee80211_hw *hw,
668 u32 regaddr, u32 bitmask,
669 u32 data)
670 {
671 struct rtl_priv *rtlpriv = rtl_priv(hw);
672 struct rtl_phy *rtlphy = &(rtlpriv->phy);
673
674 if (regaddr == RTXAGC_A_RATE18_06) {
675 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][0] =
676 data;
677 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
678 ("MCSTxPowerLevelOriginalOffset[%d][0] = 0x%ulx\n",
679 rtlphy->pwrgroup_cnt,
680 rtlphy->mcs_txpwrlevel_origoffset
681 [rtlphy->pwrgroup_cnt][0]));
682 }
683 if (regaddr == RTXAGC_A_RATE54_24) {
684 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][1] =
685 data;
686 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
687 ("MCSTxPowerLevelOriginalOffset[%d][1] = 0x%ulx\n",
688 rtlphy->pwrgroup_cnt,
689 rtlphy->mcs_txpwrlevel_origoffset
690 [rtlphy->pwrgroup_cnt][1]));
691 }
692 if (regaddr == RTXAGC_A_CCK1_MCS32) {
693 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][6] =
694 data;
695 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
696 ("MCSTxPowerLevelOriginalOffset[%d][6] = 0x%ulx\n",
697 rtlphy->pwrgroup_cnt,
698 rtlphy->mcs_txpwrlevel_origoffset
699 [rtlphy->pwrgroup_cnt][6]));
700 }
701 if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0xffffff00) {
702 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][7] =
703 data;
704 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
705 ("MCSTxPowerLevelOriginalOffset[%d][7] = 0x%ulx\n",
706 rtlphy->pwrgroup_cnt,
707 rtlphy->mcs_txpwrlevel_origoffset
708 [rtlphy->pwrgroup_cnt][7]));
709 }
710 if (regaddr == RTXAGC_A_MCS03_MCS00) {
711 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][2] =
712 data;
713 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
714 ("MCSTxPowerLevelOriginalOffset[%d][2] = 0x%ulx\n",
715 rtlphy->pwrgroup_cnt,
716 rtlphy->mcs_txpwrlevel_origoffset
717 [rtlphy->pwrgroup_cnt][2]));
718 }
719 if (regaddr == RTXAGC_A_MCS07_MCS04) {
720 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][3] =
721 data;
722 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
723 ("MCSTxPowerLevelOriginalOffset[%d][3] = 0x%ulx\n",
724 rtlphy->pwrgroup_cnt,
725 rtlphy->mcs_txpwrlevel_origoffset
726 [rtlphy->pwrgroup_cnt][3]));
727 }
728 if (regaddr == RTXAGC_A_MCS11_MCS08) {
729 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][4] =
730 data;
731 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
732 ("MCSTxPowerLevelOriginalOffset[%d][4] = 0x%ulx\n",
733 rtlphy->pwrgroup_cnt,
734 rtlphy->mcs_txpwrlevel_origoffset
735 [rtlphy->pwrgroup_cnt][4]));
736 }
737 if (regaddr == RTXAGC_A_MCS15_MCS12) {
738 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][5] =
739 data;
740 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
741 ("MCSTxPowerLevelOriginalOffset[%d][5] = 0x%ulx\n",
742 rtlphy->pwrgroup_cnt,
743 rtlphy->mcs_txpwrlevel_origoffset
744 [rtlphy->pwrgroup_cnt][5]));
745 }
746 if (regaddr == RTXAGC_B_RATE18_06) {
747 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][8] =
748 data;
749 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
750 ("MCSTxPowerLevelOriginalOffset[%d][8] = 0x%ulx\n",
751 rtlphy->pwrgroup_cnt,
752 rtlphy->mcs_txpwrlevel_origoffset
753 [rtlphy->pwrgroup_cnt][8]));
754 }
755 if (regaddr == RTXAGC_B_RATE54_24) {
756 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][9] =
757 data;
758 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
759 ("MCSTxPowerLevelOriginalOffset[%d][9] = 0x%ulx\n",
760 rtlphy->pwrgroup_cnt,
761 rtlphy->mcs_txpwrlevel_origoffset
762 [rtlphy->pwrgroup_cnt][9]));
763 }
764 if (regaddr == RTXAGC_B_CCK1_55_MCS32) {
765 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][14] =
766 data;
767 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
768 ("MCSTxPowerLevelOriginalOffset[%d][14] = 0x%ulx\n",
769 rtlphy->pwrgroup_cnt,
770 rtlphy->mcs_txpwrlevel_origoffset
771 [rtlphy->pwrgroup_cnt][14]));
772 }
773 if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0x000000ff) {
774 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][15] =
775 data;
776 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
777 ("MCSTxPowerLevelOriginalOffset[%d][15] = 0x%ulx\n",
778 rtlphy->pwrgroup_cnt,
779 rtlphy->mcs_txpwrlevel_origoffset
780 [rtlphy->pwrgroup_cnt][15]));
781 }
782 if (regaddr == RTXAGC_B_MCS03_MCS00) {
783 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][10] =
784 data;
785 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
786 ("MCSTxPowerLevelOriginalOffset[%d][10] = 0x%ulx\n",
787 rtlphy->pwrgroup_cnt,
788 rtlphy->mcs_txpwrlevel_origoffset
789 [rtlphy->pwrgroup_cnt][10]));
790 }
791 if (regaddr == RTXAGC_B_MCS07_MCS04) {
792 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][11] =
793 data;
794 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
795 ("MCSTxPowerLevelOriginalOffset[%d][11] = 0x%ulx\n",
796 rtlphy->pwrgroup_cnt,
797 rtlphy->mcs_txpwrlevel_origoffset
798 [rtlphy->pwrgroup_cnt][11]));
799 }
800 if (regaddr == RTXAGC_B_MCS11_MCS08) {
801 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][12] =
802 data;
803 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
804 ("MCSTxPowerLevelOriginalOffset[%d][12] = 0x%ulx\n",
805 rtlphy->pwrgroup_cnt,
806 rtlphy->mcs_txpwrlevel_origoffset
807 [rtlphy->pwrgroup_cnt][12]));
808 }
809 if (regaddr == RTXAGC_B_MCS15_MCS12) {
810 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][13] =
811 data;
812 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
813 ("MCSTxPowerLevelOriginalOffset[%d][13] = 0x%ulx\n",
814 rtlphy->pwrgroup_cnt,
815 rtlphy->mcs_txpwrlevel_origoffset
816 [rtlphy->pwrgroup_cnt][13]));
817 rtlphy->pwrgroup_cnt++;
818 }
819 }
820
821 static bool _rtl92d_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
822 u8 configtype)
823 {
824 struct rtl_priv *rtlpriv = rtl_priv(hw);
825 int i;
826 u32 *phy_regarray_table_pg;
827 u16 phy_regarray_pg_len;
828
829 phy_regarray_pg_len = PHY_REG_ARRAY_PG_LENGTH;
830 phy_regarray_table_pg = rtl8192de_phy_reg_array_pg;
831 if (configtype == BASEBAND_CONFIG_PHY_REG) {
832 for (i = 0; i < phy_regarray_pg_len; i = i + 3) {
833 if (phy_regarray_table_pg[i] == 0xfe)
834 mdelay(50);
835 else if (phy_regarray_table_pg[i] == 0xfd)
836 mdelay(5);
837 else if (phy_regarray_table_pg[i] == 0xfc)
838 mdelay(1);
839 else if (phy_regarray_table_pg[i] == 0xfb)
840 udelay(50);
841 else if (phy_regarray_table_pg[i] == 0xfa)
842 udelay(5);
843 else if (phy_regarray_table_pg[i] == 0xf9)
844 udelay(1);
845 _rtl92d_store_pwrindex_diffrate_offset(hw,
846 phy_regarray_table_pg[i],
847 phy_regarray_table_pg[i + 1],
848 phy_regarray_table_pg[i + 2]);
849 }
850 } else {
851 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
852 ("configtype != BaseBand_Config_PHY_REG\n"));
853 }
854 return true;
855 }
856
857 static bool _rtl92d_phy_bb_config(struct ieee80211_hw *hw)
858 {
859 struct rtl_priv *rtlpriv = rtl_priv(hw);
860 struct rtl_phy *rtlphy = &(rtlpriv->phy);
861 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
862 bool rtstatus = true;
863
864 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, ("==>\n"));
865 rtstatus = _rtl92d_phy_config_bb_with_headerfile(hw,
866 BASEBAND_CONFIG_PHY_REG);
867 if (rtstatus != true) {
868 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("Write BB Reg Fail!!"));
869 return false;
870 }
871
872 /* if (rtlphy->rf_type == RF_1T2R) {
873 * _rtl92c_phy_bb_config_1t(hw);
874 * RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, ("Config to 1T!!\n"));
875 *} */
876
877 if (rtlefuse->autoload_failflag == false) {
878 rtlphy->pwrgroup_cnt = 0;
879 rtstatus = _rtl92d_phy_config_bb_with_pgheaderfile(hw,
880 BASEBAND_CONFIG_PHY_REG);
881 }
882 if (rtstatus != true) {
883 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("BB_PG Reg Fail!!"));
884 return false;
885 }
886 rtstatus = _rtl92d_phy_config_bb_with_headerfile(hw,
887 BASEBAND_CONFIG_AGC_TAB);
888 if (rtstatus != true) {
889 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("AGC Table Fail\n"));
890 return false;
891 }
892 rtlphy->cck_high_power = (bool) (rtl_get_bbreg(hw,
893 RFPGA0_XA_HSSIPARAMETER2, 0x200));
894
895 return true;
896 }
897
898 bool rtl92d_phy_bb_config(struct ieee80211_hw *hw)
899 {
900 struct rtl_priv *rtlpriv = rtl_priv(hw);
901 u16 regval;
902 u32 regvaldw;
903 u8 value;
904
905 _rtl92d_phy_init_bb_rf_register_definition(hw);
906 regval = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
907 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN,
908 regval | BIT(13) | BIT(0) | BIT(1));
909 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x83);
910 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL + 1, 0xdb);
911 /* 0x1f bit7 bit6 represent for mac0/mac1 driver ready */
912 value = rtl_read_byte(rtlpriv, REG_RF_CTRL);
913 rtl_write_byte(rtlpriv, REG_RF_CTRL, value | RF_EN | RF_RSTB |
914 RF_SDMRSTB);
915 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, FEN_PPLL | FEN_PCIEA |
916 FEN_DIO_PCIE | FEN_BB_GLB_RSTn | FEN_BBRSTB);
917 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL + 1, 0x80);
918 if (!(IS_92D_SINGLEPHY(rtlpriv->rtlhal.version))) {
919 regvaldw = rtl_read_dword(rtlpriv, REG_LEDCFG0);
920 rtl_write_dword(rtlpriv, REG_LEDCFG0, regvaldw | BIT(23));
921 }
922
923 return _rtl92d_phy_bb_config(hw);
924 }
925
926 bool rtl92d_phy_rf_config(struct ieee80211_hw *hw)
927 {
928 return rtl92d_phy_rf6052_config(hw);
929 }
930
931 bool rtl92d_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
932 enum rf_content content,
933 enum radio_path rfpath)
934 {
935 int i;
936 u32 *radioa_array_table;
937 u32 *radiob_array_table;
938 u16 radioa_arraylen, radiob_arraylen;
939 struct rtl_priv *rtlpriv = rtl_priv(hw);
940
941 radioa_arraylen = RADIOA_2T_ARRAYLENGTH;
942 radioa_array_table = rtl8192de_radioa_2tarray;
943 radiob_arraylen = RADIOB_2T_ARRAYLENGTH;
944 radiob_array_table = rtl8192de_radiob_2tarray;
945 if (rtlpriv->efuse.internal_pa_5g[0]) {
946 radioa_arraylen = RADIOA_2T_INT_PA_ARRAYLENGTH;
947 radioa_array_table = rtl8192de_radioa_2t_int_paarray;
948 }
949 if (rtlpriv->efuse.internal_pa_5g[1]) {
950 radiob_arraylen = RADIOB_2T_INT_PA_ARRAYLENGTH;
951 radiob_array_table = rtl8192de_radiob_2t_int_paarray;
952 }
953 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
954 ("PHY_ConfigRFWithHeaderFile() "
955 "Radio_A:Rtl819XRadioA_1TArray\n"));
956 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
957 ("PHY_ConfigRFWithHeaderFile() "
958 "Radio_B:Rtl819XRadioB_1TArray\n"));
959 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, ("Radio No %x\n", rfpath));
960
961 /* this only happens when DMDP, mac0 start on 2.4G,
962 * mac1 start on 5G, mac 0 has to set phy0&phy1
963 * pathA or mac1 has to set phy0&phy1 pathA */
964 if ((content == radiob_txt) && (rfpath == RF90_PATH_A)) {
965 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
966 (" ===> althougth Path A, we load radiob.txt\n"));
967 radioa_arraylen = radiob_arraylen;
968 radioa_array_table = radiob_array_table;
969 }
970 switch (rfpath) {
971 case RF90_PATH_A:
972 for (i = 0; i < radioa_arraylen; i = i + 2) {
973 if (radioa_array_table[i] == 0xfe) {
974 mdelay(50);
975 } else if (radioa_array_table[i] == 0xfd) {
976 /* delay_ms(5); */
977 mdelay(5);
978 } else if (radioa_array_table[i] == 0xfc) {
979 /* delay_ms(1); */
980 mdelay(1);
981 } else if (radioa_array_table[i] == 0xfb) {
982 udelay(50);
983 } else if (radioa_array_table[i] == 0xfa) {
984 udelay(5);
985 } else if (radioa_array_table[i] == 0xf9) {
986 udelay(1);
987 } else {
988 rtl_set_rfreg(hw, rfpath, radioa_array_table[i],
989 BRFREGOFFSETMASK,
990 radioa_array_table[i + 1]);
991 /* Add 1us delay between BB/RF register set. */
992 udelay(1);
993 }
994 }
995 break;
996 case RF90_PATH_B:
997 for (i = 0; i < radiob_arraylen; i = i + 2) {
998 if (radiob_array_table[i] == 0xfe) {
999 /* Delay specific ms. Only RF configuration
1000 * requires delay. */
1001 mdelay(50);
1002 } else if (radiob_array_table[i] == 0xfd) {
1003 /* delay_ms(5); */
1004 mdelay(5);
1005 } else if (radiob_array_table[i] == 0xfc) {
1006 /* delay_ms(1); */
1007 mdelay(1);
1008 } else if (radiob_array_table[i] == 0xfb) {
1009 udelay(50);
1010 } else if (radiob_array_table[i] == 0xfa) {
1011 udelay(5);
1012 } else if (radiob_array_table[i] == 0xf9) {
1013 udelay(1);
1014 } else {
1015 rtl_set_rfreg(hw, rfpath, radiob_array_table[i],
1016 BRFREGOFFSETMASK,
1017 radiob_array_table[i + 1]);
1018 /* Add 1us delay between BB/RF register set. */
1019 udelay(1);
1020 }
1021 }
1022 break;
1023 case RF90_PATH_C:
1024 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1025 ("switch case not process\n"));
1026 break;
1027 case RF90_PATH_D:
1028 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1029 ("switch case not process\n"));
1030 break;
1031 }
1032 return true;
1033 }
1034
1035 void rtl92d_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw)
1036 {
1037 struct rtl_priv *rtlpriv = rtl_priv(hw);
1038 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1039
1040 rtlphy->default_initialgain[0] =
1041 (u8) rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, BMASKBYTE0);
1042 rtlphy->default_initialgain[1] =
1043 (u8) rtl_get_bbreg(hw, ROFDM0_XBAGCCORE1, BMASKBYTE0);
1044 rtlphy->default_initialgain[2] =
1045 (u8) rtl_get_bbreg(hw, ROFDM0_XCAGCCORE1, BMASKBYTE0);
1046 rtlphy->default_initialgain[3] =
1047 (u8) rtl_get_bbreg(hw, ROFDM0_XDAGCCORE1, BMASKBYTE0);
1048 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1049 ("Default initial gain (c50=0x%x, "
1050 "c58=0x%x, c60=0x%x, c68=0x%x\n",
1051 rtlphy->default_initialgain[0],
1052 rtlphy->default_initialgain[1],
1053 rtlphy->default_initialgain[2],
1054 rtlphy->default_initialgain[3]));
1055 rtlphy->framesync = (u8)rtl_get_bbreg(hw, ROFDM0_RXDETECTOR3,
1056 BMASKBYTE0);
1057 rtlphy->framesync_c34 = rtl_get_bbreg(hw, ROFDM0_RXDETECTOR2,
1058 BMASKDWORD);
1059 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1060 ("Default framesync (0x%x) = 0x%x\n",
1061 ROFDM0_RXDETECTOR3, rtlphy->framesync));
1062 }
1063
1064 static void _rtl92d_get_txpower_index(struct ieee80211_hw *hw, u8 channel,
1065 u8 *cckpowerlevel, u8 *ofdmpowerlevel)
1066 {
1067 struct rtl_priv *rtlpriv = rtl_priv(hw);
1068 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1069 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
1070 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1071 u8 index = (channel - 1);
1072
1073 /* 1. CCK */
1074 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
1075 /* RF-A */
1076 cckpowerlevel[RF90_PATH_A] =
1077 rtlefuse->txpwrlevel_cck[RF90_PATH_A][index];
1078 /* RF-B */
1079 cckpowerlevel[RF90_PATH_B] =
1080 rtlefuse->txpwrlevel_cck[RF90_PATH_B][index];
1081 } else {
1082 cckpowerlevel[RF90_PATH_A] = 0;
1083 cckpowerlevel[RF90_PATH_B] = 0;
1084 }
1085 /* 2. OFDM for 1S or 2S */
1086 if (rtlphy->rf_type == RF_1T2R || rtlphy->rf_type == RF_1T1R) {
1087 /* Read HT 40 OFDM TX power */
1088 ofdmpowerlevel[RF90_PATH_A] =
1089 rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_A][index];
1090 ofdmpowerlevel[RF90_PATH_B] =
1091 rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_B][index];
1092 } else if (rtlphy->rf_type == RF_2T2R) {
1093 /* Read HT 40 OFDM TX power */
1094 ofdmpowerlevel[RF90_PATH_A] =
1095 rtlefuse->txpwrlevel_ht40_2s[RF90_PATH_A][index];
1096 ofdmpowerlevel[RF90_PATH_B] =
1097 rtlefuse->txpwrlevel_ht40_2s[RF90_PATH_B][index];
1098 }
1099 }
1100
1101 static void _rtl92d_ccxpower_index_check(struct ieee80211_hw *hw,
1102 u8 channel, u8 *cckpowerlevel, u8 *ofdmpowerlevel)
1103 {
1104 struct rtl_priv *rtlpriv = rtl_priv(hw);
1105 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1106
1107 rtlphy->cur_cck_txpwridx = cckpowerlevel[0];
1108 rtlphy->cur_ofdm24g_txpwridx = ofdmpowerlevel[0];
1109 }
1110
1111 static u8 _rtl92c_phy_get_rightchnlplace(u8 chnl)
1112 {
1113 u8 channel_5g[59] = {
1114 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
1115 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58,
1116 60, 62, 64, 100, 102, 104, 106, 108, 110, 112,
1117 114, 116, 118, 120, 122, 124, 126, 128,
1118 130, 132, 134, 136, 138, 140, 149, 151,
1119 153, 155, 157, 159, 161, 163, 165
1120 };
1121 u8 place = chnl;
1122
1123 if (chnl > 14) {
1124 for (place = 14; place < sizeof(channel_5g); place++) {
1125 if (channel_5g[place] == chnl) {
1126 place++;
1127 break;
1128 }
1129 }
1130 }
1131 return place;
1132 }
1133
1134 void rtl92d_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel)
1135 {
1136 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1137 struct rtl_priv *rtlpriv = rtl_priv(hw);
1138 u8 cckpowerlevel[2], ofdmpowerlevel[2];
1139
1140 if (rtlefuse->txpwr_fromeprom == false)
1141 return;
1142 channel = _rtl92c_phy_get_rightchnlplace(channel);
1143 _rtl92d_get_txpower_index(hw, channel, &cckpowerlevel[0],
1144 &ofdmpowerlevel[0]);
1145 if (rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G)
1146 _rtl92d_ccxpower_index_check(hw, channel, &cckpowerlevel[0],
1147 &ofdmpowerlevel[0]);
1148 if (rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G)
1149 rtl92d_phy_rf6052_set_cck_txpower(hw, &cckpowerlevel[0]);
1150 rtl92d_phy_rf6052_set_ofdm_txpower(hw, &ofdmpowerlevel[0], channel);
1151 }
1152
1153 void rtl92d_phy_scan_operation_backup(struct ieee80211_hw *hw, u8 operation)
1154 {
1155 struct rtl_priv *rtlpriv = rtl_priv(hw);
1156 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1157 enum io_type iotype;
1158
1159 if (!is_hal_stop(rtlhal)) {
1160 switch (operation) {
1161 case SCAN_OPT_BACKUP:
1162 rtlhal->current_bandtypebackup =
1163 rtlhal->current_bandtype;
1164 iotype = IO_CMD_PAUSE_DM_BY_SCAN;
1165 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_IO_CMD,
1166 (u8 *)&iotype);
1167 break;
1168 case SCAN_OPT_RESTORE:
1169 iotype = IO_CMD_RESUME_DM_BY_SCAN;
1170 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_IO_CMD,
1171 (u8 *)&iotype);
1172 break;
1173 default:
1174 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1175 ("Unknown Scan Backup operation.\n"));
1176 break;
1177 }
1178 }
1179 }
1180
1181 void rtl92d_phy_set_bw_mode(struct ieee80211_hw *hw,
1182 enum nl80211_channel_type ch_type)
1183 {
1184 struct rtl_priv *rtlpriv = rtl_priv(hw);
1185 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1186 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1187 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1188 unsigned long flag = 0;
1189 u8 reg_prsr_rsc;
1190 u8 reg_bw_opmode;
1191
1192 if (rtlphy->set_bwmode_inprogress)
1193 return;
1194 if ((is_hal_stop(rtlhal)) || (RT_CANNOT_IO(hw))) {
1195 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1196 ("FALSE driver sleep or unload\n"));
1197 return;
1198 }
1199 rtlphy->set_bwmode_inprogress = true;
1200 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE,
1201 ("Switch to %s bandwidth\n",
1202 rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ?
1203 "20MHz" : "40MHz"));
1204 reg_bw_opmode = rtl_read_byte(rtlpriv, REG_BWOPMODE);
1205 reg_prsr_rsc = rtl_read_byte(rtlpriv, REG_RRSR + 2);
1206 switch (rtlphy->current_chan_bw) {
1207 case HT_CHANNEL_WIDTH_20:
1208 reg_bw_opmode |= BW_OPMODE_20MHZ;
1209 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
1210 break;
1211 case HT_CHANNEL_WIDTH_20_40:
1212 reg_bw_opmode &= ~BW_OPMODE_20MHZ;
1213 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
1214
1215 reg_prsr_rsc = (reg_prsr_rsc & 0x90) |
1216 (mac->cur_40_prime_sc << 5);
1217 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_prsr_rsc);
1218 break;
1219 default:
1220 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1221 ("unknown bandwidth: %#X\n", rtlphy->current_chan_bw));
1222 break;
1223 }
1224 switch (rtlphy->current_chan_bw) {
1225 case HT_CHANNEL_WIDTH_20:
1226 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0);
1227 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0);
1228 /* SET BIT10 BIT11 for receive cck */
1229 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10) |
1230 BIT(11), 3);
1231 break;
1232 case HT_CHANNEL_WIDTH_20_40:
1233 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1);
1234 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1);
1235 /* Set Control channel to upper or lower.
1236 * These settings are required only for 40MHz */
1237 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
1238 rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag);
1239 rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCKSIDEBAND,
1240 (mac->cur_40_prime_sc >> 1));
1241 rtl92d_release_cckandrw_pagea_ctl(hw, &flag);
1242 }
1243 rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc);
1244 /* SET BIT10 BIT11 for receive cck */
1245 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10) |
1246 BIT(11), 0);
1247 rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)),
1248 (mac->cur_40_prime_sc ==
1249 HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1);
1250 break;
1251 default:
1252 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1253 ("unknown bandwidth: %#X\n", rtlphy->current_chan_bw));
1254 break;
1255
1256 }
1257 rtl92d_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw);
1258 rtlphy->set_bwmode_inprogress = false;
1259 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, ("<==\n"));
1260 }
1261
1262 static void _rtl92d_phy_stop_trx_before_changeband(struct ieee80211_hw *hw)
1263 {
1264 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0);
1265 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0);
1266 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, BMASKBYTE0, 0x00);
1267 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x0);
1268 }
1269
1270 static void rtl92d_phy_switch_wirelessband(struct ieee80211_hw *hw, u8 band)
1271 {
1272 struct rtl_priv *rtlpriv = rtl_priv(hw);
1273 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1274 u8 value8;
1275
1276 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("==>\n"));
1277 rtlhal->bandset = band;
1278 rtlhal->current_bandtype = band;
1279 if (IS_92D_SINGLEPHY(rtlhal->version))
1280 rtlhal->bandset = BAND_ON_BOTH;
1281 /* stop RX/Tx */
1282 _rtl92d_phy_stop_trx_before_changeband(hw);
1283 /* reconfig BB/RF according to wireless mode */
1284 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
1285 /* BB & RF Config */
1286 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, ("====>2.4G\n"));
1287 if (rtlhal->interfaceindex == 1)
1288 _rtl92d_phy_config_bb_with_headerfile(hw,
1289 BASEBAND_CONFIG_AGC_TAB);
1290 } else {
1291 /* 5G band */
1292 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, ("====>5G\n"));
1293 if (rtlhal->interfaceindex == 1)
1294 _rtl92d_phy_config_bb_with_headerfile(hw,
1295 BASEBAND_CONFIG_AGC_TAB);
1296 }
1297 rtl92d_update_bbrf_configuration(hw);
1298 if (rtlhal->current_bandtype == BAND_ON_2_4G)
1299 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
1300 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
1301
1302 /* 20M BW. */
1303 /* rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1); */
1304 rtlhal->reloadtxpowerindex = true;
1305 /* notice fw know band status 0x81[1]/0x53[1] = 0: 5G, 1: 2G */
1306 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
1307 value8 = rtl_read_byte(rtlpriv, (rtlhal->interfaceindex ==
1308 0 ? REG_MAC0 : REG_MAC1));
1309 value8 |= BIT(1);
1310 rtl_write_byte(rtlpriv, (rtlhal->interfaceindex ==
1311 0 ? REG_MAC0 : REG_MAC1), value8);
1312 } else {
1313 value8 = rtl_read_byte(rtlpriv, (rtlhal->interfaceindex ==
1314 0 ? REG_MAC0 : REG_MAC1));
1315 value8 &= (~BIT(1));
1316 rtl_write_byte(rtlpriv, (rtlhal->interfaceindex ==
1317 0 ? REG_MAC0 : REG_MAC1), value8);
1318 }
1319 mdelay(1);
1320 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("<==Switch Band OK.\n"));
1321 }
1322
1323 static void _rtl92d_phy_reload_imr_setting(struct ieee80211_hw *hw,
1324 u8 channel, u8 rfpath)
1325 {
1326 struct rtl_priv *rtlpriv = rtl_priv(hw);
1327 u32 imr_num = MAX_RF_IMR_INDEX;
1328 u32 rfmask = BRFREGOFFSETMASK;
1329 u8 group, i;
1330 unsigned long flag = 0;
1331
1332 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, ("====>path %d\n", rfpath));
1333 if (rtlpriv->rtlhal.current_bandtype == BAND_ON_5G) {
1334 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, ("====>5G\n"));
1335 rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(25) | BIT(24), 0);
1336 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0xf);
1337 /* fc area 0xd2c */
1338 if (channel > 99)
1339 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(13) |
1340 BIT(14), 2);
1341 else
1342 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(13) |
1343 BIT(14), 1);
1344 /* leave 0 for channel1-14. */
1345 group = channel <= 64 ? 1 : 2;
1346 imr_num = MAX_RF_IMR_INDEX_NORMAL;
1347 for (i = 0; i < imr_num; i++)
1348 rtl_set_rfreg(hw, (enum radio_path)rfpath,
1349 rf_reg_for_5g_swchnl_normal[i], rfmask,
1350 rf_imr_param_normal[0][group][i]);
1351 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0);
1352 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 1);
1353 } else {
1354 /* G band. */
1355 RT_TRACE(rtlpriv, COMP_SCAN, DBG_LOUD,
1356 ("Load RF IMR parameters for G band. IMR already "
1357 "setting %d\n",
1358 rtlpriv->rtlhal.load_imrandiqk_setting_for2g));
1359 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, ("====>2.4G\n"));
1360 if (!rtlpriv->rtlhal.load_imrandiqk_setting_for2g) {
1361 RT_TRACE(rtlpriv, COMP_SCAN, DBG_LOUD,
1362 ("Load RF IMR parameters "
1363 "for G band. %d\n", rfpath));
1364 rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag);
1365 rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(25) | BIT(24), 0);
1366 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4,
1367 0x00f00000, 0xf);
1368 imr_num = MAX_RF_IMR_INDEX_NORMAL;
1369 for (i = 0; i < imr_num; i++) {
1370 rtl_set_rfreg(hw, (enum radio_path)rfpath,
1371 rf_reg_for_5g_swchnl_normal[i],
1372 BRFREGOFFSETMASK,
1373 rf_imr_param_normal[0][0][i]);
1374 }
1375 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4,
1376 0x00f00000, 0);
1377 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN | BCCKEN, 3);
1378 rtl92d_release_cckandrw_pagea_ctl(hw, &flag);
1379 }
1380 }
1381 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, ("<====\n"));
1382 }
1383
1384 static void _rtl92d_phy_enable_rf_env(struct ieee80211_hw *hw,
1385 u8 rfpath, u32 *pu4_regval)
1386 {
1387 struct rtl_priv *rtlpriv = rtl_priv(hw);
1388 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1389 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
1390
1391 RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD, ("====>\n"));
1392 /*----Store original RFENV control type----*/
1393 switch (rfpath) {
1394 case RF90_PATH_A:
1395 case RF90_PATH_C:
1396 *pu4_regval = rtl_get_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV);
1397 break;
1398 case RF90_PATH_B:
1399 case RF90_PATH_D:
1400 *pu4_regval =
1401 rtl_get_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV << 16);
1402 break;
1403 }
1404 /*----Set RF_ENV enable----*/
1405 rtl_set_bbreg(hw, pphyreg->rfintfe, BRFSI_RFENV << 16, 0x1);
1406 udelay(1);
1407 /*----Set RF_ENV output high----*/
1408 rtl_set_bbreg(hw, pphyreg->rfintfo, BRFSI_RFENV, 0x1);
1409 udelay(1);
1410 /* Set bit number of Address and Data for RF register */
1411 /* Set 1 to 4 bits for 8255 */
1412 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, B3WIREADDRESSLENGTH, 0x0);
1413 udelay(1);
1414 /*Set 0 to 12 bits for 8255 */
1415 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, B3WIREDATALENGTH, 0x0);
1416 udelay(1);
1417 RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD, ("<====\n"));
1418 }
1419
1420 static void _rtl92d_phy_restore_rf_env(struct ieee80211_hw *hw, u8 rfpath,
1421 u32 *pu4_regval)
1422 {
1423 struct rtl_priv *rtlpriv = rtl_priv(hw);
1424 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1425 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
1426
1427 RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD, ("=====>\n"));
1428 /*----Restore RFENV control type----*/ ;
1429 switch (rfpath) {
1430 case RF90_PATH_A:
1431 case RF90_PATH_C:
1432 rtl_set_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV, *pu4_regval);
1433 break;
1434 case RF90_PATH_B:
1435 case RF90_PATH_D:
1436 rtl_set_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV << 16,
1437 *pu4_regval);
1438 break;
1439 }
1440 RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD, ("<=====\n"));
1441 }
1442
1443 static void _rtl92d_phy_switch_rf_setting(struct ieee80211_hw *hw, u8 channel)
1444 {
1445 struct rtl_priv *rtlpriv = rtl_priv(hw);
1446 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1447 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
1448 u8 path = rtlhal->current_bandtype ==
1449 BAND_ON_5G ? RF90_PATH_A : RF90_PATH_B;
1450 u8 index = 0, i = 0, rfpath = RF90_PATH_A;
1451 bool need_pwr_down = false, internal_pa = false;
1452 u32 u4regvalue, mask = 0x1C000, value = 0, u4tmp, u4tmp2;
1453
1454 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, ("====>\n"));
1455 /* config path A for 5G */
1456 if (rtlhal->current_bandtype == BAND_ON_5G) {
1457 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, ("====>5G\n"));
1458 u4tmp = curveindex_5g[channel - 1];
1459 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("ver 1 set RF-A, 5G, "
1460 "0x28 = 0x%x !!\n", u4tmp));
1461 for (i = 0; i < RF_CHNL_NUM_5G; i++) {
1462 if (channel == rf_chnl_5g[i] && channel <= 140)
1463 index = 0;
1464 }
1465 for (i = 0; i < RF_CHNL_NUM_5G_40M; i++) {
1466 if (channel == rf_chnl_5g_40m[i] && channel <= 140)
1467 index = 1;
1468 }
1469 if (channel == 149 || channel == 155 || channel == 161)
1470 index = 2;
1471 else if (channel == 151 || channel == 153 || channel == 163
1472 || channel == 165)
1473 index = 3;
1474 else if (channel == 157 || channel == 159)
1475 index = 4;
1476
1477 if (rtlhal->macphymode == DUALMAC_DUALPHY
1478 && rtlhal->interfaceindex == 1) {
1479 need_pwr_down = rtl92d_phy_enable_anotherphy(hw, false);
1480 rtlhal->during_mac1init_radioa = true;
1481 /* asume no this case */
1482 if (need_pwr_down)
1483 _rtl92d_phy_enable_rf_env(hw, path,
1484 &u4regvalue);
1485 }
1486 for (i = 0; i < RF_REG_NUM_FOR_C_CUT_5G; i++) {
1487 if (i == 0 && (rtlhal->macphymode == DUALMAC_DUALPHY)) {
1488 rtl_set_rfreg(hw, (enum radio_path)path,
1489 rf_reg_for_c_cut_5g[i],
1490 BRFREGOFFSETMASK, 0xE439D);
1491 } else if (rf_reg_for_c_cut_5g[i] == RF_SYN_G4) {
1492 u4tmp2 = (rf_reg_pram_c_5g[index][i] &
1493 0x7FF) | (u4tmp << 11);
1494 if (channel == 36)
1495 u4tmp2 &= ~(BIT(7) | BIT(6));
1496 rtl_set_rfreg(hw, (enum radio_path)path,
1497 rf_reg_for_c_cut_5g[i],
1498 BRFREGOFFSETMASK, u4tmp2);
1499 } else {
1500 rtl_set_rfreg(hw, (enum radio_path)path,
1501 rf_reg_for_c_cut_5g[i],
1502 BRFREGOFFSETMASK,
1503 rf_reg_pram_c_5g[index][i]);
1504 }
1505 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
1506 ("offset 0x%x value 0x%x "
1507 "path %d index %d readback 0x%x\n",
1508 rf_reg_for_c_cut_5g[i],
1509 rf_reg_pram_c_5g[index][i], path,
1510 index, rtl_get_rfreg(hw, (enum radio_path)path,
1511 rf_reg_for_c_cut_5g[i], BRFREGOFFSETMASK)));
1512 }
1513 if (need_pwr_down)
1514 _rtl92d_phy_restore_rf_env(hw, path, &u4regvalue);
1515 if (rtlhal->during_mac1init_radioa)
1516 rtl92d_phy_powerdown_anotherphy(hw, false);
1517 if (channel < 149)
1518 value = 0x07;
1519 else if (channel >= 149)
1520 value = 0x02;
1521 if (channel >= 36 && channel <= 64)
1522 index = 0;
1523 else if (channel >= 100 && channel <= 140)
1524 index = 1;
1525 else
1526 index = 2;
1527 for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath;
1528 rfpath++) {
1529 if (rtlhal->macphymode == DUALMAC_DUALPHY &&
1530 rtlhal->interfaceindex == 1) /* MAC 1 5G */
1531 internal_pa = rtlpriv->efuse.internal_pa_5g[1];
1532 else
1533 internal_pa =
1534 rtlpriv->efuse.internal_pa_5g[rfpath];
1535 if (internal_pa) {
1536 for (i = 0;
1537 i < RF_REG_NUM_FOR_C_CUT_5G_INTERNALPA;
1538 i++) {
1539 rtl_set_rfreg(hw, rfpath,
1540 rf_for_c_cut_5g_internal_pa[i],
1541 BRFREGOFFSETMASK,
1542 rf_pram_c_5g_int_pa[index][i]);
1543 RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD,
1544 ("offset 0x%x value 0x%x "
1545 "path %d index %d\n",
1546 rf_for_c_cut_5g_internal_pa[i],
1547 rf_pram_c_5g_int_pa[index][i],
1548 rfpath, index));
1549 }
1550 } else {
1551 rtl_set_rfreg(hw, (enum radio_path)rfpath, 0x0B,
1552 mask, value);
1553 }
1554 }
1555 } else if (rtlhal->current_bandtype == BAND_ON_2_4G) {
1556 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, ("====>2.4G\n"));
1557 u4tmp = curveindex_2g[channel - 1];
1558 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("ver 3 set RF-B, 2G, "
1559 "0x28 = 0x%x !!\n", u4tmp));
1560 if (channel == 1 || channel == 2 || channel == 4 || channel == 9
1561 || channel == 10 || channel == 11 || channel == 12)
1562 index = 0;
1563 else if (channel == 3 || channel == 13 || channel == 14)
1564 index = 1;
1565 else if (channel >= 5 && channel <= 8)
1566 index = 2;
1567 if (rtlhal->macphymode == DUALMAC_DUALPHY) {
1568 path = RF90_PATH_A;
1569 if (rtlhal->interfaceindex == 0) {
1570 need_pwr_down =
1571 rtl92d_phy_enable_anotherphy(hw, true);
1572 rtlhal->during_mac0init_radiob = true;
1573
1574 if (need_pwr_down)
1575 _rtl92d_phy_enable_rf_env(hw, path,
1576 &u4regvalue);
1577 }
1578 }
1579 for (i = 0; i < RF_REG_NUM_FOR_C_CUT_2G; i++) {
1580 if (rf_reg_for_c_cut_2g[i] == RF_SYN_G7)
1581 rtl_set_rfreg(hw, (enum radio_path)path,
1582 rf_reg_for_c_cut_2g[i],
1583 BRFREGOFFSETMASK,
1584 (rf_reg_param_for_c_cut_2g[index][i] |
1585 BIT(17)));
1586 else
1587 rtl_set_rfreg(hw, (enum radio_path)path,
1588 rf_reg_for_c_cut_2g[i],
1589 BRFREGOFFSETMASK,
1590 rf_reg_param_for_c_cut_2g
1591 [index][i]);
1592 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
1593 ("offset 0x%x value 0x%x mak 0x%x path %d "
1594 "index %d readback 0x%x\n",
1595 rf_reg_for_c_cut_2g[i],
1596 rf_reg_param_for_c_cut_2g[index][i],
1597 rf_reg_mask_for_c_cut_2g[i], path, index,
1598 rtl_get_rfreg(hw, (enum radio_path)path,
1599 rf_reg_for_c_cut_2g[i],
1600 BRFREGOFFSETMASK)));
1601 }
1602 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1603 ("cosa ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n",
1604 rf_syn_g4_for_c_cut_2g | (u4tmp << 11)));
1605
1606 rtl_set_rfreg(hw, (enum radio_path)path, RF_SYN_G4,
1607 BRFREGOFFSETMASK,
1608 rf_syn_g4_for_c_cut_2g | (u4tmp << 11));
1609 if (need_pwr_down)
1610 _rtl92d_phy_restore_rf_env(hw, path, &u4regvalue);
1611 if (rtlhal->during_mac0init_radiob)
1612 rtl92d_phy_powerdown_anotherphy(hw, true);
1613 }
1614 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, ("<====\n"));
1615 }
1616
1617 u8 rtl92d_get_rightchnlplace_for_iqk(u8 chnl)
1618 {
1619 u8 channel_all[59] = {
1620 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
1621 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58,
1622 60, 62, 64, 100, 102, 104, 106, 108, 110, 112,
1623 114, 116, 118, 120, 122, 124, 126, 128, 130,
1624 132, 134, 136, 138, 140, 149, 151, 153, 155,
1625 157, 159, 161, 163, 165
1626 };
1627 u8 place = chnl;
1628
1629 if (chnl > 14) {
1630 for (place = 14; place < sizeof(channel_all); place++) {
1631 if (channel_all[place] == chnl)
1632 return place - 13;
1633 }
1634 }
1635
1636 return 0;
1637 }
1638
1639 #define MAX_TOLERANCE 5
1640 #define IQK_DELAY_TIME 1 /* ms */
1641 #define MAX_TOLERANCE_92D 3
1642
1643 /* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */
1644 static u8 _rtl92d_phy_patha_iqk(struct ieee80211_hw *hw, bool configpathb)
1645 {
1646 struct rtl_priv *rtlpriv = rtl_priv(hw);
1647 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1648 u32 regeac, rege94, rege9c, regea4;
1649 u8 result = 0;
1650
1651 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("Path A IQK!\n"));
1652 /* path-A IQK setting */
1653 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("Path-A IQK setting!\n"));
1654 if (rtlhal->interfaceindex == 0) {
1655 rtl_set_bbreg(hw, 0xe30, BMASKDWORD, 0x10008c1f);
1656 rtl_set_bbreg(hw, 0xe34, BMASKDWORD, 0x10008c1f);
1657 } else {
1658 rtl_set_bbreg(hw, 0xe30, BMASKDWORD, 0x10008c22);
1659 rtl_set_bbreg(hw, 0xe34, BMASKDWORD, 0x10008c22);
1660 }
1661 rtl_set_bbreg(hw, 0xe38, BMASKDWORD, 0x82140102);
1662 rtl_set_bbreg(hw, 0xe3c, BMASKDWORD, 0x28160206);
1663 /* path-B IQK setting */
1664 if (configpathb) {
1665 rtl_set_bbreg(hw, 0xe50, BMASKDWORD, 0x10008c22);
1666 rtl_set_bbreg(hw, 0xe54, BMASKDWORD, 0x10008c22);
1667 rtl_set_bbreg(hw, 0xe58, BMASKDWORD, 0x82140102);
1668 rtl_set_bbreg(hw, 0xe5c, BMASKDWORD, 0x28160206);
1669 }
1670 /* LO calibration setting */
1671 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("LO calibration setting!\n"));
1672 rtl_set_bbreg(hw, 0xe4c, BMASKDWORD, 0x00462911);
1673 /* One shot, path A LOK & IQK */
1674 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("One shot, path A LOK & IQK!\n"));
1675 rtl_set_bbreg(hw, 0xe48, BMASKDWORD, 0xf9000000);
1676 rtl_set_bbreg(hw, 0xe48, BMASKDWORD, 0xf8000000);
1677 /* delay x ms */
1678 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1679 ("Delay %d ms for One shot, path A LOK & IQK.\n",
1680 IQK_DELAY_TIME));
1681 mdelay(IQK_DELAY_TIME);
1682 /* Check failed */
1683 regeac = rtl_get_bbreg(hw, 0xeac, BMASKDWORD);
1684 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("0xeac = 0x%x\n", regeac));
1685 rege94 = rtl_get_bbreg(hw, 0xe94, BMASKDWORD);
1686 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("0xe94 = 0x%x\n", rege94));
1687 rege9c = rtl_get_bbreg(hw, 0xe9c, BMASKDWORD);
1688 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("0xe9c = 0x%x\n", rege9c));
1689 regea4 = rtl_get_bbreg(hw, 0xea4, BMASKDWORD);
1690 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("0xea4 = 0x%x\n", regea4));
1691 if (!(regeac & BIT(28)) && (((rege94 & 0x03FF0000) >> 16) != 0x142) &&
1692 (((rege9c & 0x03FF0000) >> 16) != 0x42))
1693 result |= 0x01;
1694 else /* if Tx not OK, ignore Rx */
1695 return result;
1696 /* if Tx is OK, check whether Rx is OK */
1697 if (!(regeac & BIT(27)) && (((regea4 & 0x03FF0000) >> 16) != 0x132) &&
1698 (((regeac & 0x03FF0000) >> 16) != 0x36))
1699 result |= 0x02;
1700 else
1701 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("Path A Rx IQK fail!!\n"));
1702 return result;
1703 }
1704
1705 /* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */
1706 static u8 _rtl92d_phy_patha_iqk_5g_normal(struct ieee80211_hw *hw,
1707 bool configpathb)
1708 {
1709 struct rtl_priv *rtlpriv = rtl_priv(hw);
1710 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1711 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1712 u32 regeac, rege94, rege9c, regea4;
1713 u8 result = 0;
1714 u8 i;
1715 u8 retrycount = 2;
1716 u32 TxOKBit = BIT(28), RxOKBit = BIT(27);
1717
1718 if (rtlhal->interfaceindex == 1) { /* PHY1 */
1719 TxOKBit = BIT(31);
1720 RxOKBit = BIT(30);
1721 }
1722 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("Path A IQK!\n"));
1723 /* path-A IQK setting */
1724 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("Path-A IQK setting!\n"));
1725 rtl_set_bbreg(hw, 0xe30, BMASKDWORD, 0x18008c1f);
1726 rtl_set_bbreg(hw, 0xe34, BMASKDWORD, 0x18008c1f);
1727 rtl_set_bbreg(hw, 0xe38, BMASKDWORD, 0x82140307);
1728 rtl_set_bbreg(hw, 0xe3c, BMASKDWORD, 0x68160960);
1729 /* path-B IQK setting */
1730 if (configpathb) {
1731 rtl_set_bbreg(hw, 0xe50, BMASKDWORD, 0x18008c2f);
1732 rtl_set_bbreg(hw, 0xe54, BMASKDWORD, 0x18008c2f);
1733 rtl_set_bbreg(hw, 0xe58, BMASKDWORD, 0x82110000);
1734 rtl_set_bbreg(hw, 0xe5c, BMASKDWORD, 0x68110000);
1735 }
1736 /* LO calibration setting */
1737 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("LO calibration setting!\n"));
1738 rtl_set_bbreg(hw, 0xe4c, BMASKDWORD, 0x00462911);
1739 /* path-A PA on */
1740 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, BMASKDWORD, 0x07000f60);
1741 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, BMASKDWORD, 0x66e60e30);
1742 for (i = 0; i < retrycount; i++) {
1743 /* One shot, path A LOK & IQK */
1744 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1745 ("One shot, path A LOK & IQK!\n"));
1746 rtl_set_bbreg(hw, 0xe48, BMASKDWORD, 0xf9000000);
1747 rtl_set_bbreg(hw, 0xe48, BMASKDWORD, 0xf8000000);
1748 /* delay x ms */
1749 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1750 ("Delay %d ms for One shot, path A LOK & IQK.\n",
1751 IQK_DELAY_TIME));
1752 mdelay(IQK_DELAY_TIME * 10);
1753 /* Check failed */
1754 regeac = rtl_get_bbreg(hw, 0xeac, BMASKDWORD);
1755 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("0xeac = 0x%x\n", regeac));
1756 rege94 = rtl_get_bbreg(hw, 0xe94, BMASKDWORD);
1757 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("0xe94 = 0x%x\n", rege94));
1758 rege9c = rtl_get_bbreg(hw, 0xe9c, BMASKDWORD);
1759 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("0xe9c = 0x%x\n", rege9c));
1760 regea4 = rtl_get_bbreg(hw, 0xea4, BMASKDWORD);
1761 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("0xea4 = 0x%x\n", regea4));
1762 if (!(regeac & TxOKBit) &&
1763 (((rege94 & 0x03FF0000) >> 16) != 0x142)) {
1764 result |= 0x01;
1765 } else { /* if Tx not OK, ignore Rx */
1766 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1767 ("Path A Tx IQK fail!!\n"));
1768 continue;
1769 }
1770
1771 /* if Tx is OK, check whether Rx is OK */
1772 if (!(regeac & RxOKBit) &&
1773 (((regea4 & 0x03FF0000) >> 16) != 0x132)) {
1774 result |= 0x02;
1775 break;
1776 } else {
1777 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1778 ("Path A Rx IQK fail!!\n"));
1779 }
1780 }
1781 /* path A PA off */
1782 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, BMASKDWORD,
1783 rtlphy->iqk_bb_backup[0]);
1784 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, BMASKDWORD,
1785 rtlphy->iqk_bb_backup[1]);
1786 return result;
1787 }
1788
1789 /* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */
1790 static u8 _rtl92d_phy_pathb_iqk(struct ieee80211_hw *hw)
1791 {
1792 struct rtl_priv *rtlpriv = rtl_priv(hw);
1793 u32 regeac, regeb4, regebc, regec4, regecc;
1794 u8 result = 0;
1795
1796 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("Path B IQK!\n"));
1797 /* One shot, path B LOK & IQK */
1798 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("One shot, path A LOK & IQK!\n"));
1799 rtl_set_bbreg(hw, 0xe60, BMASKDWORD, 0x00000002);
1800 rtl_set_bbreg(hw, 0xe60, BMASKDWORD, 0x00000000);
1801 /* delay x ms */
1802 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1803 ("Delay %d ms for One shot, path B LOK & IQK.\n",
1804 IQK_DELAY_TIME));
1805 mdelay(IQK_DELAY_TIME);
1806 /* Check failed */
1807 regeac = rtl_get_bbreg(hw, 0xeac, BMASKDWORD);
1808 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("0xeac = 0x%x\n", regeac));
1809 regeb4 = rtl_get_bbreg(hw, 0xeb4, BMASKDWORD);
1810 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("0xeb4 = 0x%x\n", regeb4));
1811 regebc = rtl_get_bbreg(hw, 0xebc, BMASKDWORD);
1812 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("0xebc = 0x%x\n", regebc));
1813 regec4 = rtl_get_bbreg(hw, 0xec4, BMASKDWORD);
1814 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("0xec4 = 0x%x\n", regec4));
1815 regecc = rtl_get_bbreg(hw, 0xecc, BMASKDWORD);
1816 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("0xecc = 0x%x\n", regecc));
1817 if (!(regeac & BIT(31)) && (((regeb4 & 0x03FF0000) >> 16) != 0x142) &&
1818 (((regebc & 0x03FF0000) >> 16) != 0x42))
1819 result |= 0x01;
1820 else
1821 return result;
1822 if (!(regeac & BIT(30)) && (((regec4 & 0x03FF0000) >> 16) != 0x132) &&
1823 (((regecc & 0x03FF0000) >> 16) != 0x36))
1824 result |= 0x02;
1825 else
1826 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("Path B Rx IQK fail!!\n"));
1827 return result;
1828 }
1829
1830 /* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */
1831 static u8 _rtl92d_phy_pathb_iqk_5g_normal(struct ieee80211_hw *hw)
1832 {
1833 struct rtl_priv *rtlpriv = rtl_priv(hw);
1834 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1835 u32 regeac, regeb4, regebc, regec4, regecc;
1836 u8 result = 0;
1837 u8 i;
1838 u8 retrycount = 2;
1839
1840 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("Path B IQK!\n"));
1841 /* path-A IQK setting */
1842 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("Path-A IQK setting!\n"));
1843 rtl_set_bbreg(hw, 0xe30, BMASKDWORD, 0x18008c1f);
1844 rtl_set_bbreg(hw, 0xe34, BMASKDWORD, 0x18008c1f);
1845 rtl_set_bbreg(hw, 0xe38, BMASKDWORD, 0x82110000);
1846 rtl_set_bbreg(hw, 0xe3c, BMASKDWORD, 0x68110000);
1847
1848 /* path-B IQK setting */
1849 rtl_set_bbreg(hw, 0xe50, BMASKDWORD, 0x18008c2f);
1850 rtl_set_bbreg(hw, 0xe54, BMASKDWORD, 0x18008c2f);
1851 rtl_set_bbreg(hw, 0xe58, BMASKDWORD, 0x82140307);
1852 rtl_set_bbreg(hw, 0xe5c, BMASKDWORD, 0x68160960);
1853
1854 /* LO calibration setting */
1855 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("LO calibration setting!\n"));
1856 rtl_set_bbreg(hw, 0xe4c, BMASKDWORD, 0x00462911);
1857
1858 /* path-B PA on */
1859 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, BMASKDWORD, 0x0f600700);
1860 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, BMASKDWORD, 0x061f0d30);
1861
1862 for (i = 0; i < retrycount; i++) {
1863 /* One shot, path B LOK & IQK */
1864 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1865 ("One shot, path A LOK & IQK!\n"));
1866 rtl_set_bbreg(hw, 0xe48, BMASKDWORD, 0xfa000000);
1867 rtl_set_bbreg(hw, 0xe48, BMASKDWORD, 0xf8000000);
1868
1869 /* delay x ms */
1870 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1871 ("Delay %d ms for One shot, path B LOK & IQK.\n", 10));
1872 mdelay(IQK_DELAY_TIME * 10);
1873
1874 /* Check failed */
1875 regeac = rtl_get_bbreg(hw, 0xeac, BMASKDWORD);
1876 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("0xeac = 0x%x\n", regeac));
1877 regeb4 = rtl_get_bbreg(hw, 0xeb4, BMASKDWORD);
1878 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("0xeb4 = 0x%x\n", regeb4));
1879 regebc = rtl_get_bbreg(hw, 0xebc, BMASKDWORD);
1880 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("0xebc = 0x%x\n", regebc));
1881 regec4 = rtl_get_bbreg(hw, 0xec4, BMASKDWORD);
1882 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("0xec4 = 0x%x\n", regec4));
1883 regecc = rtl_get_bbreg(hw, 0xecc, BMASKDWORD);
1884 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("0xecc = 0x%x\n", regecc));
1885 if (!(regeac & BIT(31)) &&
1886 (((regeb4 & 0x03FF0000) >> 16) != 0x142))
1887 result |= 0x01;
1888 else
1889 continue;
1890 if (!(regeac & BIT(30)) &&
1891 (((regec4 & 0x03FF0000) >> 16) != 0x132)) {
1892 result |= 0x02;
1893 break;
1894 } else {
1895 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1896 ("Path B Rx IQK fail!!\n"));
1897 }
1898 }
1899
1900 /* path B PA off */
1901 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, BMASKDWORD,
1902 rtlphy->iqk_bb_backup[0]);
1903 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, BMASKDWORD,
1904 rtlphy->iqk_bb_backup[2]);
1905 return result;
1906 }
1907
1908 static void _rtl92d_phy_save_adda_registers(struct ieee80211_hw *hw,
1909 u32 *adda_reg, u32 *adda_backup,
1910 u32 regnum)
1911 {
1912 struct rtl_priv *rtlpriv = rtl_priv(hw);
1913 u32 i;
1914
1915 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("Save ADDA parameters.\n"));
1916 for (i = 0; i < regnum; i++)
1917 adda_backup[i] = rtl_get_bbreg(hw, adda_reg[i], BMASKDWORD);
1918 }
1919
1920 static void _rtl92d_phy_save_mac_registers(struct ieee80211_hw *hw,
1921 u32 *macreg, u32 *macbackup)
1922 {
1923 struct rtl_priv *rtlpriv = rtl_priv(hw);
1924 u32 i;
1925
1926 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("Save MAC parameters.\n"));
1927 for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
1928 macbackup[i] = rtl_read_byte(rtlpriv, macreg[i]);
1929 macbackup[i] = rtl_read_dword(rtlpriv, macreg[i]);
1930 }
1931
1932 static void _rtl92d_phy_reload_adda_registers(struct ieee80211_hw *hw,
1933 u32 *adda_reg, u32 *adda_backup,
1934 u32 regnum)
1935 {
1936 struct rtl_priv *rtlpriv = rtl_priv(hw);
1937 u32 i;
1938
1939 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1940 ("Reload ADDA power saving parameters !\n"));
1941 for (i = 0; i < regnum; i++)
1942 rtl_set_bbreg(hw, adda_reg[i], BMASKDWORD, adda_backup[i]);
1943 }
1944
1945 static void _rtl92d_phy_reload_mac_registers(struct ieee80211_hw *hw,
1946 u32 *macreg, u32 *macbackup)
1947 {
1948 struct rtl_priv *rtlpriv = rtl_priv(hw);
1949 u32 i;
1950
1951 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("Reload MAC parameters !\n"));
1952 for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
1953 rtl_write_byte(rtlpriv, macreg[i], (u8) macbackup[i]);
1954 rtl_write_byte(rtlpriv, macreg[i], macbackup[i]);
1955 }
1956
1957 static void _rtl92d_phy_path_adda_on(struct ieee80211_hw *hw,
1958 u32 *adda_reg, bool patha_on, bool is2t)
1959 {
1960 struct rtl_priv *rtlpriv = rtl_priv(hw);
1961 u32 pathon;
1962 u32 i;
1963
1964 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("ADDA ON.\n"));
1965 pathon = patha_on ? 0x04db25a4 : 0x0b1b25a4;
1966 if (patha_on)
1967 pathon = rtlpriv->rtlhal.interfaceindex == 0 ?
1968 0x04db25a4 : 0x0b1b25a4;
1969 for (i = 0; i < IQK_ADDA_REG_NUM; i++)
1970 rtl_set_bbreg(hw, adda_reg[i], BMASKDWORD, pathon);
1971 }
1972
1973 static void _rtl92d_phy_mac_setting_calibration(struct ieee80211_hw *hw,
1974 u32 *macreg, u32 *macbackup)
1975 {
1976 struct rtl_priv *rtlpriv = rtl_priv(hw);
1977 u32 i;
1978
1979 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("MAC settings for Calibration.\n"));
1980 rtl_write_byte(rtlpriv, macreg[0], 0x3F);
1981
1982 for (i = 1; i < (IQK_MAC_REG_NUM - 1); i++)
1983 rtl_write_byte(rtlpriv, macreg[i], (u8)(macbackup[i] &
1984 (~BIT(3))));
1985 rtl_write_byte(rtlpriv, macreg[i], (u8) (macbackup[i] & (~BIT(5))));
1986 }
1987
1988 static void _rtl92d_phy_patha_standby(struct ieee80211_hw *hw)
1989 {
1990 struct rtl_priv *rtlpriv = rtl_priv(hw);
1991 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("Path-A standby mode!\n"));
1992
1993 rtl_set_bbreg(hw, 0xe28, BMASKDWORD, 0x0);
1994 rtl_set_bbreg(hw, RFPGA0_XA_LSSIPARAMETER, BMASKDWORD, 0x00010000);
1995 rtl_set_bbreg(hw, 0xe28, BMASKDWORD, 0x80800000);
1996 }
1997
1998 static void _rtl92d_phy_pimode_switch(struct ieee80211_hw *hw, bool pi_mode)
1999 {
2000 struct rtl_priv *rtlpriv = rtl_priv(hw);
2001 u32 mode;
2002
2003 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2004 ("BB Switch to %s mode!\n", (pi_mode ? "PI" : "SI")));
2005 mode = pi_mode ? 0x01000100 : 0x01000000;
2006 rtl_set_bbreg(hw, 0x820, BMASKDWORD, mode);
2007 rtl_set_bbreg(hw, 0x828, BMASKDWORD, mode);
2008 }
2009
2010 static void _rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw, long result[][8],
2011 u8 t, bool is2t)
2012 {
2013 struct rtl_priv *rtlpriv = rtl_priv(hw);
2014 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2015 u32 i;
2016 u8 patha_ok, pathb_ok;
2017 static u32 adda_reg[IQK_ADDA_REG_NUM] = {
2018 RFPGA0_XCD_SWITCHCONTROL, 0xe6c, 0xe70, 0xe74,
2019 0xe78, 0xe7c, 0xe80, 0xe84,
2020 0xe88, 0xe8c, 0xed0, 0xed4,
2021 0xed8, 0xedc, 0xee0, 0xeec
2022 };
2023 static u32 iqk_mac_reg[IQK_MAC_REG_NUM] = {
2024 0x522, 0x550, 0x551, 0x040
2025 };
2026 static u32 iqk_bb_reg[IQK_BB_REG_NUM] = {
2027 RFPGA0_XAB_RFINTERFACESW, RFPGA0_XA_RFINTERFACEOE,
2028 RFPGA0_XB_RFINTERFACEOE, ROFDM0_TRMUXPAR,
2029 RFPGA0_XCD_RFINTERFACESW, ROFDM0_TRXPATHENABLE,
2030 RFPGA0_RFMOD, RFPGA0_ANALOGPARAMETER4,
2031 ROFDM0_XAAGCCORE1, ROFDM0_XBAGCCORE1
2032 };
2033 const u32 retrycount = 2;
2034 u32 bbvalue;
2035
2036 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("IQK for 2.4G :Start!!!\n"));
2037 if (t == 0) {
2038 bbvalue = rtl_get_bbreg(hw, RFPGA0_RFMOD, BMASKDWORD);
2039 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("==>0x%08x\n", bbvalue));
2040 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("IQ Calibration for %s\n",
2041 (is2t ? "2T2R" : "1T1R")));
2042
2043 /* Save ADDA parameters, turn Path A ADDA on */
2044 _rtl92d_phy_save_adda_registers(hw, adda_reg,
2045 rtlphy->adda_backup, IQK_ADDA_REG_NUM);
2046 _rtl92d_phy_save_mac_registers(hw, iqk_mac_reg,
2047 rtlphy->iqk_mac_backup);
2048 _rtl92d_phy_save_adda_registers(hw, iqk_bb_reg,
2049 rtlphy->iqk_bb_backup, IQK_BB_REG_NUM);
2050 }
2051 _rtl92d_phy_path_adda_on(hw, adda_reg, true, is2t);
2052 if (t == 0)
2053 rtlphy->rfpi_enable = (u8) rtl_get_bbreg(hw,
2054 RFPGA0_XA_HSSIPARAMETER1, BIT(8));
2055
2056 /* Switch BB to PI mode to do IQ Calibration. */
2057 if (!rtlphy->rfpi_enable)
2058 _rtl92d_phy_pimode_switch(hw, true);
2059
2060 rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(24), 0x00);
2061 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, BMASKDWORD, 0x03a05600);
2062 rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, BMASKDWORD, 0x000800e4);
2063 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, BMASKDWORD, 0x22204000);
2064 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xf00000, 0x0f);
2065 if (is2t) {
2066 rtl_set_bbreg(hw, RFPGA0_XA_LSSIPARAMETER, BMASKDWORD,
2067 0x00010000);
2068 rtl_set_bbreg(hw, RFPGA0_XB_LSSIPARAMETER, BMASKDWORD,
2069 0x00010000);
2070 }
2071 /* MAC settings */
2072 _rtl92d_phy_mac_setting_calibration(hw, iqk_mac_reg,
2073 rtlphy->iqk_mac_backup);
2074 /* Page B init */
2075 rtl_set_bbreg(hw, 0xb68, BMASKDWORD, 0x0f600000);
2076 if (is2t)
2077 rtl_set_bbreg(hw, 0xb6c, BMASKDWORD, 0x0f600000);
2078 /* IQ calibration setting */
2079 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("IQK setting!\n"));
2080 rtl_set_bbreg(hw, 0xe28, BMASKDWORD, 0x80800000);
2081 rtl_set_bbreg(hw, 0xe40, BMASKDWORD, 0x01007c00);
2082 rtl_set_bbreg(hw, 0xe44, BMASKDWORD, 0x01004800);
2083 for (i = 0; i < retrycount; i++) {
2084 patha_ok = _rtl92d_phy_patha_iqk(hw, is2t);
2085 if (patha_ok == 0x03) {
2086 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2087 ("Path A IQK Success!!\n"));
2088 result[t][0] = (rtl_get_bbreg(hw, 0xe94, BMASKDWORD) &
2089 0x3FF0000) >> 16;
2090 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, BMASKDWORD) &
2091 0x3FF0000) >> 16;
2092 result[t][2] = (rtl_get_bbreg(hw, 0xea4, BMASKDWORD) &
2093 0x3FF0000) >> 16;
2094 result[t][3] = (rtl_get_bbreg(hw, 0xeac, BMASKDWORD) &
2095 0x3FF0000) >> 16;
2096 break;
2097 } else if (i == (retrycount - 1) && patha_ok == 0x01) {
2098 /* Tx IQK OK */
2099 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2100 ("Path A IQK Only Tx Success!!\n"));
2101
2102 result[t][0] = (rtl_get_bbreg(hw, 0xe94, BMASKDWORD) &
2103 0x3FF0000) >> 16;
2104 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, BMASKDWORD) &
2105 0x3FF0000) >> 16;
2106 }
2107 }
2108 if (0x00 == patha_ok)
2109 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("Path A IQK failed!!\n"));
2110 if (is2t) {
2111 _rtl92d_phy_patha_standby(hw);
2112 /* Turn Path B ADDA on */
2113 _rtl92d_phy_path_adda_on(hw, adda_reg, false, is2t);
2114 for (i = 0; i < retrycount; i++) {
2115 pathb_ok = _rtl92d_phy_pathb_iqk(hw);
2116 if (pathb_ok == 0x03) {
2117 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2118 ("Path B IQK Success!!\n"));
2119 result[t][4] = (rtl_get_bbreg(hw, 0xeb4,
2120 BMASKDWORD) & 0x3FF0000) >> 16;
2121 result[t][5] = (rtl_get_bbreg(hw, 0xebc,
2122 BMASKDWORD) & 0x3FF0000) >> 16;
2123 result[t][6] = (rtl_get_bbreg(hw, 0xec4,
2124 BMASKDWORD) & 0x3FF0000) >> 16;
2125 result[t][7] = (rtl_get_bbreg(hw, 0xecc,
2126 BMASKDWORD) & 0x3FF0000) >> 16;
2127 break;
2128 } else if (i == (retrycount - 1) && pathb_ok == 0x01) {
2129 /* Tx IQK OK */
2130 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2131 ("Path B Only Tx IQK Success!!\n"));
2132 result[t][4] = (rtl_get_bbreg(hw, 0xeb4,
2133 BMASKDWORD) & 0x3FF0000) >> 16;
2134 result[t][5] = (rtl_get_bbreg(hw, 0xebc,
2135 BMASKDWORD) & 0x3FF0000) >> 16;
2136 }
2137 }
2138 if (0x00 == pathb_ok)
2139 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2140 ("Path B IQK failed!!\n"));
2141 }
2142
2143 /* Back to BB mode, load original value */
2144 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2145 ("IQK:Back to BB mode, load original value!\n"));
2146
2147 rtl_set_bbreg(hw, 0xe28, BMASKDWORD, 0);
2148 if (t != 0) {
2149 /* Switch back BB to SI mode after finish IQ Calibration. */
2150 if (!rtlphy->rfpi_enable)
2151 _rtl92d_phy_pimode_switch(hw, false);
2152 /* Reload ADDA power saving parameters */
2153 _rtl92d_phy_reload_adda_registers(hw, adda_reg,
2154 rtlphy->adda_backup, IQK_ADDA_REG_NUM);
2155 /* Reload MAC parameters */
2156 _rtl92d_phy_reload_mac_registers(hw, iqk_mac_reg,
2157 rtlphy->iqk_mac_backup);
2158 if (is2t)
2159 _rtl92d_phy_reload_adda_registers(hw, iqk_bb_reg,
2160 rtlphy->iqk_bb_backup,
2161 IQK_BB_REG_NUM);
2162 else
2163 _rtl92d_phy_reload_adda_registers(hw, iqk_bb_reg,
2164 rtlphy->iqk_bb_backup,
2165 IQK_BB_REG_NUM - 1);
2166 /* load 0xe30 IQC default value */
2167 rtl_set_bbreg(hw, 0xe30, BMASKDWORD, 0x01008c00);
2168 rtl_set_bbreg(hw, 0xe34, BMASKDWORD, 0x01008c00);
2169 }
2170 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("<==\n"));
2171 }
2172
2173 static void _rtl92d_phy_iq_calibrate_5g_normal(struct ieee80211_hw *hw,
2174 long result[][8], u8 t)
2175 {
2176 struct rtl_priv *rtlpriv = rtl_priv(hw);
2177 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2178 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2179 u8 patha_ok, pathb_ok;
2180 static u32 adda_reg[IQK_ADDA_REG_NUM] = {
2181 RFPGA0_XCD_SWITCHCONTROL, 0xe6c, 0xe70, 0xe74,
2182 0xe78, 0xe7c, 0xe80, 0xe84,
2183 0xe88, 0xe8c, 0xed0, 0xed4,
2184 0xed8, 0xedc, 0xee0, 0xeec
2185 };
2186 static u32 iqk_mac_reg[IQK_MAC_REG_NUM] = {
2187 0x522, 0x550, 0x551, 0x040
2188 };
2189 static u32 iqk_bb_reg[IQK_BB_REG_NUM] = {
2190 RFPGA0_XAB_RFINTERFACESW, RFPGA0_XA_RFINTERFACEOE,
2191 RFPGA0_XB_RFINTERFACEOE, ROFDM0_TRMUXPAR,
2192 RFPGA0_XCD_RFINTERFACESW, ROFDM0_TRXPATHENABLE,
2193 RFPGA0_RFMOD, RFPGA0_ANALOGPARAMETER4,
2194 ROFDM0_XAAGCCORE1, ROFDM0_XBAGCCORE1
2195 };
2196 u32 bbvalue;
2197 bool is2t = IS_92D_SINGLEPHY(rtlhal->version);
2198
2199 /* Note: IQ calibration must be performed after loading
2200 * PHY_REG.txt , and radio_a, radio_b.txt */
2201
2202 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("IQK for 5G NORMAL:Start!!!\n"));
2203 mdelay(IQK_DELAY_TIME * 20);
2204 if (t == 0) {
2205 bbvalue = rtl_get_bbreg(hw, RFPGA0_RFMOD, BMASKDWORD);
2206 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("==>0x%08x\n", bbvalue));
2207 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("IQ Calibration for %s\n",
2208 (is2t ? "2T2R" : "1T1R")));
2209 /* Save ADDA parameters, turn Path A ADDA on */
2210 _rtl92d_phy_save_adda_registers(hw, adda_reg,
2211 rtlphy->adda_backup,
2212 IQK_ADDA_REG_NUM);
2213 _rtl92d_phy_save_mac_registers(hw, iqk_mac_reg,
2214 rtlphy->iqk_mac_backup);
2215 if (is2t)
2216 _rtl92d_phy_save_adda_registers(hw, iqk_bb_reg,
2217 rtlphy->iqk_bb_backup,
2218 IQK_BB_REG_NUM);
2219 else
2220 _rtl92d_phy_save_adda_registers(hw, iqk_bb_reg,
2221 rtlphy->iqk_bb_backup,
2222 IQK_BB_REG_NUM - 1);
2223 }
2224 _rtl92d_phy_path_adda_on(hw, adda_reg, true, is2t);
2225 /* MAC settings */
2226 _rtl92d_phy_mac_setting_calibration(hw, iqk_mac_reg,
2227 rtlphy->iqk_mac_backup);
2228 if (t == 0)
2229 rtlphy->rfpi_enable = (u8) rtl_get_bbreg(hw,
2230 RFPGA0_XA_HSSIPARAMETER1, BIT(8));
2231 /* Switch BB to PI mode to do IQ Calibration. */
2232 if (!rtlphy->rfpi_enable)
2233 _rtl92d_phy_pimode_switch(hw, true);
2234 rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(24), 0x00);
2235 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, BMASKDWORD, 0x03a05600);
2236 rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, BMASKDWORD, 0x000800e4);
2237 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, BMASKDWORD, 0x22208000);
2238 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xf00000, 0x0f);
2239
2240 /* Page B init */
2241 rtl_set_bbreg(hw, 0xb68, BMASKDWORD, 0x0f600000);
2242 if (is2t)
2243 rtl_set_bbreg(hw, 0xb6c, BMASKDWORD, 0x0f600000);
2244 /* IQ calibration setting */
2245 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("IQK setting!\n"));
2246 rtl_set_bbreg(hw, 0xe28, BMASKDWORD, 0x80800000);
2247 rtl_set_bbreg(hw, 0xe40, BMASKDWORD, 0x10007c00);
2248 rtl_set_bbreg(hw, 0xe44, BMASKDWORD, 0x01004800);
2249 patha_ok = _rtl92d_phy_patha_iqk_5g_normal(hw, is2t);
2250 if (patha_ok == 0x03) {
2251 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("Path A IQK Success!!\n"));
2252 result[t][0] = (rtl_get_bbreg(hw, 0xe94, BMASKDWORD) &
2253 0x3FF0000) >> 16;
2254 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, BMASKDWORD) &
2255 0x3FF0000) >> 16;
2256 result[t][2] = (rtl_get_bbreg(hw, 0xea4, BMASKDWORD) &
2257 0x3FF0000) >> 16;
2258 result[t][3] = (rtl_get_bbreg(hw, 0xeac, BMASKDWORD) &
2259 0x3FF0000) >> 16;
2260 } else if (patha_ok == 0x01) { /* Tx IQK OK */
2261 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2262 ("Path A IQK Only Tx Success!!\n"));
2263
2264 result[t][0] = (rtl_get_bbreg(hw, 0xe94, BMASKDWORD) &
2265 0x3FF0000) >> 16;
2266 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, BMASKDWORD) &
2267 0x3FF0000) >> 16;
2268 } else {
2269 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("Path A IQK Fail!!\n"));
2270 }
2271 if (is2t) {
2272 /* _rtl92d_phy_patha_standby(hw); */
2273 /* Turn Path B ADDA on */
2274 _rtl92d_phy_path_adda_on(hw, adda_reg, false, is2t);
2275 pathb_ok = _rtl92d_phy_pathb_iqk_5g_normal(hw);
2276 if (pathb_ok == 0x03) {
2277 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2278 ("Path B IQK Success!!\n"));
2279 result[t][4] = (rtl_get_bbreg(hw, 0xeb4, BMASKDWORD) &
2280 0x3FF0000) >> 16;
2281 result[t][5] = (rtl_get_bbreg(hw, 0xebc, BMASKDWORD) &
2282 0x3FF0000) >> 16;
2283 result[t][6] = (rtl_get_bbreg(hw, 0xec4, BMASKDWORD) &
2284 0x3FF0000) >> 16;
2285 result[t][7] = (rtl_get_bbreg(hw, 0xecc, BMASKDWORD) &
2286 0x3FF0000) >> 16;
2287 } else if (pathb_ok == 0x01) { /* Tx IQK OK */
2288 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2289 ("Path B Only Tx IQK Success!!\n"));
2290 result[t][4] = (rtl_get_bbreg(hw, 0xeb4, BMASKDWORD) &
2291 0x3FF0000) >> 16;
2292 result[t][5] = (rtl_get_bbreg(hw, 0xebc, BMASKDWORD) &
2293 0x3FF0000) >> 16;
2294 } else {
2295 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2296 ("Path B IQK failed!!\n"));
2297 }
2298 }
2299
2300 /* Back to BB mode, load original value */
2301 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2302 ("IQK:Back to BB mode, load original value!\n"));
2303 rtl_set_bbreg(hw, 0xe28, BMASKDWORD, 0);
2304 if (t != 0) {
2305 if (is2t)
2306 _rtl92d_phy_reload_adda_registers(hw, iqk_bb_reg,
2307 rtlphy->iqk_bb_backup,
2308 IQK_BB_REG_NUM);
2309 else
2310 _rtl92d_phy_reload_adda_registers(hw, iqk_bb_reg,
2311 rtlphy->iqk_bb_backup,
2312 IQK_BB_REG_NUM - 1);
2313 /* Reload MAC parameters */
2314 _rtl92d_phy_reload_mac_registers(hw, iqk_mac_reg,
2315 rtlphy->iqk_mac_backup);
2316 /* Switch back BB to SI mode after finish IQ Calibration. */
2317 if (!rtlphy->rfpi_enable)
2318 _rtl92d_phy_pimode_switch(hw, false);
2319 /* Reload ADDA power saving parameters */
2320 _rtl92d_phy_reload_adda_registers(hw, adda_reg,
2321 rtlphy->adda_backup,
2322 IQK_ADDA_REG_NUM);
2323 }
2324 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("<==\n"));
2325 }
2326
2327 static bool _rtl92d_phy_simularity_compare(struct ieee80211_hw *hw,
2328 long result[][8], u8 c1, u8 c2)
2329 {
2330 struct rtl_priv *rtlpriv = rtl_priv(hw);
2331 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2332 u32 i, j, diff, sim_bitmap, bound;
2333 u8 final_candidate[2] = {0xFF, 0xFF}; /* for path A and path B */
2334 bool bresult = true;
2335 bool is2t = IS_92D_SINGLEPHY(rtlhal->version);
2336
2337 if (is2t)
2338 bound = 8;
2339 else
2340 bound = 4;
2341 sim_bitmap = 0;
2342 for (i = 0; i < bound; i++) {
2343 diff = (result[c1][i] > result[c2][i]) ? (result[c1][i] -
2344 result[c2][i]) : (result[c2][i] - result[c1][i]);
2345 if (diff > MAX_TOLERANCE_92D) {
2346 if ((i == 2 || i == 6) && !sim_bitmap) {
2347 if (result[c1][i] + result[c1][i + 1] == 0)
2348 final_candidate[(i / 4)] = c2;
2349 else if (result[c2][i] + result[c2][i + 1] == 0)
2350 final_candidate[(i / 4)] = c1;
2351 else
2352 sim_bitmap = sim_bitmap | (1 << i);
2353 } else {
2354 sim_bitmap = sim_bitmap | (1 << i);
2355 }
2356 }
2357 }
2358 if (sim_bitmap == 0) {
2359 for (i = 0; i < (bound / 4); i++) {
2360 if (final_candidate[i] != 0xFF) {
2361 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
2362 result[3][j] =
2363 result[final_candidate[i]][j];
2364 bresult = false;
2365 }
2366 }
2367 return bresult;
2368 }
2369 if (!(sim_bitmap & 0x0F)) { /* path A OK */
2370 for (i = 0; i < 4; i++)
2371 result[3][i] = result[c1][i];
2372 } else if (!(sim_bitmap & 0x03)) { /* path A, Tx OK */
2373 for (i = 0; i < 2; i++)
2374 result[3][i] = result[c1][i];
2375 }
2376 if (!(sim_bitmap & 0xF0) && is2t) { /* path B OK */
2377 for (i = 4; i < 8; i++)
2378 result[3][i] = result[c1][i];
2379 } else if (!(sim_bitmap & 0x30)) { /* path B, Tx OK */
2380 for (i = 4; i < 6; i++)
2381 result[3][i] = result[c1][i];
2382 }
2383 return false;
2384 }
2385
2386 static void _rtl92d_phy_patha_fill_iqk_matrix(struct ieee80211_hw *hw,
2387 bool iqk_ok, long result[][8],
2388 u8 final_candidate, bool txonly)
2389 {
2390 struct rtl_priv *rtlpriv = rtl_priv(hw);
2391 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2392 u32 oldval_0, val_x, tx0_a, reg;
2393 long val_y, tx0_c;
2394 bool is2t = IS_92D_SINGLEPHY(rtlhal->version) ||
2395 rtlhal->macphymode == DUALMAC_DUALPHY;
2396
2397 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2398 ("Path A IQ Calibration %s !\n",
2399 (iqk_ok) ? "Success" : "Failed"));
2400 if (final_candidate == 0xFF) {
2401 return;
2402 } else if (iqk_ok) {
2403 oldval_0 = (rtl_get_bbreg(hw, ROFDM0_XATxIQIMBALANCE,
2404 BMASKDWORD) >> 22) & 0x3FF; /* OFDM0_D */
2405 val_x = result[final_candidate][0];
2406 if ((val_x & 0x00000200) != 0)
2407 val_x = val_x | 0xFFFFFC00;
2408 tx0_a = (val_x * oldval_0) >> 8;
2409 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("X = 0x%x, tx0_a = 0x%x,"
2410 " oldval_0 0x%x\n", val_x, tx0_a, oldval_0));
2411 rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, 0x3FF, tx0_a);
2412 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(24),
2413 ((val_x * oldval_0 >> 7) & 0x1));
2414 val_y = result[final_candidate][1];
2415 if ((val_y & 0x00000200) != 0)
2416 val_y = val_y | 0xFFFFFC00;
2417 /* path B IQK result + 3 */
2418 if (rtlhal->interfaceindex == 1 &&
2419 rtlhal->current_bandtype == BAND_ON_5G)
2420 val_y += 3;
2421 tx0_c = (val_y * oldval_0) >> 8;
2422 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("Y = 0x%lx, tx0_c = 0x%lx\n",
2423 val_y, tx0_c));
2424 rtl_set_bbreg(hw, ROFDM0_XCTxAFE, 0xF0000000,
2425 ((tx0_c & 0x3C0) >> 6));
2426 rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, 0x003F0000,
2427 (tx0_c & 0x3F));
2428 if (is2t)
2429 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(26),
2430 ((val_y * oldval_0 >> 7) & 0x1));
2431 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("0xC80 = 0x%x\n",
2432 rtl_get_bbreg(hw, ROFDM0_XATxIQIMBALANCE,
2433 BMASKDWORD)));
2434 if (txonly) {
2435 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("only Tx OK\n"));
2436 return;
2437 }
2438 reg = result[final_candidate][2];
2439 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0x3FF, reg);
2440 reg = result[final_candidate][3] & 0x3F;
2441 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0xFC00, reg);
2442 reg = (result[final_candidate][3] >> 6) & 0xF;
2443 rtl_set_bbreg(hw, 0xca0, 0xF0000000, reg);
2444 }
2445 }
2446
2447 static void _rtl92d_phy_pathb_fill_iqk_matrix(struct ieee80211_hw *hw,
2448 bool iqk_ok, long result[][8], u8 final_candidate, bool txonly)
2449 {
2450 struct rtl_priv *rtlpriv = rtl_priv(hw);
2451 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2452 u32 oldval_1, val_x, tx1_a, reg;
2453 long val_y, tx1_c;
2454
2455 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("Path B IQ Calibration %s !\n",
2456 (iqk_ok) ? "Success" : "Failed"));
2457 if (final_candidate == 0xFF) {
2458 return;
2459 } else if (iqk_ok) {
2460 oldval_1 = (rtl_get_bbreg(hw, ROFDM0_XBTxIQIMBALANCE,
2461 BMASKDWORD) >> 22) & 0x3FF;
2462 val_x = result[final_candidate][4];
2463 if ((val_x & 0x00000200) != 0)
2464 val_x = val_x | 0xFFFFFC00;
2465 tx1_a = (val_x * oldval_1) >> 8;
2466 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("X = 0x%x, tx1_a = 0x%x\n",
2467 val_x, tx1_a));
2468 rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, 0x3FF, tx1_a);
2469 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(28),
2470 ((val_x * oldval_1 >> 7) & 0x1));
2471 val_y = result[final_candidate][5];
2472 if ((val_y & 0x00000200) != 0)
2473 val_y = val_y | 0xFFFFFC00;
2474 if (rtlhal->current_bandtype == BAND_ON_5G)
2475 val_y += 3;
2476 tx1_c = (val_y * oldval_1) >> 8;
2477 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("Y = 0x%lx, tx1_c = 0x%lx\n",
2478 val_y, tx1_c));
2479 rtl_set_bbreg(hw, ROFDM0_XDTxAFE, 0xF0000000,
2480 ((tx1_c & 0x3C0) >> 6));
2481 rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, 0x003F0000,
2482 (tx1_c & 0x3F));
2483 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(30),
2484 ((val_y * oldval_1 >> 7) & 0x1));
2485 if (txonly)
2486 return;
2487 reg = result[final_candidate][6];
2488 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0x3FF, reg);
2489 reg = result[final_candidate][7] & 0x3F;
2490 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0xFC00, reg);
2491 reg = (result[final_candidate][7] >> 6) & 0xF;
2492 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0x0000F000, reg);
2493 }
2494 }
2495
2496 void rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw)
2497 {
2498 struct rtl_priv *rtlpriv = rtl_priv(hw);
2499 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2500 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2501 long result[4][8];
2502 u8 i, final_candidate, indexforchannel;
2503 bool patha_ok, pathb_ok;
2504 long rege94, rege9c, regea4, regeac, regeb4;
2505 long regebc, regec4, regecc, regtmp = 0;
2506 bool is12simular, is13simular, is23simular;
2507 unsigned long flag = 0;
2508
2509 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2510 ("IQK:Start!!!channel %d\n", rtlphy->current_channel));
2511 for (i = 0; i < 8; i++) {
2512 result[0][i] = 0;
2513 result[1][i] = 0;
2514 result[2][i] = 0;
2515 result[3][i] = 0;
2516 }
2517 final_candidate = 0xff;
2518 patha_ok = false;
2519 pathb_ok = false;
2520 is12simular = false;
2521 is23simular = false;
2522 is13simular = false;
2523 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2524 ("IQK !!!currentband %d\n", rtlhal->current_bandtype));
2525 rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag);
2526 for (i = 0; i < 3; i++) {
2527 if (rtlhal->current_bandtype == BAND_ON_5G) {
2528 _rtl92d_phy_iq_calibrate_5g_normal(hw, result, i);
2529 } else if (rtlhal->current_bandtype == BAND_ON_2_4G) {
2530 if (IS_92D_SINGLEPHY(rtlhal->version))
2531 _rtl92d_phy_iq_calibrate(hw, result, i, true);
2532 else
2533 _rtl92d_phy_iq_calibrate(hw, result, i, false);
2534 }
2535 if (i == 1) {
2536 is12simular = _rtl92d_phy_simularity_compare(hw, result,
2537 0, 1);
2538 if (is12simular) {
2539 final_candidate = 0;
2540 break;
2541 }
2542 }
2543 if (i == 2) {
2544 is13simular = _rtl92d_phy_simularity_compare(hw, result,
2545 0, 2);
2546 if (is13simular) {
2547 final_candidate = 0;
2548 break;
2549 }
2550 is23simular = _rtl92d_phy_simularity_compare(hw, result,
2551 1, 2);
2552 if (is23simular) {
2553 final_candidate = 1;
2554 } else {
2555 for (i = 0; i < 8; i++)
2556 regtmp += result[3][i];
2557
2558 if (regtmp != 0)
2559 final_candidate = 3;
2560 else
2561 final_candidate = 0xFF;
2562 }
2563 }
2564 }
2565 rtl92d_release_cckandrw_pagea_ctl(hw, &flag);
2566 for (i = 0; i < 4; i++) {
2567 rege94 = result[i][0];
2568 rege9c = result[i][1];
2569 regea4 = result[i][2];
2570 regeac = result[i][3];
2571 regeb4 = result[i][4];
2572 regebc = result[i][5];
2573 regec4 = result[i][6];
2574 regecc = result[i][7];
2575 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2576 ("IQK: rege94=%lx rege9c=%lx regea4=%lx regeac=%lx "
2577 "regeb4=%lx regebc=%lx regec4=%lx regecc=%lx\n ",
2578 rege94, rege9c, regea4, regeac, regeb4, regebc, regec4,
2579 regecc));
2580 }
2581 if (final_candidate != 0xff) {
2582 rtlphy->reg_e94 = rege94 = result[final_candidate][0];
2583 rtlphy->reg_e9c = rege9c = result[final_candidate][1];
2584 regea4 = result[final_candidate][2];
2585 regeac = result[final_candidate][3];
2586 rtlphy->reg_eb4 = regeb4 = result[final_candidate][4];
2587 rtlphy->reg_ebc = regebc = result[final_candidate][5];
2588 regec4 = result[final_candidate][6];
2589 regecc = result[final_candidate][7];
2590 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2591 ("IQK: final_candidate is %x\n", final_candidate));
2592 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2593 ("IQK: rege94=%lx rege9c=%lx regea4=%lx regeac=%lx "
2594 "regeb4=%lx regebc=%lx regec4=%lx regecc=%lx\n ",
2595 rege94, rege9c, regea4, regeac, regeb4, regebc, regec4,
2596 regecc));
2597 patha_ok = pathb_ok = true;
2598 } else {
2599 rtlphy->reg_e94 = rtlphy->reg_eb4 = 0x100; /* X default value */
2600 rtlphy->reg_e9c = rtlphy->reg_ebc = 0x0; /* Y default value */
2601 }
2602 if ((rege94 != 0) /*&&(regea4 != 0) */)
2603 _rtl92d_phy_patha_fill_iqk_matrix(hw, patha_ok, result,
2604 final_candidate, (regea4 == 0));
2605 if (IS_92D_SINGLEPHY(rtlhal->version)) {
2606 if ((regeb4 != 0) /*&&(regec4 != 0) */)
2607 _rtl92d_phy_pathb_fill_iqk_matrix(hw, pathb_ok, result,
2608 final_candidate, (regec4 == 0));
2609 }
2610 if (final_candidate != 0xFF) {
2611 indexforchannel = rtl92d_get_rightchnlplace_for_iqk(
2612 rtlphy->current_channel);
2613
2614 for (i = 0; i < IQK_MATRIX_REG_NUM; i++)
2615 rtlphy->iqk_matrix_regsetting[indexforchannel].
2616 value[0][i] = result[final_candidate][i];
2617 rtlphy->iqk_matrix_regsetting[indexforchannel].iqk_done =
2618 true;
2619
2620 RT_TRACE(rtlpriv, COMP_SCAN | COMP_MLME, DBG_LOUD,
2621 ("\nIQK OK indexforchannel %d.\n", indexforchannel));
2622 }
2623 }
2624
2625 void rtl92d_phy_reload_iqk_setting(struct ieee80211_hw *hw, u8 channel)
2626 {
2627 struct rtl_priv *rtlpriv = rtl_priv(hw);
2628 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2629 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2630 u8 indexforchannel;
2631
2632 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, ("channel %d\n", channel));
2633 /*------Do IQK for normal chip and test chip 5G band------- */
2634 indexforchannel = rtl92d_get_rightchnlplace_for_iqk(channel);
2635 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
2636 ("indexforchannel %d done %d\n", indexforchannel,
2637 rtlphy->iqk_matrix_regsetting[indexforchannel].iqk_done));
2638 if (0 && !rtlphy->iqk_matrix_regsetting[indexforchannel].iqk_done &&
2639 rtlphy->need_iqk) {
2640 /* Re Do IQK. */
2641 RT_TRACE(rtlpriv, COMP_SCAN | COMP_INIT, DBG_LOUD,
2642 ("Do IQK Matrix reg for channel:%d....\n", channel));
2643 rtl92d_phy_iq_calibrate(hw);
2644 } else {
2645 /* Just load the value. */
2646 /* 2G band just load once. */
2647 if (((!rtlhal->load_imrandiqk_setting_for2g) &&
2648 indexforchannel == 0) || indexforchannel > 0) {
2649 RT_TRACE(rtlpriv, COMP_SCAN, DBG_LOUD,
2650 ("Just Read IQK Matrix reg for channel:%d"
2651 "....\n", channel));
2652 if ((rtlphy->iqk_matrix_regsetting[indexforchannel].
2653 value[0] != NULL)
2654 /*&&(regea4 != 0) */)
2655 _rtl92d_phy_patha_fill_iqk_matrix(hw, true,
2656 rtlphy->iqk_matrix_regsetting[
2657 indexforchannel].value, 0,
2658 (rtlphy->iqk_matrix_regsetting[
2659 indexforchannel].value[0][2] == 0));
2660 if (IS_92D_SINGLEPHY(rtlhal->version)) {
2661 if ((rtlphy->iqk_matrix_regsetting[
2662 indexforchannel].value[0][4] != 0)
2663 /*&&(regec4 != 0) */)
2664 _rtl92d_phy_pathb_fill_iqk_matrix(hw,
2665 true,
2666 rtlphy->iqk_matrix_regsetting[
2667 indexforchannel].value, 0,
2668 (rtlphy->iqk_matrix_regsetting[
2669 indexforchannel].value[0][6]
2670 == 0));
2671 }
2672 }
2673 }
2674 rtlphy->need_iqk = false;
2675 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, ("<====\n"));
2676 }
2677
2678 static u32 _rtl92d_phy_get_abs(u32 val1, u32 val2)
2679 {
2680 u32 ret;
2681
2682 if (val1 >= val2)
2683 ret = val1 - val2;
2684 else
2685 ret = val2 - val1;
2686 return ret;
2687 }
2688
2689 static bool _rtl92d_is_legal_5g_channel(struct ieee80211_hw *hw, u8 channel)
2690 {
2691
2692 int i;
2693 u8 channel_5g[45] = {
2694 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58,
2695 60, 62, 64, 100, 102, 104, 106, 108, 110, 112,
2696 114, 116, 118, 120, 122, 124, 126, 128, 130, 132,
2697 134, 136, 138, 140, 149, 151, 153, 155, 157, 159,
2698 161, 163, 165
2699 };
2700
2701 for (i = 0; i < sizeof(channel_5g); i++)
2702 if (channel == channel_5g[i])
2703 return true;
2704 return false;
2705 }
2706
2707 static void _rtl92d_phy_calc_curvindex(struct ieee80211_hw *hw,
2708 u32 *targetchnl, u32 * curvecount_val,
2709 bool is5g, u32 *curveindex)
2710 {
2711 struct rtl_priv *rtlpriv = rtl_priv(hw);
2712 u32 smallest_abs_val = 0xffffffff, u4tmp;
2713 u8 i, j;
2714 u8 chnl_num = is5g ? TARGET_CHNL_NUM_5G : TARGET_CHNL_NUM_2G;
2715
2716 for (i = 0; i < chnl_num; i++) {
2717 if (is5g && !_rtl92d_is_legal_5g_channel(hw, i + 1))
2718 continue;
2719 curveindex[i] = 0;
2720 for (j = 0; j < (CV_CURVE_CNT * 2); j++) {
2721 u4tmp = _rtl92d_phy_get_abs(targetchnl[i],
2722 curvecount_val[j]);
2723
2724 if (u4tmp < smallest_abs_val) {
2725 curveindex[i] = j;
2726 smallest_abs_val = u4tmp;
2727 }
2728 }
2729 smallest_abs_val = 0xffffffff;
2730 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("curveindex[%d] = %x\n", i,
2731 curveindex[i]));
2732 }
2733 }
2734
2735 static void _rtl92d_phy_reload_lck_setting(struct ieee80211_hw *hw,
2736 u8 channel)
2737 {
2738 struct rtl_priv *rtlpriv = rtl_priv(hw);
2739 u8 erfpath = rtlpriv->rtlhal.current_bandtype ==
2740 BAND_ON_5G ? RF90_PATH_A :
2741 IS_92D_SINGLEPHY(rtlpriv->rtlhal.version) ?
2742 RF90_PATH_B : RF90_PATH_A;
2743 u32 u4tmp = 0, u4regvalue = 0;
2744 bool bneed_powerdown_radio = false;
2745
2746 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, ("path %d\n", erfpath));
2747 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("band type = %d\n",
2748 rtlpriv->rtlhal.current_bandtype));
2749 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("channel = %d\n", channel));
2750 if (rtlpriv->rtlhal.current_bandtype == BAND_ON_5G) {/* Path-A for 5G */
2751 u4tmp = curveindex_5g[channel-1];
2752 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2753 ("ver 1 set RF-A, 5G, 0x28 = 0x%ulx !!\n", u4tmp));
2754 if (rtlpriv->rtlhal.macphymode == DUALMAC_DUALPHY &&
2755 rtlpriv->rtlhal.interfaceindex == 1) {
2756 bneed_powerdown_radio =
2757 rtl92d_phy_enable_anotherphy(hw, false);
2758 rtlpriv->rtlhal.during_mac1init_radioa = true;
2759 /* asume no this case */
2760 if (bneed_powerdown_radio)
2761 _rtl92d_phy_enable_rf_env(hw, erfpath,
2762 &u4regvalue);
2763 }
2764 rtl_set_rfreg(hw, erfpath, RF_SYN_G4, 0x3f800, u4tmp);
2765 if (bneed_powerdown_radio)
2766 _rtl92d_phy_restore_rf_env(hw, erfpath, &u4regvalue);
2767 if (rtlpriv->rtlhal.during_mac1init_radioa)
2768 rtl92d_phy_powerdown_anotherphy(hw, false);
2769 } else if (rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G) {
2770 u4tmp = curveindex_2g[channel-1];
2771 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2772 ("ver 3 set RF-B, 2G, 0x28 = 0x%ulx !!\n", u4tmp));
2773 if (rtlpriv->rtlhal.macphymode == DUALMAC_DUALPHY &&
2774 rtlpriv->rtlhal.interfaceindex == 0) {
2775 bneed_powerdown_radio =
2776 rtl92d_phy_enable_anotherphy(hw, true);
2777 rtlpriv->rtlhal.during_mac0init_radiob = true;
2778 if (bneed_powerdown_radio)
2779 _rtl92d_phy_enable_rf_env(hw, erfpath,
2780 &u4regvalue);
2781 }
2782 rtl_set_rfreg(hw, erfpath, RF_SYN_G4, 0x3f800, u4tmp);
2783 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2784 ("ver 3 set RF-B, 2G, 0x28 = 0x%ulx !!\n",
2785 rtl_get_rfreg(hw, erfpath, RF_SYN_G4, 0x3f800)));
2786 if (bneed_powerdown_radio)
2787 _rtl92d_phy_restore_rf_env(hw, erfpath, &u4regvalue);
2788 if (rtlpriv->rtlhal.during_mac0init_radiob)
2789 rtl92d_phy_powerdown_anotherphy(hw, true);
2790 }
2791 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, ("<====\n"));
2792 }
2793
2794 static void _rtl92d_phy_lc_calibrate_sw(struct ieee80211_hw *hw, bool is2t)
2795 {
2796 struct rtl_priv *rtlpriv = rtl_priv(hw);
2797 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2798 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2799 u8 tmpreg, index, rf_mode[2];
2800 u8 path = is2t ? 2 : 1;
2801 u8 i;
2802 u32 u4tmp, offset;
2803 u32 curvecount_val[CV_CURVE_CNT * 2] = {0};
2804 u16 timeout = 800, timecount = 0;
2805
2806 /* Check continuous TX and Packet TX */
2807 tmpreg = rtl_read_byte(rtlpriv, 0xd03);
2808 /* if Deal with contisuous TX case, disable all continuous TX */
2809 /* if Deal with Packet TX case, block all queues */
2810 if ((tmpreg & 0x70) != 0)
2811 rtl_write_byte(rtlpriv, 0xd03, tmpreg & 0x8F);
2812 else
2813 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
2814 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xF00000, 0x0F);
2815 for (index = 0; index < path; index++) {
2816 /* 1. Read original RF mode */
2817 offset = index == 0 ? ROFDM0_XAAGCCORE1 : ROFDM0_XBAGCCORE1;
2818 rf_mode[index] = rtl_read_byte(rtlpriv, offset);
2819 /* 2. Set RF mode = standby mode */
2820 rtl_set_rfreg(hw, (enum radio_path)index, RF_AC,
2821 BRFREGOFFSETMASK, 0x010000);
2822 if (rtlpci->init_ready) {
2823 /* switch CV-curve control by LC-calibration */
2824 rtl_set_rfreg(hw, (enum radio_path)index, RF_SYN_G7,
2825 BIT(17), 0x0);
2826 /* 4. Set LC calibration begin */
2827 rtl_set_rfreg(hw, (enum radio_path)index, RF_CHNLBW,
2828 0x08000, 0x01);
2829 }
2830 u4tmp = rtl_get_rfreg(hw, (enum radio_path)index, RF_SYN_G6,
2831 BRFREGOFFSETMASK);
2832 while ((!(u4tmp & BIT(11))) && timecount <= timeout) {
2833 mdelay(50);
2834 timecount += 50;
2835 u4tmp = rtl_get_rfreg(hw, (enum radio_path)index,
2836 RF_SYN_G6, BRFREGOFFSETMASK);
2837 }
2838 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2839 ("PHY_LCK finish delay for %d ms=2\n", timecount));
2840 u4tmp = rtl_get_rfreg(hw, index, RF_SYN_G4, BRFREGOFFSETMASK);
2841 if (index == 0 && rtlhal->interfaceindex == 0) {
2842 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2843 ("path-A / 5G LCK\n"));
2844 } else {
2845 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2846 ("path-B / 2.4G LCK\n"));
2847 }
2848 memset(&curvecount_val[0], 0, CV_CURVE_CNT * 2);
2849 /* Set LC calibration off */
2850 rtl_set_rfreg(hw, (enum radio_path)index, RF_CHNLBW,
2851 0x08000, 0x0);
2852 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("set RF 0x18[15] = 0\n"));
2853 /* save Curve-counting number */
2854 for (i = 0; i < CV_CURVE_CNT; i++) {
2855 u32 readval = 0, readval2 = 0;
2856 rtl_set_rfreg(hw, (enum radio_path)index, 0x3F,
2857 0x7f, i);
2858
2859 rtl_set_rfreg(hw, (enum radio_path)index, 0x4D,
2860 BRFREGOFFSETMASK, 0x0);
2861 readval = rtl_get_rfreg(hw, (enum radio_path)index,
2862 0x4F, BRFREGOFFSETMASK);
2863 curvecount_val[2 * i + 1] = (readval & 0xfffe0) >> 5;
2864 /* reg 0x4f [4:0] */
2865 /* reg 0x50 [19:10] */
2866 readval2 = rtl_get_rfreg(hw, (enum radio_path)index,
2867 0x50, 0xffc00);
2868 curvecount_val[2 * i] = (((readval & 0x1F) << 10) |
2869 readval2);
2870 }
2871 if (index == 0 && rtlhal->interfaceindex == 0)
2872 _rtl92d_phy_calc_curvindex(hw, targetchnl_5g,
2873 curvecount_val,
2874 true, curveindex_5g);
2875 else
2876 _rtl92d_phy_calc_curvindex(hw, targetchnl_2g,
2877 curvecount_val,
2878 false, curveindex_2g);
2879 /* switch CV-curve control mode */
2880 rtl_set_rfreg(hw, (enum radio_path)index, RF_SYN_G7,
2881 BIT(17), 0x1);
2882 }
2883
2884 /* Restore original situation */
2885 for (index = 0; index < path; index++) {
2886 offset = index == 0 ? ROFDM0_XAAGCCORE1 : ROFDM0_XBAGCCORE1;
2887 rtl_write_byte(rtlpriv, offset, 0x50);
2888 rtl_write_byte(rtlpriv, offset, rf_mode[index]);
2889 }
2890 if ((tmpreg & 0x70) != 0)
2891 rtl_write_byte(rtlpriv, 0xd03, tmpreg);
2892 else /*Deal with Packet TX case */
2893 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
2894 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xF00000, 0x00);
2895 _rtl92d_phy_reload_lck_setting(hw, rtlpriv->phy.current_channel);
2896 }
2897
2898 static void _rtl92d_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t)
2899 {
2900 struct rtl_priv *rtlpriv = rtl_priv(hw);
2901
2902 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("cosa PHY_LCK ver=2\n"));
2903 _rtl92d_phy_lc_calibrate_sw(hw, is2t);
2904 }
2905
2906 void rtl92d_phy_lc_calibrate(struct ieee80211_hw *hw)
2907 {
2908 struct rtl_priv *rtlpriv = rtl_priv(hw);
2909 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2910 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal);
2911 u32 timeout = 2000, timecount = 0;
2912
2913 while (rtlpriv->mac80211.act_scanning && timecount < timeout) {
2914 udelay(50);
2915 timecount += 50;
2916 }
2917
2918 rtlphy->lck_inprogress = true;
2919 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2920 ("LCK:Start!!! currentband %x delay %d ms\n",
2921 rtlhal->current_bandtype, timecount));
2922 if (IS_92D_SINGLEPHY(rtlhal->version)) {
2923 _rtl92d_phy_lc_calibrate(hw, true);
2924 } else {
2925 /* For 1T1R */
2926 _rtl92d_phy_lc_calibrate(hw, false);
2927 }
2928 rtlphy->lck_inprogress = false;
2929 RTPRINT(rtlpriv, FINIT, INIT_IQK, ("LCK:Finish!!!\n"));
2930 }
2931
2932 void rtl92d_phy_ap_calibrate(struct ieee80211_hw *hw, char delta)
2933 {
2934 return;
2935 }
2936
2937 static bool _rtl92d_phy_set_sw_chnl_cmdarray(struct swchnlcmd *cmdtable,
2938 u32 cmdtableidx, u32 cmdtablesz, enum swchnlcmd_id cmdid,
2939 u32 para1, u32 para2, u32 msdelay)
2940 {
2941 struct swchnlcmd *pcmd;
2942
2943 if (cmdtable == NULL) {
2944 RT_ASSERT(false, ("cmdtable cannot be NULL.\n"));
2945 return false;
2946 }
2947 if (cmdtableidx >= cmdtablesz)
2948 return false;
2949
2950 pcmd = cmdtable + cmdtableidx;
2951 pcmd->cmdid = cmdid;
2952 pcmd->para1 = para1;
2953 pcmd->para2 = para2;
2954 pcmd->msdelay = msdelay;
2955 return true;
2956 }
2957
2958 void rtl92d_phy_reset_iqk_result(struct ieee80211_hw *hw)
2959 {
2960 struct rtl_priv *rtlpriv = rtl_priv(hw);
2961 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2962 u8 i;
2963
2964 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2965 ("settings regs %d default regs %d\n",
2966 (int)(sizeof(rtlphy->iqk_matrix_regsetting) /
2967 sizeof(struct iqk_matrix_regs)),
2968 IQK_MATRIX_REG_NUM));
2969 /* 0xe94, 0xe9c, 0xea4, 0xeac, 0xeb4, 0xebc, 0xec4, 0xecc */
2970 for (i = 0; i < IQK_MATRIX_SETTINGS_NUM; i++) {
2971 rtlphy->iqk_matrix_regsetting[i].value[0][0] = 0x100;
2972 rtlphy->iqk_matrix_regsetting[i].value[0][2] = 0x100;
2973 rtlphy->iqk_matrix_regsetting[i].value[0][4] = 0x100;
2974 rtlphy->iqk_matrix_regsetting[i].value[0][6] = 0x100;
2975 rtlphy->iqk_matrix_regsetting[i].value[0][1] = 0x0;
2976 rtlphy->iqk_matrix_regsetting[i].value[0][3] = 0x0;
2977 rtlphy->iqk_matrix_regsetting[i].value[0][5] = 0x0;
2978 rtlphy->iqk_matrix_regsetting[i].value[0][7] = 0x0;
2979 rtlphy->iqk_matrix_regsetting[i].iqk_done = false;
2980 }
2981 }
2982
2983 static bool _rtl92d_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw,
2984 u8 channel, u8 *stage, u8 *step,
2985 u32 *delay)
2986 {
2987 struct rtl_priv *rtlpriv = rtl_priv(hw);
2988 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2989 struct swchnlcmd precommoncmd[MAX_PRECMD_CNT];
2990 u32 precommoncmdcnt;
2991 struct swchnlcmd postcommoncmd[MAX_POSTCMD_CNT];
2992 u32 postcommoncmdcnt;
2993 struct swchnlcmd rfdependcmd[MAX_RFDEPENDCMD_CNT];
2994 u32 rfdependcmdcnt;
2995 struct swchnlcmd *currentcmd = NULL;
2996 u8 rfpath;
2997 u8 num_total_rfpath = rtlphy->num_total_rfpath;
2998
2999 precommoncmdcnt = 0;
3000 _rtl92d_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
3001 MAX_PRECMD_CNT,
3002 CMDID_SET_TXPOWEROWER_LEVEL, 0, 0, 0);
3003 _rtl92d_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
3004 MAX_PRECMD_CNT, CMDID_END, 0, 0, 0);
3005 postcommoncmdcnt = 0;
3006 _rtl92d_phy_set_sw_chnl_cmdarray(postcommoncmd, postcommoncmdcnt++,
3007 MAX_POSTCMD_CNT, CMDID_END, 0, 0, 0);
3008 rfdependcmdcnt = 0;
3009 _rtl92d_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
3010 MAX_RFDEPENDCMD_CNT, CMDID_RF_WRITEREG,
3011 RF_CHNLBW, channel, 0);
3012 _rtl92d_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
3013 MAX_RFDEPENDCMD_CNT, CMDID_END,
3014 0, 0, 0);
3015
3016 do {
3017 switch (*stage) {
3018 case 0:
3019 currentcmd = &precommoncmd[*step];
3020 break;
3021 case 1:
3022 currentcmd = &rfdependcmd[*step];
3023 break;
3024 case 2:
3025 currentcmd = &postcommoncmd[*step];
3026 break;
3027 }
3028 if (currentcmd->cmdid == CMDID_END) {
3029 if ((*stage) == 2) {
3030 return true;
3031 } else {
3032 (*stage)++;
3033 (*step) = 0;
3034 continue;
3035 }
3036 }
3037 switch (currentcmd->cmdid) {
3038 case CMDID_SET_TXPOWEROWER_LEVEL:
3039 rtl92d_phy_set_txpower_level(hw, channel);
3040 break;
3041 case CMDID_WRITEPORT_ULONG:
3042 rtl_write_dword(rtlpriv, currentcmd->para1,
3043 currentcmd->para2);
3044 break;
3045 case CMDID_WRITEPORT_USHORT:
3046 rtl_write_word(rtlpriv, currentcmd->para1,
3047 (u16)currentcmd->para2);
3048 break;
3049 case CMDID_WRITEPORT_UCHAR:
3050 rtl_write_byte(rtlpriv, currentcmd->para1,
3051 (u8)currentcmd->para2);
3052 break;
3053 case CMDID_RF_WRITEREG:
3054 for (rfpath = 0; rfpath < num_total_rfpath; rfpath++) {
3055 rtlphy->rfreg_chnlval[rfpath] =
3056 ((rtlphy->rfreg_chnlval[rfpath] &
3057 0xffffff00) | currentcmd->para2);
3058 if (rtlpriv->rtlhal.current_bandtype ==
3059 BAND_ON_5G) {
3060 if (currentcmd->para2 > 99)
3061 rtlphy->rfreg_chnlval[rfpath] =
3062 rtlphy->rfreg_chnlval
3063 [rfpath] | (BIT(18));
3064 else
3065 rtlphy->rfreg_chnlval[rfpath] =
3066 rtlphy->rfreg_chnlval
3067 [rfpath] & (~BIT(18));
3068 rtlphy->rfreg_chnlval[rfpath] |=
3069 (BIT(16) | BIT(8));
3070 } else {
3071 rtlphy->rfreg_chnlval[rfpath] &=
3072 ~(BIT(8) | BIT(16) | BIT(18));
3073 }
3074 rtl_set_rfreg(hw, (enum radio_path)rfpath,
3075 currentcmd->para1,
3076 BRFREGOFFSETMASK,
3077 rtlphy->rfreg_chnlval[rfpath]);
3078 _rtl92d_phy_reload_imr_setting(hw, channel,
3079 rfpath);
3080 }
3081 _rtl92d_phy_switch_rf_setting(hw, channel);
3082 /* do IQK when all parameters are ready */
3083 rtl92d_phy_reload_iqk_setting(hw, channel);
3084 break;
3085 default:
3086 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
3087 ("switch case not process\n"));
3088 break;
3089 }
3090 break;
3091 } while (true);
3092 (*delay) = currentcmd->msdelay;
3093 (*step)++;
3094 return false;
3095 }
3096
3097 u8 rtl92d_phy_sw_chnl(struct ieee80211_hw *hw)
3098 {
3099 struct rtl_priv *rtlpriv = rtl_priv(hw);
3100 struct rtl_phy *rtlphy = &(rtlpriv->phy);
3101 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3102 u32 delay;
3103 u32 timeout = 1000, timecount = 0;
3104 u8 channel = rtlphy->current_channel;
3105 u32 ret_value;
3106
3107 if (rtlphy->sw_chnl_inprogress)
3108 return 0;
3109 if (rtlphy->set_bwmode_inprogress)
3110 return 0;
3111
3112 if ((is_hal_stop(rtlhal)) || (RT_CANNOT_IO(hw))) {
3113 RT_TRACE(rtlpriv, COMP_CHAN, DBG_LOUD,
3114 ("sw_chnl_inprogress false driver sleep or unload\n"));
3115 return 0;
3116 }
3117 while (rtlphy->lck_inprogress && timecount < timeout) {
3118 mdelay(50);
3119 timecount += 50;
3120 }
3121 if (rtlhal->macphymode == SINGLEMAC_SINGLEPHY &&
3122 rtlhal->bandset == BAND_ON_BOTH) {
3123 ret_value = rtl_get_bbreg(hw, RFPGA0_XAB_RFPARAMETER,
3124 BMASKDWORD);
3125 if (rtlphy->current_channel > 14 && !(ret_value & BIT(0)))
3126 rtl92d_phy_switch_wirelessband(hw, BAND_ON_5G);
3127 else if (rtlphy->current_channel <= 14 && (ret_value & BIT(0)))
3128 rtl92d_phy_switch_wirelessband(hw, BAND_ON_2_4G);
3129 }
3130 switch (rtlhal->current_bandtype) {
3131 case BAND_ON_5G:
3132 /* Get first channel error when change between
3133 * 5G and 2.4G band. */
3134 if (channel <= 14)
3135 return 0;
3136 RT_ASSERT((channel > 14), ("5G but channel<=14"));
3137 break;
3138 case BAND_ON_2_4G:
3139 /* Get first channel error when change between
3140 * 5G and 2.4G band. */
3141 if (channel > 14)
3142 return 0;
3143 RT_ASSERT((channel <= 14), ("2G but channel>14"));
3144 break;
3145 default:
3146 RT_ASSERT(false,
3147 ("Invalid WirelessMode(%#x)!!\n",
3148 rtlpriv->mac80211.mode));
3149 break;
3150 }
3151 rtlphy->sw_chnl_inprogress = true;
3152 if (channel == 0)
3153 channel = 1;
3154 rtlphy->sw_chnl_stage = 0;
3155 rtlphy->sw_chnl_step = 0;
3156 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE,
3157 ("switch to channel%d\n", rtlphy->current_channel));
3158
3159 do {
3160 if (!rtlphy->sw_chnl_inprogress)
3161 break;
3162 if (!_rtl92d_phy_sw_chnl_step_by_step(hw,
3163 rtlphy->current_channel,
3164 &rtlphy->sw_chnl_stage, &rtlphy->sw_chnl_step, &delay)) {
3165 if (delay > 0)
3166 mdelay(delay);
3167 else
3168 continue;
3169 } else {
3170 rtlphy->sw_chnl_inprogress = false;
3171 }
3172 break;
3173 } while (true);
3174 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, ("<==\n"));
3175 rtlphy->sw_chnl_inprogress = false;
3176 return 1;
3177 }
3178
3179 static void rtl92d_phy_set_io(struct ieee80211_hw *hw)
3180 {
3181 struct rtl_priv *rtlpriv = rtl_priv(hw);
3182 struct rtl_phy *rtlphy = &(rtlpriv->phy);
3183
3184 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
3185 ("--->Cmd(%#x), set_io_inprogress(%d)\n",
3186 rtlphy->current_io_type, rtlphy->set_io_inprogress));
3187 switch (rtlphy->current_io_type) {
3188 case IO_CMD_RESUME_DM_BY_SCAN:
3189 de_digtable.cur_igvalue = rtlphy->initgain_backup.xaagccore1;
3190 rtl92d_dm_write_dig(hw);
3191 rtl92d_phy_set_txpower_level(hw, rtlphy->current_channel);
3192 break;
3193 case IO_CMD_PAUSE_DM_BY_SCAN:
3194 rtlphy->initgain_backup.xaagccore1 = de_digtable.cur_igvalue;
3195 de_digtable.cur_igvalue = 0x37;
3196 rtl92d_dm_write_dig(hw);
3197 break;
3198 default:
3199 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
3200 ("switch case not process\n"));
3201 break;
3202 }
3203 rtlphy->set_io_inprogress = false;
3204 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
3205 ("<---(%#x)\n", rtlphy->current_io_type));
3206 }
3207
3208 bool rtl92d_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype)
3209 {
3210 struct rtl_priv *rtlpriv = rtl_priv(hw);
3211 struct rtl_phy *rtlphy = &(rtlpriv->phy);
3212 bool postprocessing = false;
3213
3214 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
3215 ("-->IO Cmd(%#x), set_io_inprogress(%d)\n",
3216 iotype, rtlphy->set_io_inprogress));
3217 do {
3218 switch (iotype) {
3219 case IO_CMD_RESUME_DM_BY_SCAN:
3220 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
3221 ("[IO CMD] Resume DM after scan.\n"));
3222 postprocessing = true;
3223 break;
3224 case IO_CMD_PAUSE_DM_BY_SCAN:
3225 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
3226 ("[IO CMD] Pause DM before scan.\n"));
3227 postprocessing = true;
3228 break;
3229 default:
3230 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
3231 ("switch case not process\n"));
3232 break;
3233 }
3234 } while (false);
3235 if (postprocessing && !rtlphy->set_io_inprogress) {
3236 rtlphy->set_io_inprogress = true;
3237 rtlphy->current_io_type = iotype;
3238 } else {
3239 return false;
3240 }
3241 rtl92d_phy_set_io(hw);
3242 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, ("<--IO Type(%#x)\n", iotype));
3243 return true;
3244 }
3245
3246 static void _rtl92d_phy_set_rfon(struct ieee80211_hw *hw)
3247 {
3248 struct rtl_priv *rtlpriv = rtl_priv(hw);
3249
3250 /* a. SYS_CLKR 0x08[11] = 1 restore MAC clock */
3251 /* b. SPS_CTRL 0x11[7:0] = 0x2b */
3252 if (rtlpriv->rtlhal.macphymode == SINGLEMAC_SINGLEPHY)
3253 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
3254 /* c. For PCIE: SYS_FUNC_EN 0x02[7:0] = 0xE3 enable BB TRX function */
3255 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
3256 /* RF_ON_EXCEP(d~g): */
3257 /* d. APSD_CTRL 0x600[7:0] = 0x00 */
3258 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00);
3259 /* e. SYS_FUNC_EN 0x02[7:0] = 0xE2 reset BB TRX function again */
3260 /* f. SYS_FUNC_EN 0x02[7:0] = 0xE3 enable BB TRX function*/
3261 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
3262 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
3263 /* g. txpause 0x522[7:0] = 0x00 enable mac tx queue */
3264 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
3265 }
3266
3267 static void _rtl92d_phy_set_rfsleep(struct ieee80211_hw *hw)
3268 {
3269 struct rtl_priv *rtlpriv = rtl_priv(hw);
3270 u32 u4btmp;
3271 u8 delay = 5;
3272
3273 /* a. TXPAUSE 0x522[7:0] = 0xFF Pause MAC TX queue */
3274 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
3275 /* b. RF path 0 offset 0x00 = 0x00 disable RF */
3276 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, BRFREGOFFSETMASK, 0x00);
3277 /* c. APSD_CTRL 0x600[7:0] = 0x40 */
3278 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
3279 /* d. APSD_CTRL 0x600[7:0] = 0x00
3280 * APSD_CTRL 0x600[7:0] = 0x00
3281 * RF path 0 offset 0x00 = 0x00
3282 * APSD_CTRL 0x600[7:0] = 0x40
3283 * */
3284 u4btmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, BRFREGOFFSETMASK);
3285 while (u4btmp != 0 && delay > 0) {
3286 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x0);
3287 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, BRFREGOFFSETMASK, 0x00);
3288 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
3289 u4btmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, BRFREGOFFSETMASK);
3290 delay--;
3291 }
3292 if (delay == 0) {
3293 /* Jump out the LPS turn off sequence to RF_ON_EXCEP */
3294 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00);
3295
3296 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
3297 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
3298 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
3299 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
3300 ("Fail !!! Switch RF timeout.\n"));
3301 return;
3302 }
3303 /* e. For PCIE: SYS_FUNC_EN 0x02[7:0] = 0xE2 reset BB TRX function */
3304 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
3305 /* f. SPS_CTRL 0x11[7:0] = 0x22 */
3306 if (rtlpriv->rtlhal.macphymode == SINGLEMAC_SINGLEPHY)
3307 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x22);
3308 /* g. SYS_CLKR 0x08[11] = 0 gated MAC clock */
3309 }
3310
3311 bool rtl92d_phy_set_rf_power_state(struct ieee80211_hw *hw,
3312 enum rf_pwrstate rfpwr_state)
3313 {
3314
3315 bool bresult = true;
3316 struct rtl_priv *rtlpriv = rtl_priv(hw);
3317 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
3318 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
3319 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
3320 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
3321 u8 i, queue_id;
3322 struct rtl8192_tx_ring *ring = NULL;
3323
3324 if (rfpwr_state == ppsc->rfpwr_state)
3325 return false;
3326 switch (rfpwr_state) {
3327 case ERFON:
3328 if ((ppsc->rfpwr_state == ERFOFF) &&
3329 RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
3330 bool rtstatus;
3331 u32 InitializeCount = 0;
3332 do {
3333 InitializeCount++;
3334 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
3335 ("IPS Set eRf nic enable\n"));
3336 rtstatus = rtl_ps_enable_nic(hw);
3337 } while ((rtstatus != true) &&
3338 (InitializeCount < 10));
3339
3340 RT_CLEAR_PS_LEVEL(ppsc,
3341 RT_RF_OFF_LEVL_HALT_NIC);
3342 } else {
3343 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
3344 ("awake, sleeped:%d ms state_"
3345 "inap:%x\n",
3346 jiffies_to_msecs(jiffies -
3347 ppsc->last_sleep_jiffies),
3348 rtlpriv->psc.state_inap));
3349 ppsc->last_awake_jiffies = jiffies;
3350 _rtl92d_phy_set_rfon(hw);
3351 }
3352
3353 if (mac->link_state == MAC80211_LINKED)
3354 rtlpriv->cfg->ops->led_control(hw,
3355 LED_CTL_LINK);
3356 else
3357 rtlpriv->cfg->ops->led_control(hw,
3358 LED_CTL_NO_LINK);
3359 break;
3360 case ERFOFF:
3361 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) {
3362 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
3363 ("IPS Set eRf nic disable\n"));
3364 rtl_ps_disable_nic(hw);
3365 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
3366 } else {
3367 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
3368 rtlpriv->cfg->ops->led_control(hw,
3369 LED_CTL_NO_LINK);
3370 else
3371 rtlpriv->cfg->ops->led_control(hw,
3372 LED_CTL_POWER_OFF);
3373 }
3374 break;
3375 case ERFSLEEP:
3376 if (ppsc->rfpwr_state == ERFOFF)
3377 return false;
3378
3379 for (queue_id = 0, i = 0;
3380 queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
3381 ring = &pcipriv->dev.tx_ring[queue_id];
3382 if (skb_queue_len(&ring->queue) == 0 ||
3383 queue_id == BEACON_QUEUE) {
3384 queue_id++;
3385 continue;
3386 } else if (rtlpci->pdev->current_state != PCI_D0) {
3387 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
3388 ("eRf Off/Sleep: %d times TcbBusyQueu"
3389 "e[%d] !=0 but lower power state!\n",
3390 (i + 1), queue_id));
3391 break;
3392 } else {
3393 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
3394 ("eRf Off/Sleep: %d times TcbBusyQueu"
3395 "e[%d] =%d "
3396 "before doze!\n", (i + 1), queue_id,
3397 skb_queue_len(&ring->queue)));
3398 udelay(10);
3399 i++;
3400 }
3401
3402 if (i >= MAX_DOZE_WAITING_TIMES_9x) {
3403 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
3404 ("\nERFOFF: %d times TcbBusyQueue[%d] "
3405 "= %d !\n",
3406 MAX_DOZE_WAITING_TIMES_9x, queue_id,
3407 skb_queue_len(&ring->queue)));
3408 break;
3409 }
3410 }
3411 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
3412 ("Set rfsleep awaked:%d ms\n",
3413 jiffies_to_msecs(jiffies - ppsc->last_awake_jiffies)));
3414 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG, ("sleep awaked:%d ms "
3415 "state_inap:%x\n", jiffies_to_msecs(jiffies -
3416 ppsc->last_awake_jiffies), rtlpriv->psc.state_inap));
3417 ppsc->last_sleep_jiffies = jiffies;
3418 _rtl92d_phy_set_rfsleep(hw);
3419 break;
3420 default:
3421 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
3422 ("switch case not process\n"));
3423 bresult = false;
3424 break;
3425 }
3426 if (bresult)
3427 ppsc->rfpwr_state = rfpwr_state;
3428 return bresult;
3429 }
3430
3431 void rtl92d_phy_config_macphymode(struct ieee80211_hw *hw)
3432 {
3433 struct rtl_priv *rtlpriv = rtl_priv(hw);
3434 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3435 u8 offset = REG_MAC_PHY_CTRL_NORMAL;
3436
3437 switch (rtlhal->macphymode) {
3438 case DUALMAC_DUALPHY:
3439 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3440 ("MacPhyMode: DUALMAC_DUALPHY\n"));
3441 rtl_write_byte(rtlpriv, offset, 0xF3);
3442 break;
3443 case SINGLEMAC_SINGLEPHY:
3444 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3445 ("MacPhyMode: SINGLEMAC_SINGLEPHY\n"));
3446 rtl_write_byte(rtlpriv, offset, 0xF4);
3447 break;
3448 case DUALMAC_SINGLEPHY:
3449 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3450 ("MacPhyMode: DUALMAC_SINGLEPHY\n"));
3451 rtl_write_byte(rtlpriv, offset, 0xF1);
3452 break;
3453 }
3454 }
3455
3456 void rtl92d_phy_config_macphymode_info(struct ieee80211_hw *hw)
3457 {
3458 struct rtl_priv *rtlpriv = rtl_priv(hw);
3459 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3460 struct rtl_phy *rtlphy = &(rtlpriv->phy);
3461
3462 switch (rtlhal->macphymode) {
3463 case DUALMAC_SINGLEPHY:
3464 rtlphy->rf_type = RF_2T2R;
3465 rtlhal->version |= CHIP_92D_SINGLEPHY;
3466 rtlhal->bandset = BAND_ON_BOTH;
3467 rtlhal->current_bandtype = BAND_ON_2_4G;
3468 break;
3469
3470 case SINGLEMAC_SINGLEPHY:
3471 rtlphy->rf_type = RF_2T2R;
3472 rtlhal->version |= CHIP_92D_SINGLEPHY;
3473 rtlhal->bandset = BAND_ON_BOTH;
3474 rtlhal->current_bandtype = BAND_ON_2_4G;
3475 break;
3476
3477 case DUALMAC_DUALPHY:
3478 rtlphy->rf_type = RF_1T1R;
3479 rtlhal->version &= (~CHIP_92D_SINGLEPHY);
3480 /* Now we let MAC0 run on 5G band. */
3481 if (rtlhal->interfaceindex == 0) {
3482 rtlhal->bandset = BAND_ON_5G;
3483 rtlhal->current_bandtype = BAND_ON_5G;
3484 } else {
3485 rtlhal->bandset = BAND_ON_2_4G;
3486 rtlhal->current_bandtype = BAND_ON_2_4G;
3487 }
3488 break;
3489 default:
3490 break;
3491 }
3492 }
3493
3494 u8 rtl92d_get_chnlgroup_fromarray(u8 chnl)
3495 {
3496 u8 group;
3497 u8 channel_info[59] = {
3498 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
3499 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56,
3500 58, 60, 62, 64, 100, 102, 104, 106, 108,
3501 110, 112, 114, 116, 118, 120, 122, 124,
3502 126, 128, 130, 132, 134, 136, 138, 140,
3503 149, 151, 153, 155, 157, 159, 161, 163,
3504 165
3505 };
3506
3507 if (channel_info[chnl] <= 3)
3508 group = 0;
3509 else if (channel_info[chnl] <= 9)
3510 group = 1;
3511 else if (channel_info[chnl] <= 14)
3512 group = 2;
3513 else if (channel_info[chnl] <= 44)
3514 group = 3;
3515 else if (channel_info[chnl] <= 54)
3516 group = 4;
3517 else if (channel_info[chnl] <= 64)
3518 group = 5;
3519 else if (channel_info[chnl] <= 112)
3520 group = 6;
3521 else if (channel_info[chnl] <= 126)
3522 group = 7;
3523 else if (channel_info[chnl] <= 140)
3524 group = 8;
3525 else if (channel_info[chnl] <= 153)
3526 group = 9;
3527 else if (channel_info[chnl] <= 159)
3528 group = 10;
3529 else
3530 group = 11;
3531 return group;
3532 }
3533
3534 void rtl92d_phy_set_poweron(struct ieee80211_hw *hw)
3535 {
3536 struct rtl_priv *rtlpriv = rtl_priv(hw);
3537 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3538 unsigned long flags;
3539 u8 value8;
3540 u16 i;
3541 u32 mac_reg = (rtlhal->interfaceindex == 0 ? REG_MAC0 : REG_MAC1);
3542
3543 /* notice fw know band status 0x81[1]/0x53[1] = 0: 5G, 1: 2G */
3544 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
3545 value8 = rtl_read_byte(rtlpriv, mac_reg);
3546 value8 |= BIT(1);
3547 rtl_write_byte(rtlpriv, mac_reg, value8);
3548 } else {
3549 value8 = rtl_read_byte(rtlpriv, mac_reg);
3550 value8 &= (~BIT(1));
3551 rtl_write_byte(rtlpriv, mac_reg, value8);
3552 }
3553
3554 if (rtlhal->macphymode == SINGLEMAC_SINGLEPHY) {
3555 value8 = rtl_read_byte(rtlpriv, REG_MAC0);
3556 rtl_write_byte(rtlpriv, REG_MAC0, value8 | MAC0_ON);
3557 } else {
3558 spin_lock_irqsave(&globalmutex_power, flags);
3559 if (rtlhal->interfaceindex == 0) {
3560 value8 = rtl_read_byte(rtlpriv, REG_MAC0);
3561 rtl_write_byte(rtlpriv, REG_MAC0, value8 | MAC0_ON);
3562 } else {
3563 value8 = rtl_read_byte(rtlpriv, REG_MAC1);
3564 rtl_write_byte(rtlpriv, REG_MAC1, value8 | MAC1_ON);
3565 }
3566 value8 = rtl_read_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS);
3567 spin_unlock_irqrestore(&globalmutex_power, flags);
3568 for (i = 0; i < 200; i++) {
3569 if ((value8 & BIT(7)) == 0) {
3570 break;
3571 } else {
3572 udelay(500);
3573 spin_lock_irqsave(&globalmutex_power, flags);
3574 value8 = rtl_read_byte(rtlpriv,
3575 REG_POWER_OFF_IN_PROCESS);
3576 spin_unlock_irqrestore(&globalmutex_power,
3577 flags);
3578 }
3579 }
3580 if (i == 200)
3581 RT_ASSERT(false, ("Another mac power off over time\n"));
3582 }
3583 }
3584
3585 void rtl92d_phy_config_maccoexist_rfpage(struct ieee80211_hw *hw)
3586 {
3587 struct rtl_priv *rtlpriv = rtl_priv(hw);
3588
3589 switch (rtlpriv->rtlhal.macphymode) {
3590 case DUALMAC_DUALPHY:
3591 rtl_write_byte(rtlpriv, REG_DMC, 0x0);
3592 rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x08);
3593 rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x13ff);
3594 break;
3595 case DUALMAC_SINGLEPHY:
3596 rtl_write_byte(rtlpriv, REG_DMC, 0xf8);
3597 rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x08);
3598 rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x13ff);
3599 break;
3600 case SINGLEMAC_SINGLEPHY:
3601 rtl_write_byte(rtlpriv, REG_DMC, 0x0);
3602 rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x10);
3603 rtl_write_word(rtlpriv, (REG_TRXFF_BNDY + 2), 0x27FF);
3604 break;
3605 default:
3606 break;
3607 }
3608 }
3609
3610 void rtl92d_update_bbrf_configuration(struct ieee80211_hw *hw)
3611 {
3612 struct rtl_priv *rtlpriv = rtl_priv(hw);
3613 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3614 struct rtl_phy *rtlphy = &(rtlpriv->phy);
3615 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
3616 u8 rfpath, i;
3617
3618 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("==>\n"));
3619 /* r_select_5G for path_A/B 0 for 2.4G, 1 for 5G */
3620 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
3621 /* r_select_5G for path_A/B,0x878 */
3622 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(0), 0x0);
3623 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0x0);
3624 if (rtlhal->macphymode != DUALMAC_DUALPHY) {
3625 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(16), 0x0);
3626 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(31), 0x0);
3627 }
3628 /* rssi_table_select:index 0 for 2.4G.1~3 for 5G,0xc78 */
3629 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, BIT(6) | BIT(7), 0x0);
3630 /* fc_area 0xd2c */
3631 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(14) | BIT(13), 0x0);
3632 /* 5G LAN ON */
3633 rtl_set_bbreg(hw, 0xB30, 0x00F00000, 0xa);
3634 /* TX BB gain shift*1,Just for testchip,0xc80,0xc88 */
3635 rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, BMASKDWORD,
3636 0x40000100);
3637 rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, BMASKDWORD,
3638 0x40000100);
3639 if (rtlhal->macphymode == DUALMAC_DUALPHY) {
3640 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW,
3641 BIT(10) | BIT(6) | BIT(5),
3642 ((rtlefuse->eeprom_c9 & BIT(3)) >> 3) |
3643 (rtlefuse->eeprom_c9 & BIT(1)) |
3644 ((rtlefuse->eeprom_cc & BIT(1)) << 4));
3645 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE,
3646 BIT(10) | BIT(6) | BIT(5),
3647 ((rtlefuse->eeprom_c9 & BIT(2)) >> 2) |
3648 ((rtlefuse->eeprom_c9 & BIT(0)) << 1) |
3649 ((rtlefuse->eeprom_cc & BIT(0)) << 5));
3650 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0);
3651 } else {
3652 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW,
3653 BIT(26) | BIT(22) | BIT(21) | BIT(10) |
3654 BIT(6) | BIT(5),
3655 ((rtlefuse->eeprom_c9 & BIT(3)) >> 3) |
3656 (rtlefuse->eeprom_c9 & BIT(1)) |
3657 ((rtlefuse->eeprom_cc & BIT(1)) << 4) |
3658 ((rtlefuse->eeprom_c9 & BIT(7)) << 9) |
3659 ((rtlefuse->eeprom_c9 & BIT(5)) << 12) |
3660 ((rtlefuse->eeprom_cc & BIT(3)) << 18));
3661 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE,
3662 BIT(10) | BIT(6) | BIT(5),
3663 ((rtlefuse->eeprom_c9 & BIT(2)) >> 2) |
3664 ((rtlefuse->eeprom_c9 & BIT(0)) << 1) |
3665 ((rtlefuse->eeprom_cc & BIT(0)) << 5));
3666 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE,
3667 BIT(10) | BIT(6) | BIT(5),
3668 ((rtlefuse->eeprom_c9 & BIT(6)) >> 6) |
3669 ((rtlefuse->eeprom_c9 & BIT(4)) >> 3) |
3670 ((rtlefuse->eeprom_cc & BIT(2)) << 3));
3671 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER,
3672 BIT(31) | BIT(15), 0);
3673 }
3674 /* 1.5V_LDO */
3675 } else {
3676 /* r_select_5G for path_A/B */
3677 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(0), 0x1);
3678 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0x1);
3679 if (rtlhal->macphymode != DUALMAC_DUALPHY) {
3680 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(16), 0x1);
3681 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(31), 0x1);
3682 }
3683 /* rssi_table_select:index 0 for 2.4G.1~3 for 5G */
3684 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, BIT(6) | BIT(7), 0x1);
3685 /* fc_area */
3686 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(14) | BIT(13), 0x1);
3687 /* 5G LAN ON */
3688 rtl_set_bbreg(hw, 0xB30, 0x00F00000, 0x0);
3689 /* TX BB gain shift,Just for testchip,0xc80,0xc88 */
3690 if (rtlefuse->internal_pa_5g[0])
3691 rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, BMASKDWORD,
3692 0x2d4000b5);
3693 else
3694 rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, BMASKDWORD,
3695 0x20000080);
3696 if (rtlefuse->internal_pa_5g[1])
3697 rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, BMASKDWORD,
3698 0x2d4000b5);
3699 else
3700 rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, BMASKDWORD,
3701 0x20000080);
3702 if (rtlhal->macphymode == DUALMAC_DUALPHY) {
3703 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW,
3704 BIT(10) | BIT(6) | BIT(5),
3705 (rtlefuse->eeprom_cc & BIT(5)));
3706 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, BIT(10),
3707 ((rtlefuse->eeprom_cc & BIT(4)) >> 4));
3708 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15),
3709 (rtlefuse->eeprom_cc & BIT(4)) >> 4);
3710 } else {
3711 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW,
3712 BIT(26) | BIT(22) | BIT(21) | BIT(10) |
3713 BIT(6) | BIT(5),
3714 (rtlefuse->eeprom_cc & BIT(5)) |
3715 ((rtlefuse->eeprom_cc & BIT(7)) << 14));
3716 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, BIT(10),
3717 ((rtlefuse->eeprom_cc & BIT(4)) >> 4));
3718 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, BIT(10),
3719 ((rtlefuse->eeprom_cc & BIT(6)) >> 6));
3720 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER,
3721 BIT(31) | BIT(15),
3722 ((rtlefuse->eeprom_cc & BIT(4)) >> 4) |
3723 ((rtlefuse->eeprom_cc & BIT(6)) << 10));
3724 }
3725 }
3726 /* update IQK related settings */
3727 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, BMASKDWORD, 0x40000100);
3728 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, BMASKDWORD, 0x40000100);
3729 rtl_set_bbreg(hw, ROFDM0_XCTxAFE, 0xF0000000, 0x00);
3730 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(30) | BIT(28) |
3731 BIT(26) | BIT(24), 0x00);
3732 rtl_set_bbreg(hw, ROFDM0_XDTxAFE, 0xF0000000, 0x00);
3733 rtl_set_bbreg(hw, 0xca0, 0xF0000000, 0x00);
3734 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0x0000F000, 0x00);
3735
3736 /* Update RF */
3737 for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath;
3738 rfpath++) {
3739 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
3740 /* MOD_AG for RF paht_A 0x18 BIT8,BIT16 */
3741 rtl_set_rfreg(hw, rfpath, RF_CHNLBW, BIT(8) | BIT(16) |
3742 BIT(18), 0);
3743 /* RF0x0b[16:14] =3b'111 */
3744 rtl_set_rfreg(hw, (enum radio_path)rfpath, 0x0B,
3745 0x1c000, 0x07);
3746 } else {
3747 /* MOD_AG for RF paht_A 0x18 BIT8,BIT16 */
3748 rtl_set_rfreg(hw, rfpath, RF_CHNLBW, BIT(8) |
3749 BIT(16) | BIT(18),
3750 (BIT(16) | BIT(8)) >> 8);
3751 }
3752 }
3753 /* Update for all band. */
3754 /* DMDP */
3755 if (rtlphy->rf_type == RF_1T1R) {
3756 /* Use antenna 0,0xc04,0xd04 */
3757 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, BMASKBYTE0, 0x11);
3758 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x1);
3759
3760 /* enable ad/da clock1 for dual-phy reg0x888 */
3761 if (rtlhal->interfaceindex == 0) {
3762 rtl_set_bbreg(hw, RFPGA0_ADDALLOCKEN, BIT(12) |
3763 BIT(13), 0x3);
3764 } else {
3765 rtl92d_phy_enable_anotherphy(hw, false);
3766 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3767 ("MAC1 use DBI to update 0x888"));
3768 /* 0x888 */
3769 rtl92de_write_dword_dbi(hw, RFPGA0_ADDALLOCKEN,
3770 rtl92de_read_dword_dbi(hw,
3771 RFPGA0_ADDALLOCKEN,
3772 BIT(3)) | BIT(12) | BIT(13),
3773 BIT(3));
3774 rtl92d_phy_powerdown_anotherphy(hw, false);
3775 }
3776 } else {
3777 /* Single PHY */
3778 /* Use antenna 0 & 1,0xc04,0xd04 */
3779 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, BMASKBYTE0, 0x33);
3780 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x3);
3781 /* disable ad/da clock1,0x888 */
3782 rtl_set_bbreg(hw, RFPGA0_ADDALLOCKEN, BIT(12) | BIT(13), 0);
3783 }
3784 for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath;
3785 rfpath++) {
3786 rtlphy->rfreg_chnlval[rfpath] = rtl_get_rfreg(hw, rfpath,
3787 RF_CHNLBW, BRFREGOFFSETMASK);
3788 rtlphy->reg_rf3c[rfpath] = rtl_get_rfreg(hw, rfpath, 0x3C,
3789 BRFREGOFFSETMASK);
3790 }
3791 for (i = 0; i < 2; i++)
3792 RT_TRACE(rtlpriv, COMP_RF, DBG_LOUD, ("RF 0x18 = 0x%x\n",
3793 rtlphy->rfreg_chnlval[i]));
3794 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("<==\n"));
3795
3796 }
3797
3798 bool rtl92d_phy_check_poweroff(struct ieee80211_hw *hw)
3799 {
3800 struct rtl_priv *rtlpriv = rtl_priv(hw);
3801 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3802 u8 u1btmp;
3803 unsigned long flags;
3804
3805 if (rtlhal->macphymode == SINGLEMAC_SINGLEPHY) {
3806 u1btmp = rtl_read_byte(rtlpriv, REG_MAC0);
3807 rtl_write_byte(rtlpriv, REG_MAC0, u1btmp & (~MAC0_ON));
3808 return true;
3809 }
3810 spin_lock_irqsave(&globalmutex_power, flags);
3811 if (rtlhal->interfaceindex == 0) {
3812 u1btmp = rtl_read_byte(rtlpriv, REG_MAC0);
3813 rtl_write_byte(rtlpriv, REG_MAC0, u1btmp & (~MAC0_ON));
3814 u1btmp = rtl_read_byte(rtlpriv, REG_MAC1);
3815 u1btmp &= MAC1_ON;
3816 } else {
3817 u1btmp = rtl_read_byte(rtlpriv, REG_MAC1);
3818 rtl_write_byte(rtlpriv, REG_MAC1, u1btmp & (~MAC1_ON));
3819 u1btmp = rtl_read_byte(rtlpriv, REG_MAC0);
3820 u1btmp &= MAC0_ON;
3821 }
3822 if (u1btmp) {
3823 spin_unlock_irqrestore(&globalmutex_power, flags);
3824 return false;
3825 }
3826 u1btmp = rtl_read_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS);
3827 u1btmp |= BIT(7);
3828 rtl_write_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS, u1btmp);
3829 spin_unlock_irqrestore(&globalmutex_power, flags);
3830 return true;
3831 }