drivers/net/wireless/wl12xx/io.c

   1 /*
   2  * This file is part of wl1271
   3  *
   4  * Copyright (C) 2008-2010 Nokia Corporation
   5  *
   6  * Contact: Luciano Coelho <luciano.coelho@nokia.com>
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License
  10  * version 2 as published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful, but
  13  * WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  20  * 02110-1301 USA
  21  *
  22  */
  23
  24 #include <linux/module.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/spi/spi.h>
  27 #include <linux/interrupt.h>
  28
  29 #include "wl12xx.h"
  30 #include "debug.h"
  31 #include "wl12xx_80211.h"
  32 #include "io.h"
  33 #include "tx.h"
  34
  35 #define OCP_CMD_LOOP  32
  36
  37 #define OCP_CMD_WRITE 0x1
  38 #define OCP_CMD_READ  0x2
  39
  40 #define OCP_READY_MASK  BIT(18)
  41 #define OCP_STATUS_MASK (BIT(16) | BIT(17))
  42
  43 #define OCP_STATUS_NO_RESP    0x00000
  44 #define OCP_STATUS_OK         0x10000
  45 #define OCP_STATUS_REQ_FAILED 0x20000
  46 #define OCP_STATUS_RESP_ERROR 0x30000
  47
  48 bool wl1271_set_block_size(struct wl1271 *wl)
  49 {
  50         if (wl->if_ops->set_block_size) {
  51                 wl->if_ops->set_block_size(wl->dev, WL12XX_BUS_BLOCK_SIZE);
  52                 return true;
  53         }
  54
  55         return false;
  56 }
  57
  58 void wl1271_disable_interrupts(struct wl1271 *wl)
  59 {
  60         disable_irq(wl->irq);
  61 }
  62
  63 void wl1271_enable_interrupts(struct wl1271 *wl)
  64 {
  65         enable_irq(wl->irq);
  66 }
  67
  68 /* Set the SPI partitions to access the chip addresses
  69  *
  70  * To simplify driver code, a fixed (virtual) memory map is defined for
  71  * register and memory addresses. Because in the chipset, in different stages
  72  * of operation, those addresses will move around, an address translation
  73  * mechanism is required.
  74  *
  75  * There are four partitions (three memory and one register partition),
  76  * which are mapped to two different areas of the hardware memory.
  77  *
  78  *                                Virtual address
  79  *                                     space
  80  *
  81  *                                    |    |
  82  *                                 ...+----+--> mem.start
  83  *          Physical address    ...   |    |
  84  *               space       ...      |    | [PART_0]
  85  *                        ...         |    |
  86  *  00000000  <--+----+...         ...+----+--> mem.start + mem.size
  87  *               |    |         ...   |    |
  88  *               |MEM |      ...      |    |
  89  *               |    |   ...         |    |
  90  *  mem.size  <--+----+...            |    | {unused area)
  91  *               |    |   ...         |    |
  92  *               |REG |      ...      |    |
  93  *  mem.size     |    |         ...   |    |
  94  *      +     <--+----+...         ...+----+--> reg.start
  95  *  reg.size     |    |   ...         |    |
  96  *               |MEM2|      ...      |    | [PART_1]
  97  *               |    |         ...   |    |
  98  *                                 ...+----+--> reg.start + reg.size
  99  *                                    |    |
 100  *
 101  */
 102 int wl1271_set_partition(struct wl1271 *wl,
 103                          struct wl1271_partition_set *p)
 104 {
 105         /* copy partition info */
 106         memcpy(&wl->part, p, sizeof(*p));
 107
 108         wl1271_debug(DEBUG_SPI, "mem_start %08X mem_size %08X",
 109                      p->mem.start, p->mem.size);
 110         wl1271_debug(DEBUG_SPI, "reg_start %08X reg_size %08X",
 111                      p->reg.start, p->reg.size);
 112         wl1271_debug(DEBUG_SPI, "mem2_start %08X mem2_size %08X",
 113                      p->mem2.start, p->mem2.size);
 114         wl1271_debug(DEBUG_SPI, "mem3_start %08X mem3_size %08X",
 115                      p->mem3.start, p->mem3.size);
 116
 117         /* write partition info to the chipset */
 118         wl1271_raw_write32(wl, HW_PART0_START_ADDR, p->mem.start);
 119         wl1271_raw_write32(wl, HW_PART0_SIZE_ADDR, p->mem.size);
 120         wl1271_raw_write32(wl, HW_PART1_START_ADDR, p->reg.start);
 121         wl1271_raw_write32(wl, HW_PART1_SIZE_ADDR, p->reg.size);
 122         wl1271_raw_write32(wl, HW_PART2_START_ADDR, p->mem2.start);
 123         wl1271_raw_write32(wl, HW_PART2_SIZE_ADDR, p->mem2.size);
 124         wl1271_raw_write32(wl, HW_PART3_START_ADDR, p->mem3.start);
 125
 126         return 0;
 127 }
 128 EXPORT_SYMBOL_GPL(wl1271_set_partition);
 129
 130 void wl1271_io_reset(struct wl1271 *wl)
 131 {
 132         if (wl->if_ops->reset)
 133                 wl->if_ops->reset(wl->dev);
 134 }
 135
 136 void wl1271_io_init(struct wl1271 *wl)
 137 {
 138         if (wl->if_ops->init)
 139                 wl->if_ops->init(wl->dev);
 140 }
 141
 142 void wl1271_top_reg_write(struct wl1271 *wl, int addr, u16 val)
 143 {
 144         /* write address >> 1 + 0x30000 to OCP_POR_CTR */
 145         addr = (addr >> 1) + 0x30000;
 146         wl1271_write32(wl, OCP_POR_CTR, addr);
 147
 148         /* write value to OCP_POR_WDATA */
 149         wl1271_write32(wl, OCP_DATA_WRITE, val);
 150
 151         /* write 1 to OCP_CMD */
 152         wl1271_write32(wl, OCP_CMD, OCP_CMD_WRITE);
 153 }
 154
 155 u16 wl1271_top_reg_read(struct wl1271 *wl, int addr)
 156 {
 157         u32 val;
 158         int timeout = OCP_CMD_LOOP;
 159
 160         /* write address >> 1 + 0x30000 to OCP_POR_CTR */
 161         addr = (addr >> 1) + 0x30000;
 162         wl1271_write32(wl, OCP_POR_CTR, addr);
 163
 164         /* write 2 to OCP_CMD */
 165         wl1271_write32(wl, OCP_CMD, OCP_CMD_READ);
 166
 167         /* poll for data ready */
 168         do {
 169                 val = wl1271_read32(wl, OCP_DATA_READ);
 170         } while (!(val & OCP_READY_MASK) && --timeout);
 171
 172         if (!timeout) {
 173                 wl1271_warning("Top register access timed out.");
 174                 return 0xffff;
 175         }
 176
 177         /* check data status and return if OK */
 178         if ((val & OCP_STATUS_MASK) == OCP_STATUS_OK)
 179                 return val & 0xffff;
 180         else {
 181                 wl1271_warning("Top register access returned error.");
 182                 return 0xffff;
 183         }
 184 }
 185