drivers/net/wireless/wl12xx/reg.h

   1 /*
   2  * This file is part of wl12xx
   3  *
   4  * Copyright (C) 1998-2009 Texas Instruments. All rights reserved.
   5  * Copyright (C) 2009 Nokia Corporation
   6  *
   7  * Contact: Luciano Coelho <luciano.coelho@nokia.com>
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License
  11  * version 2 as published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16  * General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  21  * 02110-1301 USA
  22  *
  23  */
  24
  25 #ifndef __REG_H__
  26 #define __REG_H__
  27
  28 #include <linux/bitops.h>
  29
  30 #define REGISTERS_BASE 0x00300000
  31 #define DRPW_BASE      0x00310000
  32
  33 #define REGISTERS_DOWN_SIZE 0x00008800
  34 #define REGISTERS_WORK_SIZE 0x0000b000
  35
  36 #define HW_ACCESS_ELP_CTRL_REG_ADDR         0x1FFFC
  37 #define FW_STATUS_ADDR                      (0x14FC0 + 0xA000)
  38
  39 /* ELP register commands */
  40 #define ELPCTRL_WAKE_UP             0x1
  41 #define ELPCTRL_WAKE_UP_WLAN_READY  0x5
  42 #define ELPCTRL_SLEEP               0x0
  43 /* ELP WLAN_READY bit */
  44 #define ELPCTRL_WLAN_READY          0x2
  45
  46 /*===============================================
  47    Host Software Reset - 32bit RW
  48  ------------------------------------------
  49     [31:1] Reserved
  50     0  SOFT_RESET Soft Reset  - When this bit is set,
  51     it holds the Wlan hardware in a soft reset state.
  52     This reset disables all MAC and baseband processor
  53     clocks except the CardBus/PCI interface clock.
  54     It also initializes all MAC state machines except
  55     the host interface. It does not reload the
  56     contents of the EEPROM. When this bit is cleared
  57     (not self-clearing), the Wlan hardware
  58     exits the software reset state.
  59 ===============================================*/
  60 #define ACX_REG_SLV_SOFT_RESET         (REGISTERS_BASE + 0x0000)
  61
  62 #define WL1271_SLV_REG_DATA            (REGISTERS_BASE + 0x0008)
  63 #define WL1271_SLV_REG_ADATA           (REGISTERS_BASE + 0x000c)
  64 #define WL1271_SLV_MEM_DATA            (REGISTERS_BASE + 0x0018)
  65
  66 #define ACX_REG_INTERRUPT_TRIG         (REGISTERS_BASE + 0x0474)
  67 #define ACX_REG_INTERRUPT_TRIG_H       (REGISTERS_BASE + 0x0478)
  68
  69 /*=============================================
  70   Host Interrupt Mask Register - 32bit (RW)
  71   ------------------------------------------
  72   Setting a bit in this register masks the
  73   corresponding interrupt to the host.
  74   0 - RX0               - Rx first dubble buffer Data Interrupt
  75   1 - TXD               - Tx Data Interrupt
  76   2 - TXXFR             - Tx Transfer Interrupt
  77   3 - RX1               - Rx second dubble buffer Data Interrupt
  78   4 - RXXFR             - Rx Transfer Interrupt
  79   5 - EVENT_A   - Event Mailbox interrupt
  80   6 - EVENT_B   - Event Mailbox interrupt
  81   7 - WNONHST   - Wake On Host Interrupt
  82   8 - TRACE_A   - Debug Trace interrupt
  83   9 - TRACE_B   - Debug Trace interrupt
  84  10 - CDCMP             - Command Complete Interrupt
  85  11 -
  86  12 -
  87  13 -
  88  14 - ICOMP             - Initialization Complete Interrupt
  89  16 - SG SE             - Soft Gemini - Sense enable interrupt
  90  17 - SG SD             - Soft Gemini - Sense disable interrupt
  91  18 -                   -
  92  19 -                   -
  93  20 -                   -
  94  21-                    -
  95  Default: 0x0001
  96 *==============================================*/
  97 #define ACX_REG_INTERRUPT_MASK         (REGISTERS_BASE + 0x04DC)
  98
  99 /*=============================================
 100   Host Interrupt Mask Set 16bit, (Write only)
 101   ------------------------------------------
 102  Setting a bit in this register sets
 103  the corresponding bin in ACX_HINT_MASK register
 104  without effecting the mask
 105  state of other bits (0 = no effect).
 106 ==============================================*/
 107 #define ACX_REG_HINT_MASK_SET          (REGISTERS_BASE + 0x04E0)
 108
 109 /*=============================================
 110   Host Interrupt Mask Clear 16bit,(Write only)
 111   ------------------------------------------
 112  Setting a bit in this register clears
 113  the corresponding bin in ACX_HINT_MASK register
 114  without effecting the mask
 115  state of other bits (0 = no effect).
 116 =============================================*/
 117 #define ACX_REG_HINT_MASK_CLR          (REGISTERS_BASE + 0x04E4)
 118
 119 /*=============================================
 120   Host Interrupt Status Nondestructive Read
 121   16bit,(Read only)
 122   ------------------------------------------
 123  The host can read this register to determine
 124  which interrupts are active.
 125  Reading this register doesn't
 126  effect its content.
 127 =============================================*/
 128 #define ACX_REG_INTERRUPT_NO_CLEAR     (REGISTERS_BASE + 0x04E8)
 129
 130 /*=============================================
 131   Host Interrupt Status Clear on Read  Register
 132   16bit,(Read only)
 133   ------------------------------------------
 134  The host can read this register to determine
 135  which interrupts are active.
 136  Reading this register clears it,
 137  thus making all interrupts inactive.
 138 ==============================================*/
 139 #define ACX_REG_INTERRUPT_CLEAR        (REGISTERS_BASE + 0x04F8)
 140
 141 /*=============================================
 142   Host Interrupt Acknowledge Register
 143   16bit,(Write only)
 144   ------------------------------------------
 145  The host can set individual bits in this
 146  register to clear (acknowledge) the corresp.
 147  interrupt status bits in the HINT_STS_CLR and
 148  HINT_STS_ND registers, thus making the
 149  assotiated interrupt inactive. (0-no effect)
 150 ==============================================*/
 151 #define ACX_REG_INTERRUPT_ACK          (REGISTERS_BASE + 0x04F0)
 152
 153 #define RX_DRIVER_COUNTER_ADDRESS      (REGISTERS_BASE + 0x0538)
 154
 155 /* Device Configuration registers*/
 156 #define SOR_CFG                        (REGISTERS_BASE + 0x0800)
 157
 158 /* Embedded ARM CPU Control */
 159
 160 /*===============================================
 161  Halt eCPU   - 32bit RW
 162  ------------------------------------------
 163  0 HALT_ECPU Halt Embedded CPU - This bit is the
 164  compliment of bit 1 (MDATA2) in the SOR_CFG register.
 165  During a hardware reset, this bit holds
 166  the inverse of MDATA2.
 167  When downloading firmware from the host,
 168  set this bit (pull down MDATA2).
 169  The host clears this bit after downloading the firmware into
 170  zero-wait-state SSRAM.
 171  When loading firmware from Flash, clear this bit (pull up MDATA2)
 172  so that the eCPU can run the bootloader code in Flash
 173  HALT_ECPU eCPU State
 174  --------------------
 175  1 halt eCPU
 176  0 enable eCPU
 177  ===============================================*/
 178 #define ACX_REG_ECPU_CONTROL           (REGISTERS_BASE + 0x0804)
 179
 180 #define HI_CFG                         (REGISTERS_BASE + 0x0808)
 181
 182 /*===============================================
 183  EEPROM Burst Read Start  - 32bit RW
 184  ------------------------------------------
 185  [31:1] Reserved
 186  0  ACX_EE_START -  EEPROM Burst Read Start 0
 187  Setting this bit starts a burst read from
 188  the external EEPROM.
 189  If this bit is set (after reset) before an EEPROM read/write,
 190  the burst read starts at EEPROM address 0.
 191  Otherwise, it starts at the address
 192  following the address of the previous access.
 193  TheWlan hardware hardware clears this bit automatically.
 194
 195  Default: 0x00000000
 196 *================================================*/
 197 #define ACX_REG_EE_START               (REGISTERS_BASE + 0x080C)
 198
 199 #define OCP_POR_CTR                    (REGISTERS_BASE + 0x09B4)
 200 #define OCP_DATA_WRITE                 (REGISTERS_BASE + 0x09B8)
 201 #define OCP_DATA_READ                  (REGISTERS_BASE + 0x09BC)
 202 #define OCP_CMD                        (REGISTERS_BASE + 0x09C0)
 203
 204 #define WL1271_HOST_WR_ACCESS          (REGISTERS_BASE + 0x09F8)
 205
 206 #define CHIP_ID_B                      (REGISTERS_BASE + 0x5674)
 207
 208 #define CHIP_ID_1271_PG10              (0x4030101)
 209 #define CHIP_ID_1271_PG20              (0x4030111)
 210 #define CHIP_ID_1283_PG10              (0x05030101)
 211 #define CHIP_ID_1283_PG20              (0x05030111)
 212
 213 #define ENABLE                         (REGISTERS_BASE + 0x5450)
 214
 215 /* Power Management registers */
 216 #define ELP_CFG_MODE                   (REGISTERS_BASE + 0x5804)
 217 #define ELP_CMD                        (REGISTERS_BASE + 0x5808)
 218 #define PLL_CAL_TIME                   (REGISTERS_BASE + 0x5810)
 219 #define CLK_REQ_TIME                   (REGISTERS_BASE + 0x5814)
 220 #define CLK_BUF_TIME                   (REGISTERS_BASE + 0x5818)
 221
 222 #define CFG_PLL_SYNC_CNT               (REGISTERS_BASE + 0x5820)
 223
 224 /* Scratch Pad registers*/
 225 #define SCR_PAD0                       (REGISTERS_BASE + 0x5608)
 226 #define SCR_PAD1                       (REGISTERS_BASE + 0x560C)
 227 #define SCR_PAD2                       (REGISTERS_BASE + 0x5610)
 228 #define SCR_PAD3                       (REGISTERS_BASE + 0x5614)
 229 #define SCR_PAD4                       (REGISTERS_BASE + 0x5618)
 230 #define SCR_PAD4_SET                   (REGISTERS_BASE + 0x561C)
 231 #define SCR_PAD4_CLR                   (REGISTERS_BASE + 0x5620)
 232 #define SCR_PAD5                       (REGISTERS_BASE + 0x5624)
 233 #define SCR_PAD5_SET                   (REGISTERS_BASE + 0x5628)
 234 #define SCR_PAD5_CLR                   (REGISTERS_BASE + 0x562C)
 235 #define SCR_PAD6                       (REGISTERS_BASE + 0x5630)
 236 #define SCR_PAD7                       (REGISTERS_BASE + 0x5634)
 237 #define SCR_PAD8                       (REGISTERS_BASE + 0x5638)
 238 #define SCR_PAD9                       (REGISTERS_BASE + 0x563C)
 239
 240 /* Spare registers*/
 241 #define SPARE_A1                       (REGISTERS_BASE + 0x0994)
 242 #define SPARE_A2                       (REGISTERS_BASE + 0x0998)
 243 #define SPARE_A3                       (REGISTERS_BASE + 0x099C)
 244 #define SPARE_A4                       (REGISTERS_BASE + 0x09A0)
 245 #define SPARE_A5                       (REGISTERS_BASE + 0x09A4)
 246 #define SPARE_A6                       (REGISTERS_BASE + 0x09A8)
 247 #define SPARE_A7                       (REGISTERS_BASE + 0x09AC)
 248 #define SPARE_A8                       (REGISTERS_BASE + 0x09B0)
 249 #define SPARE_B1                       (REGISTERS_BASE + 0x5420)
 250 #define SPARE_B2                       (REGISTERS_BASE + 0x5424)
 251 #define SPARE_B3                       (REGISTERS_BASE + 0x5428)
 252 #define SPARE_B4                       (REGISTERS_BASE + 0x542C)
 253 #define SPARE_B5                       (REGISTERS_BASE + 0x5430)
 254 #define SPARE_B6                       (REGISTERS_BASE + 0x5434)
 255 #define SPARE_B7                       (REGISTERS_BASE + 0x5438)
 256 #define SPARE_B8                       (REGISTERS_BASE + 0x543C)
 257
 258 #define PLL_PARAMETERS                 (REGISTERS_BASE + 0x6040)
 259 #define WU_COUNTER_PAUSE               (REGISTERS_BASE + 0x6008)
 260 #define WELP_ARM_COMMAND               (REGISTERS_BASE + 0x6100)
 261 #define DRPW_SCRATCH_START             (DRPW_BASE + 0x002C)
 262
 263
 264 #define ACX_SLV_SOFT_RESET_BIT   BIT(1)
 265 #define ACX_REG_EEPROM_START_BIT BIT(1)
 266
 267 /* Command/Information Mailbox Pointers */
 268
 269 /*===============================================
 270   Command Mailbox Pointer - 32bit RW
 271  ------------------------------------------
 272  This register holds the start address of
 273  the command mailbox located in the Wlan hardware memory.
 274  The host must read this pointer after a reset to
 275  find the location of the command mailbox.
 276  The Wlan hardware initializes the command mailbox
 277  pointer with the default address of the command mailbox.
 278  The command mailbox pointer is not valid until after
 279  the host receives the Init Complete interrupt from
 280  the Wlan hardware.
 281  ===============================================*/
 282 #define REG_COMMAND_MAILBOX_PTR                         (SCR_PAD0)
 283
 284 /*===============================================
 285   Information Mailbox Pointer - 32bit RW
 286  ------------------------------------------
 287  This register holds the start address of
 288  the information mailbox located in the Wlan hardware memory.
 289  The host must read this pointer after a reset to find
 290  the location of the information mailbox.
 291  The Wlan hardware initializes the information mailbox pointer
 292  with the default address of the information mailbox.
 293  The information mailbox pointer is not valid
 294  until after the host receives the Init Complete interrupt from
 295  the Wlan hardware.
 296  ===============================================*/
 297 #define REG_EVENT_MAILBOX_PTR                           (SCR_PAD1)
 298
 299 /*===============================================
 300  EEPROM Read/Write Request 32bit RW
 301  ------------------------------------------
 302  1 EE_READ - EEPROM Read Request 1 - Setting this bit
 303  loads a single byte of data into the EE_DATA
 304  register from the EEPROM location specified in
 305  the EE_ADDR register.
 306  The Wlan hardware hardware clears this bit automatically.
 307  EE_DATA is valid when this bit is cleared.
 308
 309  0 EE_WRITE  - EEPROM Write Request  - Setting this bit
 310  writes a single byte of data from the EE_DATA register into the
 311  EEPROM location specified in the EE_ADDR register.
 312  The Wlan hardware hardware clears this bit automatically.
 313 *===============================================*/
 314 #define ACX_EE_CTL_REG                      EE_CTL
 315 #define EE_WRITE                            0x00000001ul
 316 #define EE_READ                             0x00000002ul
 317
 318 /*===============================================
 319   EEPROM Address  - 32bit RW
 320   ------------------------------------------
 321   This register specifies the address
 322   within the EEPROM from/to which to read/write data.
 323   ===============================================*/
 324 #define ACX_EE_ADDR_REG                     EE_ADDR
 325
 326 /*===============================================
 327   EEPROM Data  - 32bit RW
 328   ------------------------------------------
 329   This register either holds the read 8 bits of
 330   data from the EEPROM or the write data
 331   to be written to the EEPROM.
 332   ===============================================*/
 333 #define ACX_EE_DATA_REG                     EE_DATA
 334
 335 /*===============================================
 336   EEPROM Base Address  - 32bit RW
 337   ------------------------------------------
 338   This register holds the upper nine bits
 339   [23:15] of the 24-bit Wlan hardware memory
 340   address for burst reads from EEPROM accesses.
 341   The EEPROM provides the lower 15 bits of this address.
 342   The MSB of the address from the EEPROM is ignored.
 343   ===============================================*/
 344 #define ACX_EE_CFG                          EE_CFG
 345
 346 /*===============================================
 347   GPIO Output Values  -32bit, RW
 348   ------------------------------------------
 349   [31:16]  Reserved
 350   [15: 0]  Specify the output values (at the output driver inputs) for
 351   GPIO[15:0], respectively.
 352   ===============================================*/
 353 #define ACX_GPIO_OUT_REG            GPIO_OUT
 354 #define ACX_MAX_GPIO_LINES          15
 355
 356 /*===============================================
 357   Contention window  -32bit, RW
 358   ------------------------------------------
 359   [31:26]  Reserved
 360   [25:16]  Max (0x3ff)
 361   [15:07]  Reserved
 362   [06:00]  Current contention window value - default is 0x1F
 363   ===============================================*/
 364 #define ACX_CONT_WIND_CFG_REG    CONT_WIND_CFG
 365 #define ACX_CONT_WIND_MIN_MASK   0x0000007f
 366 #define ACX_CONT_WIND_MAX        0x03ff0000
 367
 368 /*===============================================
 369   HI_CFG Interface Configuration Register Values
 370   ------------------------------------------
 371   ===============================================*/
 372 #define HI_CFG_UART_ENABLE          0x00000004
 373 #define HI_CFG_RST232_ENABLE        0x00000008
 374 #define HI_CFG_CLOCK_REQ_SELECT     0x00000010
 375 #define HI_CFG_HOST_INT_ENABLE      0x00000020
 376 #define HI_CFG_VLYNQ_OUTPUT_ENABLE  0x00000040
 377 #define HI_CFG_HOST_INT_ACTIVE_LOW  0x00000080
 378 #define HI_CFG_UART_TX_OUT_GPIO_15  0x00000100
 379 #define HI_CFG_UART_TX_OUT_GPIO_14  0x00000200
 380 #define HI_CFG_UART_TX_OUT_GPIO_7   0x00000400
 381
 382 #define HI_CFG_DEF_VAL              \
 383         (HI_CFG_UART_ENABLE |        \
 384         HI_CFG_RST232_ENABLE |      \
 385         HI_CFG_CLOCK_REQ_SELECT |   \
 386         HI_CFG_HOST_INT_ENABLE)
 387
 388 #define REF_FREQ_19_2                       0
 389 #define REF_FREQ_26_0                       1
 390 #define REF_FREQ_38_4                       2
 391 #define REF_FREQ_40_0                       3
 392 #define REF_FREQ_33_6                       4
 393 #define REF_FREQ_NUM                        5
 394
 395 #define LUT_PARAM_INTEGER_DIVIDER           0
 396 #define LUT_PARAM_FRACTIONAL_DIVIDER        1
 397 #define LUT_PARAM_ATTN_BB                   2
 398 #define LUT_PARAM_ALPHA_BB                  3
 399 #define LUT_PARAM_STOP_TIME_BB              4
 400 #define LUT_PARAM_BB_PLL_LOOP_FILTER        5
 401 #define LUT_PARAM_NUM                       6
 402
 403 #define ACX_EEPROMLESS_IND_REG              (SCR_PAD4)
 404 #define USE_EEPROM                          0
 405 #define SOFT_RESET_MAX_TIME                 1000000
 406 #define SOFT_RESET_STALL_TIME               1000
 407 #define NVS_DATA_BUNDARY_ALIGNMENT          4
 408
 409
 410 /* Firmware image load chunk size */
 411 #define CHUNK_SIZE      16384
 412
 413 /* Firmware image header size */
 414 #define FW_HDR_SIZE 8
 415
 416 #define ECPU_CONTROL_HALT                                       0x00000101
 417
 418
 419 /******************************************************************************
 420
 421     CHANNELS, BAND & REG DOMAINS definitions
 422
 423 ******************************************************************************/
 424
 425
 426 enum {
 427         RADIO_BAND_2_4GHZ = 0,  /* 2.4 Ghz band */
 428         RADIO_BAND_5GHZ = 1,    /* 5 Ghz band */
 429         RADIO_BAND_JAPAN_4_9_GHZ = 2,
 430         DEFAULT_BAND = RADIO_BAND_2_4GHZ,
 431         INVALID_BAND = 0xFE,
 432         MAX_RADIO_BANDS = 0xFF
 433 };
 434
 435 #define SHORT_PREAMBLE_BIT   BIT(0) /* CCK or Barker depending on the rate */
 436 #define OFDM_RATE_BIT        BIT(6)
 437 #define PBCC_RATE_BIT        BIT(7)
 438
 439 enum {
 440         CCK_LONG = 0,
 441         CCK_SHORT = SHORT_PREAMBLE_BIT,
 442         PBCC_LONG = PBCC_RATE_BIT,
 443         PBCC_SHORT = PBCC_RATE_BIT | SHORT_PREAMBLE_BIT,
 444         OFDM = OFDM_RATE_BIT
 445 };
 446
 447 /******************************************************************************
 448
 449 Transmit-Descriptor RATE-SET field definitions...
 450
 451 Define a new "Rate-Set" for TX path that incorporates the
 452 Rate & Modulation info into a single 16-bit field.
 453
 454 TxdRateSet_t:
 455 b15   - Indicates Preamble type (1=SHORT, 0=LONG).
 456         Notes:
 457         Must be LONG (0) for 1Mbps rate.
 458         Does not apply (set to 0) for RevG-OFDM rates.
 459 b14   - Indicates PBCC encoding (1=PBCC, 0=not).
 460         Notes:
 461         Does not apply (set to 0) for rates 1 and 2 Mbps.
 462         Does not apply (set to 0) for RevG-OFDM rates.
 463 b13    - Unused (set to 0).
 464 b12-b0 - Supported Rate indicator bits as defined below.
 465
 466 ******************************************************************************/
 467
 468
 469 /*************************************************************************
 470
 471     Interrupt Trigger Register (Host -> WiLink)
 472
 473 **************************************************************************/
 474
 475 /* Hardware to Embedded CPU Interrupts - first 32-bit register set */
 476
 477 /*
 478  * Host Command Interrupt. Setting this bit masks
 479  * the interrupt that the host issues to inform
 480  * the FW that it has sent a command
 481  * to the Wlan hardware Command Mailbox.
 482  */
 483 #define INTR_TRIG_CMD       BIT(0)
 484
 485 /*
 486  * Host Event Acknowlegde Interrupt. The host
 487  * sets this bit to acknowledge that it received
 488  * the unsolicited information from the event
 489  * mailbox.
 490  */
 491 #define INTR_TRIG_EVENT_ACK BIT(1)
 492
 493 /*
 494  * The host sets this bit to inform the Wlan
 495  * FW that a TX packet is in the XFER
 496  * Buffer #0.
 497  */
 498 #define INTR_TRIG_TX_PROC0 BIT(2)
 499
 500 /*
 501  * The host sets this bit to inform the FW
 502  * that it read a packet from RX XFER
 503  * Buffer #0.
 504  */
 505 #define INTR_TRIG_RX_PROC0 BIT(3)
 506
 507 #define INTR_TRIG_DEBUG_ACK BIT(4)
 508
 509 #define INTR_TRIG_STATE_CHANGED BIT(5)
 510
 511
 512 /* Hardware to Embedded CPU Interrupts - second 32-bit register set */
 513
 514 /*
 515  * The host sets this bit to inform the FW
 516  * that it read a packet from RX XFER
 517  * Buffer #1.
 518  */
 519 #define INTR_TRIG_RX_PROC1 BIT(17)
 520
 521 /*
 522  * The host sets this bit to inform the Wlan
 523  * hardware that a TX packet is in the XFER
 524  * Buffer #1.
 525  */
 526 #define INTR_TRIG_TX_PROC1 BIT(18)
 527
 528 #endif