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spi-topcliff-pch: add recovery processing in case wait-event timeout
[zen-stable.git] / drivers / scsi / megaraid / megaraid_sas_fusion.h
blob088c9f91da95fc4f2a0da32e427502dcde3ea267
1 /*
2 * Linux MegaRAID driver for SAS based RAID controllers
3 *
4 * Copyright (c) 2009-2011 LSI Corporation.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 *
20 * FILE: megaraid_sas_fusion.h
21 *
22 * Authors: LSI Corporation
23 * Manoj Jose
24 * Sumant Patro
25 *
26 * Send feedback to: <megaraidlinux@lsi.com>
27 *
28 * Mail to: LSI Corporation, 1621 Barber Lane, Milpitas, CA 95035
29 * ATTN: Linuxraid
30 */
31
32 #ifndef _MEGARAID_SAS_FUSION_H_
33 #define _MEGARAID_SAS_FUSION_H_
34
35 /* Fusion defines */
36 #define MEGASAS_MAX_SZ_CHAIN_FRAME 1024
37 #define MFI_FUSION_ENABLE_INTERRUPT_MASK (0x00000009)
38 #define MEGA_MPI2_RAID_DEFAULT_IO_FRAME_SIZE 256
39 #define MEGASAS_MPI2_FUNCTION_PASSTHRU_IO_REQUEST 0xF0
40 #define MEGASAS_MPI2_FUNCTION_LD_IO_REQUEST 0xF1
41 #define MEGASAS_LOAD_BALANCE_FLAG 0x1
42 #define MEGASAS_DCMD_MBOX_PEND_FLAG 0x1
43 #define HOST_DIAG_WRITE_ENABLE 0x80
44 #define HOST_DIAG_RESET_ADAPTER 0x4
45 #define MEGASAS_FUSION_MAX_RESET_TRIES 3
46 #define MAX_MSIX_QUEUES_FUSION 16
47
48 /* Invader defines */
49 #define MPI2_TYPE_CUDA 0x2
50 #define MPI25_SAS_DEVICE0_FLAGS_ENABLED_FAST_PATH 0x4000
51 #define MR_RL_FLAGS_GRANT_DESTINATION_CPU0 0x00
52 #define MR_RL_FLAGS_GRANT_DESTINATION_CPU1 0x10
53 #define MR_RL_FLAGS_GRANT_DESTINATION_CUDA 0x80
54 #define MR_RL_FLAGS_SEQ_NUM_ENABLE 0x8
55
56 /* T10 PI defines */
57 #define MR_PROT_INFO_TYPE_CONTROLLER 0x8
58 #define MEGASAS_SCSI_VARIABLE_LENGTH_CMD 0x7f
59 #define MEGASAS_SCSI_SERVICE_ACTION_READ32 0x9
60 #define MEGASAS_SCSI_SERVICE_ACTION_WRITE32 0xB
61 #define MEGASAS_SCSI_ADDL_CDB_LEN 0x18
62 #define MEGASAS_RD_WR_PROTECT_CHECK_ALL 0x20
63 #define MEGASAS_RD_WR_PROTECT_CHECK_NONE 0x60
64 #define MEGASAS_EEDPBLOCKSIZE 512
65
66 /*
67 * Raid context flags
68 */
69
70 #define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_SHIFT 0x4
71 #define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_MASK 0x30
72 enum MR_RAID_FLAGS_IO_SUB_TYPE {
73 MR_RAID_FLAGS_IO_SUB_TYPE_NONE = 0,
74 MR_RAID_FLAGS_IO_SUB_TYPE_SYSTEM_PD = 1,
75 };
76
77 /*
78 * Request descriptor types
79 */
80 #define MEGASAS_REQ_DESCRIPT_FLAGS_LD_IO 0x7
81 #define MEGASAS_REQ_DESCRIPT_FLAGS_MFA 0x1
82 #define MEGASAS_REQ_DESCRIPT_FLAGS_NO_LOCK 0x2
83 #define MEGASAS_REQ_DESCRIPT_FLAGS_TYPE_SHIFT 1
84
85 #define MEGASAS_FP_CMD_LEN 16
86 #define MEGASAS_FUSION_IN_RESET 0
87
88 /*
89 * Raid Context structure which describes MegaRAID specific IO Paramenters
90 * This resides at offset 0x60 where the SGL normally starts in MPT IO Frames
91 */
92
93 struct RAID_CONTEXT {
94 u8 Type:4;
95 u8 nseg:4;
96 u8 resvd0;
97 u16 timeoutValue;
98 u8 regLockFlags;
99 u8 resvd1;
100 u16 VirtualDiskTgtId;
101 u64 regLockRowLBA;
102 u32 regLockLength;
103 u16 nextLMId;
104 u8 exStatus;
105 u8 status;
106 u8 RAIDFlags;
107 u8 numSGE;
108 u16 configSeqNum;
109 u8 spanArm;
110 u8 resvd2[3];
111 };
112
113 #define RAID_CTX_SPANARM_ARM_SHIFT (0)
114 #define RAID_CTX_SPANARM_ARM_MASK (0x1f)
115
116 #define RAID_CTX_SPANARM_SPAN_SHIFT (5)
117 #define RAID_CTX_SPANARM_SPAN_MASK (0xE0)
118
119 /*
120 * define region lock types
121 */
122 enum REGION_TYPE {
123 REGION_TYPE_UNUSED = 0,
124 REGION_TYPE_SHARED_READ = 1,
125 REGION_TYPE_SHARED_WRITE = 2,
126 REGION_TYPE_EXCLUSIVE = 3,
127 };
128
129 /* MPI2 defines */
130 #define MPI2_FUNCTION_IOC_INIT (0x02) /* IOC Init */
131 #define MPI2_WHOINIT_HOST_DRIVER (0x04)
132 #define MPI2_VERSION_MAJOR (0x02)
133 #define MPI2_VERSION_MINOR (0x00)
134 #define MPI2_VERSION_MAJOR_MASK (0xFF00)
135 #define MPI2_VERSION_MAJOR_SHIFT (8)
136 #define MPI2_VERSION_MINOR_MASK (0x00FF)
137 #define MPI2_VERSION_MINOR_SHIFT (0)
138 #define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \
139 MPI2_VERSION_MINOR)
140 #define MPI2_HEADER_VERSION_UNIT (0x10)
141 #define MPI2_HEADER_VERSION_DEV (0x00)
142 #define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00)
143 #define MPI2_HEADER_VERSION_UNIT_SHIFT (8)
144 #define MPI2_HEADER_VERSION_DEV_MASK (0x00FF)
145 #define MPI2_HEADER_VERSION_DEV_SHIFT (0)
146 #define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | \
147 MPI2_HEADER_VERSION_DEV)
148 #define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03)
149 #define MPI2_SCSIIO_EEDPFLAGS_INC_PRI_REFTAG (0x8000)
150 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_REFTAG (0x0400)
151 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_REMOVE_OP (0x0003)
152 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_APPTAG (0x0200)
153 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_GUARD (0x0100)
154 #define MPI2_SCSIIO_EEDPFLAGS_INSERT_OP (0x0004)
155 #define MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) /* SCSI IO */
156 #define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06)
157 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00)
158 #define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02)
159 #define MPI2_SCSIIO_CONTROL_WRITE (0x01000000)
160 #define MPI2_SCSIIO_CONTROL_READ (0x02000000)
161 #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x0E)
162 #define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F)
163 #define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00)
164 #define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F)
165 #define MPI2_WRSEQ_FLUSH_KEY_VALUE (0x0)
166 #define MPI2_WRITE_SEQUENCE_OFFSET (0x00000004)
167 #define MPI2_WRSEQ_1ST_KEY_VALUE (0xF)
168 #define MPI2_WRSEQ_2ND_KEY_VALUE (0x4)
169 #define MPI2_WRSEQ_3RD_KEY_VALUE (0xB)
170 #define MPI2_WRSEQ_4TH_KEY_VALUE (0x2)
171 #define MPI2_WRSEQ_5TH_KEY_VALUE (0x7)
172 #define MPI2_WRSEQ_6TH_KEY_VALUE (0xD)
173
174 struct MPI25_IEEE_SGE_CHAIN64 {
175 u64 Address;
176 u32 Length;
177 u16 Reserved1;
178 u8 NextChainOffset;
179 u8 Flags;
180 };
181
182 struct MPI2_SGE_SIMPLE_UNION {
183 u32 FlagsLength;
184 union {
185 u32 Address32;
186 u64 Address64;
187 } u;
188 };
189
190 struct MPI2_SCSI_IO_CDB_EEDP32 {
191 u8 CDB[20]; /* 0x00 */
192 u32 PrimaryReferenceTag; /* 0x14 */
193 u16 PrimaryApplicationTag; /* 0x18 */
194 u16 PrimaryApplicationTagMask; /* 0x1A */
195 u32 TransferLength; /* 0x1C */
196 };
197
198 struct MPI2_SGE_CHAIN_UNION {
199 u16 Length;
200 u8 NextChainOffset;
201 u8 Flags;
202 union {
203 u32 Address32;
204 u64 Address64;
205 } u;
206 };
207
208 struct MPI2_IEEE_SGE_SIMPLE32 {
209 u32 Address;
210 u32 FlagsLength;
211 };
212
213 struct MPI2_IEEE_SGE_CHAIN32 {
214 u32 Address;
215 u32 FlagsLength;
216 };
217
218 struct MPI2_IEEE_SGE_SIMPLE64 {
219 u64 Address;
220 u32 Length;
221 u16 Reserved1;
222 u8 Reserved2;
223 u8 Flags;
224 };
225
226 struct MPI2_IEEE_SGE_CHAIN64 {
227 u64 Address;
228 u32 Length;
229 u16 Reserved1;
230 u8 Reserved2;
231 u8 Flags;
232 };
233
234 union MPI2_IEEE_SGE_SIMPLE_UNION {
235 struct MPI2_IEEE_SGE_SIMPLE32 Simple32;
236 struct MPI2_IEEE_SGE_SIMPLE64 Simple64;
237 };
238
239 union MPI2_IEEE_SGE_CHAIN_UNION {
240 struct MPI2_IEEE_SGE_CHAIN32 Chain32;
241 struct MPI2_IEEE_SGE_CHAIN64 Chain64;
242 };
243
244 union MPI2_SGE_IO_UNION {
245 struct MPI2_SGE_SIMPLE_UNION MpiSimple;
246 struct MPI2_SGE_CHAIN_UNION MpiChain;
247 union MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple;
248 union MPI2_IEEE_SGE_CHAIN_UNION IeeeChain;
249 };
250
251 union MPI2_SCSI_IO_CDB_UNION {
252 u8 CDB32[32];
253 struct MPI2_SCSI_IO_CDB_EEDP32 EEDP32;
254 struct MPI2_SGE_SIMPLE_UNION SGE;
255 };
256
257 /*
258 * RAID SCSI IO Request Message
259 * Total SGE count will be one less than _MPI2_SCSI_IO_REQUEST
260 */
261 struct MPI2_RAID_SCSI_IO_REQUEST {
262 u16 DevHandle; /* 0x00 */
263 u8 ChainOffset; /* 0x02 */
264 u8 Function; /* 0x03 */
265 u16 Reserved1; /* 0x04 */
266 u8 Reserved2; /* 0x06 */
267 u8 MsgFlags; /* 0x07 */
268 u8 VP_ID; /* 0x08 */
269 u8 VF_ID; /* 0x09 */
270 u16 Reserved3; /* 0x0A */
271 u32 SenseBufferLowAddress; /* 0x0C */
272 u16 SGLFlags; /* 0x10 */
273 u8 SenseBufferLength; /* 0x12 */
274 u8 Reserved4; /* 0x13 */
275 u8 SGLOffset0; /* 0x14 */
276 u8 SGLOffset1; /* 0x15 */
277 u8 SGLOffset2; /* 0x16 */
278 u8 SGLOffset3; /* 0x17 */
279 u32 SkipCount; /* 0x18 */
280 u32 DataLength; /* 0x1C */
281 u32 BidirectionalDataLength; /* 0x20 */
282 u16 IoFlags; /* 0x24 */
283 u16 EEDPFlags; /* 0x26 */
284 u32 EEDPBlockSize; /* 0x28 */
285 u32 SecondaryReferenceTag; /* 0x2C */
286 u16 SecondaryApplicationTag; /* 0x30 */
287 u16 ApplicationTagTranslationMask; /* 0x32 */
288 u8 LUN[8]; /* 0x34 */
289 u32 Control; /* 0x3C */
290 union MPI2_SCSI_IO_CDB_UNION CDB; /* 0x40 */
291 struct RAID_CONTEXT RaidContext; /* 0x60 */
292 union MPI2_SGE_IO_UNION SGL; /* 0x80 */
293 };
294
295 /*
296 * MPT RAID MFA IO Descriptor.
297 */
298 struct MEGASAS_RAID_MFA_IO_REQUEST_DESCRIPTOR {
299 u32 RequestFlags:8;
300 u32 MessageAddress1:24; /* bits 31:8*/
301 u32 MessageAddress2; /* bits 61:32 */
302 };
303
304 /* Default Request Descriptor */
305 struct MPI2_DEFAULT_REQUEST_DESCRIPTOR {
306 u8 RequestFlags; /* 0x00 */
307 u8 MSIxIndex; /* 0x01 */
308 u16 SMID; /* 0x02 */
309 u16 LMID; /* 0x04 */
310 u16 DescriptorTypeDependent; /* 0x06 */
311 };
312
313 /* High Priority Request Descriptor */
314 struct MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR {
315 u8 RequestFlags; /* 0x00 */
316 u8 MSIxIndex; /* 0x01 */
317 u16 SMID; /* 0x02 */
318 u16 LMID; /* 0x04 */
319 u16 Reserved1; /* 0x06 */
320 };
321
322 /* SCSI IO Request Descriptor */
323 struct MPI2_SCSI_IO_REQUEST_DESCRIPTOR {
324 u8 RequestFlags; /* 0x00 */
325 u8 MSIxIndex; /* 0x01 */
326 u16 SMID; /* 0x02 */
327 u16 LMID; /* 0x04 */
328 u16 DevHandle; /* 0x06 */
329 };
330
331 /* SCSI Target Request Descriptor */
332 struct MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR {
333 u8 RequestFlags; /* 0x00 */
334 u8 MSIxIndex; /* 0x01 */
335 u16 SMID; /* 0x02 */
336 u16 LMID; /* 0x04 */
337 u16 IoIndex; /* 0x06 */
338 };
339
340 /* RAID Accelerator Request Descriptor */
341 struct MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR {
342 u8 RequestFlags; /* 0x00 */
343 u8 MSIxIndex; /* 0x01 */
344 u16 SMID; /* 0x02 */
345 u16 LMID; /* 0x04 */
346 u16 Reserved; /* 0x06 */
347 };
348
349 /* union of Request Descriptors */
350 union MEGASAS_REQUEST_DESCRIPTOR_UNION {
351 struct MPI2_DEFAULT_REQUEST_DESCRIPTOR Default;
352 struct MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR HighPriority;
353 struct MPI2_SCSI_IO_REQUEST_DESCRIPTOR SCSIIO;
354 struct MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR SCSITarget;
355 struct MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR RAIDAccelerator;
356 struct MEGASAS_RAID_MFA_IO_REQUEST_DESCRIPTOR MFAIo;
357 union {
358 struct {
359 u32 low;
360 u32 high;
361 } u;
362 u64 Words;
363 };
364 };
365
366 /* Default Reply Descriptor */
367 struct MPI2_DEFAULT_REPLY_DESCRIPTOR {
368 u8 ReplyFlags; /* 0x00 */
369 u8 MSIxIndex; /* 0x01 */
370 u16 DescriptorTypeDependent1; /* 0x02 */
371 u32 DescriptorTypeDependent2; /* 0x04 */
372 };
373
374 /* Address Reply Descriptor */
375 struct MPI2_ADDRESS_REPLY_DESCRIPTOR {
376 u8 ReplyFlags; /* 0x00 */
377 u8 MSIxIndex; /* 0x01 */
378 u16 SMID; /* 0x02 */
379 u32 ReplyFrameAddress; /* 0x04 */
380 };
381
382 /* SCSI IO Success Reply Descriptor */
383 struct MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR {
384 u8 ReplyFlags; /* 0x00 */
385 u8 MSIxIndex; /* 0x01 */
386 u16 SMID; /* 0x02 */
387 u16 TaskTag; /* 0x04 */
388 u16 Reserved1; /* 0x06 */
389 };
390
391 /* TargetAssist Success Reply Descriptor */
392 struct MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR {
393 u8 ReplyFlags; /* 0x00 */
394 u8 MSIxIndex; /* 0x01 */
395 u16 SMID; /* 0x02 */
396 u8 SequenceNumber; /* 0x04 */
397 u8 Reserved1; /* 0x05 */
398 u16 IoIndex; /* 0x06 */
399 };
400
401 /* Target Command Buffer Reply Descriptor */
402 struct MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR {
403 u8 ReplyFlags; /* 0x00 */
404 u8 MSIxIndex; /* 0x01 */
405 u8 VP_ID; /* 0x02 */
406 u8 Flags; /* 0x03 */
407 u16 InitiatorDevHandle; /* 0x04 */
408 u16 IoIndex; /* 0x06 */
409 };
410
411 /* RAID Accelerator Success Reply Descriptor */
412 struct MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR {
413 u8 ReplyFlags; /* 0x00 */
414 u8 MSIxIndex; /* 0x01 */
415 u16 SMID; /* 0x02 */
416 u32 Reserved; /* 0x04 */
417 };
418
419 /* union of Reply Descriptors */
420 union MPI2_REPLY_DESCRIPTORS_UNION {
421 struct MPI2_DEFAULT_REPLY_DESCRIPTOR Default;
422 struct MPI2_ADDRESS_REPLY_DESCRIPTOR AddressReply;
423 struct MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR SCSIIOSuccess;
424 struct MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR TargetAssistSuccess;
425 struct MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer;
426 struct MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR
427 RAIDAcceleratorSuccess;
428 u64 Words;
429 };
430
431 /* IOCInit Request message */
432 struct MPI2_IOC_INIT_REQUEST {
433 u8 WhoInit; /* 0x00 */
434 u8 Reserved1; /* 0x01 */
435 u8 ChainOffset; /* 0x02 */
436 u8 Function; /* 0x03 */
437 u16 Reserved2; /* 0x04 */
438 u8 Reserved3; /* 0x06 */
439 u8 MsgFlags; /* 0x07 */
440 u8 VP_ID; /* 0x08 */
441 u8 VF_ID; /* 0x09 */
442 u16 Reserved4; /* 0x0A */
443 u16 MsgVersion; /* 0x0C */
444 u16 HeaderVersion; /* 0x0E */
445 u32 Reserved5; /* 0x10 */
446 u16 Reserved6; /* 0x14 */
447 u8 Reserved7; /* 0x16 */
448 u8 HostMSIxVectors; /* 0x17 */
449 u16 Reserved8; /* 0x18 */
450 u16 SystemRequestFrameSize; /* 0x1A */
451 u16 ReplyDescriptorPostQueueDepth; /* 0x1C */
452 u16 ReplyFreeQueueDepth; /* 0x1E */
453 u32 SenseBufferAddressHigh; /* 0x20 */
454 u32 SystemReplyAddressHigh; /* 0x24 */
455 u64 SystemRequestFrameBaseAddress; /* 0x28 */
456 u64 ReplyDescriptorPostQueueAddress;/* 0x30 */
457 u64 ReplyFreeQueueAddress; /* 0x38 */
458 u64 TimeStamp; /* 0x40 */
459 };
460
461 /* mrpriv defines */
462 #define MR_PD_INVALID 0xFFFF
463 #define MAX_SPAN_DEPTH 8
464 #define MAX_RAIDMAP_SPAN_DEPTH (MAX_SPAN_DEPTH)
465 #define MAX_ROW_SIZE 32
466 #define MAX_RAIDMAP_ROW_SIZE (MAX_ROW_SIZE)
467 #define MAX_LOGICAL_DRIVES 64
468 #define MAX_RAIDMAP_LOGICAL_DRIVES (MAX_LOGICAL_DRIVES)
469 #define MAX_RAIDMAP_VIEWS (MAX_LOGICAL_DRIVES)
470 #define MAX_ARRAYS 128
471 #define MAX_RAIDMAP_ARRAYS (MAX_ARRAYS)
472 #define MAX_PHYSICAL_DEVICES 256
473 #define MAX_RAIDMAP_PHYSICAL_DEVICES (MAX_PHYSICAL_DEVICES)
474 #define MR_DCMD_LD_MAP_GET_INFO 0x0300e101
475
476 struct MR_DEV_HANDLE_INFO {
477 u16 curDevHdl;
478 u8 validHandles;
479 u8 reserved;
480 u16 devHandle[2];
481 };
482
483 struct MR_ARRAY_INFO {
484 u16 pd[MAX_RAIDMAP_ROW_SIZE];
485 };
486
487 struct MR_QUAD_ELEMENT {
488 u64 logStart;
489 u64 logEnd;
490 u64 offsetInSpan;
491 u32 diff;
492 u32 reserved1;
493 };
494
495 struct MR_SPAN_INFO {
496 u32 noElements;
497 u32 reserved1;
498 struct MR_QUAD_ELEMENT quad[MAX_RAIDMAP_SPAN_DEPTH];
499 };
500
501 struct MR_LD_SPAN {
502 u64 startBlk;
503 u64 numBlks;
504 u16 arrayRef;
505 u8 reserved[6];
506 };
507
508 struct MR_SPAN_BLOCK_INFO {
509 u64 num_rows;
510 struct MR_LD_SPAN span;
511 struct MR_SPAN_INFO block_span_info;
512 };
513
514 struct MR_LD_RAID {
515 struct {
516 u32 fpCapable:1;
517 u32 reserved5:3;
518 u32 ldPiMode:4;
519 u32 pdPiMode:4;
520 u32 encryptionType:8;
521 u32 fpWriteCapable:1;
522 u32 fpReadCapable:1;
523 u32 fpWriteAcrossStripe:1;
524 u32 fpReadAcrossStripe:1;
525 u32 reserved4:8;
526 } capability;
527 u32 reserved6;
528 u64 size;
529 u8 spanDepth;
530 u8 level;
531 u8 stripeShift;
532 u8 rowSize;
533 u8 rowDataSize;
534 u8 writeMode;
535 u8 PRL;
536 u8 SRL;
537 u16 targetId;
538 u8 ldState;
539 u8 regTypeReqOnWrite;
540 u8 modFactor;
541 u8 regTypeReqOnRead;
542 u16 seqNum;
543
544 struct {
545 u32 ldSyncRequired:1;
546 u32 reserved:31;
547 } flags;
548
549 u8 reserved3[0x5C];
550 };
551
552 struct MR_LD_SPAN_MAP {
553 struct MR_LD_RAID ldRaid;
554 u8 dataArmMap[MAX_RAIDMAP_ROW_SIZE];
555 struct MR_SPAN_BLOCK_INFO spanBlock[MAX_RAIDMAP_SPAN_DEPTH];
556 };
557
558 struct MR_FW_RAID_MAP {
559 u32 totalSize;
560 union {
561 struct {
562 u32 maxLd;
563 u32 maxSpanDepth;
564 u32 maxRowSize;
565 u32 maxPdCount;
566 u32 maxArrays;
567 } validationInfo;
568 u32 version[5];
569 u32 reserved1[5];
570 };
571
572 u32 ldCount;
573 u32 Reserved1;
574 u8 ldTgtIdToLd[MAX_RAIDMAP_LOGICAL_DRIVES+
575 MAX_RAIDMAP_VIEWS];
576 u8 fpPdIoTimeoutSec;
577 u8 reserved2[7];
578 struct MR_ARRAY_INFO arMapInfo[MAX_RAIDMAP_ARRAYS];
579 struct MR_DEV_HANDLE_INFO devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES];
580 struct MR_LD_SPAN_MAP ldSpanMap[1];
581 };
582
583 struct IO_REQUEST_INFO {
584 u64 ldStartBlock;
585 u32 numBlocks;
586 u16 ldTgtId;
587 u8 isRead;
588 u16 devHandle;
589 u64 pdBlock;
590 u8 fpOkForIo;
591 };
592
593 struct MR_LD_TARGET_SYNC {
594 u8 targetId;
595 u8 reserved;
596 u16 seqNum;
597 };
598
599 #define IEEE_SGE_FLAGS_ADDR_MASK (0x03)
600 #define IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00)
601 #define IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01)
602 #define IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02)
603 #define IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03)
604 #define IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80)
605 #define IEEE_SGE_FLAGS_END_OF_LIST (0x40)
606
607 struct megasas_register_set;
608 struct megasas_instance;
609
610 union desc_word {
611 u64 word;
612 struct {
613 u32 low;
614 u32 high;
615 } u;
616 };
617
618 struct megasas_cmd_fusion {
619 struct MPI2_RAID_SCSI_IO_REQUEST *io_request;
620 dma_addr_t io_request_phys_addr;
621
622 union MPI2_SGE_IO_UNION *sg_frame;
623 dma_addr_t sg_frame_phys_addr;
624
625 u8 *sense;
626 dma_addr_t sense_phys_addr;
627
628 struct list_head list;
629 struct scsi_cmnd *scmd;
630 struct megasas_instance *instance;
631
632 u8 retry_for_fw_reset;
633 union MEGASAS_REQUEST_DESCRIPTOR_UNION *request_desc;
634
635 /*
636 * Context for a MFI frame.
637 * Used to get the mfi cmd from list when a MFI cmd is completed
638 */
639 u32 sync_cmd_idx;
640 u32 index;
641 u8 flags;
642 };
643
644 struct LD_LOAD_BALANCE_INFO {
645 u8 loadBalanceFlag;
646 u8 reserved1;
647 u16 raid1DevHandle[2];
648 atomic_t scsi_pending_cmds[2];
649 u64 last_accessed_block[2];
650 };
651
652 struct MR_FW_RAID_MAP_ALL {
653 struct MR_FW_RAID_MAP raidMap;
654 struct MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES - 1];
655 } __attribute__ ((packed));
656
657 struct fusion_context {
658 struct megasas_cmd_fusion **cmd_list;
659 struct list_head cmd_pool;
660
661 spinlock_t cmd_pool_lock;
662
663 dma_addr_t req_frames_desc_phys;
664 u8 *req_frames_desc;
665
666 struct dma_pool *io_request_frames_pool;
667 dma_addr_t io_request_frames_phys;
668 u8 *io_request_frames;
669
670 struct dma_pool *sg_dma_pool;
671 struct dma_pool *sense_dma_pool;
672
673 dma_addr_t reply_frames_desc_phys;
674 union MPI2_REPLY_DESCRIPTORS_UNION *reply_frames_desc;
675 struct dma_pool *reply_frames_desc_pool;
676
677 u16 last_reply_idx[MAX_MSIX_QUEUES_FUSION];
678
679 u32 reply_q_depth;
680 u32 request_alloc_sz;
681 u32 reply_alloc_sz;
682 u32 io_frames_alloc_sz;
683
684 u16 max_sge_in_main_msg;
685 u16 max_sge_in_chain;
686
687 u8 chain_offset_io_request;
688 u8 chain_offset_mfi_pthru;
689
690 struct MR_FW_RAID_MAP_ALL *ld_map[2];
691 dma_addr_t ld_map_phys[2];
692
693 u32 map_sz;
694 u8 fast_path_io;
695 struct LD_LOAD_BALANCE_INFO load_balance_info[MAX_LOGICAL_DRIVES];
696 };
697
698 union desc_value {
699 u64 word;
700 struct {
701 u32 low;
702 u32 high;
703 } u;
704 };
705
706 #endif /* _MEGARAID_SAS_FUSION_H_ */