drivers/usb/host/ehci-pci.c

   1 /*
   2  * EHCI HCD (Host Controller Driver) PCI Bus Glue.
   3  *
   4  * Copyright (c) 2000-2004 by David Brownell
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License as published by the
   8  * Free Software Foundation; either version 2 of the License, or (at your
   9  * option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful, but
  12  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  14  * for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software Foundation,
  18  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  19  */
  20
  21 #ifndef CONFIG_PCI
  22 #error "This file is PCI bus glue.  CONFIG_PCI must be defined."
  23 #endif
  24
  25 /* defined here to avoid adding to pci_ids.h for single instance use */
  26 #define PCI_DEVICE_ID_INTEL_CE4100_USB  0x2e70
  27
  28 /*-------------------------------------------------------------------------*/
  29
  30 /* called after powerup, by probe or system-pm "wakeup" */
  31 static int ehci_pci_reinit(struct ehci_hcd *ehci, struct pci_dev *pdev)
  32 {
  33         int                     retval;
  34
  35         /* we expect static quirk code to handle the "extended capabilities"
  36          * (currently just BIOS handoff) allowed starting with EHCI 0.96
  37          */
  38
  39         /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
  40         retval = pci_set_mwi(pdev);
  41         if (!retval)
  42                 ehci_dbg(ehci, "MWI active\n");
  43
  44         return 0;
  45 }
  46
  47 /* called during probe() after chip reset completes */
  48 static int ehci_pci_setup(struct usb_hcd *hcd)
  49 {
  50         struct ehci_hcd         *ehci = hcd_to_ehci(hcd);
  51         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
  52         struct pci_dev          *p_smbus;
  53         u8                      rev;
  54         u32                     temp;
  55         int                     retval;
  56
  57         switch (pdev->vendor) {
  58         case PCI_VENDOR_ID_TOSHIBA_2:
  59                 /* celleb's companion chip */
  60                 if (pdev->device == 0x01b5) {
  61 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
  62                         ehci->big_endian_mmio = 1;
  63 #else
  64                         ehci_warn(ehci,
  65                                   "unsupported big endian Toshiba quirk\n");
  66 #endif
  67                 }
  68                 break;
  69         }
  70
  71         ehci->caps = hcd->regs;
  72         ehci->regs = hcd->regs +
  73                 HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase));
  74
  75         dbg_hcs_params(ehci, "reset");
  76         dbg_hcc_params(ehci, "reset");
  77
  78         /* ehci_init() causes memory for DMA transfers to be
  79          * allocated.  Thus, any vendor-specific workarounds based on
  80          * limiting the type of memory used for DMA transfers must
  81          * happen before ehci_init() is called. */
  82         switch (pdev->vendor) {
  83         case PCI_VENDOR_ID_NVIDIA:
  84                 /* NVidia reports that certain chips don't handle
  85                  * QH, ITD, or SITD addresses above 2GB.  (But TD,
  86                  * data buffer, and periodic schedule are normal.)
  87                  */
  88                 switch (pdev->device) {
  89                 case 0x003c:    /* MCP04 */
  90                 case 0x005b:    /* CK804 */
  91                 case 0x00d8:    /* CK8 */
  92                 case 0x00e8:    /* CK8S */
  93                         if (pci_set_consistent_dma_mask(pdev,
  94                                                 DMA_BIT_MASK(31)) < 0)
  95                                 ehci_warn(ehci, "can't enable NVidia "
  96                                         "workaround for >2GB RAM\n");
  97                         break;
  98                 }
  99                 break;
 100         }
 101
 102         /* cache this readonly data; minimize chip reads */
 103         ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
 104
 105         retval = ehci_halt(ehci);
 106         if (retval)
 107                 return retval;
 108
 109         if ((pdev->vendor == PCI_VENDOR_ID_AMD && pdev->device == 0x7808) ||
 110             (pdev->vendor == PCI_VENDOR_ID_ATI && pdev->device == 0x4396)) {
 111                 /* EHCI controller on AMD SB700/SB800/Hudson-2/3 platforms may
 112                  * read/write memory space which does not belong to it when
 113                  * there is NULL pointer with T-bit set to 1 in the frame list
 114                  * table. To avoid the issue, the frame list link pointer
 115                  * should always contain a valid pointer to a inactive qh.
 116                  */
 117                 ehci->use_dummy_qh = 1;
 118                 ehci_info(ehci, "applying AMD SB700/SB800/Hudson-2/3 EHCI "
 119                                 "dummy qh workaround\n");
 120         }
 121
 122         /* data structure init */
 123         retval = ehci_init(hcd);
 124         if (retval)
 125                 return retval;
 126
 127         switch (pdev->vendor) {
 128         case PCI_VENDOR_ID_NEC:
 129                 ehci->need_io_watchdog = 0;
 130                 break;
 131         case PCI_VENDOR_ID_INTEL:
 132                 ehci->need_io_watchdog = 0;
 133                 ehci->fs_i_thresh = 1;
 134                 if (pdev->device == 0x27cc) {
 135                         ehci->broken_periodic = 1;
 136                         ehci_info(ehci, "using broken periodic workaround\n");
 137                 }
 138                 if (pdev->device == 0x0806 || pdev->device == 0x0811
 139                                 || pdev->device == 0x0829) {
 140                         ehci_info(ehci, "disable lpm for langwell/penwell\n");
 141                         ehci->has_lpm = 0;
 142                 }
 143                 if (pdev->device == PCI_DEVICE_ID_INTEL_CE4100_USB) {
 144                         hcd->has_tt = 1;
 145                         tdi_reset(ehci);
 146                 }
 147                 if (pdev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK) {
 148                         /* EHCI #1 or #2 on 6 Series/C200 Series chipset */
 149                         if (pdev->device == 0x1c26 || pdev->device == 0x1c2d) {
 150                                 ehci_info(ehci, "broken D3 during system sleep on ASUS\n");
 151                                 hcd->broken_pci_sleep = 1;
 152                                 device_set_wakeup_capable(&pdev->dev, false);
 153                         }
 154                 }
 155                 break;
 156         case PCI_VENDOR_ID_TDI:
 157                 if (pdev->device == PCI_DEVICE_ID_TDI_EHCI) {
 158                         hcd->has_tt = 1;
 159                         tdi_reset(ehci);
 160                 }
 161                 break;
 162         case PCI_VENDOR_ID_AMD:
 163                 /* AMD PLL quirk */
 164                 if (usb_amd_find_chipset_info())
 165                         ehci->amd_pll_fix = 1;
 166                 /* AMD8111 EHCI doesn't work, according to AMD errata */
 167                 if (pdev->device == 0x7463) {
 168                         ehci_info(ehci, "ignoring AMD8111 (errata)\n");
 169                         retval = -EIO;
 170                         goto done;
 171                 }
 172                 break;
 173         case PCI_VENDOR_ID_NVIDIA:
 174                 switch (pdev->device) {
 175                 /* Some NForce2 chips have problems with selective suspend;
 176                  * fixed in newer silicon.
 177                  */
 178                 case 0x0068:
 179                         if (pdev->revision < 0xa4)
 180                                 ehci->no_selective_suspend = 1;
 181                         break;
 182
 183                 /* MCP89 chips on the MacBookAir3,1 give EPROTO when
 184                  * fetching device descriptors unless LPM is disabled.
 185                  * There are also intermittent problems enumerating
 186                  * devices with PPCD enabled.
 187                  */
 188                 case 0x0d9d:
 189                         ehci_info(ehci, "disable lpm/ppcd for nvidia mcp89");
 190                         ehci->has_lpm = 0;
 191                         ehci->has_ppcd = 0;
 192                         ehci->command &= ~CMD_PPCEE;
 193                         break;
 194                 }
 195                 break;
 196         case PCI_VENDOR_ID_VIA:
 197                 if (pdev->device == 0x3104 && (pdev->revision & 0xf0) == 0x60) {
 198                         u8 tmp;
 199
 200                         /* The VT6212 defaults to a 1 usec EHCI sleep time which
 201                          * hogs the PCI bus *badly*. Setting bit 5 of 0x4B makes
 202                          * that sleep time use the conventional 10 usec.
 203                          */
 204                         pci_read_config_byte(pdev, 0x4b, &tmp);
 205                         if (tmp & 0x20)
 206                                 break;
 207                         pci_write_config_byte(pdev, 0x4b, tmp | 0x20);
 208                 }
 209                 break;
 210         case PCI_VENDOR_ID_ATI:
 211                 /* AMD PLL quirk */
 212                 if (usb_amd_find_chipset_info())
 213                         ehci->amd_pll_fix = 1;
 214                 /* SB600 and old version of SB700 have a bug in EHCI controller,
 215                  * which causes usb devices lose response in some cases.
 216                  */
 217                 if ((pdev->device == 0x4386) || (pdev->device == 0x4396)) {
 218                         p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
 219                                                  PCI_DEVICE_ID_ATI_SBX00_SMBUS,
 220                                                  NULL);
 221                         if (!p_smbus)
 222                                 break;
 223                         rev = p_smbus->revision;
 224                         if ((pdev->device == 0x4386) || (rev == 0x3a)
 225                             || (rev == 0x3b)) {
 226                                 u8 tmp;
 227                                 ehci_info(ehci, "applying AMD SB600/SB700 USB "
 228                                         "freeze workaround\n");
 229                                 pci_read_config_byte(pdev, 0x53, &tmp);
 230                                 pci_write_config_byte(pdev, 0x53, tmp | (1<<3));
 231                         }
 232                         pci_dev_put(p_smbus);
 233                 }
 234                 break;
 235         case PCI_VENDOR_ID_NETMOS:
 236                 /* MosChip frame-index-register bug */
 237                 ehci_info(ehci, "applying MosChip frame-index workaround\n");
 238                 ehci->frame_index_bug = 1;
 239                 break;
 240         }
 241
 242         /* optional debug port, normally in the first BAR */
 243         temp = pci_find_capability(pdev, 0x0a);
 244         if (temp) {
 245                 pci_read_config_dword(pdev, temp, &temp);
 246                 temp >>= 16;
 247                 if ((temp & (3 << 13)) == (1 << 13)) {
 248                         temp &= 0x1fff;
 249                         ehci->debug = ehci_to_hcd(ehci)->regs + temp;
 250                         temp = ehci_readl(ehci, &ehci->debug->control);
 251                         ehci_info(ehci, "debug port %d%s\n",
 252                                 HCS_DEBUG_PORT(ehci->hcs_params),
 253                                 (temp & DBGP_ENABLED)
 254                                         ? " IN USE"
 255                                         : "");
 256                         if (!(temp & DBGP_ENABLED))
 257                                 ehci->debug = NULL;
 258                 }
 259         }
 260
 261         ehci_reset(ehci);
 262
 263         /* at least the Genesys GL880S needs fixup here */
 264         temp = HCS_N_CC(ehci->hcs_params) * HCS_N_PCC(ehci->hcs_params);
 265         temp &= 0x0f;
 266         if (temp && HCS_N_PORTS(ehci->hcs_params) > temp) {
 267                 ehci_dbg(ehci, "bogus port configuration: "
 268                         "cc=%d x pcc=%d < ports=%d\n",
 269                         HCS_N_CC(ehci->hcs_params),
 270                         HCS_N_PCC(ehci->hcs_params),
 271                         HCS_N_PORTS(ehci->hcs_params));
 272
 273                 switch (pdev->vendor) {
 274                 case 0x17a0:            /* GENESYS */
 275                         /* GL880S: should be PORTS=2 */
 276                         temp |= (ehci->hcs_params & ~0xf);
 277                         ehci->hcs_params = temp;
 278                         break;
 279                 case PCI_VENDOR_ID_NVIDIA:
 280                         /* NF4: should be PCC=10 */
 281                         break;
 282                 }
 283         }
 284
 285         /* Serial Bus Release Number is at PCI 0x60 offset */
 286         pci_read_config_byte(pdev, 0x60, &ehci->sbrn);
 287         if (pdev->vendor == PCI_VENDOR_ID_STMICRO
 288             && pdev->device == PCI_DEVICE_ID_STMICRO_USB_HOST)
 289                 ehci->sbrn = 0x20; /* ConneXT has no sbrn register */
 290
 291         /* Keep this around for a while just in case some EHCI
 292          * implementation uses legacy PCI PM support.  This test
 293          * can be removed on 17 Dec 2009 if the dev_warn() hasn't
 294          * been triggered by then.
 295          */
 296         if (!device_can_wakeup(&pdev->dev)) {
 297                 u16     port_wake;
 298
 299                 pci_read_config_word(pdev, 0x62, &port_wake);
 300                 if (port_wake & 0x0001) {
 301                         dev_warn(&pdev->dev, "Enabling legacy PCI PM\n");
 302                         device_set_wakeup_capable(&pdev->dev, 1);
 303                 }
 304         }
 305
 306 #ifdef  CONFIG_USB_SUSPEND
 307         /* REVISIT: the controller works fine for wakeup iff the root hub
 308          * itself is "globally" suspended, but usbcore currently doesn't
 309          * understand such things.
 310          *
 311          * System suspend currently expects to be able to suspend the entire
 312          * device tree, device-at-a-time.  If we failed selective suspend
 313          * reports, system suspend would fail; so the root hub code must claim
 314          * success.  That's lying to usbcore, and it matters for runtime
 315          * PM scenarios with selective suspend and remote wakeup...
 316          */
 317         if (ehci->no_selective_suspend && device_can_wakeup(&pdev->dev))
 318                 ehci_warn(ehci, "selective suspend/wakeup unavailable\n");
 319 #endif
 320
 321         ehci_port_power(ehci, 1);
 322         retval = ehci_pci_reinit(ehci, pdev);
 323 done:
 324         return retval;
 325 }
 326
 327 /*-------------------------------------------------------------------------*/
 328
 329 #ifdef  CONFIG_PM
 330
 331 /* suspend/resume, section 4.3 */
 332
 333 /* These routines rely on the PCI bus glue
 334  * to handle powerdown and wakeup, and currently also on
 335  * transceivers that don't need any software attention to set up
 336  * the right sort of wakeup.
 337  * Also they depend on separate root hub suspend/resume.
 338  */
 339
 340 static int ehci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
 341 {
 342         struct ehci_hcd         *ehci = hcd_to_ehci(hcd);
 343         unsigned long           flags;
 344         int                     rc = 0;
 345
 346         if (time_before(jiffies, ehci->next_statechange))
 347                 msleep(10);
 348
 349         /* Root hub was already suspended. Disable irq emission and
 350          * mark HW unaccessible.  The PM and USB cores make sure that
 351          * the root hub is either suspended or stopped.
 352          */
 353         ehci_prepare_ports_for_controller_suspend(ehci, do_wakeup);
 354         spin_lock_irqsave (&ehci->lock, flags);
 355         ehci_writel(ehci, 0, &ehci->regs->intr_enable);
 356         (void)ehci_readl(ehci, &ehci->regs->intr_enable);
 357
 358         clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
 359         spin_unlock_irqrestore (&ehci->lock, flags);
 360
 361         // could save FLADJ in case of Vaux power loss
 362         // ... we'd only use it to handle clock skew
 363
 364         return rc;
 365 }
 366
 367 static bool usb_is_intel_switchable_ehci(struct pci_dev *pdev)
 368 {
 369         return pdev->class == PCI_CLASS_SERIAL_USB_EHCI &&
 370                 pdev->vendor == PCI_VENDOR_ID_INTEL &&
 371                 pdev->device == 0x1E26;
 372 }
 373
 374 static void ehci_enable_xhci_companion(void)
 375 {
 376         struct pci_dev          *companion = NULL;
 377
 378         /* The xHCI and EHCI controllers are not on the same PCI slot */
 379         for_each_pci_dev(companion) {
 380                 if (!usb_is_intel_switchable_xhci(companion))
 381                         continue;
 382                 usb_enable_xhci_ports(companion);
 383                 return;
 384         }
 385 }
 386
 387 static int ehci_pci_resume(struct usb_hcd *hcd, bool hibernated)
 388 {
 389         struct ehci_hcd         *ehci = hcd_to_ehci(hcd);
 390         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 391
 392         /* The BIOS on systems with the Intel Panther Point chipset may or may
 393          * not support xHCI natively.  That means that during system resume, it
 394          * may switch the ports back to EHCI so that users can use their
 395          * keyboard to select a kernel from GRUB after resume from hibernate.
 396          *
 397          * The BIOS is supposed to remember whether the OS had xHCI ports
 398          * enabled before resume, and switch the ports back to xHCI when the
 399          * BIOS/OS semaphore is written, but we all know we can't trust BIOS
 400          * writers.
 401          *
 402          * Unconditionally switch the ports back to xHCI after a system resume.
 403          * We can't tell whether the EHCI or xHCI controller will be resumed
 404          * first, so we have to do the port switchover in both drivers.  Writing
 405          * a '1' to the port switchover registers should have no effect if the
 406          * port was already switched over.
 407          */
 408         if (usb_is_intel_switchable_ehci(pdev))
 409                 ehci_enable_xhci_companion();
 410
 411         // maybe restore FLADJ
 412
 413         if (time_before(jiffies, ehci->next_statechange))
 414                 msleep(100);
 415
 416         /* Mark hardware accessible again as we are out of D3 state by now */
 417         set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
 418
 419         /* If CF is still set and we aren't resuming from hibernation
 420          * then we maintained PCI Vaux power.
 421          * Just undo the effect of ehci_pci_suspend().
 422          */
 423         if (ehci_readl(ehci, &ehci->regs->configured_flag) == FLAG_CF &&
 424                                 !hibernated) {
 425                 int     mask = INTR_MASK;
 426
 427                 ehci_prepare_ports_for_controller_resume(ehci);
 428                 if (!hcd->self.root_hub->do_remote_wakeup)
 429                         mask &= ~STS_PCD;
 430                 ehci_writel(ehci, mask, &ehci->regs->intr_enable);
 431                 ehci_readl(ehci, &ehci->regs->intr_enable);
 432                 return 0;
 433         }
 434
 435         usb_root_hub_lost_power(hcd->self.root_hub);
 436
 437         /* Else reset, to cope with power loss or flush-to-storage
 438          * style "resume" having let BIOS kick in during reboot.
 439          */
 440         (void) ehci_halt(ehci);
 441         (void) ehci_reset(ehci);
 442         (void) ehci_pci_reinit(ehci, pdev);
 443
 444         /* emptying the schedule aborts any urbs */
 445         spin_lock_irq(&ehci->lock);
 446         if (ehci->reclaim)
 447                 end_unlink_async(ehci);
 448         ehci_work(ehci);
 449         spin_unlock_irq(&ehci->lock);
 450
 451         ehci_writel(ehci, ehci->command, &ehci->regs->command);
 452         ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag);
 453         ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */
 454
 455         /* here we "know" root ports should always stay powered */
 456         ehci_port_power(ehci, 1);
 457
 458         ehci->rh_state = EHCI_RH_SUSPENDED;
 459         return 0;
 460 }
 461 #endif
 462
 463 static int ehci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
 464 {
 465         struct ehci_hcd *ehci = hcd_to_ehci(hcd);
 466         int rc = 0;
 467
 468         if (!udev->parent) /* udev is root hub itself, impossible */
 469                 rc = -1;
 470         /* we only support lpm device connected to root hub yet */
 471         if (ehci->has_lpm && !udev->parent->parent) {
 472                 rc = ehci_lpm_set_da(ehci, udev->devnum, udev->portnum);
 473                 if (!rc)
 474                         rc = ehci_lpm_check(ehci, udev->portnum);
 475         }
 476         return rc;
 477 }
 478
 479 static const struct hc_driver ehci_pci_hc_driver = {
 480         .description =          hcd_name,
 481         .product_desc =         "EHCI Host Controller",
 482         .hcd_priv_size =        sizeof(struct ehci_hcd),
 483
 484         /*
 485          * generic hardware linkage
 486          */
 487         .irq =                  ehci_irq,
 488         .flags =                HCD_MEMORY | HCD_USB2,
 489
 490         /*
 491          * basic lifecycle operations
 492          */
 493         .reset =                ehci_pci_setup,
 494         .start =                ehci_run,
 495 #ifdef  CONFIG_PM
 496         .pci_suspend =          ehci_pci_suspend,
 497         .pci_resume =           ehci_pci_resume,
 498 #endif
 499         .stop =                 ehci_stop,
 500         .shutdown =             ehci_shutdown,
 501
 502         /*
 503          * managing i/o requests and associated device resources
 504          */
 505         .urb_enqueue =          ehci_urb_enqueue,
 506         .urb_dequeue =          ehci_urb_dequeue,
 507         .endpoint_disable =     ehci_endpoint_disable,
 508         .endpoint_reset =       ehci_endpoint_reset,
 509
 510         /*
 511          * scheduling support
 512          */
 513         .get_frame_number =     ehci_get_frame,
 514
 515         /*
 516          * root hub support
 517          */
 518         .hub_status_data =      ehci_hub_status_data,
 519         .hub_control =          ehci_hub_control,
 520         .bus_suspend =          ehci_bus_suspend,
 521         .bus_resume =           ehci_bus_resume,
 522         .relinquish_port =      ehci_relinquish_port,
 523         .port_handed_over =     ehci_port_handed_over,
 524
 525         /*
 526          * call back when device connected and addressed
 527          */
 528         .update_device =        ehci_update_device,
 529
 530         .clear_tt_buffer_complete       = ehci_clear_tt_buffer_complete,
 531 };
 532
 533 /*-------------------------------------------------------------------------*/
 534
 535 /* PCI driver selection metadata; PCI hotplugging uses this */
 536 static const struct pci_device_id pci_ids [] = { {
 537         /* handle any USB 2.0 EHCI controller */
 538         PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_EHCI, ~0),
 539         .driver_data =  (unsigned long) &ehci_pci_hc_driver,
 540         }, {
 541         PCI_VDEVICE(STMICRO, PCI_DEVICE_ID_STMICRO_USB_HOST),
 542         .driver_data = (unsigned long) &ehci_pci_hc_driver,
 543         },
 544         { /* end: all zeroes */ }
 545 };
 546 MODULE_DEVICE_TABLE(pci, pci_ids);
 547
 548 /* pci driver glue; this is a "new style" PCI driver module */
 549 static struct pci_driver ehci_pci_driver = {
 550         .name =         (char *) hcd_name,
 551         .id_table =     pci_ids,
 552
 553         .probe =        usb_hcd_pci_probe,
 554         .remove =       usb_hcd_pci_remove,
 555         .shutdown =     usb_hcd_pci_shutdown,
 556
 557 #ifdef CONFIG_PM_SLEEP
 558         .driver =       {
 559                 .pm =   &usb_hcd_pci_pm_ops
 560         },
 561 #endif
 562 };