?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
spi-topcliff-pch: add recovery processing in case wait-event timeout
[zen-stable.git] / sound / pci / hda / hda_intel.c
blobf0032c712d095fbb40dc053c2f3810746aaaae5d
1 /*
2 *
3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
37 #include <linux/delay.h>
38 #include <linux/interrupt.h>
39 #include <linux/kernel.h>
40 #include <linux/module.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/moduleparam.h>
43 #include <linux/init.h>
44 #include <linux/slab.h>
45 #include <linux/pci.h>
46 #include <linux/mutex.h>
47 #include <linux/reboot.h>
48 #include <linux/io.h>
49 #ifdef CONFIG_X86
50 /* for snoop control */
51 #include <asm/pgtable.h>
52 #include <asm/cacheflush.h>
53 #endif
54 #include <sound/core.h>
55 #include <sound/initval.h>
56 #include "hda_codec.h"
57
58
59 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
60 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
61 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
62 static char *model[SNDRV_CARDS];
63 static int position_fix[SNDRV_CARDS];
64 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
65 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
66 static int probe_only[SNDRV_CARDS];
67 static bool single_cmd;
68 static int enable_msi = -1;
69 #ifdef CONFIG_SND_HDA_PATCH_LOADER
70 static char *patch[SNDRV_CARDS];
71 #endif
72 #ifdef CONFIG_SND_HDA_INPUT_BEEP
73 static int beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
74 CONFIG_SND_HDA_INPUT_BEEP_MODE};
75 #endif
76
77 module_param_array(index, int, NULL, 0444);
78 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
79 module_param_array(id, charp, NULL, 0444);
80 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
81 module_param_array(enable, bool, NULL, 0444);
82 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
83 module_param_array(model, charp, NULL, 0444);
84 MODULE_PARM_DESC(model, "Use the given board model.");
85 module_param_array(position_fix, int, NULL, 0444);
86 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
87 "(0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO).");
88 module_param_array(bdl_pos_adj, int, NULL, 0644);
89 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
90 module_param_array(probe_mask, int, NULL, 0444);
91 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
92 module_param_array(probe_only, int, NULL, 0444);
93 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
94 module_param(single_cmd, bool, 0444);
95 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
96 "(for debugging only).");
97 module_param(enable_msi, int, 0444);
98 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
99 #ifdef CONFIG_SND_HDA_PATCH_LOADER
100 module_param_array(patch, charp, NULL, 0444);
101 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
102 #endif
103 #ifdef CONFIG_SND_HDA_INPUT_BEEP
104 module_param_array(beep_mode, int, NULL, 0444);
105 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
106 "(0=off, 1=on, 2=mute switch on/off) (default=1).");
107 #endif
108
109 #ifdef CONFIG_SND_HDA_POWER_SAVE
110 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
111 module_param(power_save, int, 0644);
112 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
113 "(in second, 0 = disable).");
114
115 /* reset the HD-audio controller in power save mode.
116 * this may give more power-saving, but will take longer time to
117 * wake up.
118 */
119 static bool power_save_controller = 1;
120 module_param(power_save_controller, bool, 0644);
121 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
122 #endif
123
124 static bool align_buffer_size = 1;
125 module_param(align_buffer_size, bool, 0644);
126 MODULE_PARM_DESC(align_buffer_size,
127 "Force buffer and period sizes to be multiple of 128 bytes.");
128
129 #ifdef CONFIG_X86
130 static bool hda_snoop = true;
131 module_param_named(snoop, hda_snoop, bool, 0444);
132 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
133 #define azx_snoop(chip) (chip)->snoop
134 #else
135 #define hda_snoop true
136 #define azx_snoop(chip) true
137 #endif
138
139
140 MODULE_LICENSE("GPL");
141 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
142 "{Intel, ICH6M},"
143 "{Intel, ICH7},"
144 "{Intel, ESB2},"
145 "{Intel, ICH8},"
146 "{Intel, ICH9},"
147 "{Intel, ICH10},"
148 "{Intel, PCH},"
149 "{Intel, CPT},"
150 "{Intel, PPT},"
151 "{Intel, PBG},"
152 "{Intel, SCH},"
153 "{ATI, SB450},"
154 "{ATI, SB600},"
155 "{ATI, RS600},"
156 "{ATI, RS690},"
157 "{ATI, RS780},"
158 "{ATI, R600},"
159 "{ATI, RV630},"
160 "{ATI, RV610},"
161 "{ATI, RV670},"
162 "{ATI, RV635},"
163 "{ATI, RV620},"
164 "{ATI, RV770},"
165 "{VIA, VT8251},"
166 "{VIA, VT8237A},"
167 "{SiS, SIS966},"
168 "{ULI, M5461}}");
169 MODULE_DESCRIPTION("Intel HDA driver");
170
171 #ifdef CONFIG_SND_VERBOSE_PRINTK
172 #define SFX /* nop */
173 #else
174 #define SFX "hda-intel: "
175 #endif
176
177 /*
178 * registers
179 */
180 #define ICH6_REG_GCAP 0x00
181 #define ICH6_GCAP_64OK (1 << 0) /* 64bit address support */
182 #define ICH6_GCAP_NSDO (3 << 1) /* # of serial data out signals */
183 #define ICH6_GCAP_BSS (31 << 3) /* # of bidirectional streams */
184 #define ICH6_GCAP_ISS (15 << 8) /* # of input streams */
185 #define ICH6_GCAP_OSS (15 << 12) /* # of output streams */
186 #define ICH6_REG_VMIN 0x02
187 #define ICH6_REG_VMAJ 0x03
188 #define ICH6_REG_OUTPAY 0x04
189 #define ICH6_REG_INPAY 0x06
190 #define ICH6_REG_GCTL 0x08
191 #define ICH6_GCTL_RESET (1 << 0) /* controller reset */
192 #define ICH6_GCTL_FCNTRL (1 << 1) /* flush control */
193 #define ICH6_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */
194 #define ICH6_REG_WAKEEN 0x0c
195 #define ICH6_REG_STATESTS 0x0e
196 #define ICH6_REG_GSTS 0x10
197 #define ICH6_GSTS_FSTS (1 << 1) /* flush status */
198 #define ICH6_REG_INTCTL 0x20
199 #define ICH6_REG_INTSTS 0x24
200 #define ICH6_REG_WALLCLK 0x30 /* 24Mhz source */
201 #define ICH6_REG_OLD_SSYNC 0x34 /* SSYNC for old ICH */
202 #define ICH6_REG_SSYNC 0x38
203 #define ICH6_REG_CORBLBASE 0x40
204 #define ICH6_REG_CORBUBASE 0x44
205 #define ICH6_REG_CORBWP 0x48
206 #define ICH6_REG_CORBRP 0x4a
207 #define ICH6_CORBRP_RST (1 << 15) /* read pointer reset */
208 #define ICH6_REG_CORBCTL 0x4c
209 #define ICH6_CORBCTL_RUN (1 << 1) /* enable DMA */
210 #define ICH6_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */
211 #define ICH6_REG_CORBSTS 0x4d
212 #define ICH6_CORBSTS_CMEI (1 << 0) /* memory error indication */
213 #define ICH6_REG_CORBSIZE 0x4e
214
215 #define ICH6_REG_RIRBLBASE 0x50
216 #define ICH6_REG_RIRBUBASE 0x54
217 #define ICH6_REG_RIRBWP 0x58
218 #define ICH6_RIRBWP_RST (1 << 15) /* write pointer reset */
219 #define ICH6_REG_RINTCNT 0x5a
220 #define ICH6_REG_RIRBCTL 0x5c
221 #define ICH6_RBCTL_IRQ_EN (1 << 0) /* enable IRQ */
222 #define ICH6_RBCTL_DMA_EN (1 << 1) /* enable DMA */
223 #define ICH6_RBCTL_OVERRUN_EN (1 << 2) /* enable overrun irq */
224 #define ICH6_REG_RIRBSTS 0x5d
225 #define ICH6_RBSTS_IRQ (1 << 0) /* response irq */
226 #define ICH6_RBSTS_OVERRUN (1 << 2) /* overrun irq */
227 #define ICH6_REG_RIRBSIZE 0x5e
228
229 #define ICH6_REG_IC 0x60
230 #define ICH6_REG_IR 0x64
231 #define ICH6_REG_IRS 0x68
232 #define ICH6_IRS_VALID (1<<1)
233 #define ICH6_IRS_BUSY (1<<0)
234
235 #define ICH6_REG_DPLBASE 0x70
236 #define ICH6_REG_DPUBASE 0x74
237 #define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
238
239 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
240 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
241
242 /* stream register offsets from stream base */
243 #define ICH6_REG_SD_CTL 0x00
244 #define ICH6_REG_SD_STS 0x03
245 #define ICH6_REG_SD_LPIB 0x04
246 #define ICH6_REG_SD_CBL 0x08
247 #define ICH6_REG_SD_LVI 0x0c
248 #define ICH6_REG_SD_FIFOW 0x0e
249 #define ICH6_REG_SD_FIFOSIZE 0x10
250 #define ICH6_REG_SD_FORMAT 0x12
251 #define ICH6_REG_SD_BDLPL 0x18
252 #define ICH6_REG_SD_BDLPU 0x1c
253
254 /* PCI space */
255 #define ICH6_PCIREG_TCSEL 0x44
256
257 /*
258 * other constants
259 */
260
261 /* max number of SDs */
262 /* ICH, ATI and VIA have 4 playback and 4 capture */
263 #define ICH6_NUM_CAPTURE 4
264 #define ICH6_NUM_PLAYBACK 4
265
266 /* ULI has 6 playback and 5 capture */
267 #define ULI_NUM_CAPTURE 5
268 #define ULI_NUM_PLAYBACK 6
269
270 /* ATI HDMI has 1 playback and 0 capture */
271 #define ATIHDMI_NUM_CAPTURE 0
272 #define ATIHDMI_NUM_PLAYBACK 1
273
274 /* TERA has 4 playback and 3 capture */
275 #define TERA_NUM_CAPTURE 3
276 #define TERA_NUM_PLAYBACK 4
277
278 /* this number is statically defined for simplicity */
279 #define MAX_AZX_DEV 16
280
281 /* max number of fragments - we may use more if allocating more pages for BDL */
282 #define BDL_SIZE 4096
283 #define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16)
284 #define AZX_MAX_FRAG 32
285 /* max buffer size - no h/w limit, you can increase as you like */
286 #define AZX_MAX_BUF_SIZE (1024*1024*1024)
287
288 /* RIRB int mask: overrun[2], response[0] */
289 #define RIRB_INT_RESPONSE 0x01
290 #define RIRB_INT_OVERRUN 0x04
291 #define RIRB_INT_MASK 0x05
292
293 /* STATESTS int mask: S3,SD2,SD1,SD0 */
294 #define AZX_MAX_CODECS 8
295 #define AZX_DEFAULT_CODECS 4
296 #define STATESTS_INT_MASK ((1 << AZX_MAX_CODECS) - 1)
297
298 /* SD_CTL bits */
299 #define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
300 #define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
301 #define SD_CTL_STRIPE (3 << 16) /* stripe control */
302 #define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */
303 #define SD_CTL_DIR (1 << 19) /* bi-directional stream */
304 #define SD_CTL_STREAM_TAG_MASK (0xf << 20)
305 #define SD_CTL_STREAM_TAG_SHIFT 20
306
307 /* SD_CTL and SD_STS */
308 #define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
309 #define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
310 #define SD_INT_COMPLETE 0x04 /* completion interrupt */
311 #define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
312 SD_INT_COMPLETE)
313
314 /* SD_STS */
315 #define SD_STS_FIFO_READY 0x20 /* FIFO ready */
316
317 /* INTCTL and INTSTS */
318 #define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
319 #define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
320 #define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
321
322 /* below are so far hardcoded - should read registers in future */
323 #define ICH6_MAX_CORB_ENTRIES 256
324 #define ICH6_MAX_RIRB_ENTRIES 256
325
326 /* position fix mode */
327 enum {
328 POS_FIX_AUTO,
329 POS_FIX_LPIB,
330 POS_FIX_POSBUF,
331 POS_FIX_VIACOMBO,
332 };
333
334 /* Defines for ATI HD Audio support in SB450 south bridge */
335 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
336 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
337
338 /* Defines for Nvidia HDA support */
339 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
340 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
341 #define NVIDIA_HDA_ISTRM_COH 0x4d
342 #define NVIDIA_HDA_OSTRM_COH 0x4c
343 #define NVIDIA_HDA_ENABLE_COHBIT 0x01
344
345 /* Defines for Intel SCH HDA snoop control */
346 #define INTEL_SCH_HDA_DEVC 0x78
347 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
348
349 /* Define IN stream 0 FIFO size offset in VIA controller */
350 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
351 /* Define VIA HD Audio Device ID*/
352 #define VIA_HDAC_DEVICE_ID 0x3288
353
354 /* HD Audio class code */
355 #define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403
356
357 /*
358 */
359
360 struct azx_dev {
361 struct snd_dma_buffer bdl; /* BDL buffer */
362 u32 *posbuf; /* position buffer pointer */
363
364 unsigned int bufsize; /* size of the play buffer in bytes */
365 unsigned int period_bytes; /* size of the period in bytes */
366 unsigned int frags; /* number for period in the play buffer */
367 unsigned int fifo_size; /* FIFO size */
368 unsigned long start_wallclk; /* start + minimum wallclk */
369 unsigned long period_wallclk; /* wallclk for period */
370
371 void __iomem *sd_addr; /* stream descriptor pointer */
372
373 u32 sd_int_sta_mask; /* stream int status mask */
374
375 /* pcm support */
376 struct snd_pcm_substream *substream; /* assigned substream,
377 * set in PCM open
378 */
379 unsigned int format_val; /* format value to be set in the
380 * controller and the codec
381 */
382 unsigned char stream_tag; /* assigned stream */
383 unsigned char index; /* stream index */
384 int assigned_key; /* last device# key assigned to */
385
386 unsigned int opened :1;
387 unsigned int running :1;
388 unsigned int irq_pending :1;
389 /*
390 * For VIA:
391 * A flag to ensure DMA position is 0
392 * when link position is not greater than FIFO size
393 */
394 unsigned int insufficient :1;
395 unsigned int wc_marked:1;
396 };
397
398 /* CORB/RIRB */
399 struct azx_rb {
400 u32 *buf; /* CORB/RIRB buffer
401 * Each CORB entry is 4byte, RIRB is 8byte
402 */
403 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
404 /* for RIRB */
405 unsigned short rp, wp; /* read/write pointers */
406 int cmds[AZX_MAX_CODECS]; /* number of pending requests */
407 u32 res[AZX_MAX_CODECS]; /* last read value */
408 };
409
410 struct azx_pcm {
411 struct azx *chip;
412 struct snd_pcm *pcm;
413 struct hda_codec *codec;
414 struct hda_pcm_stream *hinfo[2];
415 struct list_head list;
416 };
417
418 struct azx {
419 struct snd_card *card;
420 struct pci_dev *pci;
421 int dev_index;
422
423 /* chip type specific */
424 int driver_type;
425 unsigned int driver_caps;
426 int playback_streams;
427 int playback_index_offset;
428 int capture_streams;
429 int capture_index_offset;
430 int num_streams;
431
432 /* pci resources */
433 unsigned long addr;
434 void __iomem *remap_addr;
435 int irq;
436
437 /* locks */
438 spinlock_t reg_lock;
439 struct mutex open_mutex;
440
441 /* streams (x num_streams) */
442 struct azx_dev *azx_dev;
443
444 /* PCM */
445 struct list_head pcm_list; /* azx_pcm list */
446
447 /* HD codec */
448 unsigned short codec_mask;
449 int codec_probe_mask; /* copied from probe_mask option */
450 struct hda_bus *bus;
451 unsigned int beep_mode;
452
453 /* CORB/RIRB */
454 struct azx_rb corb;
455 struct azx_rb rirb;
456
457 /* CORB/RIRB and position buffers */
458 struct snd_dma_buffer rb;
459 struct snd_dma_buffer posbuf;
460
461 /* flags */
462 int position_fix[2]; /* for both playback/capture streams */
463 int poll_count;
464 unsigned int running :1;
465 unsigned int initialized :1;
466 unsigned int single_cmd :1;
467 unsigned int polling_mode :1;
468 unsigned int msi :1;
469 unsigned int irq_pending_warned :1;
470 unsigned int probing :1; /* codec probing phase */
471 unsigned int snoop:1;
472 unsigned int align_buffer_size:1;
473
474 /* for debugging */
475 unsigned int last_cmd[AZX_MAX_CODECS];
476
477 /* for pending irqs */
478 struct work_struct irq_pending_work;
479
480 /* reboot notifier (for mysterious hangup problem at power-down) */
481 struct notifier_block reboot_notifier;
482 };
483
484 /* driver types */
485 enum {
486 AZX_DRIVER_ICH,
487 AZX_DRIVER_PCH,
488 AZX_DRIVER_SCH,
489 AZX_DRIVER_ATI,
490 AZX_DRIVER_ATIHDMI,
491 AZX_DRIVER_ATIHDMI_NS,
492 AZX_DRIVER_VIA,
493 AZX_DRIVER_SIS,
494 AZX_DRIVER_ULI,
495 AZX_DRIVER_NVIDIA,
496 AZX_DRIVER_TERA,
497 AZX_DRIVER_CTX,
498 AZX_DRIVER_GENERIC,
499 AZX_NUM_DRIVERS, /* keep this as last entry */
500 };
501
502 /* driver quirks (capabilities) */
503 /* bits 0-7 are used for indicating driver type */
504 #define AZX_DCAPS_NO_TCSEL (1 << 8) /* No Intel TCSEL bit */
505 #define AZX_DCAPS_NO_MSI (1 << 9) /* No MSI support */
506 #define AZX_DCAPS_ATI_SNOOP (1 << 10) /* ATI snoop enable */
507 #define AZX_DCAPS_NVIDIA_SNOOP (1 << 11) /* Nvidia snoop enable */
508 #define AZX_DCAPS_SCH_SNOOP (1 << 12) /* SCH/PCH snoop enable */
509 #define AZX_DCAPS_RIRB_DELAY (1 << 13) /* Long delay in read loop */
510 #define AZX_DCAPS_RIRB_PRE_DELAY (1 << 14) /* Put a delay before read */
511 #define AZX_DCAPS_CTX_WORKAROUND (1 << 15) /* X-Fi workaround */
512 #define AZX_DCAPS_POSFIX_LPIB (1 << 16) /* Use LPIB as default */
513 #define AZX_DCAPS_POSFIX_VIA (1 << 17) /* Use VIACOMBO as default */
514 #define AZX_DCAPS_NO_64BIT (1 << 18) /* No 64bit address */
515 #define AZX_DCAPS_SYNC_WRITE (1 << 19) /* sync each cmd write */
516 #define AZX_DCAPS_OLD_SSYNC (1 << 20) /* Old SSYNC reg for ICH */
517 #define AZX_DCAPS_BUFSIZE (1 << 21) /* no buffer size alignment */
518
519 /* quirks for ATI SB / AMD Hudson */
520 #define AZX_DCAPS_PRESET_ATI_SB \
521 (AZX_DCAPS_ATI_SNOOP | AZX_DCAPS_NO_TCSEL | \
522 AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
523
524 /* quirks for ATI/AMD HDMI */
525 #define AZX_DCAPS_PRESET_ATI_HDMI \
526 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
527
528 /* quirks for Nvidia */
529 #define AZX_DCAPS_PRESET_NVIDIA \
530 (AZX_DCAPS_NVIDIA_SNOOP | AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI)
531
532 static char *driver_short_names[] __devinitdata = {
533 [AZX_DRIVER_ICH] = "HDA Intel",
534 [AZX_DRIVER_PCH] = "HDA Intel PCH",
535 [AZX_DRIVER_SCH] = "HDA Intel MID",
536 [AZX_DRIVER_ATI] = "HDA ATI SB",
537 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
538 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
539 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
540 [AZX_DRIVER_SIS] = "HDA SIS966",
541 [AZX_DRIVER_ULI] = "HDA ULI M5461",
542 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
543 [AZX_DRIVER_TERA] = "HDA Teradici",
544 [AZX_DRIVER_CTX] = "HDA Creative",
545 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
546 };
547
548 /*
549 * macros for easy use
550 */
551 #define azx_writel(chip,reg,value) \
552 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
553 #define azx_readl(chip,reg) \
554 readl((chip)->remap_addr + ICH6_REG_##reg)
555 #define azx_writew(chip,reg,value) \
556 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
557 #define azx_readw(chip,reg) \
558 readw((chip)->remap_addr + ICH6_REG_##reg)
559 #define azx_writeb(chip,reg,value) \
560 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
561 #define azx_readb(chip,reg) \
562 readb((chip)->remap_addr + ICH6_REG_##reg)
563
564 #define azx_sd_writel(dev,reg,value) \
565 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
566 #define azx_sd_readl(dev,reg) \
567 readl((dev)->sd_addr + ICH6_REG_##reg)
568 #define azx_sd_writew(dev,reg,value) \
569 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
570 #define azx_sd_readw(dev,reg) \
571 readw((dev)->sd_addr + ICH6_REG_##reg)
572 #define azx_sd_writeb(dev,reg,value) \
573 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
574 #define azx_sd_readb(dev,reg) \
575 readb((dev)->sd_addr + ICH6_REG_##reg)
576
577 /* for pcm support */
578 #define get_azx_dev(substream) (substream->runtime->private_data)
579
580 #ifdef CONFIG_X86
581 static void __mark_pages_wc(struct azx *chip, void *addr, size_t size, bool on)
582 {
583 if (azx_snoop(chip))
584 return;
585 if (addr && size) {
586 int pages = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
587 if (on)
588 set_memory_wc((unsigned long)addr, pages);
589 else
590 set_memory_wb((unsigned long)addr, pages);
591 }
592 }
593
594 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
595 bool on)
596 {
597 __mark_pages_wc(chip, buf->area, buf->bytes, on);
598 }
599 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
600 struct snd_pcm_runtime *runtime, bool on)
601 {
602 if (azx_dev->wc_marked != on) {
603 __mark_pages_wc(chip, runtime->dma_area, runtime->dma_bytes, on);
604 azx_dev->wc_marked = on;
605 }
606 }
607 #else
608 /* NOP for other archs */
609 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
610 bool on)
611 {
612 }
613 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
614 struct snd_pcm_runtime *runtime, bool on)
615 {
616 }
617 #endif
618
619 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
620 static int azx_send_cmd(struct hda_bus *bus, unsigned int val);
621 /*
622 * Interface for HD codec
623 */
624
625 /*
626 * CORB / RIRB interface
627 */
628 static int azx_alloc_cmd_io(struct azx *chip)
629 {
630 int err;
631
632 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
633 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
634 snd_dma_pci_data(chip->pci),
635 PAGE_SIZE, &chip->rb);
636 if (err < 0) {
637 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
638 return err;
639 }
640 mark_pages_wc(chip, &chip->rb, true);
641 return 0;
642 }
643
644 static void azx_init_cmd_io(struct azx *chip)
645 {
646 spin_lock_irq(&chip->reg_lock);
647 /* CORB set up */
648 chip->corb.addr = chip->rb.addr;
649 chip->corb.buf = (u32 *)chip->rb.area;
650 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
651 azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
652
653 /* set the corb size to 256 entries (ULI requires explicitly) */
654 azx_writeb(chip, CORBSIZE, 0x02);
655 /* set the corb write pointer to 0 */
656 azx_writew(chip, CORBWP, 0);
657 /* reset the corb hw read pointer */
658 azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
659 /* enable corb dma */
660 azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
661
662 /* RIRB set up */
663 chip->rirb.addr = chip->rb.addr + 2048;
664 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
665 chip->rirb.wp = chip->rirb.rp = 0;
666 memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
667 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
668 azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
669
670 /* set the rirb size to 256 entries (ULI requires explicitly) */
671 azx_writeb(chip, RIRBSIZE, 0x02);
672 /* reset the rirb hw write pointer */
673 azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
674 /* set N=1, get RIRB response interrupt for new entry */
675 if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
676 azx_writew(chip, RINTCNT, 0xc0);
677 else
678 azx_writew(chip, RINTCNT, 1);
679 /* enable rirb dma and response irq */
680 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
681 spin_unlock_irq(&chip->reg_lock);
682 }
683
684 static void azx_free_cmd_io(struct azx *chip)
685 {
686 spin_lock_irq(&chip->reg_lock);
687 /* disable ringbuffer DMAs */
688 azx_writeb(chip, RIRBCTL, 0);
689 azx_writeb(chip, CORBCTL, 0);
690 spin_unlock_irq(&chip->reg_lock);
691 }
692
693 static unsigned int azx_command_addr(u32 cmd)
694 {
695 unsigned int addr = cmd >> 28;
696
697 if (addr >= AZX_MAX_CODECS) {
698 snd_BUG();
699 addr = 0;
700 }
701
702 return addr;
703 }
704
705 static unsigned int azx_response_addr(u32 res)
706 {
707 unsigned int addr = res & 0xf;
708
709 if (addr >= AZX_MAX_CODECS) {
710 snd_BUG();
711 addr = 0;
712 }
713
714 return addr;
715 }
716
717 /* send a command */
718 static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
719 {
720 struct azx *chip = bus->private_data;
721 unsigned int addr = azx_command_addr(val);
722 unsigned int wp;
723
724 spin_lock_irq(&chip->reg_lock);
725
726 /* add command to corb */
727 wp = azx_readb(chip, CORBWP);
728 wp++;
729 wp %= ICH6_MAX_CORB_ENTRIES;
730
731 chip->rirb.cmds[addr]++;
732 chip->corb.buf[wp] = cpu_to_le32(val);
733 azx_writel(chip, CORBWP, wp);
734
735 spin_unlock_irq(&chip->reg_lock);
736
737 return 0;
738 }
739
740 #define ICH6_RIRB_EX_UNSOL_EV (1<<4)
741
742 /* retrieve RIRB entry - called from interrupt handler */
743 static void azx_update_rirb(struct azx *chip)
744 {
745 unsigned int rp, wp;
746 unsigned int addr;
747 u32 res, res_ex;
748
749 wp = azx_readb(chip, RIRBWP);
750 if (wp == chip->rirb.wp)
751 return;
752 chip->rirb.wp = wp;
753
754 while (chip->rirb.rp != wp) {
755 chip->rirb.rp++;
756 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
757
758 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
759 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
760 res = le32_to_cpu(chip->rirb.buf[rp]);
761 addr = azx_response_addr(res_ex);
762 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
763 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
764 else if (chip->rirb.cmds[addr]) {
765 chip->rirb.res[addr] = res;
766 smp_wmb();
767 chip->rirb.cmds[addr]--;
768 } else
769 snd_printk(KERN_ERR SFX "spurious response %#x:%#x, "
770 "last cmd=%#08x\n",
771 res, res_ex,
772 chip->last_cmd[addr]);
773 }
774 }
775
776 /* receive a response */
777 static unsigned int azx_rirb_get_response(struct hda_bus *bus,
778 unsigned int addr)
779 {
780 struct azx *chip = bus->private_data;
781 unsigned long timeout;
782 unsigned long loopcounter;
783 int do_poll = 0;
784
785 again:
786 timeout = jiffies + msecs_to_jiffies(1000);
787
788 for (loopcounter = 0;; loopcounter++) {
789 if (chip->polling_mode || do_poll) {
790 spin_lock_irq(&chip->reg_lock);
791 azx_update_rirb(chip);
792 spin_unlock_irq(&chip->reg_lock);
793 }
794 if (!chip->rirb.cmds[addr]) {
795 smp_rmb();
796 bus->rirb_error = 0;
797
798 if (!do_poll)
799 chip->poll_count = 0;
800 return chip->rirb.res[addr]; /* the last value */
801 }
802 if (time_after(jiffies, timeout))
803 break;
804 if (bus->needs_damn_long_delay || loopcounter > 3000)
805 msleep(2); /* temporary workaround */
806 else {
807 udelay(10);
808 cond_resched();
809 }
810 }
811
812 if (!chip->polling_mode && chip->poll_count < 2) {
813 snd_printdd(SFX "azx_get_response timeout, "
814 "polling the codec once: last cmd=0x%08x\n",
815 chip->last_cmd[addr]);
816 do_poll = 1;
817 chip->poll_count++;
818 goto again;
819 }
820
821
822 if (!chip->polling_mode) {
823 snd_printk(KERN_WARNING SFX "azx_get_response timeout, "
824 "switching to polling mode: last cmd=0x%08x\n",
825 chip->last_cmd[addr]);
826 chip->polling_mode = 1;
827 goto again;
828 }
829
830 if (chip->msi) {
831 snd_printk(KERN_WARNING SFX "No response from codec, "
832 "disabling MSI: last cmd=0x%08x\n",
833 chip->last_cmd[addr]);
834 free_irq(chip->irq, chip);
835 chip->irq = -1;
836 pci_disable_msi(chip->pci);
837 chip->msi = 0;
838 if (azx_acquire_irq(chip, 1) < 0) {
839 bus->rirb_error = 1;
840 return -1;
841 }
842 goto again;
843 }
844
845 if (chip->probing) {
846 /* If this critical timeout happens during the codec probing
847 * phase, this is likely an access to a non-existing codec
848 * slot. Better to return an error and reset the system.
849 */
850 return -1;
851 }
852
853 /* a fatal communication error; need either to reset or to fallback
854 * to the single_cmd mode
855 */
856 bus->rirb_error = 1;
857 if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
858 bus->response_reset = 1;
859 return -1; /* give a chance to retry */
860 }
861
862 snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
863 "switching to single_cmd mode: last cmd=0x%08x\n",
864 chip->last_cmd[addr]);
865 chip->single_cmd = 1;
866 bus->response_reset = 0;
867 /* release CORB/RIRB */
868 azx_free_cmd_io(chip);
869 /* disable unsolicited responses */
870 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
871 return -1;
872 }
873
874 /*
875 * Use the single immediate command instead of CORB/RIRB for simplicity
876 *
877 * Note: according to Intel, this is not preferred use. The command was
878 * intended for the BIOS only, and may get confused with unsolicited
879 * responses. So, we shouldn't use it for normal operation from the
880 * driver.
881 * I left the codes, however, for debugging/testing purposes.
882 */
883
884 /* receive a response */
885 static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
886 {
887 int timeout = 50;
888
889 while (timeout--) {
890 /* check IRV busy bit */
891 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
892 /* reuse rirb.res as the response return value */
893 chip->rirb.res[addr] = azx_readl(chip, IR);
894 return 0;
895 }
896 udelay(1);
897 }
898 if (printk_ratelimit())
899 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
900 azx_readw(chip, IRS));
901 chip->rirb.res[addr] = -1;
902 return -EIO;
903 }
904
905 /* send a command */
906 static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
907 {
908 struct azx *chip = bus->private_data;
909 unsigned int addr = azx_command_addr(val);
910 int timeout = 50;
911
912 bus->rirb_error = 0;
913 while (timeout--) {
914 /* check ICB busy bit */
915 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
916 /* Clear IRV valid bit */
917 azx_writew(chip, IRS, azx_readw(chip, IRS) |
918 ICH6_IRS_VALID);
919 azx_writel(chip, IC, val);
920 azx_writew(chip, IRS, azx_readw(chip, IRS) |
921 ICH6_IRS_BUSY);
922 return azx_single_wait_for_response(chip, addr);
923 }
924 udelay(1);
925 }
926 if (printk_ratelimit())
927 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
928 azx_readw(chip, IRS), val);
929 return -EIO;
930 }
931
932 /* receive a response */
933 static unsigned int azx_single_get_response(struct hda_bus *bus,
934 unsigned int addr)
935 {
936 struct azx *chip = bus->private_data;
937 return chip->rirb.res[addr];
938 }
939
940 /*
941 * The below are the main callbacks from hda_codec.
942 *
943 * They are just the skeleton to call sub-callbacks according to the
944 * current setting of chip->single_cmd.
945 */
946
947 /* send a command */
948 static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
949 {
950 struct azx *chip = bus->private_data;
951
952 chip->last_cmd[azx_command_addr(val)] = val;
953 if (chip->single_cmd)
954 return azx_single_send_cmd(bus, val);
955 else
956 return azx_corb_send_cmd(bus, val);
957 }
958
959 /* get a response */
960 static unsigned int azx_get_response(struct hda_bus *bus,
961 unsigned int addr)
962 {
963 struct azx *chip = bus->private_data;
964 if (chip->single_cmd)
965 return azx_single_get_response(bus, addr);
966 else
967 return azx_rirb_get_response(bus, addr);
968 }
969
970 #ifdef CONFIG_SND_HDA_POWER_SAVE
971 static void azx_power_notify(struct hda_bus *bus);
972 #endif
973
974 /* reset codec link */
975 static int azx_reset(struct azx *chip, int full_reset)
976 {
977 int count;
978
979 if (!full_reset)
980 goto __skip;
981
982 /* clear STATESTS */
983 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
984
985 /* reset controller */
986 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
987
988 count = 50;
989 while (azx_readb(chip, GCTL) && --count)
990 msleep(1);
991
992 /* delay for >= 100us for codec PLL to settle per spec
993 * Rev 0.9 section 5.5.1
994 */
995 msleep(1);
996
997 /* Bring controller out of reset */
998 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
999
1000 count = 50;
1001 while (!azx_readb(chip, GCTL) && --count)
1002 msleep(1);
1003
1004 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
1005 msleep(1);
1006
1007 __skip:
1008 /* check to see if controller is ready */
1009 if (!azx_readb(chip, GCTL)) {
1010 snd_printd(SFX "azx_reset: controller not ready!\n");
1011 return -EBUSY;
1012 }
1013
1014 /* Accept unsolicited responses */
1015 if (!chip->single_cmd)
1016 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
1017 ICH6_GCTL_UNSOL);
1018
1019 /* detect codecs */
1020 if (!chip->codec_mask) {
1021 chip->codec_mask = azx_readw(chip, STATESTS);
1022 snd_printdd(SFX "codec_mask = 0x%x\n", chip->codec_mask);
1023 }
1024
1025 return 0;
1026 }
1027
1028
1029 /*
1030 * Lowlevel interface
1031 */
1032
1033 /* enable interrupts */
1034 static void azx_int_enable(struct azx *chip)
1035 {
1036 /* enable controller CIE and GIE */
1037 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
1038 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
1039 }
1040
1041 /* disable interrupts */
1042 static void azx_int_disable(struct azx *chip)
1043 {
1044 int i;
1045
1046 /* disable interrupts in stream descriptor */
1047 for (i = 0; i < chip->num_streams; i++) {
1048 struct azx_dev *azx_dev = &chip->azx_dev[i];
1049 azx_sd_writeb(azx_dev, SD_CTL,
1050 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
1051 }
1052
1053 /* disable SIE for all streams */
1054 azx_writeb(chip, INTCTL, 0);
1055
1056 /* disable controller CIE and GIE */
1057 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
1058 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
1059 }
1060
1061 /* clear interrupts */
1062 static void azx_int_clear(struct azx *chip)
1063 {
1064 int i;
1065
1066 /* clear stream status */
1067 for (i = 0; i < chip->num_streams; i++) {
1068 struct azx_dev *azx_dev = &chip->azx_dev[i];
1069 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1070 }
1071
1072 /* clear STATESTS */
1073 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
1074
1075 /* clear rirb status */
1076 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1077
1078 /* clear int status */
1079 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
1080 }
1081
1082 /* start a stream */
1083 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
1084 {
1085 /*
1086 * Before stream start, initialize parameter
1087 */
1088 azx_dev->insufficient = 1;
1089
1090 /* enable SIE */
1091 azx_writel(chip, INTCTL,
1092 azx_readl(chip, INTCTL) | (1 << azx_dev->index));
1093 /* set DMA start and interrupt mask */
1094 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1095 SD_CTL_DMA_START | SD_INT_MASK);
1096 }
1097
1098 /* stop DMA */
1099 static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
1100 {
1101 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
1102 ~(SD_CTL_DMA_START | SD_INT_MASK));
1103 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
1104 }
1105
1106 /* stop a stream */
1107 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
1108 {
1109 azx_stream_clear(chip, azx_dev);
1110 /* disable SIE */
1111 azx_writel(chip, INTCTL,
1112 azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
1113 }
1114
1115
1116 /*
1117 * reset and start the controller registers
1118 */
1119 static void azx_init_chip(struct azx *chip, int full_reset)
1120 {
1121 if (chip->initialized)
1122 return;
1123
1124 /* reset controller */
1125 azx_reset(chip, full_reset);
1126
1127 /* initialize interrupts */
1128 azx_int_clear(chip);
1129 azx_int_enable(chip);
1130
1131 /* initialize the codec command I/O */
1132 if (!chip->single_cmd)
1133 azx_init_cmd_io(chip);
1134
1135 /* program the position buffer */
1136 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
1137 azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
1138
1139 chip->initialized = 1;
1140 }
1141
1142 /*
1143 * initialize the PCI registers
1144 */
1145 /* update bits in a PCI register byte */
1146 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
1147 unsigned char mask, unsigned char val)
1148 {
1149 unsigned char data;
1150
1151 pci_read_config_byte(pci, reg, &data);
1152 data &= ~mask;
1153 data |= (val & mask);
1154 pci_write_config_byte(pci, reg, data);
1155 }
1156
1157 static void azx_init_pci(struct azx *chip)
1158 {
1159 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
1160 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
1161 * Ensuring these bits are 0 clears playback static on some HD Audio
1162 * codecs.
1163 * The PCI register TCSEL is defined in the Intel manuals.
1164 */
1165 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
1166 snd_printdd(SFX "Clearing TCSEL\n");
1167 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
1168 }
1169
1170 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
1171 * we need to enable snoop.
1172 */
1173 if (chip->driver_caps & AZX_DCAPS_ATI_SNOOP) {
1174 snd_printdd(SFX "Setting ATI snoop: %d\n", azx_snoop(chip));
1175 update_pci_byte(chip->pci,
1176 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
1177 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
1178 }
1179
1180 /* For NVIDIA HDA, enable snoop */
1181 if (chip->driver_caps & AZX_DCAPS_NVIDIA_SNOOP) {
1182 snd_printdd(SFX "Setting Nvidia snoop: %d\n", azx_snoop(chip));
1183 update_pci_byte(chip->pci,
1184 NVIDIA_HDA_TRANSREG_ADDR,
1185 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
1186 update_pci_byte(chip->pci,
1187 NVIDIA_HDA_ISTRM_COH,
1188 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1189 update_pci_byte(chip->pci,
1190 NVIDIA_HDA_OSTRM_COH,
1191 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1192 }
1193
1194 /* Enable SCH/PCH snoop if needed */
1195 if (chip->driver_caps & AZX_DCAPS_SCH_SNOOP) {
1196 unsigned short snoop;
1197 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
1198 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
1199 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
1200 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
1201 if (!azx_snoop(chip))
1202 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
1203 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
1204 pci_read_config_word(chip->pci,
1205 INTEL_SCH_HDA_DEVC, &snoop);
1206 }
1207 snd_printdd(SFX "SCH snoop: %s\n",
1208 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
1209 ? "Disabled" : "Enabled");
1210 }
1211 }
1212
1213
1214 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1215
1216 /*
1217 * interrupt handler
1218 */
1219 static irqreturn_t azx_interrupt(int irq, void *dev_id)
1220 {
1221 struct azx *chip = dev_id;
1222 struct azx_dev *azx_dev;
1223 u32 status;
1224 u8 sd_status;
1225 int i, ok;
1226
1227 spin_lock(&chip->reg_lock);
1228
1229 status = azx_readl(chip, INTSTS);
1230 if (status == 0) {
1231 spin_unlock(&chip->reg_lock);
1232 return IRQ_NONE;
1233 }
1234
1235 for (i = 0; i < chip->num_streams; i++) {
1236 azx_dev = &chip->azx_dev[i];
1237 if (status & azx_dev->sd_int_sta_mask) {
1238 sd_status = azx_sd_readb(azx_dev, SD_STS);
1239 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1240 if (!azx_dev->substream || !azx_dev->running ||
1241 !(sd_status & SD_INT_COMPLETE))
1242 continue;
1243 /* check whether this IRQ is really acceptable */
1244 ok = azx_position_ok(chip, azx_dev);
1245 if (ok == 1) {
1246 azx_dev->irq_pending = 0;
1247 spin_unlock(&chip->reg_lock);
1248 snd_pcm_period_elapsed(azx_dev->substream);
1249 spin_lock(&chip->reg_lock);
1250 } else if (ok == 0 && chip->bus && chip->bus->workq) {
1251 /* bogus IRQ, process it later */
1252 azx_dev->irq_pending = 1;
1253 queue_work(chip->bus->workq,
1254 &chip->irq_pending_work);
1255 }
1256 }
1257 }
1258
1259 /* clear rirb int */
1260 status = azx_readb(chip, RIRBSTS);
1261 if (status & RIRB_INT_MASK) {
1262 if (status & RIRB_INT_RESPONSE) {
1263 if (chip->driver_caps & AZX_DCAPS_RIRB_PRE_DELAY)
1264 udelay(80);
1265 azx_update_rirb(chip);
1266 }
1267 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1268 }
1269
1270 #if 0
1271 /* clear state status int */
1272 if (azx_readb(chip, STATESTS) & 0x04)
1273 azx_writeb(chip, STATESTS, 0x04);
1274 #endif
1275 spin_unlock(&chip->reg_lock);
1276
1277 return IRQ_HANDLED;
1278 }
1279
1280
1281 /*
1282 * set up a BDL entry
1283 */
1284 static int setup_bdle(struct snd_pcm_substream *substream,
1285 struct azx_dev *azx_dev, u32 **bdlp,
1286 int ofs, int size, int with_ioc)
1287 {
1288 u32 *bdl = *bdlp;
1289
1290 while (size > 0) {
1291 dma_addr_t addr;
1292 int chunk;
1293
1294 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1295 return -EINVAL;
1296
1297 addr = snd_pcm_sgbuf_get_addr(substream, ofs);
1298 /* program the address field of the BDL entry */
1299 bdl[0] = cpu_to_le32((u32)addr);
1300 bdl[1] = cpu_to_le32(upper_32_bits(addr));
1301 /* program the size field of the BDL entry */
1302 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
1303 bdl[2] = cpu_to_le32(chunk);
1304 /* program the IOC to enable interrupt
1305 * only when the whole fragment is processed
1306 */
1307 size -= chunk;
1308 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1309 bdl += 4;
1310 azx_dev->frags++;
1311 ofs += chunk;
1312 }
1313 *bdlp = bdl;
1314 return ofs;
1315 }
1316
1317 /*
1318 * set up BDL entries
1319 */
1320 static int azx_setup_periods(struct azx *chip,
1321 struct snd_pcm_substream *substream,
1322 struct azx_dev *azx_dev)
1323 {
1324 u32 *bdl;
1325 int i, ofs, periods, period_bytes;
1326 int pos_adj;
1327
1328 /* reset BDL address */
1329 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1330 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1331
1332 period_bytes = azx_dev->period_bytes;
1333 periods = azx_dev->bufsize / period_bytes;
1334
1335 /* program the initial BDL entries */
1336 bdl = (u32 *)azx_dev->bdl.area;
1337 ofs = 0;
1338 azx_dev->frags = 0;
1339 pos_adj = bdl_pos_adj[chip->dev_index];
1340 if (pos_adj > 0) {
1341 struct snd_pcm_runtime *runtime = substream->runtime;
1342 int pos_align = pos_adj;
1343 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1344 if (!pos_adj)
1345 pos_adj = pos_align;
1346 else
1347 pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1348 pos_align;
1349 pos_adj = frames_to_bytes(runtime, pos_adj);
1350 if (pos_adj >= period_bytes) {
1351 snd_printk(KERN_WARNING SFX "Too big adjustment %d\n",
1352 bdl_pos_adj[chip->dev_index]);
1353 pos_adj = 0;
1354 } else {
1355 ofs = setup_bdle(substream, azx_dev,
1356 &bdl, ofs, pos_adj,
1357 !substream->runtime->no_period_wakeup);
1358 if (ofs < 0)
1359 goto error;
1360 }
1361 } else
1362 pos_adj = 0;
1363 for (i = 0; i < periods; i++) {
1364 if (i == periods - 1 && pos_adj)
1365 ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1366 period_bytes - pos_adj, 0);
1367 else
1368 ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1369 period_bytes,
1370 !substream->runtime->no_period_wakeup);
1371 if (ofs < 0)
1372 goto error;
1373 }
1374 return 0;
1375
1376 error:
1377 snd_printk(KERN_ERR SFX "Too many BDL entries: buffer=%d, period=%d\n",
1378 azx_dev->bufsize, period_bytes);
1379 return -EINVAL;
1380 }
1381
1382 /* reset stream */
1383 static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1384 {
1385 unsigned char val;
1386 int timeout;
1387
1388 azx_stream_clear(chip, azx_dev);
1389
1390 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1391 SD_CTL_STREAM_RESET);
1392 udelay(3);
1393 timeout = 300;
1394 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1395 --timeout)
1396 ;
1397 val &= ~SD_CTL_STREAM_RESET;
1398 azx_sd_writeb(azx_dev, SD_CTL, val);
1399 udelay(3);
1400
1401 timeout = 300;
1402 /* waiting for hardware to report that the stream is out of reset */
1403 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1404 --timeout)
1405 ;
1406
1407 /* reset first position - may not be synced with hw at this time */
1408 *azx_dev->posbuf = 0;
1409 }
1410
1411 /*
1412 * set up the SD for streaming
1413 */
1414 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1415 {
1416 unsigned int val;
1417 /* make sure the run bit is zero for SD */
1418 azx_stream_clear(chip, azx_dev);
1419 /* program the stream_tag */
1420 val = azx_sd_readl(azx_dev, SD_CTL);
1421 val = (val & ~SD_CTL_STREAM_TAG_MASK) |
1422 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
1423 if (!azx_snoop(chip))
1424 val |= SD_CTL_TRAFFIC_PRIO;
1425 azx_sd_writel(azx_dev, SD_CTL, val);
1426
1427 /* program the length of samples in cyclic buffer */
1428 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1429
1430 /* program the stream format */
1431 /* this value needs to be the same as the one programmed */
1432 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1433
1434 /* program the stream LVI (last valid index) of the BDL */
1435 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1436
1437 /* program the BDL address */
1438 /* lower BDL address */
1439 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1440 /* upper BDL address */
1441 azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1442
1443 /* enable the position buffer */
1444 if (chip->position_fix[0] != POS_FIX_LPIB ||
1445 chip->position_fix[1] != POS_FIX_LPIB) {
1446 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1447 azx_writel(chip, DPLBASE,
1448 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1449 }
1450
1451 /* set the interrupt enable bits in the descriptor control register */
1452 azx_sd_writel(azx_dev, SD_CTL,
1453 azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1454
1455 return 0;
1456 }
1457
1458 /*
1459 * Probe the given codec address
1460 */
1461 static int probe_codec(struct azx *chip, int addr)
1462 {
1463 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1464 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1465 unsigned int res;
1466
1467 mutex_lock(&chip->bus->cmd_mutex);
1468 chip->probing = 1;
1469 azx_send_cmd(chip->bus, cmd);
1470 res = azx_get_response(chip->bus, addr);
1471 chip->probing = 0;
1472 mutex_unlock(&chip->bus->cmd_mutex);
1473 if (res == -1)
1474 return -EIO;
1475 snd_printdd(SFX "codec #%d probed OK\n", addr);
1476 return 0;
1477 }
1478
1479 static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1480 struct hda_pcm *cpcm);
1481 static void azx_stop_chip(struct azx *chip);
1482
1483 static void azx_bus_reset(struct hda_bus *bus)
1484 {
1485 struct azx *chip = bus->private_data;
1486
1487 bus->in_reset = 1;
1488 azx_stop_chip(chip);
1489 azx_init_chip(chip, 1);
1490 #ifdef CONFIG_PM
1491 if (chip->initialized) {
1492 struct azx_pcm *p;
1493 list_for_each_entry(p, &chip->pcm_list, list)
1494 snd_pcm_suspend_all(p->pcm);
1495 snd_hda_suspend(chip->bus);
1496 snd_hda_resume(chip->bus);
1497 }
1498 #endif
1499 bus->in_reset = 0;
1500 }
1501
1502 /*
1503 * Codec initialization
1504 */
1505
1506 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1507 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] __devinitdata = {
1508 [AZX_DRIVER_NVIDIA] = 8,
1509 [AZX_DRIVER_TERA] = 1,
1510 };
1511
1512 static int __devinit azx_codec_create(struct azx *chip, const char *model)
1513 {
1514 struct hda_bus_template bus_temp;
1515 int c, codecs, err;
1516 int max_slots;
1517
1518 memset(&bus_temp, 0, sizeof(bus_temp));
1519 bus_temp.private_data = chip;
1520 bus_temp.modelname = model;
1521 bus_temp.pci = chip->pci;
1522 bus_temp.ops.command = azx_send_cmd;
1523 bus_temp.ops.get_response = azx_get_response;
1524 bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
1525 bus_temp.ops.bus_reset = azx_bus_reset;
1526 #ifdef CONFIG_SND_HDA_POWER_SAVE
1527 bus_temp.power_save = &power_save;
1528 bus_temp.ops.pm_notify = azx_power_notify;
1529 #endif
1530
1531 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1532 if (err < 0)
1533 return err;
1534
1535 if (chip->driver_caps & AZX_DCAPS_RIRB_DELAY) {
1536 snd_printd(SFX "Enable delay in RIRB handling\n");
1537 chip->bus->needs_damn_long_delay = 1;
1538 }
1539
1540 codecs = 0;
1541 max_slots = azx_max_codecs[chip->driver_type];
1542 if (!max_slots)
1543 max_slots = AZX_DEFAULT_CODECS;
1544
1545 /* First try to probe all given codec slots */
1546 for (c = 0; c < max_slots; c++) {
1547 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1548 if (probe_codec(chip, c) < 0) {
1549 /* Some BIOSen give you wrong codec addresses
1550 * that don't exist
1551 */
1552 snd_printk(KERN_WARNING SFX
1553 "Codec #%d probe error; "
1554 "disabling it...\n", c);
1555 chip->codec_mask &= ~(1 << c);
1556 /* More badly, accessing to a non-existing
1557 * codec often screws up the controller chip,
1558 * and disturbs the further communications.
1559 * Thus if an error occurs during probing,
1560 * better to reset the controller chip to
1561 * get back to the sanity state.
1562 */
1563 azx_stop_chip(chip);
1564 azx_init_chip(chip, 1);
1565 }
1566 }
1567 }
1568
1569 /* AMD chipsets often cause the communication stalls upon certain
1570 * sequence like the pin-detection. It seems that forcing the synced
1571 * access works around the stall. Grrr...
1572 */
1573 if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) {
1574 snd_printd(SFX "Enable sync_write for stable communication\n");
1575 chip->bus->sync_write = 1;
1576 chip->bus->allow_bus_reset = 1;
1577 }
1578
1579 /* Then create codec instances */
1580 for (c = 0; c < max_slots; c++) {
1581 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1582 struct hda_codec *codec;
1583 err = snd_hda_codec_new(chip->bus, c, &codec);
1584 if (err < 0)
1585 continue;
1586 codec->beep_mode = chip->beep_mode;
1587 codecs++;
1588 }
1589 }
1590 if (!codecs) {
1591 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1592 return -ENXIO;
1593 }
1594 return 0;
1595 }
1596
1597 /* configure each codec instance */
1598 static int __devinit azx_codec_configure(struct azx *chip)
1599 {
1600 struct hda_codec *codec;
1601 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1602 snd_hda_codec_configure(codec);
1603 }
1604 return 0;
1605 }
1606
1607
1608 /*
1609 * PCM support
1610 */
1611
1612 /* assign a stream for the PCM */
1613 static inline struct azx_dev *
1614 azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
1615 {
1616 int dev, i, nums;
1617 struct azx_dev *res = NULL;
1618 /* make a non-zero unique key for the substream */
1619 int key = (substream->pcm->device << 16) | (substream->number << 2) |
1620 (substream->stream + 1);
1621
1622 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1623 dev = chip->playback_index_offset;
1624 nums = chip->playback_streams;
1625 } else {
1626 dev = chip->capture_index_offset;
1627 nums = chip->capture_streams;
1628 }
1629 for (i = 0; i < nums; i++, dev++)
1630 if (!chip->azx_dev[dev].opened) {
1631 res = &chip->azx_dev[dev];
1632 if (res->assigned_key == key)
1633 break;
1634 }
1635 if (res) {
1636 res->opened = 1;
1637 res->assigned_key = key;
1638 }
1639 return res;
1640 }
1641
1642 /* release the assigned stream */
1643 static inline void azx_release_device(struct azx_dev *azx_dev)
1644 {
1645 azx_dev->opened = 0;
1646 }
1647
1648 static struct snd_pcm_hardware azx_pcm_hw = {
1649 .info = (SNDRV_PCM_INFO_MMAP |
1650 SNDRV_PCM_INFO_INTERLEAVED |
1651 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1652 SNDRV_PCM_INFO_MMAP_VALID |
1653 /* No full-resume yet implemented */
1654 /* SNDRV_PCM_INFO_RESUME |*/
1655 SNDRV_PCM_INFO_PAUSE |
1656 SNDRV_PCM_INFO_SYNC_START |
1657 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
1658 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1659 .rates = SNDRV_PCM_RATE_48000,
1660 .rate_min = 48000,
1661 .rate_max = 48000,
1662 .channels_min = 2,
1663 .channels_max = 2,
1664 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
1665 .period_bytes_min = 128,
1666 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
1667 .periods_min = 2,
1668 .periods_max = AZX_MAX_FRAG,
1669 .fifo_size = 0,
1670 };
1671
1672 static int azx_pcm_open(struct snd_pcm_substream *substream)
1673 {
1674 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1675 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1676 struct azx *chip = apcm->chip;
1677 struct azx_dev *azx_dev;
1678 struct snd_pcm_runtime *runtime = substream->runtime;
1679 unsigned long flags;
1680 int err;
1681 int buff_step;
1682
1683 mutex_lock(&chip->open_mutex);
1684 azx_dev = azx_assign_device(chip, substream);
1685 if (azx_dev == NULL) {
1686 mutex_unlock(&chip->open_mutex);
1687 return -EBUSY;
1688 }
1689 runtime->hw = azx_pcm_hw;
1690 runtime->hw.channels_min = hinfo->channels_min;
1691 runtime->hw.channels_max = hinfo->channels_max;
1692 runtime->hw.formats = hinfo->formats;
1693 runtime->hw.rates = hinfo->rates;
1694 snd_pcm_limit_hw_rates(runtime);
1695 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1696 if (chip->align_buffer_size)
1697 /* constrain buffer sizes to be multiple of 128
1698 bytes. This is more efficient in terms of memory
1699 access but isn't required by the HDA spec and
1700 prevents users from specifying exact period/buffer
1701 sizes. For example for 44.1kHz, a period size set
1702 to 20ms will be rounded to 19.59ms. */
1703 buff_step = 128;
1704 else
1705 /* Don't enforce steps on buffer sizes, still need to
1706 be multiple of 4 bytes (HDA spec). Tested on Intel
1707 HDA controllers, may not work on all devices where
1708 option needs to be disabled */
1709 buff_step = 4;
1710
1711 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1712 buff_step);
1713 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1714 buff_step);
1715 snd_hda_power_up(apcm->codec);
1716 err = hinfo->ops.open(hinfo, apcm->codec, substream);
1717 if (err < 0) {
1718 azx_release_device(azx_dev);
1719 snd_hda_power_down(apcm->codec);
1720 mutex_unlock(&chip->open_mutex);
1721 return err;
1722 }
1723 snd_pcm_limit_hw_rates(runtime);
1724 /* sanity check */
1725 if (snd_BUG_ON(!runtime->hw.channels_min) ||
1726 snd_BUG_ON(!runtime->hw.channels_max) ||
1727 snd_BUG_ON(!runtime->hw.formats) ||
1728 snd_BUG_ON(!runtime->hw.rates)) {
1729 azx_release_device(azx_dev);
1730 hinfo->ops.close(hinfo, apcm->codec, substream);
1731 snd_hda_power_down(apcm->codec);
1732 mutex_unlock(&chip->open_mutex);
1733 return -EINVAL;
1734 }
1735 spin_lock_irqsave(&chip->reg_lock, flags);
1736 azx_dev->substream = substream;
1737 azx_dev->running = 0;
1738 spin_unlock_irqrestore(&chip->reg_lock, flags);
1739
1740 runtime->private_data = azx_dev;
1741 snd_pcm_set_sync(substream);
1742 mutex_unlock(&chip->open_mutex);
1743 return 0;
1744 }
1745
1746 static int azx_pcm_close(struct snd_pcm_substream *substream)
1747 {
1748 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1749 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1750 struct azx *chip = apcm->chip;
1751 struct azx_dev *azx_dev = get_azx_dev(substream);
1752 unsigned long flags;
1753
1754 mutex_lock(&chip->open_mutex);
1755 spin_lock_irqsave(&chip->reg_lock, flags);
1756 azx_dev->substream = NULL;
1757 azx_dev->running = 0;
1758 spin_unlock_irqrestore(&chip->reg_lock, flags);
1759 azx_release_device(azx_dev);
1760 hinfo->ops.close(hinfo, apcm->codec, substream);
1761 snd_hda_power_down(apcm->codec);
1762 mutex_unlock(&chip->open_mutex);
1763 return 0;
1764 }
1765
1766 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1767 struct snd_pcm_hw_params *hw_params)
1768 {
1769 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1770 struct azx *chip = apcm->chip;
1771 struct snd_pcm_runtime *runtime = substream->runtime;
1772 struct azx_dev *azx_dev = get_azx_dev(substream);
1773 int ret;
1774
1775 mark_runtime_wc(chip, azx_dev, runtime, false);
1776 azx_dev->bufsize = 0;
1777 azx_dev->period_bytes = 0;
1778 azx_dev->format_val = 0;
1779 ret = snd_pcm_lib_malloc_pages(substream,
1780 params_buffer_bytes(hw_params));
1781 if (ret < 0)
1782 return ret;
1783 mark_runtime_wc(chip, azx_dev, runtime, true);
1784 return ret;
1785 }
1786
1787 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1788 {
1789 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1790 struct azx_dev *azx_dev = get_azx_dev(substream);
1791 struct azx *chip = apcm->chip;
1792 struct snd_pcm_runtime *runtime = substream->runtime;
1793 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1794
1795 /* reset BDL address */
1796 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1797 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1798 azx_sd_writel(azx_dev, SD_CTL, 0);
1799 azx_dev->bufsize = 0;
1800 azx_dev->period_bytes = 0;
1801 azx_dev->format_val = 0;
1802
1803 snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
1804
1805 mark_runtime_wc(chip, azx_dev, runtime, false);
1806 return snd_pcm_lib_free_pages(substream);
1807 }
1808
1809 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1810 {
1811 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1812 struct azx *chip = apcm->chip;
1813 struct azx_dev *azx_dev = get_azx_dev(substream);
1814 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1815 struct snd_pcm_runtime *runtime = substream->runtime;
1816 unsigned int bufsize, period_bytes, format_val, stream_tag;
1817 int err;
1818 struct hda_spdif_out *spdif =
1819 snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid);
1820 unsigned short ctls = spdif ? spdif->ctls : 0;
1821
1822 azx_stream_reset(chip, azx_dev);
1823 format_val = snd_hda_calc_stream_format(runtime->rate,
1824 runtime->channels,
1825 runtime->format,
1826 hinfo->maxbps,
1827 ctls);
1828 if (!format_val) {
1829 snd_printk(KERN_ERR SFX
1830 "invalid format_val, rate=%d, ch=%d, format=%d\n",
1831 runtime->rate, runtime->channels, runtime->format);
1832 return -EINVAL;
1833 }
1834
1835 bufsize = snd_pcm_lib_buffer_bytes(substream);
1836 period_bytes = snd_pcm_lib_period_bytes(substream);
1837
1838 snd_printdd(SFX "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
1839 bufsize, format_val);
1840
1841 if (bufsize != azx_dev->bufsize ||
1842 period_bytes != azx_dev->period_bytes ||
1843 format_val != azx_dev->format_val) {
1844 azx_dev->bufsize = bufsize;
1845 azx_dev->period_bytes = period_bytes;
1846 azx_dev->format_val = format_val;
1847 err = azx_setup_periods(chip, substream, azx_dev);
1848 if (err < 0)
1849 return err;
1850 }
1851
1852 /* wallclk has 24Mhz clock source */
1853 azx_dev->period_wallclk = (((runtime->period_size * 24000) /
1854 runtime->rate) * 1000);
1855 azx_setup_controller(chip, azx_dev);
1856 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1857 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1858 else
1859 azx_dev->fifo_size = 0;
1860
1861 stream_tag = azx_dev->stream_tag;
1862 /* CA-IBG chips need the playback stream starting from 1 */
1863 if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) &&
1864 stream_tag > chip->capture_streams)
1865 stream_tag -= chip->capture_streams;
1866 return snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
1867 azx_dev->format_val, substream);
1868 }
1869
1870 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1871 {
1872 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1873 struct azx *chip = apcm->chip;
1874 struct azx_dev *azx_dev;
1875 struct snd_pcm_substream *s;
1876 int rstart = 0, start, nsync = 0, sbits = 0;
1877 int nwait, timeout;
1878
1879 switch (cmd) {
1880 case SNDRV_PCM_TRIGGER_START:
1881 rstart = 1;
1882 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1883 case SNDRV_PCM_TRIGGER_RESUME:
1884 start = 1;
1885 break;
1886 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1887 case SNDRV_PCM_TRIGGER_SUSPEND:
1888 case SNDRV_PCM_TRIGGER_STOP:
1889 start = 0;
1890 break;
1891 default:
1892 return -EINVAL;
1893 }
1894
1895 snd_pcm_group_for_each_entry(s, substream) {
1896 if (s->pcm->card != substream->pcm->card)
1897 continue;
1898 azx_dev = get_azx_dev(s);
1899 sbits |= 1 << azx_dev->index;
1900 nsync++;
1901 snd_pcm_trigger_done(s, substream);
1902 }
1903
1904 spin_lock(&chip->reg_lock);
1905 if (nsync > 1) {
1906 /* first, set SYNC bits of corresponding streams */
1907 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
1908 azx_writel(chip, OLD_SSYNC,
1909 azx_readl(chip, OLD_SSYNC) | sbits);
1910 else
1911 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) | sbits);
1912 }
1913 snd_pcm_group_for_each_entry(s, substream) {
1914 if (s->pcm->card != substream->pcm->card)
1915 continue;
1916 azx_dev = get_azx_dev(s);
1917 if (start) {
1918 azx_dev->start_wallclk = azx_readl(chip, WALLCLK);
1919 if (!rstart)
1920 azx_dev->start_wallclk -=
1921 azx_dev->period_wallclk;
1922 azx_stream_start(chip, azx_dev);
1923 } else {
1924 azx_stream_stop(chip, azx_dev);
1925 }
1926 azx_dev->running = start;
1927 }
1928 spin_unlock(&chip->reg_lock);
1929 if (start) {
1930 if (nsync == 1)
1931 return 0;
1932 /* wait until all FIFOs get ready */
1933 for (timeout = 5000; timeout; timeout--) {
1934 nwait = 0;
1935 snd_pcm_group_for_each_entry(s, substream) {
1936 if (s->pcm->card != substream->pcm->card)
1937 continue;
1938 azx_dev = get_azx_dev(s);
1939 if (!(azx_sd_readb(azx_dev, SD_STS) &
1940 SD_STS_FIFO_READY))
1941 nwait++;
1942 }
1943 if (!nwait)
1944 break;
1945 cpu_relax();
1946 }
1947 } else {
1948 /* wait until all RUN bits are cleared */
1949 for (timeout = 5000; timeout; timeout--) {
1950 nwait = 0;
1951 snd_pcm_group_for_each_entry(s, substream) {
1952 if (s->pcm->card != substream->pcm->card)
1953 continue;
1954 azx_dev = get_azx_dev(s);
1955 if (azx_sd_readb(azx_dev, SD_CTL) &
1956 SD_CTL_DMA_START)
1957 nwait++;
1958 }
1959 if (!nwait)
1960 break;
1961 cpu_relax();
1962 }
1963 }
1964 if (nsync > 1) {
1965 spin_lock(&chip->reg_lock);
1966 /* reset SYNC bits */
1967 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
1968 azx_writel(chip, OLD_SSYNC,
1969 azx_readl(chip, OLD_SSYNC) & ~sbits);
1970 else
1971 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) & ~sbits);
1972 spin_unlock(&chip->reg_lock);
1973 }
1974 return 0;
1975 }
1976
1977 /* get the current DMA position with correction on VIA chips */
1978 static unsigned int azx_via_get_position(struct azx *chip,
1979 struct azx_dev *azx_dev)
1980 {
1981 unsigned int link_pos, mini_pos, bound_pos;
1982 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
1983 unsigned int fifo_size;
1984
1985 link_pos = azx_sd_readl(azx_dev, SD_LPIB);
1986 if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1987 /* Playback, no problem using link position */
1988 return link_pos;
1989 }
1990
1991 /* Capture */
1992 /* For new chipset,
1993 * use mod to get the DMA position just like old chipset
1994 */
1995 mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
1996 mod_dma_pos %= azx_dev->period_bytes;
1997
1998 /* azx_dev->fifo_size can't get FIFO size of in stream.
1999 * Get from base address + offset.
2000 */
2001 fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
2002
2003 if (azx_dev->insufficient) {
2004 /* Link position never gather than FIFO size */
2005 if (link_pos <= fifo_size)
2006 return 0;
2007
2008 azx_dev->insufficient = 0;
2009 }
2010
2011 if (link_pos <= fifo_size)
2012 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
2013 else
2014 mini_pos = link_pos - fifo_size;
2015
2016 /* Find nearest previous boudary */
2017 mod_mini_pos = mini_pos % azx_dev->period_bytes;
2018 mod_link_pos = link_pos % azx_dev->period_bytes;
2019 if (mod_link_pos >= fifo_size)
2020 bound_pos = link_pos - mod_link_pos;
2021 else if (mod_dma_pos >= mod_mini_pos)
2022 bound_pos = mini_pos - mod_mini_pos;
2023 else {
2024 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
2025 if (bound_pos >= azx_dev->bufsize)
2026 bound_pos = 0;
2027 }
2028
2029 /* Calculate real DMA position we want */
2030 return bound_pos + mod_dma_pos;
2031 }
2032
2033 static unsigned int azx_get_position(struct azx *chip,
2034 struct azx_dev *azx_dev,
2035 bool with_check)
2036 {
2037 unsigned int pos;
2038 int stream = azx_dev->substream->stream;
2039
2040 switch (chip->position_fix[stream]) {
2041 case POS_FIX_LPIB:
2042 /* read LPIB */
2043 pos = azx_sd_readl(azx_dev, SD_LPIB);
2044 break;
2045 case POS_FIX_VIACOMBO:
2046 pos = azx_via_get_position(chip, azx_dev);
2047 break;
2048 default:
2049 /* use the position buffer */
2050 pos = le32_to_cpu(*azx_dev->posbuf);
2051 if (with_check && chip->position_fix[stream] == POS_FIX_AUTO) {
2052 if (!pos || pos == (u32)-1) {
2053 printk(KERN_WARNING
2054 "hda-intel: Invalid position buffer, "
2055 "using LPIB read method instead.\n");
2056 chip->position_fix[stream] = POS_FIX_LPIB;
2057 pos = azx_sd_readl(azx_dev, SD_LPIB);
2058 } else
2059 chip->position_fix[stream] = POS_FIX_POSBUF;
2060 }
2061 break;
2062 }
2063
2064 if (pos >= azx_dev->bufsize)
2065 pos = 0;
2066 return pos;
2067 }
2068
2069 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
2070 {
2071 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2072 struct azx *chip = apcm->chip;
2073 struct azx_dev *azx_dev = get_azx_dev(substream);
2074 return bytes_to_frames(substream->runtime,
2075 azx_get_position(chip, azx_dev, false));
2076 }
2077
2078 /*
2079 * Check whether the current DMA position is acceptable for updating
2080 * periods. Returns non-zero if it's OK.
2081 *
2082 * Many HD-audio controllers appear pretty inaccurate about
2083 * the update-IRQ timing. The IRQ is issued before actually the
2084 * data is processed. So, we need to process it afterwords in a
2085 * workqueue.
2086 */
2087 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
2088 {
2089 u32 wallclk;
2090 unsigned int pos;
2091 int stream;
2092
2093 wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
2094 if (wallclk < (azx_dev->period_wallclk * 2) / 3)
2095 return -1; /* bogus (too early) interrupt */
2096
2097 stream = azx_dev->substream->stream;
2098 pos = azx_get_position(chip, azx_dev, true);
2099
2100 if (WARN_ONCE(!azx_dev->period_bytes,
2101 "hda-intel: zero azx_dev->period_bytes"))
2102 return -1; /* this shouldn't happen! */
2103 if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
2104 pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
2105 /* NG - it's below the first next period boundary */
2106 return bdl_pos_adj[chip->dev_index] ? 0 : -1;
2107 azx_dev->start_wallclk += wallclk;
2108 return 1; /* OK, it's fine */
2109 }
2110
2111 /*
2112 * The work for pending PCM period updates.
2113 */
2114 static void azx_irq_pending_work(struct work_struct *work)
2115 {
2116 struct azx *chip = container_of(work, struct azx, irq_pending_work);
2117 int i, pending, ok;
2118
2119 if (!chip->irq_pending_warned) {
2120 printk(KERN_WARNING
2121 "hda-intel: IRQ timing workaround is activated "
2122 "for card #%d. Suggest a bigger bdl_pos_adj.\n",
2123 chip->card->number);
2124 chip->irq_pending_warned = 1;
2125 }
2126
2127 for (;;) {
2128 pending = 0;
2129 spin_lock_irq(&chip->reg_lock);
2130 for (i = 0; i < chip->num_streams; i++) {
2131 struct azx_dev *azx_dev = &chip->azx_dev[i];
2132 if (!azx_dev->irq_pending ||
2133 !azx_dev->substream ||
2134 !azx_dev->running)
2135 continue;
2136 ok = azx_position_ok(chip, azx_dev);
2137 if (ok > 0) {
2138 azx_dev->irq_pending = 0;
2139 spin_unlock(&chip->reg_lock);
2140 snd_pcm_period_elapsed(azx_dev->substream);
2141 spin_lock(&chip->reg_lock);
2142 } else if (ok < 0) {
2143 pending = 0; /* too early */
2144 } else
2145 pending++;
2146 }
2147 spin_unlock_irq(&chip->reg_lock);
2148 if (!pending)
2149 return;
2150 msleep(1);
2151 }
2152 }
2153
2154 /* clear irq_pending flags and assure no on-going workq */
2155 static void azx_clear_irq_pending(struct azx *chip)
2156 {
2157 int i;
2158
2159 spin_lock_irq(&chip->reg_lock);
2160 for (i = 0; i < chip->num_streams; i++)
2161 chip->azx_dev[i].irq_pending = 0;
2162 spin_unlock_irq(&chip->reg_lock);
2163 }
2164
2165 #ifdef CONFIG_X86
2166 static int azx_pcm_mmap(struct snd_pcm_substream *substream,
2167 struct vm_area_struct *area)
2168 {
2169 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2170 struct azx *chip = apcm->chip;
2171 if (!azx_snoop(chip))
2172 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2173 return snd_pcm_lib_default_mmap(substream, area);
2174 }
2175 #else
2176 #define azx_pcm_mmap NULL
2177 #endif
2178
2179 static struct snd_pcm_ops azx_pcm_ops = {
2180 .open = azx_pcm_open,
2181 .close = azx_pcm_close,
2182 .ioctl = snd_pcm_lib_ioctl,
2183 .hw_params = azx_pcm_hw_params,
2184 .hw_free = azx_pcm_hw_free,
2185 .prepare = azx_pcm_prepare,
2186 .trigger = azx_pcm_trigger,
2187 .pointer = azx_pcm_pointer,
2188 .mmap = azx_pcm_mmap,
2189 .page = snd_pcm_sgbuf_ops_page,
2190 };
2191
2192 static void azx_pcm_free(struct snd_pcm *pcm)
2193 {
2194 struct azx_pcm *apcm = pcm->private_data;
2195 if (apcm) {
2196 list_del(&apcm->list);
2197 kfree(apcm);
2198 }
2199 }
2200
2201 #define MAX_PREALLOC_SIZE (32 * 1024 * 1024)
2202
2203 static int
2204 azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
2205 struct hda_pcm *cpcm)
2206 {
2207 struct azx *chip = bus->private_data;
2208 struct snd_pcm *pcm;
2209 struct azx_pcm *apcm;
2210 int pcm_dev = cpcm->device;
2211 unsigned int size;
2212 int s, err;
2213
2214 list_for_each_entry(apcm, &chip->pcm_list, list) {
2215 if (apcm->pcm->device == pcm_dev) {
2216 snd_printk(KERN_ERR SFX "PCM %d already exists\n", pcm_dev);
2217 return -EBUSY;
2218 }
2219 }
2220 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
2221 cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
2222 cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
2223 &pcm);
2224 if (err < 0)
2225 return err;
2226 strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
2227 apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
2228 if (apcm == NULL)
2229 return -ENOMEM;
2230 apcm->chip = chip;
2231 apcm->pcm = pcm;
2232 apcm->codec = codec;
2233 pcm->private_data = apcm;
2234 pcm->private_free = azx_pcm_free;
2235 if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
2236 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
2237 list_add_tail(&apcm->list, &chip->pcm_list);
2238 cpcm->pcm = pcm;
2239 for (s = 0; s < 2; s++) {
2240 apcm->hinfo[s] = &cpcm->stream[s];
2241 if (cpcm->stream[s].substreams)
2242 snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
2243 }
2244 /* buffer pre-allocation */
2245 size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
2246 if (size > MAX_PREALLOC_SIZE)
2247 size = MAX_PREALLOC_SIZE;
2248 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
2249 snd_dma_pci_data(chip->pci),
2250 size, MAX_PREALLOC_SIZE);
2251 return 0;
2252 }
2253
2254 /*
2255 * mixer creation - all stuff is implemented in hda module
2256 */
2257 static int __devinit azx_mixer_create(struct azx *chip)
2258 {
2259 return snd_hda_build_controls(chip->bus);
2260 }
2261
2262
2263 /*
2264 * initialize SD streams
2265 */
2266 static int __devinit azx_init_stream(struct azx *chip)
2267 {
2268 int i;
2269
2270 /* initialize each stream (aka device)
2271 * assign the starting bdl address to each stream (device)
2272 * and initialize
2273 */
2274 for (i = 0; i < chip->num_streams; i++) {
2275 struct azx_dev *azx_dev = &chip->azx_dev[i];
2276 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
2277 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
2278 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
2279 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
2280 azx_dev->sd_int_sta_mask = 1 << i;
2281 /* stream tag: must be non-zero and unique */
2282 azx_dev->index = i;
2283 azx_dev->stream_tag = i + 1;
2284 }
2285
2286 return 0;
2287 }
2288
2289 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
2290 {
2291 if (request_irq(chip->pci->irq, azx_interrupt,
2292 chip->msi ? 0 : IRQF_SHARED,
2293 KBUILD_MODNAME, chip)) {
2294 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
2295 "disabling device\n", chip->pci->irq);
2296 if (do_disconnect)
2297 snd_card_disconnect(chip->card);
2298 return -1;
2299 }
2300 chip->irq = chip->pci->irq;
2301 pci_intx(chip->pci, !chip->msi);
2302 return 0;
2303 }
2304
2305
2306 static void azx_stop_chip(struct azx *chip)
2307 {
2308 if (!chip->initialized)
2309 return;
2310
2311 /* disable interrupts */
2312 azx_int_disable(chip);
2313 azx_int_clear(chip);
2314
2315 /* disable CORB/RIRB */
2316 azx_free_cmd_io(chip);
2317
2318 /* disable position buffer */
2319 azx_writel(chip, DPLBASE, 0);
2320 azx_writel(chip, DPUBASE, 0);
2321
2322 chip->initialized = 0;
2323 }
2324
2325 #ifdef CONFIG_SND_HDA_POWER_SAVE
2326 /* power-up/down the controller */
2327 static void azx_power_notify(struct hda_bus *bus)
2328 {
2329 struct azx *chip = bus->private_data;
2330 struct hda_codec *c;
2331 int power_on = 0;
2332
2333 list_for_each_entry(c, &bus->codec_list, list) {
2334 if (c->power_on) {
2335 power_on = 1;
2336 break;
2337 }
2338 }
2339 if (power_on)
2340 azx_init_chip(chip, 1);
2341 else if (chip->running && power_save_controller &&
2342 !bus->power_keep_link_on)
2343 azx_stop_chip(chip);
2344 }
2345 #endif /* CONFIG_SND_HDA_POWER_SAVE */
2346
2347 #ifdef CONFIG_PM
2348 /*
2349 * power management
2350 */
2351
2352 static int snd_hda_codecs_inuse(struct hda_bus *bus)
2353 {
2354 struct hda_codec *codec;
2355
2356 list_for_each_entry(codec, &bus->codec_list, list) {
2357 if (snd_hda_codec_needs_resume(codec))
2358 return 1;
2359 }
2360 return 0;
2361 }
2362
2363 static int azx_suspend(struct pci_dev *pci, pm_message_t state)
2364 {
2365 struct snd_card *card = pci_get_drvdata(pci);
2366 struct azx *chip = card->private_data;
2367 struct azx_pcm *p;
2368
2369 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2370 azx_clear_irq_pending(chip);
2371 list_for_each_entry(p, &chip->pcm_list, list)
2372 snd_pcm_suspend_all(p->pcm);
2373 if (chip->initialized)
2374 snd_hda_suspend(chip->bus);
2375 azx_stop_chip(chip);
2376 if (chip->irq >= 0) {
2377 free_irq(chip->irq, chip);
2378 chip->irq = -1;
2379 }
2380 if (chip->msi)
2381 pci_disable_msi(chip->pci);
2382 pci_disable_device(pci);
2383 pci_save_state(pci);
2384 pci_set_power_state(pci, pci_choose_state(pci, state));
2385 return 0;
2386 }
2387
2388 static int azx_resume(struct pci_dev *pci)
2389 {
2390 struct snd_card *card = pci_get_drvdata(pci);
2391 struct azx *chip = card->private_data;
2392
2393 pci_set_power_state(pci, PCI_D0);
2394 pci_restore_state(pci);
2395 if (pci_enable_device(pci) < 0) {
2396 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2397 "disabling device\n");
2398 snd_card_disconnect(card);
2399 return -EIO;
2400 }
2401 pci_set_master(pci);
2402 if (chip->msi)
2403 if (pci_enable_msi(pci) < 0)
2404 chip->msi = 0;
2405 if (azx_acquire_irq(chip, 1) < 0)
2406 return -EIO;
2407 azx_init_pci(chip);
2408
2409 if (snd_hda_codecs_inuse(chip->bus))
2410 azx_init_chip(chip, 1);
2411
2412 snd_hda_resume(chip->bus);
2413 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2414 return 0;
2415 }
2416 #endif /* CONFIG_PM */
2417
2418
2419 /*
2420 * reboot notifier for hang-up problem at power-down
2421 */
2422 static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
2423 {
2424 struct azx *chip = container_of(nb, struct azx, reboot_notifier);
2425 snd_hda_bus_reboot_notify(chip->bus);
2426 azx_stop_chip(chip);
2427 return NOTIFY_OK;
2428 }
2429
2430 static void azx_notifier_register(struct azx *chip)
2431 {
2432 chip->reboot_notifier.notifier_call = azx_halt;
2433 register_reboot_notifier(&chip->reboot_notifier);
2434 }
2435
2436 static void azx_notifier_unregister(struct azx *chip)
2437 {
2438 if (chip->reboot_notifier.notifier_call)
2439 unregister_reboot_notifier(&chip->reboot_notifier);
2440 }
2441
2442 /*
2443 * destructor
2444 */
2445 static int azx_free(struct azx *chip)
2446 {
2447 int i;
2448
2449 azx_notifier_unregister(chip);
2450
2451 if (chip->initialized) {
2452 azx_clear_irq_pending(chip);
2453 for (i = 0; i < chip->num_streams; i++)
2454 azx_stream_stop(chip, &chip->azx_dev[i]);
2455 azx_stop_chip(chip);
2456 }
2457
2458 if (chip->irq >= 0)
2459 free_irq(chip->irq, (void*)chip);
2460 if (chip->msi)
2461 pci_disable_msi(chip->pci);
2462 if (chip->remap_addr)
2463 iounmap(chip->remap_addr);
2464
2465 if (chip->azx_dev) {
2466 for (i = 0; i < chip->num_streams; i++)
2467 if (chip->azx_dev[i].bdl.area) {
2468 mark_pages_wc(chip, &chip->azx_dev[i].bdl, false);
2469 snd_dma_free_pages(&chip->azx_dev[i].bdl);
2470 }
2471 }
2472 if (chip->rb.area) {
2473 mark_pages_wc(chip, &chip->rb, false);
2474 snd_dma_free_pages(&chip->rb);
2475 }
2476 if (chip->posbuf.area) {
2477 mark_pages_wc(chip, &chip->posbuf, false);
2478 snd_dma_free_pages(&chip->posbuf);
2479 }
2480 pci_release_regions(chip->pci);
2481 pci_disable_device(chip->pci);
2482 kfree(chip->azx_dev);
2483 kfree(chip);
2484
2485 return 0;
2486 }
2487
2488 static int azx_dev_free(struct snd_device *device)
2489 {
2490 return azx_free(device->device_data);
2491 }
2492
2493 /*
2494 * white/black-listing for position_fix
2495 */
2496 static struct snd_pci_quirk position_fix_list[] __devinitdata = {
2497 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2498 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2499 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
2500 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
2501 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
2502 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
2503 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
2504 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
2505 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
2506 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
2507 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
2508 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
2509 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
2510 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
2511 {}
2512 };
2513
2514 static int __devinit check_position_fix(struct azx *chip, int fix)
2515 {
2516 const struct snd_pci_quirk *q;
2517
2518 switch (fix) {
2519 case POS_FIX_LPIB:
2520 case POS_FIX_POSBUF:
2521 case POS_FIX_VIACOMBO:
2522 return fix;
2523 }
2524
2525 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
2526 if (q) {
2527 printk(KERN_INFO
2528 "hda_intel: position_fix set to %d "
2529 "for device %04x:%04x\n",
2530 q->value, q->subvendor, q->subdevice);
2531 return q->value;
2532 }
2533
2534 /* Check VIA/ATI HD Audio Controller exist */
2535 if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
2536 snd_printd(SFX "Using VIACOMBO position fix\n");
2537 return POS_FIX_VIACOMBO;
2538 }
2539 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
2540 snd_printd(SFX "Using LPIB position fix\n");
2541 return POS_FIX_LPIB;
2542 }
2543 return POS_FIX_AUTO;
2544 }
2545
2546 /*
2547 * black-lists for probe_mask
2548 */
2549 static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
2550 /* Thinkpad often breaks the controller communication when accessing
2551 * to the non-working (or non-existing) modem codec slot.
2552 */
2553 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
2554 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
2555 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
2556 /* broken BIOS */
2557 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
2558 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
2559 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
2560 /* forced codec slots */
2561 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
2562 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
2563 {}
2564 };
2565
2566 #define AZX_FORCE_CODEC_MASK 0x100
2567
2568 static void __devinit check_probe_mask(struct azx *chip, int dev)
2569 {
2570 const struct snd_pci_quirk *q;
2571
2572 chip->codec_probe_mask = probe_mask[dev];
2573 if (chip->codec_probe_mask == -1) {
2574 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
2575 if (q) {
2576 printk(KERN_INFO
2577 "hda_intel: probe_mask set to 0x%x "
2578 "for device %04x:%04x\n",
2579 q->value, q->subvendor, q->subdevice);
2580 chip->codec_probe_mask = q->value;
2581 }
2582 }
2583
2584 /* check forced option */
2585 if (chip->codec_probe_mask != -1 &&
2586 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
2587 chip->codec_mask = chip->codec_probe_mask & 0xff;
2588 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
2589 chip->codec_mask);
2590 }
2591 }
2592
2593 /*
2594 * white/black-list for enable_msi
2595 */
2596 static struct snd_pci_quirk msi_black_list[] __devinitdata = {
2597 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
2598 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
2599 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
2600 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
2601 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
2602 {}
2603 };
2604
2605 static void __devinit check_msi(struct azx *chip)
2606 {
2607 const struct snd_pci_quirk *q;
2608
2609 if (enable_msi >= 0) {
2610 chip->msi = !!enable_msi;
2611 return;
2612 }
2613 chip->msi = 1; /* enable MSI as default */
2614 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
2615 if (q) {
2616 printk(KERN_INFO
2617 "hda_intel: msi for device %04x:%04x set to %d\n",
2618 q->subvendor, q->subdevice, q->value);
2619 chip->msi = q->value;
2620 return;
2621 }
2622
2623 /* NVidia chipsets seem to cause troubles with MSI */
2624 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
2625 printk(KERN_INFO "hda_intel: Disabling MSI\n");
2626 chip->msi = 0;
2627 }
2628 }
2629
2630 /* check the snoop mode availability */
2631 static void __devinit azx_check_snoop_available(struct azx *chip)
2632 {
2633 bool snoop = chip->snoop;
2634
2635 switch (chip->driver_type) {
2636 case AZX_DRIVER_VIA:
2637 /* force to non-snoop mode for a new VIA controller
2638 * when BIOS is set
2639 */
2640 if (snoop) {
2641 u8 val;
2642 pci_read_config_byte(chip->pci, 0x42, &val);
2643 if (!(val & 0x80) && chip->pci->revision == 0x30)
2644 snoop = false;
2645 }
2646 break;
2647 case AZX_DRIVER_ATIHDMI_NS:
2648 /* new ATI HDMI requires non-snoop */
2649 snoop = false;
2650 break;
2651 }
2652
2653 if (snoop != chip->snoop) {
2654 snd_printk(KERN_INFO SFX "Force to %s mode\n",
2655 snoop ? "snoop" : "non-snoop");
2656 chip->snoop = snoop;
2657 }
2658 }
2659
2660 /*
2661 * constructor
2662 */
2663 static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
2664 int dev, unsigned int driver_caps,
2665 struct azx **rchip)
2666 {
2667 struct azx *chip;
2668 int i, err;
2669 unsigned short gcap;
2670 static struct snd_device_ops ops = {
2671 .dev_free = azx_dev_free,
2672 };
2673
2674 *rchip = NULL;
2675
2676 err = pci_enable_device(pci);
2677 if (err < 0)
2678 return err;
2679
2680 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2681 if (!chip) {
2682 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
2683 pci_disable_device(pci);
2684 return -ENOMEM;
2685 }
2686
2687 spin_lock_init(&chip->reg_lock);
2688 mutex_init(&chip->open_mutex);
2689 chip->card = card;
2690 chip->pci = pci;
2691 chip->irq = -1;
2692 chip->driver_caps = driver_caps;
2693 chip->driver_type = driver_caps & 0xff;
2694 check_msi(chip);
2695 chip->dev_index = dev;
2696 INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
2697 INIT_LIST_HEAD(&chip->pcm_list);
2698
2699 chip->position_fix[0] = chip->position_fix[1] =
2700 check_position_fix(chip, position_fix[dev]);
2701 check_probe_mask(chip, dev);
2702
2703 chip->single_cmd = single_cmd;
2704 chip->snoop = hda_snoop;
2705 azx_check_snoop_available(chip);
2706
2707 if (bdl_pos_adj[dev] < 0) {
2708 switch (chip->driver_type) {
2709 case AZX_DRIVER_ICH:
2710 case AZX_DRIVER_PCH:
2711 bdl_pos_adj[dev] = 1;
2712 break;
2713 default:
2714 bdl_pos_adj[dev] = 32;
2715 break;
2716 }
2717 }
2718
2719 #if BITS_PER_LONG != 64
2720 /* Fix up base address on ULI M5461 */
2721 if (chip->driver_type == AZX_DRIVER_ULI) {
2722 u16 tmp3;
2723 pci_read_config_word(pci, 0x40, &tmp3);
2724 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
2725 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
2726 }
2727 #endif
2728
2729 err = pci_request_regions(pci, "ICH HD audio");
2730 if (err < 0) {
2731 kfree(chip);
2732 pci_disable_device(pci);
2733 return err;
2734 }
2735
2736 chip->addr = pci_resource_start(pci, 0);
2737 chip->remap_addr = pci_ioremap_bar(pci, 0);
2738 if (chip->remap_addr == NULL) {
2739 snd_printk(KERN_ERR SFX "ioremap error\n");
2740 err = -ENXIO;
2741 goto errout;
2742 }
2743
2744 if (chip->msi)
2745 if (pci_enable_msi(pci) < 0)
2746 chip->msi = 0;
2747
2748 if (azx_acquire_irq(chip, 0) < 0) {
2749 err = -EBUSY;
2750 goto errout;
2751 }
2752
2753 pci_set_master(pci);
2754 synchronize_irq(chip->irq);
2755
2756 gcap = azx_readw(chip, GCAP);
2757 snd_printdd(SFX "chipset global capabilities = 0x%x\n", gcap);
2758
2759 /* disable SB600 64bit support for safety */
2760 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
2761 struct pci_dev *p_smbus;
2762 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
2763 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2764 NULL);
2765 if (p_smbus) {
2766 if (p_smbus->revision < 0x30)
2767 gcap &= ~ICH6_GCAP_64OK;
2768 pci_dev_put(p_smbus);
2769 }
2770 }
2771
2772 /* disable 64bit DMA address on some devices */
2773 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
2774 snd_printd(SFX "Disabling 64bit DMA\n");
2775 gcap &= ~ICH6_GCAP_64OK;
2776 }
2777
2778 /* disable buffer size rounding to 128-byte multiples if supported */
2779 chip->align_buffer_size = align_buffer_size;
2780 if (chip->driver_caps & AZX_DCAPS_BUFSIZE)
2781 chip->align_buffer_size = 0;
2782
2783 /* allow 64bit DMA address if supported by H/W */
2784 if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
2785 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
2786 else {
2787 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
2788 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
2789 }
2790
2791 /* read number of streams from GCAP register instead of using
2792 * hardcoded value
2793 */
2794 chip->capture_streams = (gcap >> 8) & 0x0f;
2795 chip->playback_streams = (gcap >> 12) & 0x0f;
2796 if (!chip->playback_streams && !chip->capture_streams) {
2797 /* gcap didn't give any info, switching to old method */
2798
2799 switch (chip->driver_type) {
2800 case AZX_DRIVER_ULI:
2801 chip->playback_streams = ULI_NUM_PLAYBACK;
2802 chip->capture_streams = ULI_NUM_CAPTURE;
2803 break;
2804 case AZX_DRIVER_ATIHDMI:
2805 case AZX_DRIVER_ATIHDMI_NS:
2806 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
2807 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
2808 break;
2809 case AZX_DRIVER_GENERIC:
2810 default:
2811 chip->playback_streams = ICH6_NUM_PLAYBACK;
2812 chip->capture_streams = ICH6_NUM_CAPTURE;
2813 break;
2814 }
2815 }
2816 chip->capture_index_offset = 0;
2817 chip->playback_index_offset = chip->capture_streams;
2818 chip->num_streams = chip->playback_streams + chip->capture_streams;
2819 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
2820 GFP_KERNEL);
2821 if (!chip->azx_dev) {
2822 snd_printk(KERN_ERR SFX "cannot malloc azx_dev\n");
2823 goto errout;
2824 }
2825
2826 for (i = 0; i < chip->num_streams; i++) {
2827 /* allocate memory for the BDL for each stream */
2828 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2829 snd_dma_pci_data(chip->pci),
2830 BDL_SIZE, &chip->azx_dev[i].bdl);
2831 if (err < 0) {
2832 snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
2833 goto errout;
2834 }
2835 mark_pages_wc(chip, &chip->azx_dev[i].bdl, true);
2836 }
2837 /* allocate memory for the position buffer */
2838 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2839 snd_dma_pci_data(chip->pci),
2840 chip->num_streams * 8, &chip->posbuf);
2841 if (err < 0) {
2842 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
2843 goto errout;
2844 }
2845 mark_pages_wc(chip, &chip->posbuf, true);
2846 /* allocate CORB/RIRB */
2847 err = azx_alloc_cmd_io(chip);
2848 if (err < 0)
2849 goto errout;
2850
2851 /* initialize streams */
2852 azx_init_stream(chip);
2853
2854 /* initialize chip */
2855 azx_init_pci(chip);
2856 azx_init_chip(chip, (probe_only[dev] & 2) == 0);
2857
2858 /* codec detection */
2859 if (!chip->codec_mask) {
2860 snd_printk(KERN_ERR SFX "no codecs found!\n");
2861 err = -ENODEV;
2862 goto errout;
2863 }
2864
2865 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
2866 if (err <0) {
2867 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
2868 goto errout;
2869 }
2870
2871 strcpy(card->driver, "HDA-Intel");
2872 strlcpy(card->shortname, driver_short_names[chip->driver_type],
2873 sizeof(card->shortname));
2874 snprintf(card->longname, sizeof(card->longname),
2875 "%s at 0x%lx irq %i",
2876 card->shortname, chip->addr, chip->irq);
2877
2878 *rchip = chip;
2879 return 0;
2880
2881 errout:
2882 azx_free(chip);
2883 return err;
2884 }
2885
2886 static void power_down_all_codecs(struct azx *chip)
2887 {
2888 #ifdef CONFIG_SND_HDA_POWER_SAVE
2889 /* The codecs were powered up in snd_hda_codec_new().
2890 * Now all initialization done, so turn them down if possible
2891 */
2892 struct hda_codec *codec;
2893 list_for_each_entry(codec, &chip->bus->codec_list, list) {
2894 snd_hda_power_down(codec);
2895 }
2896 #endif
2897 }
2898
2899 static int __devinit azx_probe(struct pci_dev *pci,
2900 const struct pci_device_id *pci_id)
2901 {
2902 static int dev;
2903 struct snd_card *card;
2904 struct azx *chip;
2905 int err;
2906
2907 if (dev >= SNDRV_CARDS)
2908 return -ENODEV;
2909 if (!enable[dev]) {
2910 dev++;
2911 return -ENOENT;
2912 }
2913
2914 err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
2915 if (err < 0) {
2916 snd_printk(KERN_ERR SFX "Error creating card!\n");
2917 return err;
2918 }
2919
2920 /* set this here since it's referred in snd_hda_load_patch() */
2921 snd_card_set_dev(card, &pci->dev);
2922
2923 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2924 if (err < 0)
2925 goto out_free;
2926 card->private_data = chip;
2927
2928 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2929 chip->beep_mode = beep_mode[dev];
2930 #endif
2931
2932 /* create codec instances */
2933 err = azx_codec_create(chip, model[dev]);
2934 if (err < 0)
2935 goto out_free;
2936 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2937 if (patch[dev] && *patch[dev]) {
2938 snd_printk(KERN_ERR SFX "Applying patch firmware '%s'\n",
2939 patch[dev]);
2940 err = snd_hda_load_patch(chip->bus, patch[dev]);
2941 if (err < 0)
2942 goto out_free;
2943 }
2944 #endif
2945 if ((probe_only[dev] & 1) == 0) {
2946 err = azx_codec_configure(chip);
2947 if (err < 0)
2948 goto out_free;
2949 }
2950
2951 /* create PCM streams */
2952 err = snd_hda_build_pcms(chip->bus);
2953 if (err < 0)
2954 goto out_free;
2955
2956 /* create mixer controls */
2957 err = azx_mixer_create(chip);
2958 if (err < 0)
2959 goto out_free;
2960
2961 err = snd_card_register(card);
2962 if (err < 0)
2963 goto out_free;
2964
2965 pci_set_drvdata(pci, card);
2966 chip->running = 1;
2967 power_down_all_codecs(chip);
2968 azx_notifier_register(chip);
2969
2970 dev++;
2971 return err;
2972 out_free:
2973 snd_card_free(card);
2974 return err;
2975 }
2976
2977 static void __devexit azx_remove(struct pci_dev *pci)
2978 {
2979 snd_card_free(pci_get_drvdata(pci));
2980 pci_set_drvdata(pci, NULL);
2981 }
2982
2983 /* PCI IDs */
2984 static DEFINE_PCI_DEVICE_TABLE(azx_ids) = {
2985 /* CPT */
2986 { PCI_DEVICE(0x8086, 0x1c20),
2987 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
2988 AZX_DCAPS_BUFSIZE },
2989 /* PBG */
2990 { PCI_DEVICE(0x8086, 0x1d20),
2991 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
2992 AZX_DCAPS_BUFSIZE},
2993 /* Panther Point */
2994 { PCI_DEVICE(0x8086, 0x1e20),
2995 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
2996 AZX_DCAPS_BUFSIZE},
2997 /* SCH */
2998 { PCI_DEVICE(0x8086, 0x811b),
2999 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
3000 AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_LPIB }, /* Poulsbo */
3001 { PCI_DEVICE(0x8086, 0x080a),
3002 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
3003 AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_LPIB }, /* Oaktrail */
3004 /* ICH */
3005 { PCI_DEVICE(0x8086, 0x2668),
3006 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3007 AZX_DCAPS_BUFSIZE }, /* ICH6 */
3008 { PCI_DEVICE(0x8086, 0x27d8),
3009 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3010 AZX_DCAPS_BUFSIZE }, /* ICH7 */
3011 { PCI_DEVICE(0x8086, 0x269a),
3012 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3013 AZX_DCAPS_BUFSIZE }, /* ESB2 */
3014 { PCI_DEVICE(0x8086, 0x284b),
3015 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3016 AZX_DCAPS_BUFSIZE }, /* ICH8 */
3017 { PCI_DEVICE(0x8086, 0x293e),
3018 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3019 AZX_DCAPS_BUFSIZE }, /* ICH9 */
3020 { PCI_DEVICE(0x8086, 0x293f),
3021 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3022 AZX_DCAPS_BUFSIZE }, /* ICH9 */
3023 { PCI_DEVICE(0x8086, 0x3a3e),
3024 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3025 AZX_DCAPS_BUFSIZE }, /* ICH10 */
3026 { PCI_DEVICE(0x8086, 0x3a6e),
3027 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3028 AZX_DCAPS_BUFSIZE }, /* ICH10 */
3029 /* Generic Intel */
3030 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
3031 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3032 .class_mask = 0xffffff,
3033 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_BUFSIZE },
3034 /* ATI SB 450/600/700/800/900 */
3035 { PCI_DEVICE(0x1002, 0x437b),
3036 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3037 { PCI_DEVICE(0x1002, 0x4383),
3038 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3039 /* AMD Hudson */
3040 { PCI_DEVICE(0x1022, 0x780d),
3041 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
3042 /* ATI HDMI */
3043 { PCI_DEVICE(0x1002, 0x793b),
3044 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3045 { PCI_DEVICE(0x1002, 0x7919),
3046 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3047 { PCI_DEVICE(0x1002, 0x960f),
3048 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3049 { PCI_DEVICE(0x1002, 0x970f),
3050 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3051 { PCI_DEVICE(0x1002, 0xaa00),
3052 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3053 { PCI_DEVICE(0x1002, 0xaa08),
3054 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3055 { PCI_DEVICE(0x1002, 0xaa10),
3056 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3057 { PCI_DEVICE(0x1002, 0xaa18),
3058 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3059 { PCI_DEVICE(0x1002, 0xaa20),
3060 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3061 { PCI_DEVICE(0x1002, 0xaa28),
3062 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3063 { PCI_DEVICE(0x1002, 0xaa30),
3064 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3065 { PCI_DEVICE(0x1002, 0xaa38),
3066 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3067 { PCI_DEVICE(0x1002, 0xaa40),
3068 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3069 { PCI_DEVICE(0x1002, 0xaa48),
3070 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3071 { PCI_DEVICE(0x1002, 0x9902),
3072 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3073 { PCI_DEVICE(0x1002, 0xaaa0),
3074 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3075 { PCI_DEVICE(0x1002, 0xaaa8),
3076 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3077 { PCI_DEVICE(0x1002, 0xaab0),
3078 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
3079 /* VIA VT8251/VT8237A */
3080 { PCI_DEVICE(0x1106, 0x3288),
3081 .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
3082 /* SIS966 */
3083 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
3084 /* ULI M5461 */
3085 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
3086 /* NVIDIA MCP */
3087 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
3088 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3089 .class_mask = 0xffffff,
3090 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
3091 /* Teradici */
3092 { PCI_DEVICE(0x6549, 0x1200),
3093 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
3094 /* Creative X-Fi (CA0110-IBG) */
3095 #if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
3096 /* the following entry conflicts with snd-ctxfi driver,
3097 * as ctxfi driver mutates from HD-audio to native mode with
3098 * a special command sequence.
3099 */
3100 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
3101 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3102 .class_mask = 0xffffff,
3103 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
3104 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
3105 #else
3106 /* this entry seems still valid -- i.e. without emu20kx chip */
3107 { PCI_DEVICE(0x1102, 0x0009),
3108 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
3109 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
3110 #endif
3111 /* Vortex86MX */
3112 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
3113 /* VMware HDAudio */
3114 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
3115 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
3116 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
3117 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3118 .class_mask = 0xffffff,
3119 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
3120 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
3121 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3122 .class_mask = 0xffffff,
3123 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
3124 { 0, }
3125 };
3126 MODULE_DEVICE_TABLE(pci, azx_ids);
3127
3128 /* pci_driver definition */
3129 static struct pci_driver driver = {
3130 .name = KBUILD_MODNAME,
3131 .id_table = azx_ids,
3132 .probe = azx_probe,
3133 .remove = __devexit_p(azx_remove),
3134 #ifdef CONFIG_PM
3135 .suspend = azx_suspend,
3136 .resume = azx_resume,
3137 #endif
3138 };
3139
3140 static int __init alsa_card_azx_init(void)
3141 {
3142 return pci_register_driver(&driver);
3143 }
3144
3145 static void __exit alsa_card_azx_exit(void)
3146 {
3147 pci_unregister_driver(&driver);
3148 }
3149
3150 module_init(alsa_card_azx_init)
3151 module_exit(alsa_card_azx_exit)