spi-topcliff-pch: add recovery processing in case wait-event timeout
[zen-stable.git] / sound / pci / oxygen / wm8766.h
blobe0e849a7eaeb3c246055c57eac93aa6d3245015f
1 #ifndef WM8766_H_INCLUDED
2 #define WM8766_H_INCLUDED
4 #define WM8766_LDA1 0x00
5 #define WM8766_RDA1 0x01
6 #define WM8766_DAC_CTRL 0x02
7 #define WM8766_INT_CTRL 0x03
8 #define WM8766_LDA2 0x04
9 #define WM8766_RDA2 0x05
10 #define WM8766_LDA3 0x06
11 #define WM8766_RDA3 0x07
12 #define WM8766_MASTDA 0x08
13 #define WM8766_DAC_CTRL2 0x09
14 #define WM8766_DAC_CTRL3 0x0a
15 #define WM8766_MUTE1 0x0c
16 #define WM8766_MUTE2 0x0f
17 #define WM8766_RESET 0x1f
19 /* LDAx/RDAx/MASTDA */
20 #define WM8766_ATT_MASK 0x0ff
21 #define WM8766_UPDATE 0x100
22 /* DAC_CTRL */
23 #define WM8766_MUTEALL 0x001
24 #define WM8766_DEEMPALL 0x002
25 #define WM8766_PWDN 0x004
26 #define WM8766_ATC 0x008
27 #define WM8766_IZD 0x010
28 #define WM8766_PL_LEFT_MASK 0x060
29 #define WM8766_PL_LEFT_MUTE 0x000
30 #define WM8766_PL_LEFT_LEFT 0x020
31 #define WM8766_PL_LEFT_RIGHT 0x040
32 #define WM8766_PL_LEFT_LRMIX 0x060
33 #define WM8766_PL_RIGHT_MASK 0x180
34 #define WM8766_PL_RIGHT_MUTE 0x000
35 #define WM8766_PL_RIGHT_LEFT 0x080
36 #define WM8766_PL_RIGHT_RIGHT 0x100
37 #define WM8766_PL_RIGHT_LRMIX 0x180
38 /* INT_CTRL */
39 #define WM8766_FMT_MASK 0x003
40 #define WM8766_FMT_RJUST 0x000
41 #define WM8766_FMT_LJUST 0x001
42 #define WM8766_FMT_I2S 0x002
43 #define WM8766_FMT_DSP 0x003
44 #define WM8766_LRP 0x004
45 #define WM8766_BCP 0x008
46 #define WM8766_IWL_MASK 0x030
47 #define WM8766_IWL_16 0x000
48 #define WM8766_IWL_20 0x010
49 #define WM8766_IWL_24 0x020
50 #define WM8766_IWL_32 0x030
51 #define WM8766_PHASE_MASK 0x1c0
52 /* DAC_CTRL2 */
53 #define WM8766_ZCD 0x001
54 #define WM8766_DZFM_MASK 0x006
55 #define WM8766_DMUTE_MASK 0x038
56 #define WM8766_DEEMP_MASK 0x1c0
57 /* DAC_CTRL3 */
58 #define WM8766_DACPD_MASK 0x00e
59 #define WM8766_PWRDNALL 0x010
60 #define WM8766_MS 0x020
61 #define WM8766_RATE_MASK 0x1c0
62 #define WM8766_RATE_128 0x000
63 #define WM8766_RATE_192 0x040
64 #define WM8766_RATE_256 0x080
65 #define WM8766_RATE_384 0x0c0
66 #define WM8766_RATE_512 0x100
67 #define WM8766_RATE_768 0x140
68 /* MUTE1 */
69 #define WM8766_MPD1 0x040
70 /* MUTE2 */
71 #define WM8766_MPD2 0x020
73 #endif