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spi-topcliff-pch: add recovery processing in case wait-event timeout
[zen-stable.git] / sound / soc / sh / fsi.c
blobea4a82d01160f5657e19a4f1f4df4ca928d1737a
1 /*
2 * Fifo-attached Serial Interface (FSI) support for SH7724
3 *
4 * Copyright (C) 2009 Renesas Solutions Corp.
5 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
6 *
7 * Based on ssi.c
8 * Copyright (c) 2007 Manuel Lauss <mano@roarinelk.homelinux.net>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15 #include <linux/delay.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/io.h>
18 #include <linux/slab.h>
19 #include <linux/module.h>
20 #include <sound/soc.h>
21 #include <sound/sh_fsi.h>
22
23 /* PortA/PortB register */
24 #define REG_DO_FMT 0x0000
25 #define REG_DOFF_CTL 0x0004
26 #define REG_DOFF_ST 0x0008
27 #define REG_DI_FMT 0x000C
28 #define REG_DIFF_CTL 0x0010
29 #define REG_DIFF_ST 0x0014
30 #define REG_CKG1 0x0018
31 #define REG_CKG2 0x001C
32 #define REG_DIDT 0x0020
33 #define REG_DODT 0x0024
34 #define REG_MUTE_ST 0x0028
35 #define REG_OUT_DMAC 0x002C
36 #define REG_OUT_SEL 0x0030
37 #define REG_IN_DMAC 0x0038
38
39 /* master register */
40 #define MST_CLK_RST 0x0210
41 #define MST_SOFT_RST 0x0214
42 #define MST_FIFO_SZ 0x0218
43
44 /* core register (depend on FSI version) */
45 #define A_MST_CTLR 0x0180
46 #define B_MST_CTLR 0x01A0
47 #define CPU_INT_ST 0x01F4
48 #define CPU_IEMSK 0x01F8
49 #define CPU_IMSK 0x01FC
50 #define INT_ST 0x0200
51 #define IEMSK 0x0204
52 #define IMSK 0x0208
53
54 /* DO_FMT */
55 /* DI_FMT */
56 #define CR_BWS_24 (0x0 << 20) /* FSI2 */
57 #define CR_BWS_16 (0x1 << 20) /* FSI2 */
58 #define CR_BWS_20 (0x2 << 20) /* FSI2 */
59
60 #define CR_DTMD_PCM (0x0 << 8) /* FSI2 */
61 #define CR_DTMD_SPDIF_PCM (0x1 << 8) /* FSI2 */
62 #define CR_DTMD_SPDIF_STREAM (0x2 << 8) /* FSI2 */
63
64 #define CR_MONO (0x0 << 4)
65 #define CR_MONO_D (0x1 << 4)
66 #define CR_PCM (0x2 << 4)
67 #define CR_I2S (0x3 << 4)
68 #define CR_TDM (0x4 << 4)
69 #define CR_TDM_D (0x5 << 4)
70
71 /* DOFF_CTL */
72 /* DIFF_CTL */
73 #define IRQ_HALF 0x00100000
74 #define FIFO_CLR 0x00000001
75
76 /* DOFF_ST */
77 #define ERR_OVER 0x00000010
78 #define ERR_UNDER 0x00000001
79 #define ST_ERR (ERR_OVER | ERR_UNDER)
80
81 /* CKG1 */
82 #define ACKMD_MASK 0x00007000
83 #define BPFMD_MASK 0x00000700
84 #define DIMD (1 << 4)
85 #define DOMD (1 << 0)
86
87 /* A/B MST_CTLR */
88 #define BP (1 << 4) /* Fix the signal of Biphase output */
89 #define SE (1 << 0) /* Fix the master clock */
90
91 /* CLK_RST */
92 #define CRB (1 << 4)
93 #define CRA (1 << 0)
94
95 /* IO SHIFT / MACRO */
96 #define BI_SHIFT 12
97 #define BO_SHIFT 8
98 #define AI_SHIFT 4
99 #define AO_SHIFT 0
100 #define AB_IO(param, shift) (param << shift)
101
102 /* SOFT_RST */
103 #define PBSR (1 << 12) /* Port B Software Reset */
104 #define PASR (1 << 8) /* Port A Software Reset */
105 #define IR (1 << 4) /* Interrupt Reset */
106 #define FSISR (1 << 0) /* Software Reset */
107
108 /* OUT_SEL (FSI2) */
109 #define DMMD (1 << 4) /* SPDIF output timing 0: Biphase only */
110 /* 1: Biphase and serial */
111
112 /* FIFO_SZ */
113 #define FIFO_SZ_MASK 0x7
114
115 #define FSI_RATES SNDRV_PCM_RATE_8000_96000
116
117 #define FSI_FMTS (SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S16_LE)
118
119 typedef int (*set_rate_func)(struct device *dev, int is_porta, int rate, int enable);
120
121 /*
122 * FSI driver use below type name for variable
123 *
124 * xxx_num : number of data
125 * xxx_pos : position of data
126 * xxx_capa : capacity of data
127 */
128
129 /*
130 * period/frame/sample image
131 *
132 * ex) PCM (2ch)
133 *
134 * period pos period pos
135 * [n] [n + 1]
136 * |<-------------------- period--------------------->|
137 * ==|============================================ ... =|==
138 * | |
139 * ||<----- frame ----->|<------ frame ----->| ... |
140 * |+--------------------+--------------------+- ... |
141 * ||[ sample ][ sample ]|[ sample ][ sample ]| ... |
142 * |+--------------------+--------------------+- ... |
143 * ==|============================================ ... =|==
144 */
145
146 /*
147 * FSI FIFO image
148 *
149 * | |
150 * | |
151 * | [ sample ] |
152 * | [ sample ] |
153 * | [ sample ] |
154 * | [ sample ] |
155 * --> go to codecs
156 */
157
158 /*
159 * struct
160 */
161
162 struct fsi_stream {
163 struct snd_pcm_substream *substream;
164
165 int fifo_sample_capa; /* sample capacity of FSI FIFO */
166 int buff_sample_capa; /* sample capacity of ALSA buffer */
167 int buff_sample_pos; /* sample position of ALSA buffer */
168 int period_samples; /* sample number / 1 period */
169 int period_pos; /* current period position */
170
171 int uerr_num;
172 int oerr_num;
173 };
174
175 struct fsi_priv {
176 void __iomem *base;
177 struct fsi_master *master;
178
179 struct fsi_stream playback;
180 struct fsi_stream capture;
181
182 u32 do_fmt;
183 u32 di_fmt;
184
185 int chan_num:16;
186 int clk_master:1;
187 int spdif:1;
188
189 long rate;
190 };
191
192 struct fsi_core {
193 int ver;
194
195 u32 int_st;
196 u32 iemsk;
197 u32 imsk;
198 u32 a_mclk;
199 u32 b_mclk;
200 };
201
202 struct fsi_master {
203 void __iomem *base;
204 int irq;
205 struct fsi_priv fsia;
206 struct fsi_priv fsib;
207 struct fsi_core *core;
208 struct sh_fsi_platform_info *info;
209 spinlock_t lock;
210 };
211
212 /*
213 * basic read write function
214 */
215
216 static void __fsi_reg_write(u32 __iomem *reg, u32 data)
217 {
218 /* valid data area is 24bit */
219 data &= 0x00ffffff;
220
221 __raw_writel(data, reg);
222 }
223
224 static u32 __fsi_reg_read(u32 __iomem *reg)
225 {
226 return __raw_readl(reg);
227 }
228
229 static void __fsi_reg_mask_set(u32 __iomem *reg, u32 mask, u32 data)
230 {
231 u32 val = __fsi_reg_read(reg);
232
233 val &= ~mask;
234 val |= data & mask;
235
236 __fsi_reg_write(reg, val);
237 }
238
239 #define fsi_reg_write(p, r, d)\
240 __fsi_reg_write((p->base + REG_##r), d)
241
242 #define fsi_reg_read(p, r)\
243 __fsi_reg_read((p->base + REG_##r))
244
245 #define fsi_reg_mask_set(p, r, m, d)\
246 __fsi_reg_mask_set((p->base + REG_##r), m, d)
247
248 #define fsi_master_read(p, r) _fsi_master_read(p, MST_##r)
249 #define fsi_core_read(p, r) _fsi_master_read(p, p->core->r)
250 static u32 _fsi_master_read(struct fsi_master *master, u32 reg)
251 {
252 u32 ret;
253 unsigned long flags;
254
255 spin_lock_irqsave(&master->lock, flags);
256 ret = __fsi_reg_read(master->base + reg);
257 spin_unlock_irqrestore(&master->lock, flags);
258
259 return ret;
260 }
261
262 #define fsi_master_mask_set(p, r, m, d) _fsi_master_mask_set(p, MST_##r, m, d)
263 #define fsi_core_mask_set(p, r, m, d) _fsi_master_mask_set(p, p->core->r, m, d)
264 static void _fsi_master_mask_set(struct fsi_master *master,
265 u32 reg, u32 mask, u32 data)
266 {
267 unsigned long flags;
268
269 spin_lock_irqsave(&master->lock, flags);
270 __fsi_reg_mask_set(master->base + reg, mask, data);
271 spin_unlock_irqrestore(&master->lock, flags);
272 }
273
274 /*
275 * basic function
276 */
277
278 static struct fsi_master *fsi_get_master(struct fsi_priv *fsi)
279 {
280 return fsi->master;
281 }
282
283 static int fsi_is_clk_master(struct fsi_priv *fsi)
284 {
285 return fsi->clk_master;
286 }
287
288 static int fsi_is_port_a(struct fsi_priv *fsi)
289 {
290 return fsi->master->base == fsi->base;
291 }
292
293 static int fsi_is_spdif(struct fsi_priv *fsi)
294 {
295 return fsi->spdif;
296 }
297
298 static struct snd_soc_dai *fsi_get_dai(struct snd_pcm_substream *substream)
299 {
300 struct snd_soc_pcm_runtime *rtd = substream->private_data;
301
302 return rtd->cpu_dai;
303 }
304
305 static struct fsi_priv *fsi_get_priv_frm_dai(struct snd_soc_dai *dai)
306 {
307 struct fsi_master *master = snd_soc_dai_get_drvdata(dai);
308
309 if (dai->id == 0)
310 return &master->fsia;
311 else
312 return &master->fsib;
313 }
314
315 static struct fsi_priv *fsi_get_priv(struct snd_pcm_substream *substream)
316 {
317 return fsi_get_priv_frm_dai(fsi_get_dai(substream));
318 }
319
320 static set_rate_func fsi_get_info_set_rate(struct fsi_master *master)
321 {
322 if (!master->info)
323 return NULL;
324
325 return master->info->set_rate;
326 }
327
328 static u32 fsi_get_info_flags(struct fsi_priv *fsi)
329 {
330 int is_porta = fsi_is_port_a(fsi);
331 struct fsi_master *master = fsi_get_master(fsi);
332
333 if (!master->info)
334 return 0;
335
336 return is_porta ? master->info->porta_flags :
337 master->info->portb_flags;
338 }
339
340 static inline int fsi_stream_is_play(int stream)
341 {
342 return stream == SNDRV_PCM_STREAM_PLAYBACK;
343 }
344
345 static inline int fsi_is_play(struct snd_pcm_substream *substream)
346 {
347 return fsi_stream_is_play(substream->stream);
348 }
349
350 static inline struct fsi_stream *fsi_get_stream(struct fsi_priv *fsi,
351 int is_play)
352 {
353 return is_play ? &fsi->playback : &fsi->capture;
354 }
355
356 static u32 fsi_get_port_shift(struct fsi_priv *fsi, int is_play)
357 {
358 int is_porta = fsi_is_port_a(fsi);
359 u32 shift;
360
361 if (is_porta)
362 shift = is_play ? AO_SHIFT : AI_SHIFT;
363 else
364 shift = is_play ? BO_SHIFT : BI_SHIFT;
365
366 return shift;
367 }
368
369 static int fsi_frame2sample(struct fsi_priv *fsi, int frames)
370 {
371 return frames * fsi->chan_num;
372 }
373
374 static int fsi_sample2frame(struct fsi_priv *fsi, int samples)
375 {
376 return samples / fsi->chan_num;
377 }
378
379 static int fsi_stream_is_working(struct fsi_priv *fsi,
380 int is_play)
381 {
382 struct fsi_stream *io = fsi_get_stream(fsi, is_play);
383 struct fsi_master *master = fsi_get_master(fsi);
384 unsigned long flags;
385 int ret;
386
387 spin_lock_irqsave(&master->lock, flags);
388 ret = !!io->substream;
389 spin_unlock_irqrestore(&master->lock, flags);
390
391 return ret;
392 }
393
394 static void fsi_stream_push(struct fsi_priv *fsi,
395 int is_play,
396 struct snd_pcm_substream *substream)
397 {
398 struct fsi_stream *io = fsi_get_stream(fsi, is_play);
399 struct snd_pcm_runtime *runtime = substream->runtime;
400 struct fsi_master *master = fsi_get_master(fsi);
401 unsigned long flags;
402
403 spin_lock_irqsave(&master->lock, flags);
404 io->substream = substream;
405 io->buff_sample_capa = fsi_frame2sample(fsi, runtime->buffer_size);
406 io->buff_sample_pos = 0;
407 io->period_samples = fsi_frame2sample(fsi, runtime->period_size);
408 io->period_pos = 0;
409 io->oerr_num = -1; /* ignore 1st err */
410 io->uerr_num = -1; /* ignore 1st err */
411 spin_unlock_irqrestore(&master->lock, flags);
412 }
413
414 static void fsi_stream_pop(struct fsi_priv *fsi, int is_play)
415 {
416 struct fsi_stream *io = fsi_get_stream(fsi, is_play);
417 struct snd_soc_dai *dai = fsi_get_dai(io->substream);
418 struct fsi_master *master = fsi_get_master(fsi);
419 unsigned long flags;
420
421 spin_lock_irqsave(&master->lock, flags);
422
423 if (io->oerr_num > 0)
424 dev_err(dai->dev, "over_run = %d\n", io->oerr_num);
425
426 if (io->uerr_num > 0)
427 dev_err(dai->dev, "under_run = %d\n", io->uerr_num);
428
429 io->substream = NULL;
430 io->buff_sample_capa = 0;
431 io->buff_sample_pos = 0;
432 io->period_samples = 0;
433 io->period_pos = 0;
434 io->oerr_num = 0;
435 io->uerr_num = 0;
436 spin_unlock_irqrestore(&master->lock, flags);
437 }
438
439 static int fsi_get_current_fifo_samples(struct fsi_priv *fsi, int is_play)
440 {
441 u32 status;
442 int frames;
443
444 status = is_play ?
445 fsi_reg_read(fsi, DOFF_ST) :
446 fsi_reg_read(fsi, DIFF_ST);
447
448 frames = 0x1ff & (status >> 8);
449
450 return fsi_frame2sample(fsi, frames);
451 }
452
453 static void fsi_count_fifo_err(struct fsi_priv *fsi)
454 {
455 u32 ostatus = fsi_reg_read(fsi, DOFF_ST);
456 u32 istatus = fsi_reg_read(fsi, DIFF_ST);
457
458 if (ostatus & ERR_OVER)
459 fsi->playback.oerr_num++;
460
461 if (ostatus & ERR_UNDER)
462 fsi->playback.uerr_num++;
463
464 if (istatus & ERR_OVER)
465 fsi->capture.oerr_num++;
466
467 if (istatus & ERR_UNDER)
468 fsi->capture.uerr_num++;
469
470 fsi_reg_write(fsi, DOFF_ST, 0);
471 fsi_reg_write(fsi, DIFF_ST, 0);
472 }
473
474 /*
475 * dma function
476 */
477
478 static u8 *fsi_dma_get_area(struct fsi_priv *fsi, int stream)
479 {
480 int is_play = fsi_stream_is_play(stream);
481 struct fsi_stream *io = fsi_get_stream(fsi, is_play);
482 struct snd_pcm_runtime *runtime = io->substream->runtime;
483
484 return runtime->dma_area +
485 samples_to_bytes(runtime, io->buff_sample_pos);
486 }
487
488 static void fsi_dma_soft_push16(struct fsi_priv *fsi, int num)
489 {
490 u16 *start;
491 int i;
492
493 start = (u16 *)fsi_dma_get_area(fsi, SNDRV_PCM_STREAM_PLAYBACK);
494
495 for (i = 0; i < num; i++)
496 fsi_reg_write(fsi, DODT, ((u32)*(start + i) << 8));
497 }
498
499 static void fsi_dma_soft_pop16(struct fsi_priv *fsi, int num)
500 {
501 u16 *start;
502 int i;
503
504 start = (u16 *)fsi_dma_get_area(fsi, SNDRV_PCM_STREAM_CAPTURE);
505
506
507 for (i = 0; i < num; i++)
508 *(start + i) = (u16)(fsi_reg_read(fsi, DIDT) >> 8);
509 }
510
511 static void fsi_dma_soft_push32(struct fsi_priv *fsi, int num)
512 {
513 u32 *start;
514 int i;
515
516 start = (u32 *)fsi_dma_get_area(fsi, SNDRV_PCM_STREAM_PLAYBACK);
517
518
519 for (i = 0; i < num; i++)
520 fsi_reg_write(fsi, DODT, *(start + i));
521 }
522
523 static void fsi_dma_soft_pop32(struct fsi_priv *fsi, int num)
524 {
525 u32 *start;
526 int i;
527
528 start = (u32 *)fsi_dma_get_area(fsi, SNDRV_PCM_STREAM_CAPTURE);
529
530 for (i = 0; i < num; i++)
531 *(start + i) = fsi_reg_read(fsi, DIDT);
532 }
533
534 /*
535 * irq function
536 */
537
538 static void fsi_irq_enable(struct fsi_priv *fsi, int is_play)
539 {
540 u32 data = AB_IO(1, fsi_get_port_shift(fsi, is_play));
541 struct fsi_master *master = fsi_get_master(fsi);
542
543 fsi_core_mask_set(master, imsk, data, data);
544 fsi_core_mask_set(master, iemsk, data, data);
545 }
546
547 static void fsi_irq_disable(struct fsi_priv *fsi, int is_play)
548 {
549 u32 data = AB_IO(1, fsi_get_port_shift(fsi, is_play));
550 struct fsi_master *master = fsi_get_master(fsi);
551
552 fsi_core_mask_set(master, imsk, data, 0);
553 fsi_core_mask_set(master, iemsk, data, 0);
554 }
555
556 static u32 fsi_irq_get_status(struct fsi_master *master)
557 {
558 return fsi_core_read(master, int_st);
559 }
560
561 static void fsi_irq_clear_status(struct fsi_priv *fsi)
562 {
563 u32 data = 0;
564 struct fsi_master *master = fsi_get_master(fsi);
565
566 data |= AB_IO(1, fsi_get_port_shift(fsi, 0));
567 data |= AB_IO(1, fsi_get_port_shift(fsi, 1));
568
569 /* clear interrupt factor */
570 fsi_core_mask_set(master, int_st, data, 0);
571 }
572
573 /*
574 * SPDIF master clock function
575 *
576 * These functions are used later FSI2
577 */
578 static void fsi_spdif_clk_ctrl(struct fsi_priv *fsi, int enable)
579 {
580 struct fsi_master *master = fsi_get_master(fsi);
581 u32 mask, val;
582
583 if (master->core->ver < 2) {
584 pr_err("fsi: register access err (%s)\n", __func__);
585 return;
586 }
587
588 mask = BP | SE;
589 val = enable ? mask : 0;
590
591 fsi_is_port_a(fsi) ?
592 fsi_core_mask_set(master, a_mclk, mask, val) :
593 fsi_core_mask_set(master, b_mclk, mask, val);
594 }
595
596 /*
597 * clock function
598 */
599 static int fsi_set_master_clk(struct device *dev, struct fsi_priv *fsi,
600 long rate, int enable)
601 {
602 struct fsi_master *master = fsi_get_master(fsi);
603 set_rate_func set_rate = fsi_get_info_set_rate(master);
604 int fsi_ver = master->core->ver;
605 int ret;
606
607 ret = set_rate(dev, fsi_is_port_a(fsi), rate, enable);
608 if (ret < 0) /* error */
609 return ret;
610
611 if (!enable)
612 return 0;
613
614 if (ret > 0) {
615 u32 data = 0;
616
617 switch (ret & SH_FSI_ACKMD_MASK) {
618 default:
619 /* FALL THROUGH */
620 case SH_FSI_ACKMD_512:
621 data |= (0x0 << 12);
622 break;
623 case SH_FSI_ACKMD_256:
624 data |= (0x1 << 12);
625 break;
626 case SH_FSI_ACKMD_128:
627 data |= (0x2 << 12);
628 break;
629 case SH_FSI_ACKMD_64:
630 data |= (0x3 << 12);
631 break;
632 case SH_FSI_ACKMD_32:
633 if (fsi_ver < 2)
634 dev_err(dev, "unsupported ACKMD\n");
635 else
636 data |= (0x4 << 12);
637 break;
638 }
639
640 switch (ret & SH_FSI_BPFMD_MASK) {
641 default:
642 /* FALL THROUGH */
643 case SH_FSI_BPFMD_32:
644 data |= (0x0 << 8);
645 break;
646 case SH_FSI_BPFMD_64:
647 data |= (0x1 << 8);
648 break;
649 case SH_FSI_BPFMD_128:
650 data |= (0x2 << 8);
651 break;
652 case SH_FSI_BPFMD_256:
653 data |= (0x3 << 8);
654 break;
655 case SH_FSI_BPFMD_512:
656 data |= (0x4 << 8);
657 break;
658 case SH_FSI_BPFMD_16:
659 if (fsi_ver < 2)
660 dev_err(dev, "unsupported ACKMD\n");
661 else
662 data |= (0x7 << 8);
663 break;
664 }
665
666 fsi_reg_mask_set(fsi, CKG1, (ACKMD_MASK | BPFMD_MASK) , data);
667 udelay(10);
668 ret = 0;
669 }
670
671 return ret;
672 }
673
674 #define fsi_port_start(f, i) __fsi_port_clk_ctrl(f, i, 1)
675 #define fsi_port_stop(f, i) __fsi_port_clk_ctrl(f, i, 0)
676 static void __fsi_port_clk_ctrl(struct fsi_priv *fsi, int is_play, int enable)
677 {
678 struct fsi_master *master = fsi_get_master(fsi);
679 u32 clk = fsi_is_port_a(fsi) ? CRA : CRB;
680
681 if (enable)
682 fsi_irq_enable(fsi, is_play);
683 else
684 fsi_irq_disable(fsi, is_play);
685
686 if (fsi_is_clk_master(fsi))
687 fsi_master_mask_set(master, CLK_RST, clk, (enable) ? clk : 0);
688 }
689
690 /*
691 * ctrl function
692 */
693 static void fsi_fifo_init(struct fsi_priv *fsi,
694 int is_play,
695 struct device *dev)
696 {
697 struct fsi_master *master = fsi_get_master(fsi);
698 struct fsi_stream *io = fsi_get_stream(fsi, is_play);
699 u32 shift, i;
700 int frame_capa;
701
702 /* get on-chip RAM capacity */
703 shift = fsi_master_read(master, FIFO_SZ);
704 shift >>= fsi_get_port_shift(fsi, is_play);
705 shift &= FIFO_SZ_MASK;
706 frame_capa = 256 << shift;
707 dev_dbg(dev, "fifo = %d words\n", frame_capa);
708
709 /*
710 * The maximum number of sample data varies depending
711 * on the number of channels selected for the format.
712 *
713 * FIFOs are used in 4-channel units in 3-channel mode
714 * and in 8-channel units in 5- to 7-channel mode
715 * meaning that more FIFOs than the required size of DPRAM
716 * are used.
717 *
718 * ex) if 256 words of DP-RAM is connected
719 * 1 channel: 256 (256 x 1 = 256)
720 * 2 channels: 128 (128 x 2 = 256)
721 * 3 channels: 64 ( 64 x 3 = 192)
722 * 4 channels: 64 ( 64 x 4 = 256)
723 * 5 channels: 32 ( 32 x 5 = 160)
724 * 6 channels: 32 ( 32 x 6 = 192)
725 * 7 channels: 32 ( 32 x 7 = 224)
726 * 8 channels: 32 ( 32 x 8 = 256)
727 */
728 for (i = 1; i < fsi->chan_num; i <<= 1)
729 frame_capa >>= 1;
730 dev_dbg(dev, "%d channel %d store\n",
731 fsi->chan_num, frame_capa);
732
733 io->fifo_sample_capa = fsi_frame2sample(fsi, frame_capa);
734
735 /*
736 * set interrupt generation factor
737 * clear FIFO
738 */
739 if (is_play) {
740 fsi_reg_write(fsi, DOFF_CTL, IRQ_HALF);
741 fsi_reg_mask_set(fsi, DOFF_CTL, FIFO_CLR, FIFO_CLR);
742 } else {
743 fsi_reg_write(fsi, DIFF_CTL, IRQ_HALF);
744 fsi_reg_mask_set(fsi, DIFF_CTL, FIFO_CLR, FIFO_CLR);
745 }
746 }
747
748 static int fsi_fifo_data_ctrl(struct fsi_priv *fsi, int stream)
749 {
750 struct snd_pcm_runtime *runtime;
751 struct snd_pcm_substream *substream = NULL;
752 int is_play = fsi_stream_is_play(stream);
753 struct fsi_stream *io = fsi_get_stream(fsi, is_play);
754 int sample_residues;
755 int sample_width;
756 int samples;
757 int samples_max;
758 int over_period;
759 void (*fn)(struct fsi_priv *fsi, int size);
760
761 if (!fsi ||
762 !io->substream ||
763 !io->substream->runtime)
764 return -EINVAL;
765
766 over_period = 0;
767 substream = io->substream;
768 runtime = substream->runtime;
769
770 /* FSI FIFO has limit.
771 * So, this driver can not send periods data at a time
772 */
773 if (io->buff_sample_pos >=
774 io->period_samples * (io->period_pos + 1)) {
775
776 over_period = 1;
777 io->period_pos = (io->period_pos + 1) % runtime->periods;
778
779 if (0 == io->period_pos)
780 io->buff_sample_pos = 0;
781 }
782
783 /* get 1 sample data width */
784 sample_width = samples_to_bytes(runtime, 1);
785
786 /* get number of residue samples */
787 sample_residues = io->buff_sample_capa - io->buff_sample_pos;
788
789 if (is_play) {
790 /*
791 * for play-back
792 *
793 * samples_max : number of FSI fifo free samples space
794 * samples : number of ALSA residue samples
795 */
796 samples_max = io->fifo_sample_capa;
797 samples_max -= fsi_get_current_fifo_samples(fsi, is_play);
798
799 samples = sample_residues;
800
801 switch (sample_width) {
802 case 2:
803 fn = fsi_dma_soft_push16;
804 break;
805 case 4:
806 fn = fsi_dma_soft_push32;
807 break;
808 default:
809 return -EINVAL;
810 }
811 } else {
812 /*
813 * for capture
814 *
815 * samples_max : number of ALSA free samples space
816 * samples : number of samples in FSI fifo
817 */
818 samples_max = sample_residues;
819 samples = fsi_get_current_fifo_samples(fsi, is_play);
820
821 switch (sample_width) {
822 case 2:
823 fn = fsi_dma_soft_pop16;
824 break;
825 case 4:
826 fn = fsi_dma_soft_pop32;
827 break;
828 default:
829 return -EINVAL;
830 }
831 }
832
833 samples = min(samples, samples_max);
834
835 fn(fsi, samples);
836
837 /* update buff_sample_pos */
838 io->buff_sample_pos += samples;
839
840 if (over_period)
841 snd_pcm_period_elapsed(substream);
842
843 return 0;
844 }
845
846 static int fsi_data_pop(struct fsi_priv *fsi)
847 {
848 return fsi_fifo_data_ctrl(fsi, SNDRV_PCM_STREAM_CAPTURE);
849 }
850
851 static int fsi_data_push(struct fsi_priv *fsi)
852 {
853 return fsi_fifo_data_ctrl(fsi, SNDRV_PCM_STREAM_PLAYBACK);
854 }
855
856 static irqreturn_t fsi_interrupt(int irq, void *data)
857 {
858 struct fsi_master *master = data;
859 u32 int_st = fsi_irq_get_status(master);
860
861 /* clear irq status */
862 fsi_master_mask_set(master, SOFT_RST, IR, 0);
863 fsi_master_mask_set(master, SOFT_RST, IR, IR);
864
865 if (int_st & AB_IO(1, AO_SHIFT))
866 fsi_data_push(&master->fsia);
867 if (int_st & AB_IO(1, BO_SHIFT))
868 fsi_data_push(&master->fsib);
869 if (int_st & AB_IO(1, AI_SHIFT))
870 fsi_data_pop(&master->fsia);
871 if (int_st & AB_IO(1, BI_SHIFT))
872 fsi_data_pop(&master->fsib);
873
874 fsi_count_fifo_err(&master->fsia);
875 fsi_count_fifo_err(&master->fsib);
876
877 fsi_irq_clear_status(&master->fsia);
878 fsi_irq_clear_status(&master->fsib);
879
880 return IRQ_HANDLED;
881 }
882
883 /*
884 * dai ops
885 */
886
887 static int fsi_hw_startup(struct fsi_priv *fsi,
888 int is_play,
889 struct device *dev)
890 {
891 struct fsi_master *master = fsi_get_master(fsi);
892 int fsi_ver = master->core->ver;
893 u32 flags = fsi_get_info_flags(fsi);
894 u32 data = 0;
895
896 /* clock setting */
897 if (fsi_is_clk_master(fsi))
898 data = DIMD | DOMD;
899
900 fsi_reg_mask_set(fsi, CKG1, (DIMD | DOMD), data);
901
902 /* clock inversion (CKG2) */
903 data = 0;
904 if (SH_FSI_LRM_INV & flags)
905 data |= 1 << 12;
906 if (SH_FSI_BRM_INV & flags)
907 data |= 1 << 8;
908 if (SH_FSI_LRS_INV & flags)
909 data |= 1 << 4;
910 if (SH_FSI_BRS_INV & flags)
911 data |= 1 << 0;
912
913 fsi_reg_write(fsi, CKG2, data);
914
915 /* set format */
916 fsi_reg_write(fsi, DO_FMT, fsi->do_fmt);
917 fsi_reg_write(fsi, DI_FMT, fsi->di_fmt);
918
919 /* spdif ? */
920 if (fsi_is_spdif(fsi)) {
921 fsi_spdif_clk_ctrl(fsi, 1);
922 fsi_reg_mask_set(fsi, OUT_SEL, DMMD, DMMD);
923 }
924
925 /*
926 * FIXME
927 *
928 * FSI driver assumed that data package is in-back.
929 * FSI2 chip can select it.
930 */
931 if (fsi_ver >= 2) {
932 fsi_reg_write(fsi, OUT_DMAC, (1 << 4));
933 fsi_reg_write(fsi, IN_DMAC, (1 << 4));
934 }
935
936 /* irq clear */
937 fsi_irq_disable(fsi, is_play);
938 fsi_irq_clear_status(fsi);
939
940 /* fifo init */
941 fsi_fifo_init(fsi, is_play, dev);
942
943 return 0;
944 }
945
946 static void fsi_hw_shutdown(struct fsi_priv *fsi,
947 int is_play,
948 struct device *dev)
949 {
950 if (fsi_is_clk_master(fsi))
951 fsi_set_master_clk(dev, fsi, fsi->rate, 0);
952 }
953
954 static int fsi_dai_startup(struct snd_pcm_substream *substream,
955 struct snd_soc_dai *dai)
956 {
957 struct fsi_priv *fsi = fsi_get_priv(substream);
958 int is_play = fsi_is_play(substream);
959
960 return fsi_hw_startup(fsi, is_play, dai->dev);
961 }
962
963 static void fsi_dai_shutdown(struct snd_pcm_substream *substream,
964 struct snd_soc_dai *dai)
965 {
966 struct fsi_priv *fsi = fsi_get_priv(substream);
967 int is_play = fsi_is_play(substream);
968
969 fsi_hw_shutdown(fsi, is_play, dai->dev);
970 fsi->rate = 0;
971 }
972
973 static int fsi_dai_trigger(struct snd_pcm_substream *substream, int cmd,
974 struct snd_soc_dai *dai)
975 {
976 struct fsi_priv *fsi = fsi_get_priv(substream);
977 int is_play = fsi_is_play(substream);
978 int ret = 0;
979
980 switch (cmd) {
981 case SNDRV_PCM_TRIGGER_START:
982 fsi_stream_push(fsi, is_play, substream);
983 ret = is_play ? fsi_data_push(fsi) : fsi_data_pop(fsi);
984 fsi_port_start(fsi, is_play);
985 break;
986 case SNDRV_PCM_TRIGGER_STOP:
987 fsi_port_stop(fsi, is_play);
988 fsi_stream_pop(fsi, is_play);
989 break;
990 }
991
992 return ret;
993 }
994
995 static int fsi_set_fmt_dai(struct fsi_priv *fsi, unsigned int fmt)
996 {
997 u32 data = 0;
998
999 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1000 case SND_SOC_DAIFMT_I2S:
1001 data = CR_I2S;
1002 fsi->chan_num = 2;
1003 break;
1004 case SND_SOC_DAIFMT_LEFT_J:
1005 data = CR_PCM;
1006 fsi->chan_num = 2;
1007 break;
1008 default:
1009 return -EINVAL;
1010 }
1011
1012 fsi->do_fmt = data;
1013 fsi->di_fmt = data;
1014
1015 return 0;
1016 }
1017
1018 static int fsi_set_fmt_spdif(struct fsi_priv *fsi)
1019 {
1020 struct fsi_master *master = fsi_get_master(fsi);
1021 u32 data = 0;
1022
1023 if (master->core->ver < 2)
1024 return -EINVAL;
1025
1026 data = CR_BWS_16 | CR_DTMD_SPDIF_PCM | CR_PCM;
1027 fsi->chan_num = 2;
1028 fsi->spdif = 1;
1029
1030 fsi->do_fmt = data;
1031 fsi->di_fmt = data;
1032
1033 return 0;
1034 }
1035
1036 static int fsi_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1037 {
1038 struct fsi_priv *fsi = fsi_get_priv_frm_dai(dai);
1039 struct fsi_master *master = fsi_get_master(fsi);
1040 set_rate_func set_rate = fsi_get_info_set_rate(master);
1041 u32 flags = fsi_get_info_flags(fsi);
1042 int ret;
1043
1044 /* set master/slave audio interface */
1045 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1046 case SND_SOC_DAIFMT_CBM_CFM:
1047 fsi->clk_master = 1;
1048 break;
1049 case SND_SOC_DAIFMT_CBS_CFS:
1050 break;
1051 default:
1052 return -EINVAL;
1053 }
1054
1055 if (fsi_is_clk_master(fsi) && !set_rate) {
1056 dev_err(dai->dev, "platform doesn't have set_rate\n");
1057 return -EINVAL;
1058 }
1059
1060 /* set format */
1061 switch (flags & SH_FSI_FMT_MASK) {
1062 case SH_FSI_FMT_DAI:
1063 ret = fsi_set_fmt_dai(fsi, fmt & SND_SOC_DAIFMT_FORMAT_MASK);
1064 break;
1065 case SH_FSI_FMT_SPDIF:
1066 ret = fsi_set_fmt_spdif(fsi);
1067 break;
1068 default:
1069 ret = -EINVAL;
1070 }
1071
1072 return ret;
1073 }
1074
1075 static int fsi_dai_hw_params(struct snd_pcm_substream *substream,
1076 struct snd_pcm_hw_params *params,
1077 struct snd_soc_dai *dai)
1078 {
1079 struct fsi_priv *fsi = fsi_get_priv(substream);
1080 long rate = params_rate(params);
1081 int ret;
1082
1083 if (!fsi_is_clk_master(fsi))
1084 return 0;
1085
1086 ret = fsi_set_master_clk(dai->dev, fsi, rate, 1);
1087 if (ret < 0)
1088 return ret;
1089
1090 fsi->rate = rate;
1091
1092 return ret;
1093 }
1094
1095 static const struct snd_soc_dai_ops fsi_dai_ops = {
1096 .startup = fsi_dai_startup,
1097 .shutdown = fsi_dai_shutdown,
1098 .trigger = fsi_dai_trigger,
1099 .set_fmt = fsi_dai_set_fmt,
1100 .hw_params = fsi_dai_hw_params,
1101 };
1102
1103 /*
1104 * pcm ops
1105 */
1106
1107 static struct snd_pcm_hardware fsi_pcm_hardware = {
1108 .info = SNDRV_PCM_INFO_INTERLEAVED |
1109 SNDRV_PCM_INFO_MMAP |
1110 SNDRV_PCM_INFO_MMAP_VALID |
1111 SNDRV_PCM_INFO_PAUSE,
1112 .formats = FSI_FMTS,
1113 .rates = FSI_RATES,
1114 .rate_min = 8000,
1115 .rate_max = 192000,
1116 .channels_min = 1,
1117 .channels_max = 2,
1118 .buffer_bytes_max = 64 * 1024,
1119 .period_bytes_min = 32,
1120 .period_bytes_max = 8192,
1121 .periods_min = 1,
1122 .periods_max = 32,
1123 .fifo_size = 256,
1124 };
1125
1126 static int fsi_pcm_open(struct snd_pcm_substream *substream)
1127 {
1128 struct snd_pcm_runtime *runtime = substream->runtime;
1129 int ret = 0;
1130
1131 snd_soc_set_runtime_hwparams(substream, &fsi_pcm_hardware);
1132
1133 ret = snd_pcm_hw_constraint_integer(runtime,
1134 SNDRV_PCM_HW_PARAM_PERIODS);
1135
1136 return ret;
1137 }
1138
1139 static int fsi_hw_params(struct snd_pcm_substream *substream,
1140 struct snd_pcm_hw_params *hw_params)
1141 {
1142 return snd_pcm_lib_malloc_pages(substream,
1143 params_buffer_bytes(hw_params));
1144 }
1145
1146 static int fsi_hw_free(struct snd_pcm_substream *substream)
1147 {
1148 return snd_pcm_lib_free_pages(substream);
1149 }
1150
1151 static snd_pcm_uframes_t fsi_pointer(struct snd_pcm_substream *substream)
1152 {
1153 struct fsi_priv *fsi = fsi_get_priv(substream);
1154 struct fsi_stream *io = fsi_get_stream(fsi, fsi_is_play(substream));
1155
1156 return fsi_sample2frame(fsi, io->buff_sample_pos);
1157 }
1158
1159 static struct snd_pcm_ops fsi_pcm_ops = {
1160 .open = fsi_pcm_open,
1161 .ioctl = snd_pcm_lib_ioctl,
1162 .hw_params = fsi_hw_params,
1163 .hw_free = fsi_hw_free,
1164 .pointer = fsi_pointer,
1165 };
1166
1167 /*
1168 * snd_soc_platform
1169 */
1170
1171 #define PREALLOC_BUFFER (32 * 1024)
1172 #define PREALLOC_BUFFER_MAX (32 * 1024)
1173
1174 static void fsi_pcm_free(struct snd_pcm *pcm)
1175 {
1176 snd_pcm_lib_preallocate_free_for_all(pcm);
1177 }
1178
1179 static int fsi_pcm_new(struct snd_soc_pcm_runtime *rtd)
1180 {
1181 struct snd_pcm *pcm = rtd->pcm;
1182
1183 /*
1184 * dont use SNDRV_DMA_TYPE_DEV, since it will oops the SH kernel
1185 * in MMAP mode (i.e. aplay -M)
1186 */
1187 return snd_pcm_lib_preallocate_pages_for_all(
1188 pcm,
1189 SNDRV_DMA_TYPE_CONTINUOUS,
1190 snd_dma_continuous_data(GFP_KERNEL),
1191 PREALLOC_BUFFER, PREALLOC_BUFFER_MAX);
1192 }
1193
1194 /*
1195 * alsa struct
1196 */
1197
1198 static struct snd_soc_dai_driver fsi_soc_dai[] = {
1199 {
1200 .name = "fsia-dai",
1201 .playback = {
1202 .rates = FSI_RATES,
1203 .formats = FSI_FMTS,
1204 .channels_min = 1,
1205 .channels_max = 8,
1206 },
1207 .capture = {
1208 .rates = FSI_RATES,
1209 .formats = FSI_FMTS,
1210 .channels_min = 1,
1211 .channels_max = 8,
1212 },
1213 .ops = &fsi_dai_ops,
1214 },
1215 {
1216 .name = "fsib-dai",
1217 .playback = {
1218 .rates = FSI_RATES,
1219 .formats = FSI_FMTS,
1220 .channels_min = 1,
1221 .channels_max = 8,
1222 },
1223 .capture = {
1224 .rates = FSI_RATES,
1225 .formats = FSI_FMTS,
1226 .channels_min = 1,
1227 .channels_max = 8,
1228 },
1229 .ops = &fsi_dai_ops,
1230 },
1231 };
1232
1233 static struct snd_soc_platform_driver fsi_soc_platform = {
1234 .ops = &fsi_pcm_ops,
1235 .pcm_new = fsi_pcm_new,
1236 .pcm_free = fsi_pcm_free,
1237 };
1238
1239 /*
1240 * platform function
1241 */
1242
1243 static int fsi_probe(struct platform_device *pdev)
1244 {
1245 struct fsi_master *master;
1246 const struct platform_device_id *id_entry;
1247 struct resource *res;
1248 unsigned int irq;
1249 int ret;
1250
1251 id_entry = pdev->id_entry;
1252 if (!id_entry) {
1253 dev_err(&pdev->dev, "unknown fsi device\n");
1254 return -ENODEV;
1255 }
1256
1257 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1258 irq = platform_get_irq(pdev, 0);
1259 if (!res || (int)irq <= 0) {
1260 dev_err(&pdev->dev, "Not enough FSI platform resources.\n");
1261 ret = -ENODEV;
1262 goto exit;
1263 }
1264
1265 master = kzalloc(sizeof(*master), GFP_KERNEL);
1266 if (!master) {
1267 dev_err(&pdev->dev, "Could not allocate master\n");
1268 ret = -ENOMEM;
1269 goto exit;
1270 }
1271
1272 master->base = ioremap_nocache(res->start, resource_size(res));
1273 if (!master->base) {
1274 ret = -ENXIO;
1275 dev_err(&pdev->dev, "Unable to ioremap FSI registers.\n");
1276 goto exit_kfree;
1277 }
1278
1279 /* master setting */
1280 master->irq = irq;
1281 master->info = pdev->dev.platform_data;
1282 master->core = (struct fsi_core *)id_entry->driver_data;
1283 spin_lock_init(&master->lock);
1284
1285 /* FSI A setting */
1286 master->fsia.base = master->base;
1287 master->fsia.master = master;
1288
1289 /* FSI B setting */
1290 master->fsib.base = master->base + 0x40;
1291 master->fsib.master = master;
1292
1293 pm_runtime_enable(&pdev->dev);
1294 dev_set_drvdata(&pdev->dev, master);
1295
1296 ret = request_irq(irq, &fsi_interrupt, 0,
1297 id_entry->name, master);
1298 if (ret) {
1299 dev_err(&pdev->dev, "irq request err\n");
1300 goto exit_iounmap;
1301 }
1302
1303 ret = snd_soc_register_platform(&pdev->dev, &fsi_soc_platform);
1304 if (ret < 0) {
1305 dev_err(&pdev->dev, "cannot snd soc register\n");
1306 goto exit_free_irq;
1307 }
1308
1309 ret = snd_soc_register_dais(&pdev->dev, fsi_soc_dai,
1310 ARRAY_SIZE(fsi_soc_dai));
1311 if (ret < 0) {
1312 dev_err(&pdev->dev, "cannot snd dai register\n");
1313 goto exit_snd_soc;
1314 }
1315
1316 return ret;
1317
1318 exit_snd_soc:
1319 snd_soc_unregister_platform(&pdev->dev);
1320 exit_free_irq:
1321 free_irq(irq, master);
1322 exit_iounmap:
1323 iounmap(master->base);
1324 pm_runtime_disable(&pdev->dev);
1325 exit_kfree:
1326 kfree(master);
1327 master = NULL;
1328 exit:
1329 return ret;
1330 }
1331
1332 static int fsi_remove(struct platform_device *pdev)
1333 {
1334 struct fsi_master *master;
1335
1336 master = dev_get_drvdata(&pdev->dev);
1337
1338 free_irq(master->irq, master);
1339 pm_runtime_disable(&pdev->dev);
1340
1341 snd_soc_unregister_dais(&pdev->dev, ARRAY_SIZE(fsi_soc_dai));
1342 snd_soc_unregister_platform(&pdev->dev);
1343
1344 iounmap(master->base);
1345 kfree(master);
1346
1347 return 0;
1348 }
1349
1350 static void __fsi_suspend(struct fsi_priv *fsi,
1351 int is_play,
1352 struct device *dev)
1353 {
1354 if (!fsi_stream_is_working(fsi, is_play))
1355 return;
1356
1357 fsi_port_stop(fsi, is_play);
1358 fsi_hw_shutdown(fsi, is_play, dev);
1359 }
1360
1361 static void __fsi_resume(struct fsi_priv *fsi,
1362 int is_play,
1363 struct device *dev)
1364 {
1365 if (!fsi_stream_is_working(fsi, is_play))
1366 return;
1367
1368 fsi_hw_startup(fsi, is_play, dev);
1369
1370 if (fsi_is_clk_master(fsi) && fsi->rate)
1371 fsi_set_master_clk(dev, fsi, fsi->rate, 1);
1372
1373 fsi_port_start(fsi, is_play);
1374
1375 }
1376
1377 static int fsi_suspend(struct device *dev)
1378 {
1379 struct fsi_master *master = dev_get_drvdata(dev);
1380 struct fsi_priv *fsia = &master->fsia;
1381 struct fsi_priv *fsib = &master->fsib;
1382
1383 __fsi_suspend(fsia, 1, dev);
1384 __fsi_suspend(fsia, 0, dev);
1385
1386 __fsi_suspend(fsib, 1, dev);
1387 __fsi_suspend(fsib, 0, dev);
1388
1389 return 0;
1390 }
1391
1392 static int fsi_resume(struct device *dev)
1393 {
1394 struct fsi_master *master = dev_get_drvdata(dev);
1395 struct fsi_priv *fsia = &master->fsia;
1396 struct fsi_priv *fsib = &master->fsib;
1397
1398 __fsi_resume(fsia, 1, dev);
1399 __fsi_resume(fsia, 0, dev);
1400
1401 __fsi_resume(fsib, 1, dev);
1402 __fsi_resume(fsib, 0, dev);
1403
1404 return 0;
1405 }
1406
1407 static int fsi_runtime_nop(struct device *dev)
1408 {
1409 /* Runtime PM callback shared between ->runtime_suspend()
1410 * and ->runtime_resume(). Simply returns success.
1411 *
1412 * This driver re-initializes all registers after
1413 * pm_runtime_get_sync() anyway so there is no need
1414 * to save and restore registers here.
1415 */
1416 return 0;
1417 }
1418
1419 static struct dev_pm_ops fsi_pm_ops = {
1420 .suspend = fsi_suspend,
1421 .resume = fsi_resume,
1422 .runtime_suspend = fsi_runtime_nop,
1423 .runtime_resume = fsi_runtime_nop,
1424 };
1425
1426 static struct fsi_core fsi1_core = {
1427 .ver = 1,
1428
1429 /* Interrupt */
1430 .int_st = INT_ST,
1431 .iemsk = IEMSK,
1432 .imsk = IMSK,
1433 };
1434
1435 static struct fsi_core fsi2_core = {
1436 .ver = 2,
1437
1438 /* Interrupt */
1439 .int_st = CPU_INT_ST,
1440 .iemsk = CPU_IEMSK,
1441 .imsk = CPU_IMSK,
1442 .a_mclk = A_MST_CTLR,
1443 .b_mclk = B_MST_CTLR,
1444 };
1445
1446 static struct platform_device_id fsi_id_table[] = {
1447 { "sh_fsi", (kernel_ulong_t)&fsi1_core },
1448 { "sh_fsi2", (kernel_ulong_t)&fsi2_core },
1449 {},
1450 };
1451 MODULE_DEVICE_TABLE(platform, fsi_id_table);
1452
1453 static struct platform_driver fsi_driver = {
1454 .driver = {
1455 .name = "fsi-pcm-audio",
1456 .pm = &fsi_pm_ops,
1457 },
1458 .probe = fsi_probe,
1459 .remove = fsi_remove,
1460 .id_table = fsi_id_table,
1461 };
1462
1463 module_platform_driver(fsi_driver);
1464
1465 MODULE_LICENSE("GPL");
1466 MODULE_DESCRIPTION("SuperH onchip FSI audio driver");
1467 MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>");
1468 MODULE_ALIAS("platform:fsi-pcm-audio");