arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c

   1 /*
   2  * omap_hwmod_2xxx_3xxx_ipblock_data.c - common IP block data for OMAP2/3
   3  *
   4  * Copyright (C) 2011 Nokia Corporation
   5  * Paul Walmsley
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11 #include <plat/omap_hwmod.h>
  12 #include <plat/serial.h>
  13 #include <plat/dma.h>
  14 #include <plat/common.h>
  15
  16 #include <mach/irqs.h>
  17
  18 #include "omap_hwmod_common_data.h"
  19
  20 /* UART */
  21
  22 static struct omap_hwmod_class_sysconfig omap2_uart_sysc = {
  23         .rev_offs       = 0x50,
  24         .sysc_offs      = 0x54,
  25         .syss_offs      = 0x58,
  26         .sysc_flags     = (SYSC_HAS_SIDLEMODE |
  27                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
  28                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
  29         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
  30         .sysc_fields    = &omap_hwmod_sysc_type1,
  31 };
  32
  33 struct omap_hwmod_class omap2_uart_class = {
  34         .name   = "uart",
  35         .sysc   = &omap2_uart_sysc,
  36 };
  37
  38 /*
  39  * 'dss' class
  40  * display sub-system
  41  */
  42
  43 static struct omap_hwmod_class_sysconfig omap2_dss_sysc = {
  44         .rev_offs       = 0x0000,
  45         .sysc_offs      = 0x0010,
  46         .syss_offs      = 0x0014,
  47         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
  48                            SYSS_HAS_RESET_STATUS),
  49         .sysc_fields    = &omap_hwmod_sysc_type1,
  50 };
  51
  52 struct omap_hwmod_class omap2_dss_hwmod_class = {
  53         .name   = "dss",
  54         .sysc   = &omap2_dss_sysc,
  55         .reset  = omap_dss_reset,
  56 };
  57
  58 /*
  59  * 'dispc' class
  60  * display controller
  61  */
  62
  63 static struct omap_hwmod_class_sysconfig omap2_dispc_sysc = {
  64         .rev_offs       = 0x0000,
  65         .sysc_offs      = 0x0010,
  66         .syss_offs      = 0x0014,
  67         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
  68                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
  69         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
  70                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
  71         .sysc_fields    = &omap_hwmod_sysc_type1,
  72 };
  73
  74 struct omap_hwmod_class omap2_dispc_hwmod_class = {
  75         .name   = "dispc",
  76         .sysc   = &omap2_dispc_sysc,
  77 };
  78
  79 /*
  80  * 'rfbi' class
  81  * remote frame buffer interface
  82  */
  83
  84 static struct omap_hwmod_class_sysconfig omap2_rfbi_sysc = {
  85         .rev_offs       = 0x0000,
  86         .sysc_offs      = 0x0010,
  87         .syss_offs      = 0x0014,
  88         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
  89                            SYSC_HAS_AUTOIDLE),
  90         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
  91         .sysc_fields    = &omap_hwmod_sysc_type1,
  92 };
  93
  94 struct omap_hwmod_class omap2_rfbi_hwmod_class = {
  95         .name   = "rfbi",
  96         .sysc   = &omap2_rfbi_sysc,
  97 };
  98
  99 /*
 100  * 'venc' class
 101  * video encoder
 102  */
 103
 104 struct omap_hwmod_class omap2_venc_hwmod_class = {
 105         .name = "venc",
 106 };
 107
 108
 109 /* Common DMA request line data */
 110 struct omap_hwmod_dma_info omap2_uart1_sdma_reqs[] = {
 111         { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
 112         { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
 113         { .dma_req = -1 }
 114 };
 115
 116 struct omap_hwmod_dma_info omap2_uart2_sdma_reqs[] = {
 117         { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
 118         { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
 119         { .dma_req = -1 }
 120 };
 121
 122 struct omap_hwmod_dma_info omap2_uart3_sdma_reqs[] = {
 123         { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
 124         { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
 125         { .dma_req = -1 }
 126 };
 127
 128 struct omap_hwmod_dma_info omap2_i2c1_sdma_reqs[] = {
 129         { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
 130         { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
 131         { .dma_req = -1 }
 132 };
 133
 134 struct omap_hwmod_dma_info omap2_i2c2_sdma_reqs[] = {
 135         { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
 136         { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
 137         { .dma_req = -1 }
 138 };
 139
 140 struct omap_hwmod_dma_info omap2_mcspi1_sdma_reqs[] = {
 141         { .name = "tx0", .dma_req = 35 }, /* DMA_SPI1_TX0 */
 142         { .name = "rx0", .dma_req = 36 }, /* DMA_SPI1_RX0 */
 143         { .name = "tx1", .dma_req = 37 }, /* DMA_SPI1_TX1 */
 144         { .name = "rx1", .dma_req = 38 }, /* DMA_SPI1_RX1 */
 145         { .name = "tx2", .dma_req = 39 }, /* DMA_SPI1_TX2 */
 146         { .name = "rx2", .dma_req = 40 }, /* DMA_SPI1_RX2 */
 147         { .name = "tx3", .dma_req = 41 }, /* DMA_SPI1_TX3 */
 148         { .name = "rx3", .dma_req = 42 }, /* DMA_SPI1_RX3 */
 149         { .dma_req = -1 }
 150 };
 151
 152 struct omap_hwmod_dma_info omap2_mcspi2_sdma_reqs[] = {
 153         { .name = "tx0", .dma_req = 43 }, /* DMA_SPI2_TX0 */
 154         { .name = "rx0", .dma_req = 44 }, /* DMA_SPI2_RX0 */
 155         { .name = "tx1", .dma_req = 45 }, /* DMA_SPI2_TX1 */
 156         { .name = "rx1", .dma_req = 46 }, /* DMA_SPI2_RX1 */
 157         { .dma_req = -1 }
 158 };
 159
 160 struct omap_hwmod_dma_info omap2_mcbsp1_sdma_reqs[] = {
 161         { .name = "rx", .dma_req = 32 },
 162         { .name = "tx", .dma_req = 31 },
 163         { .dma_req = -1 }
 164 };
 165
 166 struct omap_hwmod_dma_info omap2_mcbsp2_sdma_reqs[] = {
 167         { .name = "rx", .dma_req = 34 },
 168         { .name = "tx", .dma_req = 33 },
 169         { .dma_req = -1 }
 170 };
 171
 172 struct omap_hwmod_dma_info omap2_mcbsp3_sdma_reqs[] = {
 173         { .name = "rx", .dma_req = 18 },
 174         { .name = "tx", .dma_req = 17 },
 175         { .dma_req = -1 }
 176 };
 177
 178 /* Other IP block data */
 179
 180
 181 /*
 182  * omap_hwmod class data
 183  */
 184
 185 struct omap_hwmod_class l3_hwmod_class = {
 186         .name = "l3"
 187 };
 188
 189 struct omap_hwmod_class l4_hwmod_class = {
 190         .name = "l4"
 191 };
 192
 193 struct omap_hwmod_class mpu_hwmod_class = {
 194         .name = "mpu"
 195 };
 196
 197 struct omap_hwmod_class iva_hwmod_class = {
 198         .name = "iva"
 199 };
 200
 201 /* Common MPU IRQ line data */
 202
 203 struct omap_hwmod_irq_info omap2_timer1_mpu_irqs[] = {
 204         { .irq = 37, },
 205         { .irq = -1 }
 206 };
 207
 208 struct omap_hwmod_irq_info omap2_timer2_mpu_irqs[] = {
 209         { .irq = 38, },
 210         { .irq = -1 }
 211 };
 212
 213 struct omap_hwmod_irq_info omap2_timer3_mpu_irqs[] = {
 214         { .irq = 39, },
 215         { .irq = -1 }
 216 };
 217
 218 struct omap_hwmod_irq_info omap2_timer4_mpu_irqs[] = {
 219         { .irq = 40, },
 220         { .irq = -1 }
 221 };
 222
 223 struct omap_hwmod_irq_info omap2_timer5_mpu_irqs[] = {
 224         { .irq = 41, },
 225         { .irq = -1 }
 226 };
 227
 228 struct omap_hwmod_irq_info omap2_timer6_mpu_irqs[] = {
 229         { .irq = 42, },
 230         { .irq = -1 }
 231 };
 232
 233 struct omap_hwmod_irq_info omap2_timer7_mpu_irqs[] = {
 234         { .irq = 43, },
 235         { .irq = -1 }
 236 };
 237
 238 struct omap_hwmod_irq_info omap2_timer8_mpu_irqs[] = {
 239         { .irq = 44, },
 240         { .irq = -1 }
 241 };
 242
 243 struct omap_hwmod_irq_info omap2_timer9_mpu_irqs[] = {
 244         { .irq = 45, },
 245         { .irq = -1 }
 246 };
 247
 248 struct omap_hwmod_irq_info omap2_timer10_mpu_irqs[] = {
 249         { .irq = 46, },
 250         { .irq = -1 }
 251 };
 252
 253 struct omap_hwmod_irq_info omap2_timer11_mpu_irqs[] = {
 254         { .irq = 47, },
 255         { .irq = -1 }
 256 };
 257
 258 struct omap_hwmod_irq_info omap2_uart1_mpu_irqs[] = {
 259         { .irq = INT_24XX_UART1_IRQ, },
 260         { .irq = -1 }
 261 };
 262
 263 struct omap_hwmod_irq_info omap2_uart2_mpu_irqs[] = {
 264         { .irq = INT_24XX_UART2_IRQ, },
 265         { .irq = -1 }
 266 };
 267
 268 struct omap_hwmod_irq_info omap2_uart3_mpu_irqs[] = {
 269         { .irq = INT_24XX_UART3_IRQ, },
 270         { .irq = -1 }
 271 };
 272
 273 struct omap_hwmod_irq_info omap2_dispc_irqs[] = {
 274         { .irq = 25 },
 275         { .irq = -1 }
 276 };
 277
 278 struct omap_hwmod_irq_info omap2_i2c1_mpu_irqs[] = {
 279         { .irq = INT_24XX_I2C1_IRQ, },
 280         { .irq = -1 }
 281 };
 282
 283 struct omap_hwmod_irq_info omap2_i2c2_mpu_irqs[] = {
 284         { .irq = INT_24XX_I2C2_IRQ, },
 285         { .irq = -1 }
 286 };
 287
 288 struct omap_hwmod_irq_info omap2_gpio1_irqs[] = {
 289         { .irq = 29 }, /* INT_24XX_GPIO_BANK1 */
 290         { .irq = -1 }
 291 };
 292
 293 struct omap_hwmod_irq_info omap2_gpio2_irqs[] = {
 294         { .irq = 30 }, /* INT_24XX_GPIO_BANK2 */
 295         { .irq = -1 }
 296 };
 297
 298 struct omap_hwmod_irq_info omap2_gpio3_irqs[] = {
 299         { .irq = 31 }, /* INT_24XX_GPIO_BANK3 */
 300         { .irq = -1 }
 301 };
 302
 303 struct omap_hwmod_irq_info omap2_gpio4_irqs[] = {
 304         { .irq = 32 }, /* INT_24XX_GPIO_BANK4 */
 305         { .irq = -1 }
 306 };
 307
 308 struct omap_hwmod_irq_info omap2_dma_system_irqs[] = {
 309         { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */
 310         { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */
 311         { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */
 312         { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */
 313         { .irq = -1 }
 314 };
 315
 316 struct omap_hwmod_irq_info omap2_mcspi1_mpu_irqs[] = {
 317         { .irq = 65 },
 318         { .irq = -1 }
 319 };
 320
 321 struct omap_hwmod_irq_info omap2_mcspi2_mpu_irqs[] = {
 322         { .irq = 66 },
 323         { .irq = -1 }
 324 };
 325