arch/arm/mach-s5pc100/dma.c

   1 /* linux/arch/arm/mach-s5pc100/dma.c
   2  *
   3  * Copyright (c) 2011 Samsung Electronics Co., Ltd.
   4  *              http://www.samsung.com
   5  *
   6  * Copyright (C) 2010 Samsung Electronics Co. Ltd.
   7  *      Jaswinder Singh <jassi.brar@samsung.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  22  */
  23
  24 #include <linux/dma-mapping.h>
  25 #include <linux/amba/bus.h>
  26 #include <linux/amba/pl330.h>
  27
  28 #include <asm/irq.h>
  29 #include <plat/devs.h>
  30 #include <plat/irqs.h>
  31
  32 #include <mach/map.h>
  33 #include <mach/irqs.h>
  34 #include <mach/dma.h>
  35
  36 static u64 dma_dmamask = DMA_BIT_MASK(32);
  37
  38 struct dma_pl330_peri pdma0_peri[30] = {
  39         {
  40                 .peri_id = (u8)DMACH_UART0_RX,
  41                 .rqtype = DEVTOMEM,
  42         }, {
  43                 .peri_id = (u8)DMACH_UART0_TX,
  44                 .rqtype = MEMTODEV,
  45         }, {
  46                 .peri_id = (u8)DMACH_UART1_RX,
  47                 .rqtype = DEVTOMEM,
  48         }, {
  49                 .peri_id = (u8)DMACH_UART1_TX,
  50                 .rqtype = MEMTODEV,
  51         }, {
  52                 .peri_id = (u8)DMACH_UART2_RX,
  53                 .rqtype = DEVTOMEM,
  54         }, {
  55                 .peri_id = (u8)DMACH_UART2_TX,
  56                 .rqtype = MEMTODEV,
  57         }, {
  58                 .peri_id = (u8)DMACH_UART3_RX,
  59                 .rqtype = DEVTOMEM,
  60         }, {
  61                 .peri_id = (u8)DMACH_UART3_TX,
  62                 .rqtype = MEMTODEV,
  63         }, {
  64                 .peri_id = DMACH_IRDA,
  65         }, {
  66                 .peri_id = (u8)DMACH_I2S0_RX,
  67                 .rqtype = DEVTOMEM,
  68         }, {
  69                 .peri_id = (u8)DMACH_I2S0_TX,
  70                 .rqtype = MEMTODEV,
  71         }, {
  72                 .peri_id = (u8)DMACH_I2S0S_TX,
  73                 .rqtype = MEMTODEV,
  74         }, {
  75                 .peri_id = (u8)DMACH_I2S1_RX,
  76                 .rqtype = DEVTOMEM,
  77         }, {
  78                 .peri_id = (u8)DMACH_I2S1_TX,
  79                 .rqtype = MEMTODEV,
  80         }, {
  81                 .peri_id = (u8)DMACH_I2S2_RX,
  82                 .rqtype = DEVTOMEM,
  83         }, {
  84                 .peri_id = (u8)DMACH_I2S2_TX,
  85                 .rqtype = MEMTODEV,
  86         }, {
  87                 .peri_id = (u8)DMACH_SPI0_RX,
  88                 .rqtype = DEVTOMEM,
  89         }, {
  90                 .peri_id = (u8)DMACH_SPI0_TX,
  91                 .rqtype = MEMTODEV,
  92         }, {
  93                 .peri_id = (u8)DMACH_SPI1_RX,
  94                 .rqtype = DEVTOMEM,
  95         }, {
  96                 .peri_id = (u8)DMACH_SPI1_TX,
  97                 .rqtype = MEMTODEV,
  98         }, {
  99                 .peri_id = (u8)DMACH_SPI2_RX,
 100                 .rqtype = DEVTOMEM,
 101         }, {
 102                 .peri_id = (u8)DMACH_SPI2_TX,
 103                 .rqtype = MEMTODEV,
 104         }, {
 105                 .peri_id = (u8)DMACH_AC97_MICIN,
 106                 .rqtype = DEVTOMEM,
 107         }, {
 108                 .peri_id = (u8)DMACH_AC97_PCMIN,
 109                 .rqtype = DEVTOMEM,
 110         }, {
 111                 .peri_id = (u8)DMACH_AC97_PCMOUT,
 112                 .rqtype = MEMTODEV,
 113         }, {
 114                 .peri_id = (u8)DMACH_EXTERNAL,
 115         }, {
 116                 .peri_id = (u8)DMACH_PWM,
 117         }, {
 118                 .peri_id = (u8)DMACH_SPDIF,
 119                 .rqtype = MEMTODEV,
 120         }, {
 121                 .peri_id = (u8)DMACH_HSI_RX,
 122                 .rqtype = DEVTOMEM,
 123         }, {
 124                 .peri_id = (u8)DMACH_HSI_TX,
 125                 .rqtype = MEMTODEV,
 126         },
 127 };
 128
 129 struct dma_pl330_platdata s5pc100_pdma0_pdata = {
 130         .nr_valid_peri = ARRAY_SIZE(pdma0_peri),
 131         .peri = pdma0_peri,
 132 };
 133
 134 struct amba_device s5pc100_device_pdma0 = {
 135         .dev = {
 136                 .init_name = "dma-pl330.0",
 137                 .dma_mask = &dma_dmamask,
 138                 .coherent_dma_mask = DMA_BIT_MASK(32),
 139                 .platform_data = &s5pc100_pdma0_pdata,
 140         },
 141         .res = {
 142                 .start = S5PC100_PA_PDMA0,
 143                 .end = S5PC100_PA_PDMA0 + SZ_4K,
 144                 .flags = IORESOURCE_MEM,
 145         },
 146         .irq = {IRQ_PDMA0, NO_IRQ},
 147         .periphid = 0x00041330,
 148 };
 149
 150 struct dma_pl330_peri pdma1_peri[30] = {
 151         {
 152                 .peri_id = (u8)DMACH_UART0_RX,
 153                 .rqtype = DEVTOMEM,
 154         }, {
 155                 .peri_id = (u8)DMACH_UART0_TX,
 156                 .rqtype = MEMTODEV,
 157         }, {
 158                 .peri_id = (u8)DMACH_UART1_RX,
 159                 .rqtype = DEVTOMEM,
 160         }, {
 161                 .peri_id = (u8)DMACH_UART1_TX,
 162                 .rqtype = MEMTODEV,
 163         }, {
 164                 .peri_id = (u8)DMACH_UART2_RX,
 165                 .rqtype = DEVTOMEM,
 166         }, {
 167                 .peri_id = (u8)DMACH_UART2_TX,
 168                 .rqtype = MEMTODEV,
 169         }, {
 170                 .peri_id = (u8)DMACH_UART3_RX,
 171                 .rqtype = DEVTOMEM,
 172         }, {
 173                 .peri_id = (u8)DMACH_UART3_TX,
 174                 .rqtype = MEMTODEV,
 175         }, {
 176                 .peri_id = DMACH_IRDA,
 177         }, {
 178                 .peri_id = (u8)DMACH_I2S0_RX,
 179                 .rqtype = DEVTOMEM,
 180         }, {
 181                 .peri_id = (u8)DMACH_I2S0_TX,
 182                 .rqtype = MEMTODEV,
 183         }, {
 184                 .peri_id = (u8)DMACH_I2S0S_TX,
 185                 .rqtype = MEMTODEV,
 186         }, {
 187                 .peri_id = (u8)DMACH_I2S1_RX,
 188                 .rqtype = DEVTOMEM,
 189         }, {
 190                 .peri_id = (u8)DMACH_I2S1_TX,
 191                 .rqtype = MEMTODEV,
 192         }, {
 193                 .peri_id = (u8)DMACH_I2S2_RX,
 194                 .rqtype = DEVTOMEM,
 195         }, {
 196                 .peri_id = (u8)DMACH_I2S2_TX,
 197                 .rqtype = MEMTODEV,
 198         }, {
 199                 .peri_id = (u8)DMACH_SPI0_RX,
 200                 .rqtype = DEVTOMEM,
 201         }, {
 202                 .peri_id = (u8)DMACH_SPI0_TX,
 203                 .rqtype = MEMTODEV,
 204         }, {
 205                 .peri_id = (u8)DMACH_SPI1_RX,
 206                 .rqtype = DEVTOMEM,
 207         }, {
 208                 .peri_id = (u8)DMACH_SPI1_TX,
 209                 .rqtype = MEMTODEV,
 210         }, {
 211                 .peri_id = (u8)DMACH_SPI2_RX,
 212                 .rqtype = DEVTOMEM,
 213         }, {
 214                 .peri_id = (u8)DMACH_SPI2_TX,
 215                 .rqtype = MEMTODEV,
 216         }, {
 217                 .peri_id = (u8)DMACH_PCM0_RX,
 218                 .rqtype = DEVTOMEM,
 219         }, {
 220                 .peri_id = (u8)DMACH_PCM1_TX,
 221                 .rqtype = MEMTODEV,
 222         }, {
 223                 .peri_id = (u8)DMACH_PCM1_RX,
 224                 .rqtype = DEVTOMEM,
 225         }, {
 226                 .peri_id = (u8)DMACH_PCM1_TX,
 227                 .rqtype = MEMTODEV,
 228         }, {
 229                 .peri_id = (u8)DMACH_MSM_REQ0,
 230         }, {
 231                 .peri_id = (u8)DMACH_MSM_REQ1,
 232         }, {
 233                 .peri_id = (u8)DMACH_MSM_REQ2,
 234         }, {
 235                 .peri_id = (u8)DMACH_MSM_REQ3,
 236         },
 237 };
 238
 239 struct dma_pl330_platdata s5pc100_pdma1_pdata = {
 240         .nr_valid_peri = ARRAY_SIZE(pdma1_peri),
 241         .peri = pdma1_peri,
 242 };
 243
 244 struct amba_device s5pc100_device_pdma1 = {
 245         .dev = {
 246                 .init_name = "dma-pl330.1",
 247                 .dma_mask = &dma_dmamask,
 248                 .coherent_dma_mask = DMA_BIT_MASK(32),
 249                 .platform_data = &s5pc100_pdma1_pdata,
 250         },
 251         .res = {
 252                 .start = S5PC100_PA_PDMA1,
 253                 .end = S5PC100_PA_PDMA1 + SZ_4K,
 254                 .flags = IORESOURCE_MEM,
 255         },
 256         .irq = {IRQ_PDMA1, NO_IRQ},
 257         .periphid = 0x00041330,
 258 };
 259
 260 static int __init s5pc100_dma_init(void)
 261 {
 262         amba_device_register(&s5pc100_device_pdma0, &iomem_resource);
 263         amba_device_register(&s5pc100_device_pdma1, &iomem_resource);
 264
 265         return 0;
 266 }
 267 arch_initcall(s5pc100_dma_init);