3 * hda_intel.c - Implementation of primary alsa driver code base
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
37 #include <linux/delay.h>
38 #include <linux/interrupt.h>
39 #include <linux/kernel.h>
40 #include <linux/module.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/moduleparam.h>
43 #include <linux/init.h>
44 #include <linux/slab.h>
45 #include <linux/pci.h>
46 #include <linux/mutex.h>
47 #include <linux/reboot.h>
50 /* for snoop control */
51 #include <asm/pgtable.h>
52 #include <asm/cacheflush.h>
54 #include <sound/core.h>
55 #include <sound/initval.h>
56 #include "hda_codec.h"
59 static int index
[SNDRV_CARDS
] = SNDRV_DEFAULT_IDX
;
60 static char *id
[SNDRV_CARDS
] = SNDRV_DEFAULT_STR
;
61 static int enable
[SNDRV_CARDS
] = SNDRV_DEFAULT_ENABLE_PNP
;
62 static char *model
[SNDRV_CARDS
];
63 static int position_fix
[SNDRV_CARDS
];
64 static int bdl_pos_adj
[SNDRV_CARDS
] = {[0 ... (SNDRV_CARDS
-1)] = -1};
65 static int probe_mask
[SNDRV_CARDS
] = {[0 ... (SNDRV_CARDS
-1)] = -1};
66 static int probe_only
[SNDRV_CARDS
];
67 static int single_cmd
;
68 static int enable_msi
= -1;
69 #ifdef CONFIG_SND_HDA_PATCH_LOADER
70 static char *patch
[SNDRV_CARDS
];
72 #ifdef CONFIG_SND_HDA_INPUT_BEEP
73 static int beep_mode
[SNDRV_CARDS
] = {[0 ... (SNDRV_CARDS
-1)] =
74 CONFIG_SND_HDA_INPUT_BEEP_MODE
};
77 module_param_array(index
, int, NULL
, 0444);
78 MODULE_PARM_DESC(index
, "Index value for Intel HD audio interface.");
79 module_param_array(id
, charp
, NULL
, 0444);
80 MODULE_PARM_DESC(id
, "ID string for Intel HD audio interface.");
81 module_param_array(enable
, bool, NULL
, 0444);
82 MODULE_PARM_DESC(enable
, "Enable Intel HD audio interface.");
83 module_param_array(model
, charp
, NULL
, 0444);
84 MODULE_PARM_DESC(model
, "Use the given board model.");
85 module_param_array(position_fix
, int, NULL
, 0444);
86 MODULE_PARM_DESC(position_fix
, "DMA pointer read method."
87 "(0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO).");
88 module_param_array(bdl_pos_adj
, int, NULL
, 0644);
89 MODULE_PARM_DESC(bdl_pos_adj
, "BDL position adjustment offset.");
90 module_param_array(probe_mask
, int, NULL
, 0444);
91 MODULE_PARM_DESC(probe_mask
, "Bitmask to probe codecs (default = -1).");
92 module_param_array(probe_only
, int, NULL
, 0444);
93 MODULE_PARM_DESC(probe_only
, "Only probing and no codec initialization.");
94 module_param(single_cmd
, bool, 0444);
95 MODULE_PARM_DESC(single_cmd
, "Use single command to communicate with codecs "
96 "(for debugging only).");
97 module_param(enable_msi
, int, 0444);
98 MODULE_PARM_DESC(enable_msi
, "Enable Message Signaled Interrupt (MSI)");
99 #ifdef CONFIG_SND_HDA_PATCH_LOADER
100 module_param_array(patch
, charp
, NULL
, 0444);
101 MODULE_PARM_DESC(patch
, "Patch file for Intel HD audio interface.");
103 #ifdef CONFIG_SND_HDA_INPUT_BEEP
104 module_param_array(beep_mode
, int, NULL
, 0444);
105 MODULE_PARM_DESC(beep_mode
, "Select HDA Beep registration mode "
106 "(0=off, 1=on, 2=mute switch on/off) (default=1).");
109 #ifdef CONFIG_SND_HDA_POWER_SAVE
110 static int power_save
= CONFIG_SND_HDA_POWER_SAVE_DEFAULT
;
111 module_param(power_save
, int, 0644);
112 MODULE_PARM_DESC(power_save
, "Automatic power-saving timeout "
113 "(in second, 0 = disable).");
115 /* reset the HD-audio controller in power save mode.
116 * this may give more power-saving, but will take longer time to
119 static int power_save_controller
= 1;
120 module_param(power_save_controller
, bool, 0644);
121 MODULE_PARM_DESC(power_save_controller
, "Reset controller in power save mode.");
124 static int align_buffer_size
= 1;
125 module_param(align_buffer_size
, bool, 0644);
126 MODULE_PARM_DESC(align_buffer_size
,
127 "Force buffer and period sizes to be multiple of 128 bytes.");
130 static bool hda_snoop
= true;
131 module_param_named(snoop
, hda_snoop
, bool, 0444);
132 MODULE_PARM_DESC(snoop
, "Enable/disable snooping");
133 #define azx_snoop(chip) (chip)->snoop
135 #define hda_snoop true
136 #define azx_snoop(chip) true
140 MODULE_LICENSE("GPL");
141 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
169 MODULE_DESCRIPTION("Intel HDA driver");
171 #ifdef CONFIG_SND_VERBOSE_PRINTK
172 #define SFX /* nop */
174 #define SFX "hda-intel: "
180 #define ICH6_REG_GCAP 0x00
181 #define ICH6_GCAP_64OK (1 << 0) /* 64bit address support */
182 #define ICH6_GCAP_NSDO (3 << 1) /* # of serial data out signals */
183 #define ICH6_GCAP_BSS (31 << 3) /* # of bidirectional streams */
184 #define ICH6_GCAP_ISS (15 << 8) /* # of input streams */
185 #define ICH6_GCAP_OSS (15 << 12) /* # of output streams */
186 #define ICH6_REG_VMIN 0x02
187 #define ICH6_REG_VMAJ 0x03
188 #define ICH6_REG_OUTPAY 0x04
189 #define ICH6_REG_INPAY 0x06
190 #define ICH6_REG_GCTL 0x08
191 #define ICH6_GCTL_RESET (1 << 0) /* controller reset */
192 #define ICH6_GCTL_FCNTRL (1 << 1) /* flush control */
193 #define ICH6_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */
194 #define ICH6_REG_WAKEEN 0x0c
195 #define ICH6_REG_STATESTS 0x0e
196 #define ICH6_REG_GSTS 0x10
197 #define ICH6_GSTS_FSTS (1 << 1) /* flush status */
198 #define ICH6_REG_INTCTL 0x20
199 #define ICH6_REG_INTSTS 0x24
200 #define ICH6_REG_WALLCLK 0x30 /* 24Mhz source */
201 #define ICH6_REG_OLD_SSYNC 0x34 /* SSYNC for old ICH */
202 #define ICH6_REG_SSYNC 0x38
203 #define ICH6_REG_CORBLBASE 0x40
204 #define ICH6_REG_CORBUBASE 0x44
205 #define ICH6_REG_CORBWP 0x48
206 #define ICH6_REG_CORBRP 0x4a
207 #define ICH6_CORBRP_RST (1 << 15) /* read pointer reset */
208 #define ICH6_REG_CORBCTL 0x4c
209 #define ICH6_CORBCTL_RUN (1 << 1) /* enable DMA */
210 #define ICH6_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */
211 #define ICH6_REG_CORBSTS 0x4d
212 #define ICH6_CORBSTS_CMEI (1 << 0) /* memory error indication */
213 #define ICH6_REG_CORBSIZE 0x4e
215 #define ICH6_REG_RIRBLBASE 0x50
216 #define ICH6_REG_RIRBUBASE 0x54
217 #define ICH6_REG_RIRBWP 0x58
218 #define ICH6_RIRBWP_RST (1 << 15) /* write pointer reset */
219 #define ICH6_REG_RINTCNT 0x5a
220 #define ICH6_REG_RIRBCTL 0x5c
221 #define ICH6_RBCTL_IRQ_EN (1 << 0) /* enable IRQ */
222 #define ICH6_RBCTL_DMA_EN (1 << 1) /* enable DMA */
223 #define ICH6_RBCTL_OVERRUN_EN (1 << 2) /* enable overrun irq */
224 #define ICH6_REG_RIRBSTS 0x5d
225 #define ICH6_RBSTS_IRQ (1 << 0) /* response irq */
226 #define ICH6_RBSTS_OVERRUN (1 << 2) /* overrun irq */
227 #define ICH6_REG_RIRBSIZE 0x5e
229 #define ICH6_REG_IC 0x60
230 #define ICH6_REG_IR 0x64
231 #define ICH6_REG_IRS 0x68
232 #define ICH6_IRS_VALID (1<<1)
233 #define ICH6_IRS_BUSY (1<<0)
235 #define ICH6_REG_DPLBASE 0x70
236 #define ICH6_REG_DPUBASE 0x74
237 #define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
239 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
240 enum { SDI0
, SDI1
, SDI2
, SDI3
, SDO0
, SDO1
, SDO2
, SDO3
};
242 /* stream register offsets from stream base */
243 #define ICH6_REG_SD_CTL 0x00
244 #define ICH6_REG_SD_STS 0x03
245 #define ICH6_REG_SD_LPIB 0x04
246 #define ICH6_REG_SD_CBL 0x08
247 #define ICH6_REG_SD_LVI 0x0c
248 #define ICH6_REG_SD_FIFOW 0x0e
249 #define ICH6_REG_SD_FIFOSIZE 0x10
250 #define ICH6_REG_SD_FORMAT 0x12
251 #define ICH6_REG_SD_BDLPL 0x18
252 #define ICH6_REG_SD_BDLPU 0x1c
255 #define ICH6_PCIREG_TCSEL 0x44
261 /* max number of SDs */
262 /* ICH, ATI and VIA have 4 playback and 4 capture */
263 #define ICH6_NUM_CAPTURE 4
264 #define ICH6_NUM_PLAYBACK 4
266 /* ULI has 6 playback and 5 capture */
267 #define ULI_NUM_CAPTURE 5
268 #define ULI_NUM_PLAYBACK 6
270 /* ATI HDMI has 1 playback and 0 capture */
271 #define ATIHDMI_NUM_CAPTURE 0
272 #define ATIHDMI_NUM_PLAYBACK 1
274 /* TERA has 4 playback and 3 capture */
275 #define TERA_NUM_CAPTURE 3
276 #define TERA_NUM_PLAYBACK 4
278 /* this number is statically defined for simplicity */
279 #define MAX_AZX_DEV 16
281 /* max number of fragments - we may use more if allocating more pages for BDL */
282 #define BDL_SIZE 4096
283 #define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16)
284 #define AZX_MAX_FRAG 32
285 /* max buffer size - no h/w limit, you can increase as you like */
286 #define AZX_MAX_BUF_SIZE (1024*1024*1024)
288 /* RIRB int mask: overrun[2], response[0] */
289 #define RIRB_INT_RESPONSE 0x01
290 #define RIRB_INT_OVERRUN 0x04
291 #define RIRB_INT_MASK 0x05
293 /* STATESTS int mask: S3,SD2,SD1,SD0 */
294 #define AZX_MAX_CODECS 8
295 #define AZX_DEFAULT_CODECS 4
296 #define STATESTS_INT_MASK ((1 << AZX_MAX_CODECS) - 1)
299 #define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
300 #define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
301 #define SD_CTL_STRIPE (3 << 16) /* stripe control */
302 #define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */
303 #define SD_CTL_DIR (1 << 19) /* bi-directional stream */
304 #define SD_CTL_STREAM_TAG_MASK (0xf << 20)
305 #define SD_CTL_STREAM_TAG_SHIFT 20
307 /* SD_CTL and SD_STS */
308 #define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
309 #define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
310 #define SD_INT_COMPLETE 0x04 /* completion interrupt */
311 #define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
315 #define SD_STS_FIFO_READY 0x20 /* FIFO ready */
317 /* INTCTL and INTSTS */
318 #define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
319 #define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
320 #define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
322 /* below are so far hardcoded - should read registers in future */
323 #define ICH6_MAX_CORB_ENTRIES 256
324 #define ICH6_MAX_RIRB_ENTRIES 256
326 /* position fix mode */
334 /* Defines for ATI HD Audio support in SB450 south bridge */
335 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
336 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
338 /* Defines for Nvidia HDA support */
339 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
340 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
341 #define NVIDIA_HDA_ISTRM_COH 0x4d
342 #define NVIDIA_HDA_OSTRM_COH 0x4c
343 #define NVIDIA_HDA_ENABLE_COHBIT 0x01
345 /* Defines for Intel SCH HDA snoop control */
346 #define INTEL_SCH_HDA_DEVC 0x78
347 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
349 /* Define IN stream 0 FIFO size offset in VIA controller */
350 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
351 /* Define VIA HD Audio Device ID*/
352 #define VIA_HDAC_DEVICE_ID 0x3288
354 /* HD Audio class code */
355 #define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403
361 struct snd_dma_buffer bdl
; /* BDL buffer */
362 u32
*posbuf
; /* position buffer pointer */
364 unsigned int bufsize
; /* size of the play buffer in bytes */
365 unsigned int period_bytes
; /* size of the period in bytes */
366 unsigned int frags
; /* number for period in the play buffer */
367 unsigned int fifo_size
; /* FIFO size */
368 unsigned long start_wallclk
; /* start + minimum wallclk */
369 unsigned long period_wallclk
; /* wallclk for period */
371 void __iomem
*sd_addr
; /* stream descriptor pointer */
373 u32 sd_int_sta_mask
; /* stream int status mask */
376 struct snd_pcm_substream
*substream
; /* assigned substream,
379 unsigned int format_val
; /* format value to be set in the
380 * controller and the codec
382 unsigned char stream_tag
; /* assigned stream */
383 unsigned char index
; /* stream index */
384 int assigned_key
; /* last device# key assigned to */
386 unsigned int opened
:1;
387 unsigned int running
:1;
388 unsigned int irq_pending
:1;
391 * A flag to ensure DMA position is 0
392 * when link position is not greater than FIFO size
394 unsigned int insufficient
:1;
395 unsigned int wc_marked
:1;
400 u32
*buf
; /* CORB/RIRB buffer
401 * Each CORB entry is 4byte, RIRB is 8byte
403 dma_addr_t addr
; /* physical address of CORB/RIRB buffer */
405 unsigned short rp
, wp
; /* read/write pointers */
406 int cmds
[AZX_MAX_CODECS
]; /* number of pending requests */
407 u32 res
[AZX_MAX_CODECS
]; /* last read value */
411 struct snd_card
*card
;
415 /* chip type specific */
417 unsigned int driver_caps
;
418 int playback_streams
;
419 int playback_index_offset
;
421 int capture_index_offset
;
426 void __iomem
*remap_addr
;
431 struct mutex open_mutex
;
433 /* streams (x num_streams) */
434 struct azx_dev
*azx_dev
;
437 struct snd_pcm
*pcm
[HDA_MAX_PCMS
];
440 unsigned short codec_mask
;
441 int codec_probe_mask
; /* copied from probe_mask option */
443 unsigned int beep_mode
;
449 /* CORB/RIRB and position buffers */
450 struct snd_dma_buffer rb
;
451 struct snd_dma_buffer posbuf
;
454 int position_fix
[2]; /* for both playback/capture streams */
456 unsigned int running
:1;
457 unsigned int initialized
:1;
458 unsigned int single_cmd
:1;
459 unsigned int polling_mode
:1;
461 unsigned int irq_pending_warned
:1;
462 unsigned int probing
:1; /* codec probing phase */
463 unsigned int snoop
:1;
466 unsigned int last_cmd
[AZX_MAX_CODECS
];
468 /* for pending irqs */
469 struct work_struct irq_pending_work
;
471 /* reboot notifier (for mysterious hangup problem at power-down) */
472 struct notifier_block reboot_notifier
;
489 AZX_NUM_DRIVERS
, /* keep this as last entry */
492 /* driver quirks (capabilities) */
493 /* bits 0-7 are used for indicating driver type */
494 #define AZX_DCAPS_NO_TCSEL (1 << 8) /* No Intel TCSEL bit */
495 #define AZX_DCAPS_NO_MSI (1 << 9) /* No MSI support */
496 #define AZX_DCAPS_ATI_SNOOP (1 << 10) /* ATI snoop enable */
497 #define AZX_DCAPS_NVIDIA_SNOOP (1 << 11) /* Nvidia snoop enable */
498 #define AZX_DCAPS_SCH_SNOOP (1 << 12) /* SCH/PCH snoop enable */
499 #define AZX_DCAPS_RIRB_DELAY (1 << 13) /* Long delay in read loop */
500 #define AZX_DCAPS_RIRB_PRE_DELAY (1 << 14) /* Put a delay before read */
501 #define AZX_DCAPS_CTX_WORKAROUND (1 << 15) /* X-Fi workaround */
502 #define AZX_DCAPS_POSFIX_LPIB (1 << 16) /* Use LPIB as default */
503 #define AZX_DCAPS_POSFIX_VIA (1 << 17) /* Use VIACOMBO as default */
504 #define AZX_DCAPS_NO_64BIT (1 << 18) /* No 64bit address */
505 #define AZX_DCAPS_SYNC_WRITE (1 << 19) /* sync each cmd write */
506 #define AZX_DCAPS_OLD_SSYNC (1 << 20) /* Old SSYNC reg for ICH */
507 #define AZX_DCAPS_BUFSIZE (1 << 21) /* no buffer size alignment */
509 /* quirks for ATI SB / AMD Hudson */
510 #define AZX_DCAPS_PRESET_ATI_SB \
511 (AZX_DCAPS_ATI_SNOOP | AZX_DCAPS_NO_TCSEL | \
512 AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
514 /* quirks for ATI/AMD HDMI */
515 #define AZX_DCAPS_PRESET_ATI_HDMI \
516 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
518 /* quirks for Nvidia */
519 #define AZX_DCAPS_PRESET_NVIDIA \
520 (AZX_DCAPS_NVIDIA_SNOOP | AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI)
522 static char *driver_short_names
[] __devinitdata
= {
523 [AZX_DRIVER_ICH
] = "HDA Intel",
524 [AZX_DRIVER_PCH
] = "HDA Intel PCH",
525 [AZX_DRIVER_SCH
] = "HDA Intel MID",
526 [AZX_DRIVER_ATI
] = "HDA ATI SB",
527 [AZX_DRIVER_ATIHDMI
] = "HDA ATI HDMI",
528 [AZX_DRIVER_VIA
] = "HDA VIA VT82xx",
529 [AZX_DRIVER_SIS
] = "HDA SIS966",
530 [AZX_DRIVER_ULI
] = "HDA ULI M5461",
531 [AZX_DRIVER_NVIDIA
] = "HDA NVidia",
532 [AZX_DRIVER_TERA
] = "HDA Teradici",
533 [AZX_DRIVER_CTX
] = "HDA Creative",
534 [AZX_DRIVER_GENERIC
] = "HD-Audio Generic",
538 * macros for easy use
540 #define azx_writel(chip,reg,value) \
541 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
542 #define azx_readl(chip,reg) \
543 readl((chip)->remap_addr + ICH6_REG_##reg)
544 #define azx_writew(chip,reg,value) \
545 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
546 #define azx_readw(chip,reg) \
547 readw((chip)->remap_addr + ICH6_REG_##reg)
548 #define azx_writeb(chip,reg,value) \
549 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
550 #define azx_readb(chip,reg) \
551 readb((chip)->remap_addr + ICH6_REG_##reg)
553 #define azx_sd_writel(dev,reg,value) \
554 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
555 #define azx_sd_readl(dev,reg) \
556 readl((dev)->sd_addr + ICH6_REG_##reg)
557 #define azx_sd_writew(dev,reg,value) \
558 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
559 #define azx_sd_readw(dev,reg) \
560 readw((dev)->sd_addr + ICH6_REG_##reg)
561 #define azx_sd_writeb(dev,reg,value) \
562 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
563 #define azx_sd_readb(dev,reg) \
564 readb((dev)->sd_addr + ICH6_REG_##reg)
566 /* for pcm support */
567 #define get_azx_dev(substream) (substream->runtime->private_data)
570 static void __mark_pages_wc(struct azx
*chip
, void *addr
, size_t size
, bool on
)
575 int pages
= (size
+ PAGE_SIZE
- 1) >> PAGE_SHIFT
;
577 set_memory_wc((unsigned long)addr
, pages
);
579 set_memory_wb((unsigned long)addr
, pages
);
583 static inline void mark_pages_wc(struct azx
*chip
, struct snd_dma_buffer
*buf
,
586 __mark_pages_wc(chip
, buf
->area
, buf
->bytes
, on
);
588 static inline void mark_runtime_wc(struct azx
*chip
, struct azx_dev
*azx_dev
,
589 struct snd_pcm_runtime
*runtime
, bool on
)
591 if (azx_dev
->wc_marked
!= on
) {
592 __mark_pages_wc(chip
, runtime
->dma_area
, runtime
->dma_bytes
, on
);
593 azx_dev
->wc_marked
= on
;
597 /* NOP for other archs */
598 static inline void mark_pages_wc(struct azx
*chip
, struct snd_dma_buffer
*buf
,
602 static inline void mark_runtime_wc(struct azx
*chip
, struct azx_dev
*azx_dev
,
603 struct snd_pcm_runtime
*runtime
, bool on
)
608 static int azx_acquire_irq(struct azx
*chip
, int do_disconnect
);
609 static int azx_send_cmd(struct hda_bus
*bus
, unsigned int val
);
611 * Interface for HD codec
615 * CORB / RIRB interface
617 static int azx_alloc_cmd_io(struct azx
*chip
)
621 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
622 err
= snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV
,
623 snd_dma_pci_data(chip
->pci
),
624 PAGE_SIZE
, &chip
->rb
);
626 snd_printk(KERN_ERR SFX
"cannot allocate CORB/RIRB\n");
629 mark_pages_wc(chip
, &chip
->rb
, true);
633 static void azx_init_cmd_io(struct azx
*chip
)
635 spin_lock_irq(&chip
->reg_lock
);
637 chip
->corb
.addr
= chip
->rb
.addr
;
638 chip
->corb
.buf
= (u32
*)chip
->rb
.area
;
639 azx_writel(chip
, CORBLBASE
, (u32
)chip
->corb
.addr
);
640 azx_writel(chip
, CORBUBASE
, upper_32_bits(chip
->corb
.addr
));
642 /* set the corb size to 256 entries (ULI requires explicitly) */
643 azx_writeb(chip
, CORBSIZE
, 0x02);
644 /* set the corb write pointer to 0 */
645 azx_writew(chip
, CORBWP
, 0);
646 /* reset the corb hw read pointer */
647 azx_writew(chip
, CORBRP
, ICH6_CORBRP_RST
);
648 /* enable corb dma */
649 azx_writeb(chip
, CORBCTL
, ICH6_CORBCTL_RUN
);
652 chip
->rirb
.addr
= chip
->rb
.addr
+ 2048;
653 chip
->rirb
.buf
= (u32
*)(chip
->rb
.area
+ 2048);
654 chip
->rirb
.wp
= chip
->rirb
.rp
= 0;
655 memset(chip
->rirb
.cmds
, 0, sizeof(chip
->rirb
.cmds
));
656 azx_writel(chip
, RIRBLBASE
, (u32
)chip
->rirb
.addr
);
657 azx_writel(chip
, RIRBUBASE
, upper_32_bits(chip
->rirb
.addr
));
659 /* set the rirb size to 256 entries (ULI requires explicitly) */
660 azx_writeb(chip
, RIRBSIZE
, 0x02);
661 /* reset the rirb hw write pointer */
662 azx_writew(chip
, RIRBWP
, ICH6_RIRBWP_RST
);
663 /* set N=1, get RIRB response interrupt for new entry */
664 if (chip
->driver_caps
& AZX_DCAPS_CTX_WORKAROUND
)
665 azx_writew(chip
, RINTCNT
, 0xc0);
667 azx_writew(chip
, RINTCNT
, 1);
668 /* enable rirb dma and response irq */
669 azx_writeb(chip
, RIRBCTL
, ICH6_RBCTL_DMA_EN
| ICH6_RBCTL_IRQ_EN
);
670 spin_unlock_irq(&chip
->reg_lock
);
673 static void azx_free_cmd_io(struct azx
*chip
)
675 spin_lock_irq(&chip
->reg_lock
);
676 /* disable ringbuffer DMAs */
677 azx_writeb(chip
, RIRBCTL
, 0);
678 azx_writeb(chip
, CORBCTL
, 0);
679 spin_unlock_irq(&chip
->reg_lock
);
682 static unsigned int azx_command_addr(u32 cmd
)
684 unsigned int addr
= cmd
>> 28;
686 if (addr
>= AZX_MAX_CODECS
) {
694 static unsigned int azx_response_addr(u32 res
)
696 unsigned int addr
= res
& 0xf;
698 if (addr
>= AZX_MAX_CODECS
) {
707 static int azx_corb_send_cmd(struct hda_bus
*bus
, u32 val
)
709 struct azx
*chip
= bus
->private_data
;
710 unsigned int addr
= azx_command_addr(val
);
713 spin_lock_irq(&chip
->reg_lock
);
715 /* add command to corb */
716 wp
= azx_readb(chip
, CORBWP
);
718 wp
%= ICH6_MAX_CORB_ENTRIES
;
720 chip
->rirb
.cmds
[addr
]++;
721 chip
->corb
.buf
[wp
] = cpu_to_le32(val
);
722 azx_writel(chip
, CORBWP
, wp
);
724 spin_unlock_irq(&chip
->reg_lock
);
729 #define ICH6_RIRB_EX_UNSOL_EV (1<<4)
731 /* retrieve RIRB entry - called from interrupt handler */
732 static void azx_update_rirb(struct azx
*chip
)
738 wp
= azx_readb(chip
, RIRBWP
);
739 if (wp
== chip
->rirb
.wp
)
743 while (chip
->rirb
.rp
!= wp
) {
745 chip
->rirb
.rp
%= ICH6_MAX_RIRB_ENTRIES
;
747 rp
= chip
->rirb
.rp
<< 1; /* an RIRB entry is 8-bytes */
748 res_ex
= le32_to_cpu(chip
->rirb
.buf
[rp
+ 1]);
749 res
= le32_to_cpu(chip
->rirb
.buf
[rp
]);
750 addr
= azx_response_addr(res_ex
);
751 if (res_ex
& ICH6_RIRB_EX_UNSOL_EV
)
752 snd_hda_queue_unsol_event(chip
->bus
, res
, res_ex
);
753 else if (chip
->rirb
.cmds
[addr
]) {
754 chip
->rirb
.res
[addr
] = res
;
756 chip
->rirb
.cmds
[addr
]--;
758 snd_printk(KERN_ERR SFX
"spurious response %#x:%#x, "
761 chip
->last_cmd
[addr
]);
765 /* receive a response */
766 static unsigned int azx_rirb_get_response(struct hda_bus
*bus
,
769 struct azx
*chip
= bus
->private_data
;
770 unsigned long timeout
;
774 timeout
= jiffies
+ msecs_to_jiffies(1000);
776 if (chip
->polling_mode
|| do_poll
) {
777 spin_lock_irq(&chip
->reg_lock
);
778 azx_update_rirb(chip
);
779 spin_unlock_irq(&chip
->reg_lock
);
781 if (!chip
->rirb
.cmds
[addr
]) {
786 chip
->poll_count
= 0;
787 return chip
->rirb
.res
[addr
]; /* the last value */
789 if (time_after(jiffies
, timeout
))
791 if (bus
->needs_damn_long_delay
)
792 msleep(2); /* temporary workaround */
799 if (!chip
->polling_mode
&& chip
->poll_count
< 2) {
800 snd_printdd(SFX
"azx_get_response timeout, "
801 "polling the codec once: last cmd=0x%08x\n",
802 chip
->last_cmd
[addr
]);
809 if (!chip
->polling_mode
) {
810 snd_printk(KERN_WARNING SFX
"azx_get_response timeout, "
811 "switching to polling mode: last cmd=0x%08x\n",
812 chip
->last_cmd
[addr
]);
813 chip
->polling_mode
= 1;
818 snd_printk(KERN_WARNING SFX
"No response from codec, "
819 "disabling MSI: last cmd=0x%08x\n",
820 chip
->last_cmd
[addr
]);
821 free_irq(chip
->irq
, chip
);
823 pci_disable_msi(chip
->pci
);
825 if (azx_acquire_irq(chip
, 1) < 0) {
833 /* If this critical timeout happens during the codec probing
834 * phase, this is likely an access to a non-existing codec
835 * slot. Better to return an error and reset the system.
840 /* a fatal communication error; need either to reset or to fallback
841 * to the single_cmd mode
844 if (bus
->allow_bus_reset
&& !bus
->response_reset
&& !bus
->in_reset
) {
845 bus
->response_reset
= 1;
846 return -1; /* give a chance to retry */
849 snd_printk(KERN_ERR
"hda_intel: azx_get_response timeout, "
850 "switching to single_cmd mode: last cmd=0x%08x\n",
851 chip
->last_cmd
[addr
]);
852 chip
->single_cmd
= 1;
853 bus
->response_reset
= 0;
854 /* release CORB/RIRB */
855 azx_free_cmd_io(chip
);
856 /* disable unsolicited responses */
857 azx_writel(chip
, GCTL
, azx_readl(chip
, GCTL
) & ~ICH6_GCTL_UNSOL
);
862 * Use the single immediate command instead of CORB/RIRB for simplicity
864 * Note: according to Intel, this is not preferred use. The command was
865 * intended for the BIOS only, and may get confused with unsolicited
866 * responses. So, we shouldn't use it for normal operation from the
868 * I left the codes, however, for debugging/testing purposes.
871 /* receive a response */
872 static int azx_single_wait_for_response(struct azx
*chip
, unsigned int addr
)
877 /* check IRV busy bit */
878 if (azx_readw(chip
, IRS
) & ICH6_IRS_VALID
) {
879 /* reuse rirb.res as the response return value */
880 chip
->rirb
.res
[addr
] = azx_readl(chip
, IR
);
885 if (printk_ratelimit())
886 snd_printd(SFX
"get_response timeout: IRS=0x%x\n",
887 azx_readw(chip
, IRS
));
888 chip
->rirb
.res
[addr
] = -1;
893 static int azx_single_send_cmd(struct hda_bus
*bus
, u32 val
)
895 struct azx
*chip
= bus
->private_data
;
896 unsigned int addr
= azx_command_addr(val
);
901 /* check ICB busy bit */
902 if (!((azx_readw(chip
, IRS
) & ICH6_IRS_BUSY
))) {
903 /* Clear IRV valid bit */
904 azx_writew(chip
, IRS
, azx_readw(chip
, IRS
) |
906 azx_writel(chip
, IC
, val
);
907 azx_writew(chip
, IRS
, azx_readw(chip
, IRS
) |
909 return azx_single_wait_for_response(chip
, addr
);
913 if (printk_ratelimit())
914 snd_printd(SFX
"send_cmd timeout: IRS=0x%x, val=0x%x\n",
915 azx_readw(chip
, IRS
), val
);
919 /* receive a response */
920 static unsigned int azx_single_get_response(struct hda_bus
*bus
,
923 struct azx
*chip
= bus
->private_data
;
924 return chip
->rirb
.res
[addr
];
928 * The below are the main callbacks from hda_codec.
930 * They are just the skeleton to call sub-callbacks according to the
931 * current setting of chip->single_cmd.
935 static int azx_send_cmd(struct hda_bus
*bus
, unsigned int val
)
937 struct azx
*chip
= bus
->private_data
;
939 chip
->last_cmd
[azx_command_addr(val
)] = val
;
940 if (chip
->single_cmd
)
941 return azx_single_send_cmd(bus
, val
);
943 return azx_corb_send_cmd(bus
, val
);
947 static unsigned int azx_get_response(struct hda_bus
*bus
,
950 struct azx
*chip
= bus
->private_data
;
951 if (chip
->single_cmd
)
952 return azx_single_get_response(bus
, addr
);
954 return azx_rirb_get_response(bus
, addr
);
957 #ifdef CONFIG_SND_HDA_POWER_SAVE
958 static void azx_power_notify(struct hda_bus
*bus
);
961 /* reset codec link */
962 static int azx_reset(struct azx
*chip
, int full_reset
)
970 azx_writeb(chip
, STATESTS
, STATESTS_INT_MASK
);
972 /* reset controller */
973 azx_writel(chip
, GCTL
, azx_readl(chip
, GCTL
) & ~ICH6_GCTL_RESET
);
976 while (azx_readb(chip
, GCTL
) && --count
)
979 /* delay for >= 100us for codec PLL to settle per spec
980 * Rev 0.9 section 5.5.1
984 /* Bring controller out of reset */
985 azx_writeb(chip
, GCTL
, azx_readb(chip
, GCTL
) | ICH6_GCTL_RESET
);
988 while (!azx_readb(chip
, GCTL
) && --count
)
991 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
995 /* check to see if controller is ready */
996 if (!azx_readb(chip
, GCTL
)) {
997 snd_printd(SFX
"azx_reset: controller not ready!\n");
1001 /* Accept unsolicited responses */
1002 if (!chip
->single_cmd
)
1003 azx_writel(chip
, GCTL
, azx_readl(chip
, GCTL
) |
1007 if (!chip
->codec_mask
) {
1008 chip
->codec_mask
= azx_readw(chip
, STATESTS
);
1009 snd_printdd(SFX
"codec_mask = 0x%x\n", chip
->codec_mask
);
1017 * Lowlevel interface
1020 /* enable interrupts */
1021 static void azx_int_enable(struct azx
*chip
)
1023 /* enable controller CIE and GIE */
1024 azx_writel(chip
, INTCTL
, azx_readl(chip
, INTCTL
) |
1025 ICH6_INT_CTRL_EN
| ICH6_INT_GLOBAL_EN
);
1028 /* disable interrupts */
1029 static void azx_int_disable(struct azx
*chip
)
1033 /* disable interrupts in stream descriptor */
1034 for (i
= 0; i
< chip
->num_streams
; i
++) {
1035 struct azx_dev
*azx_dev
= &chip
->azx_dev
[i
];
1036 azx_sd_writeb(azx_dev
, SD_CTL
,
1037 azx_sd_readb(azx_dev
, SD_CTL
) & ~SD_INT_MASK
);
1040 /* disable SIE for all streams */
1041 azx_writeb(chip
, INTCTL
, 0);
1043 /* disable controller CIE and GIE */
1044 azx_writel(chip
, INTCTL
, azx_readl(chip
, INTCTL
) &
1045 ~(ICH6_INT_CTRL_EN
| ICH6_INT_GLOBAL_EN
));
1048 /* clear interrupts */
1049 static void azx_int_clear(struct azx
*chip
)
1053 /* clear stream status */
1054 for (i
= 0; i
< chip
->num_streams
; i
++) {
1055 struct azx_dev
*azx_dev
= &chip
->azx_dev
[i
];
1056 azx_sd_writeb(azx_dev
, SD_STS
, SD_INT_MASK
);
1059 /* clear STATESTS */
1060 azx_writeb(chip
, STATESTS
, STATESTS_INT_MASK
);
1062 /* clear rirb status */
1063 azx_writeb(chip
, RIRBSTS
, RIRB_INT_MASK
);
1065 /* clear int status */
1066 azx_writel(chip
, INTSTS
, ICH6_INT_CTRL_EN
| ICH6_INT_ALL_STREAM
);
1069 /* start a stream */
1070 static void azx_stream_start(struct azx
*chip
, struct azx_dev
*azx_dev
)
1073 * Before stream start, initialize parameter
1075 azx_dev
->insufficient
= 1;
1078 azx_writel(chip
, INTCTL
,
1079 azx_readl(chip
, INTCTL
) | (1 << azx_dev
->index
));
1080 /* set DMA start and interrupt mask */
1081 azx_sd_writeb(azx_dev
, SD_CTL
, azx_sd_readb(azx_dev
, SD_CTL
) |
1082 SD_CTL_DMA_START
| SD_INT_MASK
);
1086 static void azx_stream_clear(struct azx
*chip
, struct azx_dev
*azx_dev
)
1088 azx_sd_writeb(azx_dev
, SD_CTL
, azx_sd_readb(azx_dev
, SD_CTL
) &
1089 ~(SD_CTL_DMA_START
| SD_INT_MASK
));
1090 azx_sd_writeb(azx_dev
, SD_STS
, SD_INT_MASK
); /* to be sure */
1094 static void azx_stream_stop(struct azx
*chip
, struct azx_dev
*azx_dev
)
1096 azx_stream_clear(chip
, azx_dev
);
1098 azx_writel(chip
, INTCTL
,
1099 azx_readl(chip
, INTCTL
) & ~(1 << azx_dev
->index
));
1104 * reset and start the controller registers
1106 static void azx_init_chip(struct azx
*chip
, int full_reset
)
1108 if (chip
->initialized
)
1111 /* reset controller */
1112 azx_reset(chip
, full_reset
);
1114 /* initialize interrupts */
1115 azx_int_clear(chip
);
1116 azx_int_enable(chip
);
1118 /* initialize the codec command I/O */
1119 if (!chip
->single_cmd
)
1120 azx_init_cmd_io(chip
);
1122 /* program the position buffer */
1123 azx_writel(chip
, DPLBASE
, (u32
)chip
->posbuf
.addr
);
1124 azx_writel(chip
, DPUBASE
, upper_32_bits(chip
->posbuf
.addr
));
1126 chip
->initialized
= 1;
1130 * initialize the PCI registers
1132 /* update bits in a PCI register byte */
1133 static void update_pci_byte(struct pci_dev
*pci
, unsigned int reg
,
1134 unsigned char mask
, unsigned char val
)
1138 pci_read_config_byte(pci
, reg
, &data
);
1140 data
|= (val
& mask
);
1141 pci_write_config_byte(pci
, reg
, data
);
1144 static void azx_init_pci(struct azx
*chip
)
1146 /* force to non-snoop mode for a new VIA controller when BIOS is set */
1147 if (chip
->snoop
&& chip
->driver_type
== AZX_DRIVER_VIA
) {
1149 pci_read_config_byte(chip
->pci
, 0x42, &snoop
);
1150 if (!(snoop
& 0x80) && chip
->pci
->revision
== 0x30) {
1152 snd_printdd(SFX
"Force to non-snoop mode\n");
1156 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
1157 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
1158 * Ensuring these bits are 0 clears playback static on some HD Audio
1160 * The PCI register TCSEL is defined in the Intel manuals.
1162 if (!(chip
->driver_caps
& AZX_DCAPS_NO_TCSEL
)) {
1163 snd_printdd(SFX
"Clearing TCSEL\n");
1164 update_pci_byte(chip
->pci
, ICH6_PCIREG_TCSEL
, 0x07, 0);
1167 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
1168 * we need to enable snoop.
1170 if (chip
->driver_caps
& AZX_DCAPS_ATI_SNOOP
) {
1171 snd_printdd(SFX
"Setting ATI snoop: %d\n", azx_snoop(chip
));
1172 update_pci_byte(chip
->pci
,
1173 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR
, 0x07,
1174 azx_snoop(chip
) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP
: 0);
1177 /* For NVIDIA HDA, enable snoop */
1178 if (chip
->driver_caps
& AZX_DCAPS_NVIDIA_SNOOP
) {
1179 snd_printdd(SFX
"Setting Nvidia snoop: %d\n", azx_snoop(chip
));
1180 update_pci_byte(chip
->pci
,
1181 NVIDIA_HDA_TRANSREG_ADDR
,
1182 0x0f, NVIDIA_HDA_ENABLE_COHBITS
);
1183 update_pci_byte(chip
->pci
,
1184 NVIDIA_HDA_ISTRM_COH
,
1185 0x01, NVIDIA_HDA_ENABLE_COHBIT
);
1186 update_pci_byte(chip
->pci
,
1187 NVIDIA_HDA_OSTRM_COH
,
1188 0x01, NVIDIA_HDA_ENABLE_COHBIT
);
1191 /* Enable SCH/PCH snoop if needed */
1192 if (chip
->driver_caps
& AZX_DCAPS_SCH_SNOOP
) {
1193 unsigned short snoop
;
1194 pci_read_config_word(chip
->pci
, INTEL_SCH_HDA_DEVC
, &snoop
);
1195 if ((!azx_snoop(chip
) && !(snoop
& INTEL_SCH_HDA_DEVC_NOSNOOP
)) ||
1196 (azx_snoop(chip
) && (snoop
& INTEL_SCH_HDA_DEVC_NOSNOOP
))) {
1197 snoop
&= ~INTEL_SCH_HDA_DEVC_NOSNOOP
;
1198 if (!azx_snoop(chip
))
1199 snoop
|= INTEL_SCH_HDA_DEVC_NOSNOOP
;
1200 pci_write_config_word(chip
->pci
, INTEL_SCH_HDA_DEVC
, snoop
);
1201 pci_read_config_word(chip
->pci
,
1202 INTEL_SCH_HDA_DEVC
, &snoop
);
1204 snd_printdd(SFX
"SCH snoop: %s\n",
1205 (snoop
& INTEL_SCH_HDA_DEVC_NOSNOOP
)
1206 ? "Disabled" : "Enabled");
1211 static int azx_position_ok(struct azx
*chip
, struct azx_dev
*azx_dev
);
1216 static irqreturn_t
azx_interrupt(int irq
, void *dev_id
)
1218 struct azx
*chip
= dev_id
;
1219 struct azx_dev
*azx_dev
;
1224 spin_lock(&chip
->reg_lock
);
1226 status
= azx_readl(chip
, INTSTS
);
1228 spin_unlock(&chip
->reg_lock
);
1232 for (i
= 0; i
< chip
->num_streams
; i
++) {
1233 azx_dev
= &chip
->azx_dev
[i
];
1234 if (status
& azx_dev
->sd_int_sta_mask
) {
1235 sd_status
= azx_sd_readb(azx_dev
, SD_STS
);
1236 azx_sd_writeb(azx_dev
, SD_STS
, SD_INT_MASK
);
1237 if (!azx_dev
->substream
|| !azx_dev
->running
||
1238 !(sd_status
& SD_INT_COMPLETE
))
1240 /* check whether this IRQ is really acceptable */
1241 ok
= azx_position_ok(chip
, azx_dev
);
1243 azx_dev
->irq_pending
= 0;
1244 spin_unlock(&chip
->reg_lock
);
1245 snd_pcm_period_elapsed(azx_dev
->substream
);
1246 spin_lock(&chip
->reg_lock
);
1247 } else if (ok
== 0 && chip
->bus
&& chip
->bus
->workq
) {
1248 /* bogus IRQ, process it later */
1249 azx_dev
->irq_pending
= 1;
1250 queue_work(chip
->bus
->workq
,
1251 &chip
->irq_pending_work
);
1256 /* clear rirb int */
1257 status
= azx_readb(chip
, RIRBSTS
);
1258 if (status
& RIRB_INT_MASK
) {
1259 if (status
& RIRB_INT_RESPONSE
) {
1260 if (chip
->driver_caps
& AZX_DCAPS_RIRB_PRE_DELAY
)
1262 azx_update_rirb(chip
);
1264 azx_writeb(chip
, RIRBSTS
, RIRB_INT_MASK
);
1268 /* clear state status int */
1269 if (azx_readb(chip
, STATESTS
) & 0x04)
1270 azx_writeb(chip
, STATESTS
, 0x04);
1272 spin_unlock(&chip
->reg_lock
);
1279 * set up a BDL entry
1281 static int setup_bdle(struct snd_pcm_substream
*substream
,
1282 struct azx_dev
*azx_dev
, u32
**bdlp
,
1283 int ofs
, int size
, int with_ioc
)
1291 if (azx_dev
->frags
>= AZX_MAX_BDL_ENTRIES
)
1294 addr
= snd_pcm_sgbuf_get_addr(substream
, ofs
);
1295 /* program the address field of the BDL entry */
1296 bdl
[0] = cpu_to_le32((u32
)addr
);
1297 bdl
[1] = cpu_to_le32(upper_32_bits(addr
));
1298 /* program the size field of the BDL entry */
1299 chunk
= snd_pcm_sgbuf_get_chunk_size(substream
, ofs
, size
);
1300 bdl
[2] = cpu_to_le32(chunk
);
1301 /* program the IOC to enable interrupt
1302 * only when the whole fragment is processed
1305 bdl
[3] = (size
|| !with_ioc
) ? 0 : cpu_to_le32(0x01);
1315 * set up BDL entries
1317 static int azx_setup_periods(struct azx
*chip
,
1318 struct snd_pcm_substream
*substream
,
1319 struct azx_dev
*azx_dev
)
1322 int i
, ofs
, periods
, period_bytes
;
1325 /* reset BDL address */
1326 azx_sd_writel(azx_dev
, SD_BDLPL
, 0);
1327 azx_sd_writel(azx_dev
, SD_BDLPU
, 0);
1329 period_bytes
= azx_dev
->period_bytes
;
1330 periods
= azx_dev
->bufsize
/ period_bytes
;
1332 /* program the initial BDL entries */
1333 bdl
= (u32
*)azx_dev
->bdl
.area
;
1336 pos_adj
= bdl_pos_adj
[chip
->dev_index
];
1338 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
1339 int pos_align
= pos_adj
;
1340 pos_adj
= (pos_adj
* runtime
->rate
+ 47999) / 48000;
1342 pos_adj
= pos_align
;
1344 pos_adj
= ((pos_adj
+ pos_align
- 1) / pos_align
) *
1346 pos_adj
= frames_to_bytes(runtime
, pos_adj
);
1347 if (pos_adj
>= period_bytes
) {
1348 snd_printk(KERN_WARNING SFX
"Too big adjustment %d\n",
1349 bdl_pos_adj
[chip
->dev_index
]);
1352 ofs
= setup_bdle(substream
, azx_dev
,
1354 !substream
->runtime
->no_period_wakeup
);
1360 for (i
= 0; i
< periods
; i
++) {
1361 if (i
== periods
- 1 && pos_adj
)
1362 ofs
= setup_bdle(substream
, azx_dev
, &bdl
, ofs
,
1363 period_bytes
- pos_adj
, 0);
1365 ofs
= setup_bdle(substream
, azx_dev
, &bdl
, ofs
,
1367 !substream
->runtime
->no_period_wakeup
);
1374 snd_printk(KERN_ERR SFX
"Too many BDL entries: buffer=%d, period=%d\n",
1375 azx_dev
->bufsize
, period_bytes
);
1380 static void azx_stream_reset(struct azx
*chip
, struct azx_dev
*azx_dev
)
1385 azx_stream_clear(chip
, azx_dev
);
1387 azx_sd_writeb(azx_dev
, SD_CTL
, azx_sd_readb(azx_dev
, SD_CTL
) |
1388 SD_CTL_STREAM_RESET
);
1391 while (!((val
= azx_sd_readb(azx_dev
, SD_CTL
)) & SD_CTL_STREAM_RESET
) &&
1394 val
&= ~SD_CTL_STREAM_RESET
;
1395 azx_sd_writeb(azx_dev
, SD_CTL
, val
);
1399 /* waiting for hardware to report that the stream is out of reset */
1400 while (((val
= azx_sd_readb(azx_dev
, SD_CTL
)) & SD_CTL_STREAM_RESET
) &&
1404 /* reset first position - may not be synced with hw at this time */
1405 *azx_dev
->posbuf
= 0;
1409 * set up the SD for streaming
1411 static int azx_setup_controller(struct azx
*chip
, struct azx_dev
*azx_dev
)
1414 /* make sure the run bit is zero for SD */
1415 azx_stream_clear(chip
, azx_dev
);
1416 /* program the stream_tag */
1417 val
= azx_sd_readl(azx_dev
, SD_CTL
);
1418 val
= (val
& ~SD_CTL_STREAM_TAG_MASK
) |
1419 (azx_dev
->stream_tag
<< SD_CTL_STREAM_TAG_SHIFT
);
1420 if (!azx_snoop(chip
))
1421 val
|= SD_CTL_TRAFFIC_PRIO
;
1422 azx_sd_writel(azx_dev
, SD_CTL
, val
);
1424 /* program the length of samples in cyclic buffer */
1425 azx_sd_writel(azx_dev
, SD_CBL
, azx_dev
->bufsize
);
1427 /* program the stream format */
1428 /* this value needs to be the same as the one programmed */
1429 azx_sd_writew(azx_dev
, SD_FORMAT
, azx_dev
->format_val
);
1431 /* program the stream LVI (last valid index) of the BDL */
1432 azx_sd_writew(azx_dev
, SD_LVI
, azx_dev
->frags
- 1);
1434 /* program the BDL address */
1435 /* lower BDL address */
1436 azx_sd_writel(azx_dev
, SD_BDLPL
, (u32
)azx_dev
->bdl
.addr
);
1437 /* upper BDL address */
1438 azx_sd_writel(azx_dev
, SD_BDLPU
, upper_32_bits(azx_dev
->bdl
.addr
));
1440 /* enable the position buffer */
1441 if (chip
->position_fix
[0] != POS_FIX_LPIB
||
1442 chip
->position_fix
[1] != POS_FIX_LPIB
) {
1443 if (!(azx_readl(chip
, DPLBASE
) & ICH6_DPLBASE_ENABLE
))
1444 azx_writel(chip
, DPLBASE
,
1445 (u32
)chip
->posbuf
.addr
| ICH6_DPLBASE_ENABLE
);
1448 /* set the interrupt enable bits in the descriptor control register */
1449 azx_sd_writel(azx_dev
, SD_CTL
,
1450 azx_sd_readl(azx_dev
, SD_CTL
) | SD_INT_MASK
);
1456 * Probe the given codec address
1458 static int probe_codec(struct azx
*chip
, int addr
)
1460 unsigned int cmd
= (addr
<< 28) | (AC_NODE_ROOT
<< 20) |
1461 (AC_VERB_PARAMETERS
<< 8) | AC_PAR_VENDOR_ID
;
1464 mutex_lock(&chip
->bus
->cmd_mutex
);
1466 azx_send_cmd(chip
->bus
, cmd
);
1467 res
= azx_get_response(chip
->bus
, addr
);
1469 mutex_unlock(&chip
->bus
->cmd_mutex
);
1472 snd_printdd(SFX
"codec #%d probed OK\n", addr
);
1476 static int azx_attach_pcm_stream(struct hda_bus
*bus
, struct hda_codec
*codec
,
1477 struct hda_pcm
*cpcm
);
1478 static void azx_stop_chip(struct azx
*chip
);
1480 static void azx_bus_reset(struct hda_bus
*bus
)
1482 struct azx
*chip
= bus
->private_data
;
1485 azx_stop_chip(chip
);
1486 azx_init_chip(chip
, 1);
1488 if (chip
->initialized
) {
1491 for (i
= 0; i
< HDA_MAX_PCMS
; i
++)
1492 snd_pcm_suspend_all(chip
->pcm
[i
]);
1493 snd_hda_suspend(chip
->bus
);
1494 snd_hda_resume(chip
->bus
);
1501 * Codec initialization
1504 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1505 static unsigned int azx_max_codecs
[AZX_NUM_DRIVERS
] __devinitdata
= {
1506 [AZX_DRIVER_NVIDIA
] = 8,
1507 [AZX_DRIVER_TERA
] = 1,
1510 static int __devinit
azx_codec_create(struct azx
*chip
, const char *model
)
1512 struct hda_bus_template bus_temp
;
1516 memset(&bus_temp
, 0, sizeof(bus_temp
));
1517 bus_temp
.private_data
= chip
;
1518 bus_temp
.modelname
= model
;
1519 bus_temp
.pci
= chip
->pci
;
1520 bus_temp
.ops
.command
= azx_send_cmd
;
1521 bus_temp
.ops
.get_response
= azx_get_response
;
1522 bus_temp
.ops
.attach_pcm
= azx_attach_pcm_stream
;
1523 bus_temp
.ops
.bus_reset
= azx_bus_reset
;
1524 #ifdef CONFIG_SND_HDA_POWER_SAVE
1525 bus_temp
.power_save
= &power_save
;
1526 bus_temp
.ops
.pm_notify
= azx_power_notify
;
1529 err
= snd_hda_bus_new(chip
->card
, &bus_temp
, &chip
->bus
);
1533 if (chip
->driver_caps
& AZX_DCAPS_RIRB_DELAY
) {
1534 snd_printd(SFX
"Enable delay in RIRB handling\n");
1535 chip
->bus
->needs_damn_long_delay
= 1;
1539 max_slots
= azx_max_codecs
[chip
->driver_type
];
1541 max_slots
= AZX_DEFAULT_CODECS
;
1543 /* First try to probe all given codec slots */
1544 for (c
= 0; c
< max_slots
; c
++) {
1545 if ((chip
->codec_mask
& (1 << c
)) & chip
->codec_probe_mask
) {
1546 if (probe_codec(chip
, c
) < 0) {
1547 /* Some BIOSen give you wrong codec addresses
1550 snd_printk(KERN_WARNING SFX
1551 "Codec #%d probe error; "
1552 "disabling it...\n", c
);
1553 chip
->codec_mask
&= ~(1 << c
);
1554 /* More badly, accessing to a non-existing
1555 * codec often screws up the controller chip,
1556 * and disturbs the further communications.
1557 * Thus if an error occurs during probing,
1558 * better to reset the controller chip to
1559 * get back to the sanity state.
1561 azx_stop_chip(chip
);
1562 azx_init_chip(chip
, 1);
1567 /* AMD chipsets often cause the communication stalls upon certain
1568 * sequence like the pin-detection. It seems that forcing the synced
1569 * access works around the stall. Grrr...
1571 if (chip
->driver_caps
& AZX_DCAPS_SYNC_WRITE
) {
1572 snd_printd(SFX
"Enable sync_write for stable communication\n");
1573 chip
->bus
->sync_write
= 1;
1574 chip
->bus
->allow_bus_reset
= 1;
1577 /* Then create codec instances */
1578 for (c
= 0; c
< max_slots
; c
++) {
1579 if ((chip
->codec_mask
& (1 << c
)) & chip
->codec_probe_mask
) {
1580 struct hda_codec
*codec
;
1581 err
= snd_hda_codec_new(chip
->bus
, c
, &codec
);
1584 codec
->beep_mode
= chip
->beep_mode
;
1589 snd_printk(KERN_ERR SFX
"no codecs initialized\n");
1595 /* configure each codec instance */
1596 static int __devinit
azx_codec_configure(struct azx
*chip
)
1598 struct hda_codec
*codec
;
1599 list_for_each_entry(codec
, &chip
->bus
->codec_list
, list
) {
1600 snd_hda_codec_configure(codec
);
1610 /* assign a stream for the PCM */
1611 static inline struct azx_dev
*
1612 azx_assign_device(struct azx
*chip
, struct snd_pcm_substream
*substream
)
1615 struct azx_dev
*res
= NULL
;
1616 /* make a non-zero unique key for the substream */
1617 int key
= (substream
->pcm
->device
<< 16) | (substream
->number
<< 2) |
1618 (substream
->stream
+ 1);
1620 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
) {
1621 dev
= chip
->playback_index_offset
;
1622 nums
= chip
->playback_streams
;
1624 dev
= chip
->capture_index_offset
;
1625 nums
= chip
->capture_streams
;
1627 for (i
= 0; i
< nums
; i
++, dev
++)
1628 if (!chip
->azx_dev
[dev
].opened
) {
1629 res
= &chip
->azx_dev
[dev
];
1630 if (res
->assigned_key
== key
)
1635 res
->assigned_key
= key
;
1640 /* release the assigned stream */
1641 static inline void azx_release_device(struct azx_dev
*azx_dev
)
1643 azx_dev
->opened
= 0;
1646 static struct snd_pcm_hardware azx_pcm_hw
= {
1647 .info
= (SNDRV_PCM_INFO_MMAP
|
1648 SNDRV_PCM_INFO_INTERLEAVED
|
1649 SNDRV_PCM_INFO_BLOCK_TRANSFER
|
1650 SNDRV_PCM_INFO_MMAP_VALID
|
1651 /* No full-resume yet implemented */
1652 /* SNDRV_PCM_INFO_RESUME |*/
1653 SNDRV_PCM_INFO_PAUSE
|
1654 SNDRV_PCM_INFO_SYNC_START
|
1655 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP
),
1656 .formats
= SNDRV_PCM_FMTBIT_S16_LE
,
1657 .rates
= SNDRV_PCM_RATE_48000
,
1662 .buffer_bytes_max
= AZX_MAX_BUF_SIZE
,
1663 .period_bytes_min
= 128,
1664 .period_bytes_max
= AZX_MAX_BUF_SIZE
/ 2,
1666 .periods_max
= AZX_MAX_FRAG
,
1672 struct hda_codec
*codec
;
1673 struct hda_pcm_stream
*hinfo
[2];
1676 static int azx_pcm_open(struct snd_pcm_substream
*substream
)
1678 struct azx_pcm
*apcm
= snd_pcm_substream_chip(substream
);
1679 struct hda_pcm_stream
*hinfo
= apcm
->hinfo
[substream
->stream
];
1680 struct azx
*chip
= apcm
->chip
;
1681 struct azx_dev
*azx_dev
;
1682 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
1683 unsigned long flags
;
1687 mutex_lock(&chip
->open_mutex
);
1688 azx_dev
= azx_assign_device(chip
, substream
);
1689 if (azx_dev
== NULL
) {
1690 mutex_unlock(&chip
->open_mutex
);
1693 runtime
->hw
= azx_pcm_hw
;
1694 runtime
->hw
.channels_min
= hinfo
->channels_min
;
1695 runtime
->hw
.channels_max
= hinfo
->channels_max
;
1696 runtime
->hw
.formats
= hinfo
->formats
;
1697 runtime
->hw
.rates
= hinfo
->rates
;
1698 snd_pcm_limit_hw_rates(runtime
);
1699 snd_pcm_hw_constraint_integer(runtime
, SNDRV_PCM_HW_PARAM_PERIODS
);
1700 if (align_buffer_size
)
1701 /* constrain buffer sizes to be multiple of 128
1702 bytes. This is more efficient in terms of memory
1703 access but isn't required by the HDA spec and
1704 prevents users from specifying exact period/buffer
1705 sizes. For example for 44.1kHz, a period size set
1706 to 20ms will be rounded to 19.59ms. */
1709 /* Don't enforce steps on buffer sizes, still need to
1710 be multiple of 4 bytes (HDA spec). Tested on Intel
1711 HDA controllers, may not work on all devices where
1712 option needs to be disabled */
1715 snd_pcm_hw_constraint_step(runtime
, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES
,
1717 snd_pcm_hw_constraint_step(runtime
, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES
,
1719 snd_hda_power_up(apcm
->codec
);
1720 err
= hinfo
->ops
.open(hinfo
, apcm
->codec
, substream
);
1722 azx_release_device(azx_dev
);
1723 snd_hda_power_down(apcm
->codec
);
1724 mutex_unlock(&chip
->open_mutex
);
1727 snd_pcm_limit_hw_rates(runtime
);
1729 if (snd_BUG_ON(!runtime
->hw
.channels_min
) ||
1730 snd_BUG_ON(!runtime
->hw
.channels_max
) ||
1731 snd_BUG_ON(!runtime
->hw
.formats
) ||
1732 snd_BUG_ON(!runtime
->hw
.rates
)) {
1733 azx_release_device(azx_dev
);
1734 hinfo
->ops
.close(hinfo
, apcm
->codec
, substream
);
1735 snd_hda_power_down(apcm
->codec
);
1736 mutex_unlock(&chip
->open_mutex
);
1739 spin_lock_irqsave(&chip
->reg_lock
, flags
);
1740 azx_dev
->substream
= substream
;
1741 azx_dev
->running
= 0;
1742 spin_unlock_irqrestore(&chip
->reg_lock
, flags
);
1744 runtime
->private_data
= azx_dev
;
1745 snd_pcm_set_sync(substream
);
1746 mutex_unlock(&chip
->open_mutex
);
1750 static int azx_pcm_close(struct snd_pcm_substream
*substream
)
1752 struct azx_pcm
*apcm
= snd_pcm_substream_chip(substream
);
1753 struct hda_pcm_stream
*hinfo
= apcm
->hinfo
[substream
->stream
];
1754 struct azx
*chip
= apcm
->chip
;
1755 struct azx_dev
*azx_dev
= get_azx_dev(substream
);
1756 unsigned long flags
;
1758 mutex_lock(&chip
->open_mutex
);
1759 spin_lock_irqsave(&chip
->reg_lock
, flags
);
1760 azx_dev
->substream
= NULL
;
1761 azx_dev
->running
= 0;
1762 spin_unlock_irqrestore(&chip
->reg_lock
, flags
);
1763 azx_release_device(azx_dev
);
1764 hinfo
->ops
.close(hinfo
, apcm
->codec
, substream
);
1765 snd_hda_power_down(apcm
->codec
);
1766 mutex_unlock(&chip
->open_mutex
);
1770 static int azx_pcm_hw_params(struct snd_pcm_substream
*substream
,
1771 struct snd_pcm_hw_params
*hw_params
)
1773 struct azx_pcm
*apcm
= snd_pcm_substream_chip(substream
);
1774 struct azx
*chip
= apcm
->chip
;
1775 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
1776 struct azx_dev
*azx_dev
= get_azx_dev(substream
);
1779 mark_runtime_wc(chip
, azx_dev
, runtime
, false);
1780 azx_dev
->bufsize
= 0;
1781 azx_dev
->period_bytes
= 0;
1782 azx_dev
->format_val
= 0;
1783 ret
= snd_pcm_lib_malloc_pages(substream
,
1784 params_buffer_bytes(hw_params
));
1787 mark_runtime_wc(chip
, azx_dev
, runtime
, true);
1791 static int azx_pcm_hw_free(struct snd_pcm_substream
*substream
)
1793 struct azx_pcm
*apcm
= snd_pcm_substream_chip(substream
);
1794 struct azx_dev
*azx_dev
= get_azx_dev(substream
);
1795 struct azx
*chip
= apcm
->chip
;
1796 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
1797 struct hda_pcm_stream
*hinfo
= apcm
->hinfo
[substream
->stream
];
1799 /* reset BDL address */
1800 azx_sd_writel(azx_dev
, SD_BDLPL
, 0);
1801 azx_sd_writel(azx_dev
, SD_BDLPU
, 0);
1802 azx_sd_writel(azx_dev
, SD_CTL
, 0);
1803 azx_dev
->bufsize
= 0;
1804 azx_dev
->period_bytes
= 0;
1805 azx_dev
->format_val
= 0;
1807 snd_hda_codec_cleanup(apcm
->codec
, hinfo
, substream
);
1809 mark_runtime_wc(chip
, azx_dev
, runtime
, false);
1810 return snd_pcm_lib_free_pages(substream
);
1813 static int azx_pcm_prepare(struct snd_pcm_substream
*substream
)
1815 struct azx_pcm
*apcm
= snd_pcm_substream_chip(substream
);
1816 struct azx
*chip
= apcm
->chip
;
1817 struct azx_dev
*azx_dev
= get_azx_dev(substream
);
1818 struct hda_pcm_stream
*hinfo
= apcm
->hinfo
[substream
->stream
];
1819 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
1820 unsigned int bufsize
, period_bytes
, format_val
, stream_tag
;
1822 struct hda_spdif_out
*spdif
=
1823 snd_hda_spdif_out_of_nid(apcm
->codec
, hinfo
->nid
);
1824 unsigned short ctls
= spdif
? spdif
->ctls
: 0;
1826 azx_stream_reset(chip
, azx_dev
);
1827 format_val
= snd_hda_calc_stream_format(runtime
->rate
,
1833 snd_printk(KERN_ERR SFX
1834 "invalid format_val, rate=%d, ch=%d, format=%d\n",
1835 runtime
->rate
, runtime
->channels
, runtime
->format
);
1839 bufsize
= snd_pcm_lib_buffer_bytes(substream
);
1840 period_bytes
= snd_pcm_lib_period_bytes(substream
);
1842 snd_printdd(SFX
"azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
1843 bufsize
, format_val
);
1845 if (bufsize
!= azx_dev
->bufsize
||
1846 period_bytes
!= azx_dev
->period_bytes
||
1847 format_val
!= azx_dev
->format_val
) {
1848 azx_dev
->bufsize
= bufsize
;
1849 azx_dev
->period_bytes
= period_bytes
;
1850 azx_dev
->format_val
= format_val
;
1851 err
= azx_setup_periods(chip
, substream
, azx_dev
);
1856 /* wallclk has 24Mhz clock source */
1857 azx_dev
->period_wallclk
= (((runtime
->period_size
* 24000) /
1858 runtime
->rate
) * 1000);
1859 azx_setup_controller(chip
, azx_dev
);
1860 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
)
1861 azx_dev
->fifo_size
= azx_sd_readw(azx_dev
, SD_FIFOSIZE
) + 1;
1863 azx_dev
->fifo_size
= 0;
1865 stream_tag
= azx_dev
->stream_tag
;
1866 /* CA-IBG chips need the playback stream starting from 1 */
1867 if ((chip
->driver_caps
& AZX_DCAPS_CTX_WORKAROUND
) &&
1868 stream_tag
> chip
->capture_streams
)
1869 stream_tag
-= chip
->capture_streams
;
1870 return snd_hda_codec_prepare(apcm
->codec
, hinfo
, stream_tag
,
1871 azx_dev
->format_val
, substream
);
1874 static int azx_pcm_trigger(struct snd_pcm_substream
*substream
, int cmd
)
1876 struct azx_pcm
*apcm
= snd_pcm_substream_chip(substream
);
1877 struct azx
*chip
= apcm
->chip
;
1878 struct azx_dev
*azx_dev
;
1879 struct snd_pcm_substream
*s
;
1880 int rstart
= 0, start
, nsync
= 0, sbits
= 0;
1884 case SNDRV_PCM_TRIGGER_START
:
1886 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE
:
1887 case SNDRV_PCM_TRIGGER_RESUME
:
1890 case SNDRV_PCM_TRIGGER_PAUSE_PUSH
:
1891 case SNDRV_PCM_TRIGGER_SUSPEND
:
1892 case SNDRV_PCM_TRIGGER_STOP
:
1899 snd_pcm_group_for_each_entry(s
, substream
) {
1900 if (s
->pcm
->card
!= substream
->pcm
->card
)
1902 azx_dev
= get_azx_dev(s
);
1903 sbits
|= 1 << azx_dev
->index
;
1905 snd_pcm_trigger_done(s
, substream
);
1908 spin_lock(&chip
->reg_lock
);
1910 /* first, set SYNC bits of corresponding streams */
1911 if (chip
->driver_caps
& AZX_DCAPS_OLD_SSYNC
)
1912 azx_writel(chip
, OLD_SSYNC
,
1913 azx_readl(chip
, OLD_SSYNC
) | sbits
);
1915 azx_writel(chip
, SSYNC
, azx_readl(chip
, SSYNC
) | sbits
);
1917 snd_pcm_group_for_each_entry(s
, substream
) {
1918 if (s
->pcm
->card
!= substream
->pcm
->card
)
1920 azx_dev
= get_azx_dev(s
);
1922 azx_dev
->start_wallclk
= azx_readl(chip
, WALLCLK
);
1924 azx_dev
->start_wallclk
-=
1925 azx_dev
->period_wallclk
;
1926 azx_stream_start(chip
, azx_dev
);
1928 azx_stream_stop(chip
, azx_dev
);
1930 azx_dev
->running
= start
;
1932 spin_unlock(&chip
->reg_lock
);
1936 /* wait until all FIFOs get ready */
1937 for (timeout
= 5000; timeout
; timeout
--) {
1939 snd_pcm_group_for_each_entry(s
, substream
) {
1940 if (s
->pcm
->card
!= substream
->pcm
->card
)
1942 azx_dev
= get_azx_dev(s
);
1943 if (!(azx_sd_readb(azx_dev
, SD_STS
) &
1952 /* wait until all RUN bits are cleared */
1953 for (timeout
= 5000; timeout
; timeout
--) {
1955 snd_pcm_group_for_each_entry(s
, substream
) {
1956 if (s
->pcm
->card
!= substream
->pcm
->card
)
1958 azx_dev
= get_azx_dev(s
);
1959 if (azx_sd_readb(azx_dev
, SD_CTL
) &
1969 spin_lock(&chip
->reg_lock
);
1970 /* reset SYNC bits */
1971 if (chip
->driver_caps
& AZX_DCAPS_OLD_SSYNC
)
1972 azx_writel(chip
, OLD_SSYNC
,
1973 azx_readl(chip
, OLD_SSYNC
) & ~sbits
);
1975 azx_writel(chip
, SSYNC
, azx_readl(chip
, SSYNC
) & ~sbits
);
1976 spin_unlock(&chip
->reg_lock
);
1981 /* get the current DMA position with correction on VIA chips */
1982 static unsigned int azx_via_get_position(struct azx
*chip
,
1983 struct azx_dev
*azx_dev
)
1985 unsigned int link_pos
, mini_pos
, bound_pos
;
1986 unsigned int mod_link_pos
, mod_dma_pos
, mod_mini_pos
;
1987 unsigned int fifo_size
;
1989 link_pos
= azx_sd_readl(azx_dev
, SD_LPIB
);
1990 if (azx_dev
->substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
) {
1991 /* Playback, no problem using link position */
1997 * use mod to get the DMA position just like old chipset
1999 mod_dma_pos
= le32_to_cpu(*azx_dev
->posbuf
);
2000 mod_dma_pos
%= azx_dev
->period_bytes
;
2002 /* azx_dev->fifo_size can't get FIFO size of in stream.
2003 * Get from base address + offset.
2005 fifo_size
= readw(chip
->remap_addr
+ VIA_IN_STREAM0_FIFO_SIZE_OFFSET
);
2007 if (azx_dev
->insufficient
) {
2008 /* Link position never gather than FIFO size */
2009 if (link_pos
<= fifo_size
)
2012 azx_dev
->insufficient
= 0;
2015 if (link_pos
<= fifo_size
)
2016 mini_pos
= azx_dev
->bufsize
+ link_pos
- fifo_size
;
2018 mini_pos
= link_pos
- fifo_size
;
2020 /* Find nearest previous boudary */
2021 mod_mini_pos
= mini_pos
% azx_dev
->period_bytes
;
2022 mod_link_pos
= link_pos
% azx_dev
->period_bytes
;
2023 if (mod_link_pos
>= fifo_size
)
2024 bound_pos
= link_pos
- mod_link_pos
;
2025 else if (mod_dma_pos
>= mod_mini_pos
)
2026 bound_pos
= mini_pos
- mod_mini_pos
;
2028 bound_pos
= mini_pos
- mod_mini_pos
+ azx_dev
->period_bytes
;
2029 if (bound_pos
>= azx_dev
->bufsize
)
2033 /* Calculate real DMA position we want */
2034 return bound_pos
+ mod_dma_pos
;
2037 static unsigned int azx_get_position(struct azx
*chip
,
2038 struct azx_dev
*azx_dev
,
2042 int stream
= azx_dev
->substream
->stream
;
2044 switch (chip
->position_fix
[stream
]) {
2047 pos
= azx_sd_readl(azx_dev
, SD_LPIB
);
2049 case POS_FIX_VIACOMBO
:
2050 pos
= azx_via_get_position(chip
, azx_dev
);
2053 /* use the position buffer */
2054 pos
= le32_to_cpu(*azx_dev
->posbuf
);
2055 if (with_check
&& chip
->position_fix
[stream
] == POS_FIX_AUTO
) {
2056 if (!pos
|| pos
== (u32
)-1) {
2058 "hda-intel: Invalid position buffer, "
2059 "using LPIB read method instead.\n");
2060 chip
->position_fix
[stream
] = POS_FIX_LPIB
;
2061 pos
= azx_sd_readl(azx_dev
, SD_LPIB
);
2063 chip
->position_fix
[stream
] = POS_FIX_POSBUF
;
2068 if (pos
>= azx_dev
->bufsize
)
2073 static snd_pcm_uframes_t
azx_pcm_pointer(struct snd_pcm_substream
*substream
)
2075 struct azx_pcm
*apcm
= snd_pcm_substream_chip(substream
);
2076 struct azx
*chip
= apcm
->chip
;
2077 struct azx_dev
*azx_dev
= get_azx_dev(substream
);
2078 return bytes_to_frames(substream
->runtime
,
2079 azx_get_position(chip
, azx_dev
, false));
2083 * Check whether the current DMA position is acceptable for updating
2084 * periods. Returns non-zero if it's OK.
2086 * Many HD-audio controllers appear pretty inaccurate about
2087 * the update-IRQ timing. The IRQ is issued before actually the
2088 * data is processed. So, we need to process it afterwords in a
2091 static int azx_position_ok(struct azx
*chip
, struct azx_dev
*azx_dev
)
2097 wallclk
= azx_readl(chip
, WALLCLK
) - azx_dev
->start_wallclk
;
2098 if (wallclk
< (azx_dev
->period_wallclk
* 2) / 3)
2099 return -1; /* bogus (too early) interrupt */
2101 stream
= azx_dev
->substream
->stream
;
2102 pos
= azx_get_position(chip
, azx_dev
, true);
2104 if (WARN_ONCE(!azx_dev
->period_bytes
,
2105 "hda-intel: zero azx_dev->period_bytes"))
2106 return -1; /* this shouldn't happen! */
2107 if (wallclk
< (azx_dev
->period_wallclk
* 5) / 4 &&
2108 pos
% azx_dev
->period_bytes
> azx_dev
->period_bytes
/ 2)
2109 /* NG - it's below the first next period boundary */
2110 return bdl_pos_adj
[chip
->dev_index
] ? 0 : -1;
2111 azx_dev
->start_wallclk
+= wallclk
;
2112 return 1; /* OK, it's fine */
2116 * The work for pending PCM period updates.
2118 static void azx_irq_pending_work(struct work_struct
*work
)
2120 struct azx
*chip
= container_of(work
, struct azx
, irq_pending_work
);
2123 if (!chip
->irq_pending_warned
) {
2125 "hda-intel: IRQ timing workaround is activated "
2126 "for card #%d. Suggest a bigger bdl_pos_adj.\n",
2127 chip
->card
->number
);
2128 chip
->irq_pending_warned
= 1;
2133 spin_lock_irq(&chip
->reg_lock
);
2134 for (i
= 0; i
< chip
->num_streams
; i
++) {
2135 struct azx_dev
*azx_dev
= &chip
->azx_dev
[i
];
2136 if (!azx_dev
->irq_pending
||
2137 !azx_dev
->substream
||
2140 ok
= azx_position_ok(chip
, azx_dev
);
2142 azx_dev
->irq_pending
= 0;
2143 spin_unlock(&chip
->reg_lock
);
2144 snd_pcm_period_elapsed(azx_dev
->substream
);
2145 spin_lock(&chip
->reg_lock
);
2146 } else if (ok
< 0) {
2147 pending
= 0; /* too early */
2151 spin_unlock_irq(&chip
->reg_lock
);
2158 /* clear irq_pending flags and assure no on-going workq */
2159 static void azx_clear_irq_pending(struct azx
*chip
)
2163 spin_lock_irq(&chip
->reg_lock
);
2164 for (i
= 0; i
< chip
->num_streams
; i
++)
2165 chip
->azx_dev
[i
].irq_pending
= 0;
2166 spin_unlock_irq(&chip
->reg_lock
);
2170 static int azx_pcm_mmap(struct snd_pcm_substream
*substream
,
2171 struct vm_area_struct
*area
)
2173 struct azx_pcm
*apcm
= snd_pcm_substream_chip(substream
);
2174 struct azx
*chip
= apcm
->chip
;
2175 if (!azx_snoop(chip
))
2176 area
->vm_page_prot
= pgprot_writecombine(area
->vm_page_prot
);
2177 return snd_pcm_lib_default_mmap(substream
, area
);
2180 #define azx_pcm_mmap NULL
2183 static struct snd_pcm_ops azx_pcm_ops
= {
2184 .open
= azx_pcm_open
,
2185 .close
= azx_pcm_close
,
2186 .ioctl
= snd_pcm_lib_ioctl
,
2187 .hw_params
= azx_pcm_hw_params
,
2188 .hw_free
= azx_pcm_hw_free
,
2189 .prepare
= azx_pcm_prepare
,
2190 .trigger
= azx_pcm_trigger
,
2191 .pointer
= azx_pcm_pointer
,
2192 .mmap
= azx_pcm_mmap
,
2193 .page
= snd_pcm_sgbuf_ops_page
,
2196 static void azx_pcm_free(struct snd_pcm
*pcm
)
2198 struct azx_pcm
*apcm
= pcm
->private_data
;
2200 apcm
->chip
->pcm
[pcm
->device
] = NULL
;
2205 #define MAX_PREALLOC_SIZE (32 * 1024 * 1024)
2208 azx_attach_pcm_stream(struct hda_bus
*bus
, struct hda_codec
*codec
,
2209 struct hda_pcm
*cpcm
)
2211 struct azx
*chip
= bus
->private_data
;
2212 struct snd_pcm
*pcm
;
2213 struct azx_pcm
*apcm
;
2214 int pcm_dev
= cpcm
->device
;
2218 if (pcm_dev
>= HDA_MAX_PCMS
) {
2219 snd_printk(KERN_ERR SFX
"Invalid PCM device number %d\n",
2223 if (chip
->pcm
[pcm_dev
]) {
2224 snd_printk(KERN_ERR SFX
"PCM %d already exists\n", pcm_dev
);
2227 err
= snd_pcm_new(chip
->card
, cpcm
->name
, pcm_dev
,
2228 cpcm
->stream
[SNDRV_PCM_STREAM_PLAYBACK
].substreams
,
2229 cpcm
->stream
[SNDRV_PCM_STREAM_CAPTURE
].substreams
,
2233 strlcpy(pcm
->name
, cpcm
->name
, sizeof(pcm
->name
));
2234 apcm
= kzalloc(sizeof(*apcm
), GFP_KERNEL
);
2238 apcm
->codec
= codec
;
2239 pcm
->private_data
= apcm
;
2240 pcm
->private_free
= azx_pcm_free
;
2241 if (cpcm
->pcm_type
== HDA_PCM_TYPE_MODEM
)
2242 pcm
->dev_class
= SNDRV_PCM_CLASS_MODEM
;
2243 chip
->pcm
[pcm_dev
] = pcm
;
2245 for (s
= 0; s
< 2; s
++) {
2246 apcm
->hinfo
[s
] = &cpcm
->stream
[s
];
2247 if (cpcm
->stream
[s
].substreams
)
2248 snd_pcm_set_ops(pcm
, s
, &azx_pcm_ops
);
2250 /* buffer pre-allocation */
2251 size
= CONFIG_SND_HDA_PREALLOC_SIZE
* 1024;
2252 if (size
> MAX_PREALLOC_SIZE
)
2253 size
= MAX_PREALLOC_SIZE
;
2254 snd_pcm_lib_preallocate_pages_for_all(pcm
, SNDRV_DMA_TYPE_DEV_SG
,
2255 snd_dma_pci_data(chip
->pci
),
2256 size
, MAX_PREALLOC_SIZE
);
2261 * mixer creation - all stuff is implemented in hda module
2263 static int __devinit
azx_mixer_create(struct azx
*chip
)
2265 return snd_hda_build_controls(chip
->bus
);
2270 * initialize SD streams
2272 static int __devinit
azx_init_stream(struct azx
*chip
)
2276 /* initialize each stream (aka device)
2277 * assign the starting bdl address to each stream (device)
2280 for (i
= 0; i
< chip
->num_streams
; i
++) {
2281 struct azx_dev
*azx_dev
= &chip
->azx_dev
[i
];
2282 azx_dev
->posbuf
= (u32 __iomem
*)(chip
->posbuf
.area
+ i
* 8);
2283 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
2284 azx_dev
->sd_addr
= chip
->remap_addr
+ (0x20 * i
+ 0x80);
2285 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
2286 azx_dev
->sd_int_sta_mask
= 1 << i
;
2287 /* stream tag: must be non-zero and unique */
2289 azx_dev
->stream_tag
= i
+ 1;
2295 static int azx_acquire_irq(struct azx
*chip
, int do_disconnect
)
2297 if (request_irq(chip
->pci
->irq
, azx_interrupt
,
2298 chip
->msi
? 0 : IRQF_SHARED
,
2299 KBUILD_MODNAME
, chip
)) {
2300 printk(KERN_ERR
"hda-intel: unable to grab IRQ %d, "
2301 "disabling device\n", chip
->pci
->irq
);
2303 snd_card_disconnect(chip
->card
);
2306 chip
->irq
= chip
->pci
->irq
;
2307 pci_intx(chip
->pci
, !chip
->msi
);
2312 static void azx_stop_chip(struct azx
*chip
)
2314 if (!chip
->initialized
)
2317 /* disable interrupts */
2318 azx_int_disable(chip
);
2319 azx_int_clear(chip
);
2321 /* disable CORB/RIRB */
2322 azx_free_cmd_io(chip
);
2324 /* disable position buffer */
2325 azx_writel(chip
, DPLBASE
, 0);
2326 azx_writel(chip
, DPUBASE
, 0);
2328 chip
->initialized
= 0;
2331 #ifdef CONFIG_SND_HDA_POWER_SAVE
2332 /* power-up/down the controller */
2333 static void azx_power_notify(struct hda_bus
*bus
)
2335 struct azx
*chip
= bus
->private_data
;
2336 struct hda_codec
*c
;
2339 list_for_each_entry(c
, &bus
->codec_list
, list
) {
2346 azx_init_chip(chip
, 1);
2347 else if (chip
->running
&& power_save_controller
&&
2348 !bus
->power_keep_link_on
)
2349 azx_stop_chip(chip
);
2351 #endif /* CONFIG_SND_HDA_POWER_SAVE */
2358 static int snd_hda_codecs_inuse(struct hda_bus
*bus
)
2360 struct hda_codec
*codec
;
2362 list_for_each_entry(codec
, &bus
->codec_list
, list
) {
2363 if (snd_hda_codec_needs_resume(codec
))
2369 static int azx_suspend(struct pci_dev
*pci
, pm_message_t state
)
2371 struct snd_card
*card
= pci_get_drvdata(pci
);
2372 struct azx
*chip
= card
->private_data
;
2375 snd_power_change_state(card
, SNDRV_CTL_POWER_D3hot
);
2376 azx_clear_irq_pending(chip
);
2377 for (i
= 0; i
< HDA_MAX_PCMS
; i
++)
2378 snd_pcm_suspend_all(chip
->pcm
[i
]);
2379 if (chip
->initialized
)
2380 snd_hda_suspend(chip
->bus
);
2381 azx_stop_chip(chip
);
2382 if (chip
->irq
>= 0) {
2383 free_irq(chip
->irq
, chip
);
2387 pci_disable_msi(chip
->pci
);
2388 pci_disable_device(pci
);
2389 pci_save_state(pci
);
2390 pci_set_power_state(pci
, pci_choose_state(pci
, state
));
2394 static int azx_resume(struct pci_dev
*pci
)
2396 struct snd_card
*card
= pci_get_drvdata(pci
);
2397 struct azx
*chip
= card
->private_data
;
2399 pci_set_power_state(pci
, PCI_D0
);
2400 pci_restore_state(pci
);
2401 if (pci_enable_device(pci
) < 0) {
2402 printk(KERN_ERR
"hda-intel: pci_enable_device failed, "
2403 "disabling device\n");
2404 snd_card_disconnect(card
);
2407 pci_set_master(pci
);
2409 if (pci_enable_msi(pci
) < 0)
2411 if (azx_acquire_irq(chip
, 1) < 0)
2415 if (snd_hda_codecs_inuse(chip
->bus
))
2416 azx_init_chip(chip
, 1);
2418 snd_hda_resume(chip
->bus
);
2419 snd_power_change_state(card
, SNDRV_CTL_POWER_D0
);
2422 #endif /* CONFIG_PM */
2426 * reboot notifier for hang-up problem at power-down
2428 static int azx_halt(struct notifier_block
*nb
, unsigned long event
, void *buf
)
2430 struct azx
*chip
= container_of(nb
, struct azx
, reboot_notifier
);
2431 snd_hda_bus_reboot_notify(chip
->bus
);
2432 azx_stop_chip(chip
);
2436 static void azx_notifier_register(struct azx
*chip
)
2438 chip
->reboot_notifier
.notifier_call
= azx_halt
;
2439 register_reboot_notifier(&chip
->reboot_notifier
);
2442 static void azx_notifier_unregister(struct azx
*chip
)
2444 if (chip
->reboot_notifier
.notifier_call
)
2445 unregister_reboot_notifier(&chip
->reboot_notifier
);
2451 static int azx_free(struct azx
*chip
)
2455 azx_notifier_unregister(chip
);
2457 if (chip
->initialized
) {
2458 azx_clear_irq_pending(chip
);
2459 for (i
= 0; i
< chip
->num_streams
; i
++)
2460 azx_stream_stop(chip
, &chip
->azx_dev
[i
]);
2461 azx_stop_chip(chip
);
2465 free_irq(chip
->irq
, (void*)chip
);
2467 pci_disable_msi(chip
->pci
);
2468 if (chip
->remap_addr
)
2469 iounmap(chip
->remap_addr
);
2471 if (chip
->azx_dev
) {
2472 for (i
= 0; i
< chip
->num_streams
; i
++)
2473 if (chip
->azx_dev
[i
].bdl
.area
) {
2474 mark_pages_wc(chip
, &chip
->azx_dev
[i
].bdl
, false);
2475 snd_dma_free_pages(&chip
->azx_dev
[i
].bdl
);
2478 if (chip
->rb
.area
) {
2479 mark_pages_wc(chip
, &chip
->rb
, false);
2480 snd_dma_free_pages(&chip
->rb
);
2482 if (chip
->posbuf
.area
) {
2483 mark_pages_wc(chip
, &chip
->posbuf
, false);
2484 snd_dma_free_pages(&chip
->posbuf
);
2486 pci_release_regions(chip
->pci
);
2487 pci_disable_device(chip
->pci
);
2488 kfree(chip
->azx_dev
);
2494 static int azx_dev_free(struct snd_device
*device
)
2496 return azx_free(device
->device_data
);
2500 * white/black-listing for position_fix
2502 static struct snd_pci_quirk position_fix_list
[] __devinitdata
= {
2503 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB
),
2504 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB
),
2505 SND_PCI_QUIRK(0x1028, 0x02c6, "Dell Inspiron 1010", POS_FIX_LPIB
),
2506 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB
),
2507 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB
),
2508 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB
),
2509 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB
),
2510 SND_PCI_QUIRK(0x1043, 0x83ce, "ASUS 1101HA", POS_FIX_LPIB
),
2511 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB
),
2512 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB
),
2513 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB
),
2514 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB
),
2515 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB
),
2516 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB
),
2517 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB
),
2521 static int __devinit
check_position_fix(struct azx
*chip
, int fix
)
2523 const struct snd_pci_quirk
*q
;
2527 case POS_FIX_POSBUF
:
2528 case POS_FIX_VIACOMBO
:
2532 q
= snd_pci_quirk_lookup(chip
->pci
, position_fix_list
);
2535 "hda_intel: position_fix set to %d "
2536 "for device %04x:%04x\n",
2537 q
->value
, q
->subvendor
, q
->subdevice
);
2541 /* Check VIA/ATI HD Audio Controller exist */
2542 if (chip
->driver_caps
& AZX_DCAPS_POSFIX_VIA
) {
2543 snd_printd(SFX
"Using VIACOMBO position fix\n");
2544 return POS_FIX_VIACOMBO
;
2546 if (chip
->driver_caps
& AZX_DCAPS_POSFIX_LPIB
) {
2547 snd_printd(SFX
"Using LPIB position fix\n");
2548 return POS_FIX_LPIB
;
2550 return POS_FIX_AUTO
;
2554 * black-lists for probe_mask
2556 static struct snd_pci_quirk probe_mask_list
[] __devinitdata
= {
2557 /* Thinkpad often breaks the controller communication when accessing
2558 * to the non-working (or non-existing) modem codec slot.
2560 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
2561 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
2562 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
2564 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
2565 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
2566 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
2567 /* forced codec slots */
2568 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
2569 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
2573 #define AZX_FORCE_CODEC_MASK 0x100
2575 static void __devinit
check_probe_mask(struct azx
*chip
, int dev
)
2577 const struct snd_pci_quirk
*q
;
2579 chip
->codec_probe_mask
= probe_mask
[dev
];
2580 if (chip
->codec_probe_mask
== -1) {
2581 q
= snd_pci_quirk_lookup(chip
->pci
, probe_mask_list
);
2584 "hda_intel: probe_mask set to 0x%x "
2585 "for device %04x:%04x\n",
2586 q
->value
, q
->subvendor
, q
->subdevice
);
2587 chip
->codec_probe_mask
= q
->value
;
2591 /* check forced option */
2592 if (chip
->codec_probe_mask
!= -1 &&
2593 (chip
->codec_probe_mask
& AZX_FORCE_CODEC_MASK
)) {
2594 chip
->codec_mask
= chip
->codec_probe_mask
& 0xff;
2595 printk(KERN_INFO
"hda_intel: codec_mask forced to 0x%x\n",
2601 * white/black-list for enable_msi
2603 static struct snd_pci_quirk msi_black_list
[] __devinitdata
= {
2604 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
2605 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
2606 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
2607 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
2608 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
2612 static void __devinit
check_msi(struct azx
*chip
)
2614 const struct snd_pci_quirk
*q
;
2616 if (enable_msi
>= 0) {
2617 chip
->msi
= !!enable_msi
;
2620 chip
->msi
= 1; /* enable MSI as default */
2621 q
= snd_pci_quirk_lookup(chip
->pci
, msi_black_list
);
2624 "hda_intel: msi for device %04x:%04x set to %d\n",
2625 q
->subvendor
, q
->subdevice
, q
->value
);
2626 chip
->msi
= q
->value
;
2630 /* NVidia chipsets seem to cause troubles with MSI */
2631 if (chip
->driver_caps
& AZX_DCAPS_NO_MSI
) {
2632 printk(KERN_INFO
"hda_intel: Disabling MSI\n");
2641 static int __devinit
azx_create(struct snd_card
*card
, struct pci_dev
*pci
,
2642 int dev
, unsigned int driver_caps
,
2647 unsigned short gcap
;
2648 static struct snd_device_ops ops
= {
2649 .dev_free
= azx_dev_free
,
2654 err
= pci_enable_device(pci
);
2658 chip
= kzalloc(sizeof(*chip
), GFP_KERNEL
);
2660 snd_printk(KERN_ERR SFX
"cannot allocate chip\n");
2661 pci_disable_device(pci
);
2665 spin_lock_init(&chip
->reg_lock
);
2666 mutex_init(&chip
->open_mutex
);
2670 chip
->driver_caps
= driver_caps
;
2671 chip
->driver_type
= driver_caps
& 0xff;
2673 chip
->dev_index
= dev
;
2674 INIT_WORK(&chip
->irq_pending_work
, azx_irq_pending_work
);
2676 chip
->position_fix
[0] = chip
->position_fix
[1] =
2677 check_position_fix(chip
, position_fix
[dev
]);
2678 check_probe_mask(chip
, dev
);
2680 chip
->single_cmd
= single_cmd
;
2681 chip
->snoop
= hda_snoop
;
2683 if (bdl_pos_adj
[dev
] < 0) {
2684 switch (chip
->driver_type
) {
2685 case AZX_DRIVER_ICH
:
2686 case AZX_DRIVER_PCH
:
2687 bdl_pos_adj
[dev
] = 1;
2690 bdl_pos_adj
[dev
] = 32;
2695 #if BITS_PER_LONG != 64
2696 /* Fix up base address on ULI M5461 */
2697 if (chip
->driver_type
== AZX_DRIVER_ULI
) {
2699 pci_read_config_word(pci
, 0x40, &tmp3
);
2700 pci_write_config_word(pci
, 0x40, tmp3
| 0x10);
2701 pci_write_config_dword(pci
, PCI_BASE_ADDRESS_1
, 0);
2705 err
= pci_request_regions(pci
, "ICH HD audio");
2708 pci_disable_device(pci
);
2712 chip
->addr
= pci_resource_start(pci
, 0);
2713 chip
->remap_addr
= pci_ioremap_bar(pci
, 0);
2714 if (chip
->remap_addr
== NULL
) {
2715 snd_printk(KERN_ERR SFX
"ioremap error\n");
2721 if (pci_enable_msi(pci
) < 0)
2724 if (azx_acquire_irq(chip
, 0) < 0) {
2729 pci_set_master(pci
);
2730 synchronize_irq(chip
->irq
);
2732 gcap
= azx_readw(chip
, GCAP
);
2733 snd_printdd(SFX
"chipset global capabilities = 0x%x\n", gcap
);
2735 /* disable SB600 64bit support for safety */
2736 if (chip
->pci
->vendor
== PCI_VENDOR_ID_ATI
) {
2737 struct pci_dev
*p_smbus
;
2738 p_smbus
= pci_get_device(PCI_VENDOR_ID_ATI
,
2739 PCI_DEVICE_ID_ATI_SBX00_SMBUS
,
2742 if (p_smbus
->revision
< 0x30)
2743 gcap
&= ~ICH6_GCAP_64OK
;
2744 pci_dev_put(p_smbus
);
2748 /* disable 64bit DMA address on some devices */
2749 if (chip
->driver_caps
& AZX_DCAPS_NO_64BIT
) {
2750 snd_printd(SFX
"Disabling 64bit DMA\n");
2751 gcap
&= ~ICH6_GCAP_64OK
;
2754 /* disable buffer size rounding to 128-byte multiples if supported */
2755 if (chip
->driver_caps
& AZX_DCAPS_BUFSIZE
)
2756 align_buffer_size
= 0;
2758 /* allow 64bit DMA address if supported by H/W */
2759 if ((gcap
& ICH6_GCAP_64OK
) && !pci_set_dma_mask(pci
, DMA_BIT_MASK(64)))
2760 pci_set_consistent_dma_mask(pci
, DMA_BIT_MASK(64));
2762 pci_set_dma_mask(pci
, DMA_BIT_MASK(32));
2763 pci_set_consistent_dma_mask(pci
, DMA_BIT_MASK(32));
2766 /* read number of streams from GCAP register instead of using
2769 chip
->capture_streams
= (gcap
>> 8) & 0x0f;
2770 chip
->playback_streams
= (gcap
>> 12) & 0x0f;
2771 if (!chip
->playback_streams
&& !chip
->capture_streams
) {
2772 /* gcap didn't give any info, switching to old method */
2774 switch (chip
->driver_type
) {
2775 case AZX_DRIVER_ULI
:
2776 chip
->playback_streams
= ULI_NUM_PLAYBACK
;
2777 chip
->capture_streams
= ULI_NUM_CAPTURE
;
2779 case AZX_DRIVER_ATIHDMI
:
2780 chip
->playback_streams
= ATIHDMI_NUM_PLAYBACK
;
2781 chip
->capture_streams
= ATIHDMI_NUM_CAPTURE
;
2783 case AZX_DRIVER_GENERIC
:
2785 chip
->playback_streams
= ICH6_NUM_PLAYBACK
;
2786 chip
->capture_streams
= ICH6_NUM_CAPTURE
;
2790 chip
->capture_index_offset
= 0;
2791 chip
->playback_index_offset
= chip
->capture_streams
;
2792 chip
->num_streams
= chip
->playback_streams
+ chip
->capture_streams
;
2793 chip
->azx_dev
= kcalloc(chip
->num_streams
, sizeof(*chip
->azx_dev
),
2795 if (!chip
->azx_dev
) {
2796 snd_printk(KERN_ERR SFX
"cannot malloc azx_dev\n");
2800 for (i
= 0; i
< chip
->num_streams
; i
++) {
2801 /* allocate memory for the BDL for each stream */
2802 err
= snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV
,
2803 snd_dma_pci_data(chip
->pci
),
2804 BDL_SIZE
, &chip
->azx_dev
[i
].bdl
);
2806 snd_printk(KERN_ERR SFX
"cannot allocate BDL\n");
2809 mark_pages_wc(chip
, &chip
->azx_dev
[i
].bdl
, true);
2811 /* allocate memory for the position buffer */
2812 err
= snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV
,
2813 snd_dma_pci_data(chip
->pci
),
2814 chip
->num_streams
* 8, &chip
->posbuf
);
2816 snd_printk(KERN_ERR SFX
"cannot allocate posbuf\n");
2819 mark_pages_wc(chip
, &chip
->posbuf
, true);
2820 /* allocate CORB/RIRB */
2821 err
= azx_alloc_cmd_io(chip
);
2825 /* initialize streams */
2826 azx_init_stream(chip
);
2828 /* initialize chip */
2830 azx_init_chip(chip
, (probe_only
[dev
] & 2) == 0);
2832 /* codec detection */
2833 if (!chip
->codec_mask
) {
2834 snd_printk(KERN_ERR SFX
"no codecs found!\n");
2839 err
= snd_device_new(card
, SNDRV_DEV_LOWLEVEL
, chip
, &ops
);
2841 snd_printk(KERN_ERR SFX
"Error creating device [card]!\n");
2845 strcpy(card
->driver
, "HDA-Intel");
2846 strlcpy(card
->shortname
, driver_short_names
[chip
->driver_type
],
2847 sizeof(card
->shortname
));
2848 snprintf(card
->longname
, sizeof(card
->longname
),
2849 "%s at 0x%lx irq %i",
2850 card
->shortname
, chip
->addr
, chip
->irq
);
2860 static void power_down_all_codecs(struct azx
*chip
)
2862 #ifdef CONFIG_SND_HDA_POWER_SAVE
2863 /* The codecs were powered up in snd_hda_codec_new().
2864 * Now all initialization done, so turn them down if possible
2866 struct hda_codec
*codec
;
2867 list_for_each_entry(codec
, &chip
->bus
->codec_list
, list
) {
2868 snd_hda_power_down(codec
);
2873 static int __devinit
azx_probe(struct pci_dev
*pci
,
2874 const struct pci_device_id
*pci_id
)
2877 struct snd_card
*card
;
2881 if (dev
>= SNDRV_CARDS
)
2888 err
= snd_card_create(index
[dev
], id
[dev
], THIS_MODULE
, 0, &card
);
2890 snd_printk(KERN_ERR SFX
"Error creating card!\n");
2894 /* set this here since it's referred in snd_hda_load_patch() */
2895 snd_card_set_dev(card
, &pci
->dev
);
2897 err
= azx_create(card
, pci
, dev
, pci_id
->driver_data
, &chip
);
2900 card
->private_data
= chip
;
2902 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2903 chip
->beep_mode
= beep_mode
[dev
];
2906 /* create codec instances */
2907 err
= azx_codec_create(chip
, model
[dev
]);
2910 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2911 if (patch
[dev
] && *patch
[dev
]) {
2912 snd_printk(KERN_ERR SFX
"Applying patch firmware '%s'\n",
2914 err
= snd_hda_load_patch(chip
->bus
, patch
[dev
]);
2919 if ((probe_only
[dev
] & 1) == 0) {
2920 err
= azx_codec_configure(chip
);
2925 /* create PCM streams */
2926 err
= snd_hda_build_pcms(chip
->bus
);
2930 /* create mixer controls */
2931 err
= azx_mixer_create(chip
);
2935 err
= snd_card_register(card
);
2939 pci_set_drvdata(pci
, card
);
2941 power_down_all_codecs(chip
);
2942 azx_notifier_register(chip
);
2947 snd_card_free(card
);
2951 static void __devexit
azx_remove(struct pci_dev
*pci
)
2953 snd_card_free(pci_get_drvdata(pci
));
2954 pci_set_drvdata(pci
, NULL
);
2958 static DEFINE_PCI_DEVICE_TABLE(azx_ids
) = {
2960 { PCI_DEVICE(0x8086, 0x1c20),
2961 .driver_data
= AZX_DRIVER_PCH
| AZX_DCAPS_SCH_SNOOP
|
2962 AZX_DCAPS_BUFSIZE
},
2964 { PCI_DEVICE(0x8086, 0x1d20),
2965 .driver_data
= AZX_DRIVER_PCH
| AZX_DCAPS_SCH_SNOOP
|
2968 { PCI_DEVICE(0x8086, 0x1e20),
2969 .driver_data
= AZX_DRIVER_PCH
| AZX_DCAPS_SCH_SNOOP
|
2972 { PCI_DEVICE(0x8086, 0x811b),
2973 .driver_data
= AZX_DRIVER_SCH
| AZX_DCAPS_SCH_SNOOP
|
2974 AZX_DCAPS_BUFSIZE
| AZX_DCAPS_POSFIX_LPIB
}, /* Poulsbo */
2976 { PCI_DEVICE(0x8086, 0x2668),
2977 .driver_data
= AZX_DRIVER_ICH
| AZX_DCAPS_OLD_SSYNC
|
2978 AZX_DCAPS_BUFSIZE
}, /* ICH6 */
2979 { PCI_DEVICE(0x8086, 0x27d8),
2980 .driver_data
= AZX_DRIVER_ICH
| AZX_DCAPS_OLD_SSYNC
|
2981 AZX_DCAPS_BUFSIZE
}, /* ICH7 */
2982 { PCI_DEVICE(0x8086, 0x269a),
2983 .driver_data
= AZX_DRIVER_ICH
| AZX_DCAPS_OLD_SSYNC
|
2984 AZX_DCAPS_BUFSIZE
}, /* ESB2 */
2985 { PCI_DEVICE(0x8086, 0x284b),
2986 .driver_data
= AZX_DRIVER_ICH
| AZX_DCAPS_OLD_SSYNC
|
2987 AZX_DCAPS_BUFSIZE
}, /* ICH8 */
2988 { PCI_DEVICE(0x8086, 0x293e),
2989 .driver_data
= AZX_DRIVER_ICH
| AZX_DCAPS_OLD_SSYNC
|
2990 AZX_DCAPS_BUFSIZE
}, /* ICH9 */
2991 { PCI_DEVICE(0x8086, 0x293f),
2992 .driver_data
= AZX_DRIVER_ICH
| AZX_DCAPS_OLD_SSYNC
|
2993 AZX_DCAPS_BUFSIZE
}, /* ICH9 */
2994 { PCI_DEVICE(0x8086, 0x3a3e),
2995 .driver_data
= AZX_DRIVER_ICH
| AZX_DCAPS_OLD_SSYNC
|
2996 AZX_DCAPS_BUFSIZE
}, /* ICH10 */
2997 { PCI_DEVICE(0x8086, 0x3a6e),
2998 .driver_data
= AZX_DRIVER_ICH
| AZX_DCAPS_OLD_SSYNC
|
2999 AZX_DCAPS_BUFSIZE
}, /* ICH10 */
3001 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_ANY_ID
),
3002 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO
<< 8,
3003 .class_mask
= 0xffffff,
3004 .driver_data
= AZX_DRIVER_ICH
| AZX_DCAPS_BUFSIZE
},
3005 /* ATI SB 450/600/700/800/900 */
3006 { PCI_DEVICE(0x1002, 0x437b),
3007 .driver_data
= AZX_DRIVER_ATI
| AZX_DCAPS_PRESET_ATI_SB
},
3008 { PCI_DEVICE(0x1002, 0x4383),
3009 .driver_data
= AZX_DRIVER_ATI
| AZX_DCAPS_PRESET_ATI_SB
},
3011 { PCI_DEVICE(0x1022, 0x780d),
3012 .driver_data
= AZX_DRIVER_GENERIC
| AZX_DCAPS_PRESET_ATI_SB
},
3014 { PCI_DEVICE(0x1002, 0x793b),
3015 .driver_data
= AZX_DRIVER_ATIHDMI
| AZX_DCAPS_PRESET_ATI_HDMI
},
3016 { PCI_DEVICE(0x1002, 0x7919),
3017 .driver_data
= AZX_DRIVER_ATIHDMI
| AZX_DCAPS_PRESET_ATI_HDMI
},
3018 { PCI_DEVICE(0x1002, 0x960f),
3019 .driver_data
= AZX_DRIVER_ATIHDMI
| AZX_DCAPS_PRESET_ATI_HDMI
},
3020 { PCI_DEVICE(0x1002, 0x970f),
3021 .driver_data
= AZX_DRIVER_ATIHDMI
| AZX_DCAPS_PRESET_ATI_HDMI
},
3022 { PCI_DEVICE(0x1002, 0xaa00),
3023 .driver_data
= AZX_DRIVER_ATIHDMI
| AZX_DCAPS_PRESET_ATI_HDMI
},
3024 { PCI_DEVICE(0x1002, 0xaa08),
3025 .driver_data
= AZX_DRIVER_ATIHDMI
| AZX_DCAPS_PRESET_ATI_HDMI
},
3026 { PCI_DEVICE(0x1002, 0xaa10),
3027 .driver_data
= AZX_DRIVER_ATIHDMI
| AZX_DCAPS_PRESET_ATI_HDMI
},
3028 { PCI_DEVICE(0x1002, 0xaa18),
3029 .driver_data
= AZX_DRIVER_ATIHDMI
| AZX_DCAPS_PRESET_ATI_HDMI
},
3030 { PCI_DEVICE(0x1002, 0xaa20),
3031 .driver_data
= AZX_DRIVER_ATIHDMI
| AZX_DCAPS_PRESET_ATI_HDMI
},
3032 { PCI_DEVICE(0x1002, 0xaa28),
3033 .driver_data
= AZX_DRIVER_ATIHDMI
| AZX_DCAPS_PRESET_ATI_HDMI
},
3034 { PCI_DEVICE(0x1002, 0xaa30),
3035 .driver_data
= AZX_DRIVER_ATIHDMI
| AZX_DCAPS_PRESET_ATI_HDMI
},
3036 { PCI_DEVICE(0x1002, 0xaa38),
3037 .driver_data
= AZX_DRIVER_ATIHDMI
| AZX_DCAPS_PRESET_ATI_HDMI
},
3038 { PCI_DEVICE(0x1002, 0xaa40),
3039 .driver_data
= AZX_DRIVER_ATIHDMI
| AZX_DCAPS_PRESET_ATI_HDMI
},
3040 { PCI_DEVICE(0x1002, 0xaa48),
3041 .driver_data
= AZX_DRIVER_ATIHDMI
| AZX_DCAPS_PRESET_ATI_HDMI
},
3042 /* VIA VT8251/VT8237A */
3043 { PCI_DEVICE(0x1106, 0x3288),
3044 .driver_data
= AZX_DRIVER_VIA
| AZX_DCAPS_POSFIX_VIA
},
3046 { PCI_DEVICE(0x1039, 0x7502), .driver_data
= AZX_DRIVER_SIS
},
3048 { PCI_DEVICE(0x10b9, 0x5461), .driver_data
= AZX_DRIVER_ULI
},
3050 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_ANY_ID
),
3051 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO
<< 8,
3052 .class_mask
= 0xffffff,
3053 .driver_data
= AZX_DRIVER_NVIDIA
| AZX_DCAPS_PRESET_NVIDIA
},
3055 { PCI_DEVICE(0x6549, 0x1200),
3056 .driver_data
= AZX_DRIVER_TERA
| AZX_DCAPS_NO_64BIT
},
3057 /* Creative X-Fi (CA0110-IBG) */
3058 #if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
3059 /* the following entry conflicts with snd-ctxfi driver,
3060 * as ctxfi driver mutates from HD-audio to native mode with
3061 * a special command sequence.
3063 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE
, PCI_ANY_ID
),
3064 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO
<< 8,
3065 .class_mask
= 0xffffff,
3066 .driver_data
= AZX_DRIVER_CTX
| AZX_DCAPS_CTX_WORKAROUND
|
3067 AZX_DCAPS_RIRB_PRE_DELAY
| AZX_DCAPS_POSFIX_LPIB
},
3069 /* this entry seems still valid -- i.e. without emu20kx chip */
3070 { PCI_DEVICE(0x1102, 0x0009),
3071 .driver_data
= AZX_DRIVER_CTX
| AZX_DCAPS_CTX_WORKAROUND
|
3072 AZX_DCAPS_RIRB_PRE_DELAY
| AZX_DCAPS_POSFIX_LPIB
},
3075 { PCI_DEVICE(0x17f3, 0x3010), .driver_data
= AZX_DRIVER_GENERIC
},
3076 /* VMware HDAudio */
3077 { PCI_DEVICE(0x15ad, 0x1977), .driver_data
= AZX_DRIVER_GENERIC
},
3078 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
3079 { PCI_DEVICE(PCI_VENDOR_ID_ATI
, PCI_ANY_ID
),
3080 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO
<< 8,
3081 .class_mask
= 0xffffff,
3082 .driver_data
= AZX_DRIVER_GENERIC
| AZX_DCAPS_PRESET_ATI_HDMI
},
3083 { PCI_DEVICE(PCI_VENDOR_ID_AMD
, PCI_ANY_ID
),
3084 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO
<< 8,
3085 .class_mask
= 0xffffff,
3086 .driver_data
= AZX_DRIVER_GENERIC
| AZX_DCAPS_PRESET_ATI_HDMI
},
3089 MODULE_DEVICE_TABLE(pci
, azx_ids
);
3091 /* pci_driver definition */
3092 static struct pci_driver driver
= {
3093 .name
= KBUILD_MODNAME
,
3094 .id_table
= azx_ids
,
3096 .remove
= __devexit_p(azx_remove
),
3098 .suspend
= azx_suspend
,
3099 .resume
= azx_resume
,
3103 static int __init
alsa_card_azx_init(void)
3105 return pci_register_driver(&driver
);
3108 static void __exit
alsa_card_azx_exit(void)
3110 pci_unregister_driver(&driver
);
3113 module_init(alsa_card_azx_init
)
3114 module_exit(alsa_card_azx_exit
)