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Revert "gma500: Fix dependencies"
[zen-stable.git] / drivers / isdn / hardware / mISDN / mISDNipac.c
blob64ecc6f5ffaf8d0159bc4e3c1cd35eb82835d82c
1 /*
2 * isac.c ISAC specific routines
3 *
4 * Author Karsten Keil <keil@isdn4linux.de>
5 *
6 * Copyright 2009 by Karsten Keil <keil@isdn4linux.de>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 *
21 */
22
23 #include <linux/slab.h>
24 #include <linux/module.h>
25 #include <linux/mISDNhw.h>
26 #include "ipac.h"
27
28
29 #define DBUSY_TIMER_VALUE 80
30 #define ARCOFI_USE 1
31
32 #define ISAC_REV "2.0"
33
34 MODULE_AUTHOR("Karsten Keil");
35 MODULE_VERSION(ISAC_REV);
36 MODULE_LICENSE("GPL v2");
37
38 #define ReadISAC(is, o) (is->read_reg(is->dch.hw, o + is->off))
39 #define WriteISAC(is, o, v) (is->write_reg(is->dch.hw, o + is->off, v))
40 #define ReadHSCX(h, o) (h->ip->read_reg(h->ip->hw, h->off + o))
41 #define WriteHSCX(h, o, v) (h->ip->write_reg(h->ip->hw, h->off + o, v))
42 #define ReadIPAC(ip, o) (ip->read_reg(ip->hw, o))
43 #define WriteIPAC(ip, o, v) (ip->write_reg(ip->hw, o, v))
44
45 static inline void
46 ph_command(struct isac_hw *isac, u8 command)
47 {
48 pr_debug("%s: ph_command %x\n", isac->name, command);
49 if (isac->type & IPAC_TYPE_ISACX)
50 WriteISAC(isac, ISACX_CIX0, (command << 4) | 0xE);
51 else
52 WriteISAC(isac, ISAC_CIX0, (command << 2) | 3);
53 }
54
55 static void
56 isac_ph_state_change(struct isac_hw *isac)
57 {
58 switch (isac->state) {
59 case (ISAC_IND_RS):
60 case (ISAC_IND_EI):
61 ph_command(isac, ISAC_CMD_DUI);
62 }
63 schedule_event(&isac->dch, FLG_PHCHANGE);
64 }
65
66 static void
67 isac_ph_state_bh(struct dchannel *dch)
68 {
69 struct isac_hw *isac = container_of(dch, struct isac_hw, dch);
70
71 switch (isac->state) {
72 case ISAC_IND_RS:
73 case ISAC_IND_EI:
74 dch->state = 0;
75 l1_event(dch->l1, HW_RESET_IND);
76 break;
77 case ISAC_IND_DID:
78 dch->state = 3;
79 l1_event(dch->l1, HW_DEACT_CNF);
80 break;
81 case ISAC_IND_DR:
82 dch->state = 3;
83 l1_event(dch->l1, HW_DEACT_IND);
84 break;
85 case ISAC_IND_PU:
86 dch->state = 4;
87 l1_event(dch->l1, HW_POWERUP_IND);
88 break;
89 case ISAC_IND_RSY:
90 if (dch->state <= 5) {
91 dch->state = 5;
92 l1_event(dch->l1, ANYSIGNAL);
93 } else {
94 dch->state = 8;
95 l1_event(dch->l1, LOSTFRAMING);
96 }
97 break;
98 case ISAC_IND_ARD:
99 dch->state = 6;
100 l1_event(dch->l1, INFO2);
101 break;
102 case ISAC_IND_AI8:
103 dch->state = 7;
104 l1_event(dch->l1, INFO4_P8);
105 break;
106 case ISAC_IND_AI10:
107 dch->state = 7;
108 l1_event(dch->l1, INFO4_P10);
109 break;
110 }
111 pr_debug("%s: TE newstate %x\n", isac->name, dch->state);
112 }
113
114 void
115 isac_empty_fifo(struct isac_hw *isac, int count)
116 {
117 u8 *ptr;
118
119 pr_debug("%s: %s %d\n", isac->name, __func__, count);
120
121 if (!isac->dch.rx_skb) {
122 isac->dch.rx_skb = mI_alloc_skb(isac->dch.maxlen, GFP_ATOMIC);
123 if (!isac->dch.rx_skb) {
124 pr_info("%s: D receive out of memory\n", isac->name);
125 WriteISAC(isac, ISAC_CMDR, 0x80);
126 return;
127 }
128 }
129 if ((isac->dch.rx_skb->len + count) >= isac->dch.maxlen) {
130 pr_debug("%s: %s overrun %d\n", isac->name, __func__,
131 isac->dch.rx_skb->len + count);
132 WriteISAC(isac, ISAC_CMDR, 0x80);
133 return;
134 }
135 ptr = skb_put(isac->dch.rx_skb, count);
136 isac->read_fifo(isac->dch.hw, isac->off, ptr, count);
137 WriteISAC(isac, ISAC_CMDR, 0x80);
138 if (isac->dch.debug & DEBUG_HW_DFIFO) {
139 char pfx[MISDN_MAX_IDLEN + 16];
140
141 snprintf(pfx, MISDN_MAX_IDLEN + 15, "D-recv %s %d ",
142 isac->name, count);
143 print_hex_dump_bytes(pfx, DUMP_PREFIX_OFFSET, ptr, count);
144 }
145 }
146
147 static void
148 isac_fill_fifo(struct isac_hw *isac)
149 {
150 int count, more;
151 u8 *ptr;
152
153 if (!isac->dch.tx_skb)
154 return;
155 count = isac->dch.tx_skb->len - isac->dch.tx_idx;
156 if (count <= 0)
157 return;
158
159 more = 0;
160 if (count > 32) {
161 more = !0;
162 count = 32;
163 }
164 pr_debug("%s: %s %d\n", isac->name, __func__, count);
165 ptr = isac->dch.tx_skb->data + isac->dch.tx_idx;
166 isac->dch.tx_idx += count;
167 isac->write_fifo(isac->dch.hw, isac->off, ptr, count);
168 WriteISAC(isac, ISAC_CMDR, more ? 0x8 : 0xa);
169 if (test_and_set_bit(FLG_BUSY_TIMER, &isac->dch.Flags)) {
170 pr_debug("%s: %s dbusytimer running\n", isac->name, __func__);
171 del_timer(&isac->dch.timer);
172 }
173 init_timer(&isac->dch.timer);
174 isac->dch.timer.expires = jiffies + ((DBUSY_TIMER_VALUE * HZ)/1000);
175 add_timer(&isac->dch.timer);
176 if (isac->dch.debug & DEBUG_HW_DFIFO) {
177 char pfx[MISDN_MAX_IDLEN + 16];
178
179 snprintf(pfx, MISDN_MAX_IDLEN + 15, "D-send %s %d ",
180 isac->name, count);
181 print_hex_dump_bytes(pfx, DUMP_PREFIX_OFFSET, ptr, count);
182 }
183 }
184
185 static void
186 isac_rme_irq(struct isac_hw *isac)
187 {
188 u8 val, count;
189
190 val = ReadISAC(isac, ISAC_RSTA);
191 if ((val & 0x70) != 0x20) {
192 if (val & 0x40) {
193 pr_debug("%s: ISAC RDO\n", isac->name);
194 #ifdef ERROR_STATISTIC
195 isac->dch.err_rx++;
196 #endif
197 }
198 if (!(val & 0x20)) {
199 pr_debug("%s: ISAC CRC error\n", isac->name);
200 #ifdef ERROR_STATISTIC
201 isac->dch.err_crc++;
202 #endif
203 }
204 WriteISAC(isac, ISAC_CMDR, 0x80);
205 if (isac->dch.rx_skb)
206 dev_kfree_skb(isac->dch.rx_skb);
207 isac->dch.rx_skb = NULL;
208 } else {
209 count = ReadISAC(isac, ISAC_RBCL) & 0x1f;
210 if (count == 0)
211 count = 32;
212 isac_empty_fifo(isac, count);
213 recv_Dchannel(&isac->dch);
214 }
215 }
216
217 static void
218 isac_xpr_irq(struct isac_hw *isac)
219 {
220 if (test_and_clear_bit(FLG_BUSY_TIMER, &isac->dch.Flags))
221 del_timer(&isac->dch.timer);
222 if (isac->dch.tx_skb && isac->dch.tx_idx < isac->dch.tx_skb->len) {
223 isac_fill_fifo(isac);
224 } else {
225 if (isac->dch.tx_skb)
226 dev_kfree_skb(isac->dch.tx_skb);
227 if (get_next_dframe(&isac->dch))
228 isac_fill_fifo(isac);
229 }
230 }
231
232 static void
233 isac_retransmit(struct isac_hw *isac)
234 {
235 if (test_and_clear_bit(FLG_BUSY_TIMER, &isac->dch.Flags))
236 del_timer(&isac->dch.timer);
237 if (test_bit(FLG_TX_BUSY, &isac->dch.Flags)) {
238 /* Restart frame */
239 isac->dch.tx_idx = 0;
240 isac_fill_fifo(isac);
241 } else if (isac->dch.tx_skb) { /* should not happen */
242 pr_info("%s: tx_skb exist but not busy\n", isac->name);
243 test_and_set_bit(FLG_TX_BUSY, &isac->dch.Flags);
244 isac->dch.tx_idx = 0;
245 isac_fill_fifo(isac);
246 } else {
247 pr_info("%s: ISAC XDU no TX_BUSY\n", isac->name);
248 if (get_next_dframe(&isac->dch))
249 isac_fill_fifo(isac);
250 }
251 }
252
253 static void
254 isac_mos_irq(struct isac_hw *isac)
255 {
256 u8 val;
257 int ret;
258
259 val = ReadISAC(isac, ISAC_MOSR);
260 pr_debug("%s: ISAC MOSR %02x\n", isac->name, val);
261 #if ARCOFI_USE
262 if (val & 0x08) {
263 if (!isac->mon_rx) {
264 isac->mon_rx = kmalloc(MAX_MON_FRAME, GFP_ATOMIC);
265 if (!isac->mon_rx) {
266 pr_info("%s: ISAC MON RX out of memory!\n",
267 isac->name);
268 isac->mocr &= 0xf0;
269 isac->mocr |= 0x0a;
270 WriteISAC(isac, ISAC_MOCR, isac->mocr);
271 goto afterMONR0;
272 } else
273 isac->mon_rxp = 0;
274 }
275 if (isac->mon_rxp >= MAX_MON_FRAME) {
276 isac->mocr &= 0xf0;
277 isac->mocr |= 0x0a;
278 WriteISAC(isac, ISAC_MOCR, isac->mocr);
279 isac->mon_rxp = 0;
280 pr_debug("%s: ISAC MON RX overflow!\n", isac->name);
281 goto afterMONR0;
282 }
283 isac->mon_rx[isac->mon_rxp++] = ReadISAC(isac, ISAC_MOR0);
284 pr_debug("%s: ISAC MOR0 %02x\n", isac->name,
285 isac->mon_rx[isac->mon_rxp - 1]);
286 if (isac->mon_rxp == 1) {
287 isac->mocr |= 0x04;
288 WriteISAC(isac, ISAC_MOCR, isac->mocr);
289 }
290 }
291 afterMONR0:
292 if (val & 0x80) {
293 if (!isac->mon_rx) {
294 isac->mon_rx = kmalloc(MAX_MON_FRAME, GFP_ATOMIC);
295 if (!isac->mon_rx) {
296 pr_info("%s: ISAC MON RX out of memory!\n",
297 isac->name);
298 isac->mocr &= 0x0f;
299 isac->mocr |= 0xa0;
300 WriteISAC(isac, ISAC_MOCR, isac->mocr);
301 goto afterMONR1;
302 } else
303 isac->mon_rxp = 0;
304 }
305 if (isac->mon_rxp >= MAX_MON_FRAME) {
306 isac->mocr &= 0x0f;
307 isac->mocr |= 0xa0;
308 WriteISAC(isac, ISAC_MOCR, isac->mocr);
309 isac->mon_rxp = 0;
310 pr_debug("%s: ISAC MON RX overflow!\n", isac->name);
311 goto afterMONR1;
312 }
313 isac->mon_rx[isac->mon_rxp++] = ReadISAC(isac, ISAC_MOR1);
314 pr_debug("%s: ISAC MOR1 %02x\n", isac->name,
315 isac->mon_rx[isac->mon_rxp - 1]);
316 isac->mocr |= 0x40;
317 WriteISAC(isac, ISAC_MOCR, isac->mocr);
318 }
319 afterMONR1:
320 if (val & 0x04) {
321 isac->mocr &= 0xf0;
322 WriteISAC(isac, ISAC_MOCR, isac->mocr);
323 isac->mocr |= 0x0a;
324 WriteISAC(isac, ISAC_MOCR, isac->mocr);
325 if (isac->monitor) {
326 ret = isac->monitor(isac->dch.hw, MONITOR_RX_0,
327 isac->mon_rx, isac->mon_rxp);
328 if (ret)
329 kfree(isac->mon_rx);
330 } else {
331 pr_info("%s: MONITOR 0 received %d but no user\n",
332 isac->name, isac->mon_rxp);
333 kfree(isac->mon_rx);
334 }
335 isac->mon_rx = NULL;
336 isac->mon_rxp = 0;
337 }
338 if (val & 0x40) {
339 isac->mocr &= 0x0f;
340 WriteISAC(isac, ISAC_MOCR, isac->mocr);
341 isac->mocr |= 0xa0;
342 WriteISAC(isac, ISAC_MOCR, isac->mocr);
343 if (isac->monitor) {
344 ret = isac->monitor(isac->dch.hw, MONITOR_RX_1,
345 isac->mon_rx, isac->mon_rxp);
346 if (ret)
347 kfree(isac->mon_rx);
348 } else {
349 pr_info("%s: MONITOR 1 received %d but no user\n",
350 isac->name, isac->mon_rxp);
351 kfree(isac->mon_rx);
352 }
353 isac->mon_rx = NULL;
354 isac->mon_rxp = 0;
355 }
356 if (val & 0x02) {
357 if ((!isac->mon_tx) || (isac->mon_txc &&
358 (isac->mon_txp >= isac->mon_txc) && !(val & 0x08))) {
359 isac->mocr &= 0xf0;
360 WriteISAC(isac, ISAC_MOCR, isac->mocr);
361 isac->mocr |= 0x0a;
362 WriteISAC(isac, ISAC_MOCR, isac->mocr);
363 if (isac->mon_txc && (isac->mon_txp >= isac->mon_txc)) {
364 if (isac->monitor)
365 ret = isac->monitor(isac->dch.hw,
366 MONITOR_TX_0, NULL, 0);
367 }
368 kfree(isac->mon_tx);
369 isac->mon_tx = NULL;
370 isac->mon_txc = 0;
371 isac->mon_txp = 0;
372 goto AfterMOX0;
373 }
374 if (isac->mon_txc && (isac->mon_txp >= isac->mon_txc)) {
375 if (isac->monitor)
376 ret = isac->monitor(isac->dch.hw,
377 MONITOR_TX_0, NULL, 0);
378 kfree(isac->mon_tx);
379 isac->mon_tx = NULL;
380 isac->mon_txc = 0;
381 isac->mon_txp = 0;
382 goto AfterMOX0;
383 }
384 WriteISAC(isac, ISAC_MOX0, isac->mon_tx[isac->mon_txp++]);
385 pr_debug("%s: ISAC %02x -> MOX0\n", isac->name,
386 isac->mon_tx[isac->mon_txp - 1]);
387 }
388 AfterMOX0:
389 if (val & 0x20) {
390 if ((!isac->mon_tx) || (isac->mon_txc &&
391 (isac->mon_txp >= isac->mon_txc) && !(val & 0x80))) {
392 isac->mocr &= 0x0f;
393 WriteISAC(isac, ISAC_MOCR, isac->mocr);
394 isac->mocr |= 0xa0;
395 WriteISAC(isac, ISAC_MOCR, isac->mocr);
396 if (isac->mon_txc && (isac->mon_txp >= isac->mon_txc)) {
397 if (isac->monitor)
398 ret = isac->monitor(isac->dch.hw,
399 MONITOR_TX_1, NULL, 0);
400 }
401 kfree(isac->mon_tx);
402 isac->mon_tx = NULL;
403 isac->mon_txc = 0;
404 isac->mon_txp = 0;
405 goto AfterMOX1;
406 }
407 if (isac->mon_txc && (isac->mon_txp >= isac->mon_txc)) {
408 if (isac->monitor)
409 ret = isac->monitor(isac->dch.hw,
410 MONITOR_TX_1, NULL, 0);
411 kfree(isac->mon_tx);
412 isac->mon_tx = NULL;
413 isac->mon_txc = 0;
414 isac->mon_txp = 0;
415 goto AfterMOX1;
416 }
417 WriteISAC(isac, ISAC_MOX1, isac->mon_tx[isac->mon_txp++]);
418 pr_debug("%s: ISAC %02x -> MOX1\n", isac->name,
419 isac->mon_tx[isac->mon_txp - 1]);
420 }
421 AfterMOX1:
422 val = 0; /* dummy to avoid warning */
423 #endif
424 }
425
426 static void
427 isac_cisq_irq(struct isac_hw *isac) {
428 u8 val;
429
430 val = ReadISAC(isac, ISAC_CIR0);
431 pr_debug("%s: ISAC CIR0 %02X\n", isac->name, val);
432 if (val & 2) {
433 pr_debug("%s: ph_state change %x->%x\n", isac->name,
434 isac->state, (val >> 2) & 0xf);
435 isac->state = (val >> 2) & 0xf;
436 isac_ph_state_change(isac);
437 }
438 if (val & 1) {
439 val = ReadISAC(isac, ISAC_CIR1);
440 pr_debug("%s: ISAC CIR1 %02X\n", isac->name, val);
441 }
442 }
443
444 static void
445 isacsx_cic_irq(struct isac_hw *isac)
446 {
447 u8 val;
448
449 val = ReadISAC(isac, ISACX_CIR0);
450 pr_debug("%s: ISACX CIR0 %02X\n", isac->name, val);
451 if (val & ISACX_CIR0_CIC0) {
452 pr_debug("%s: ph_state change %x->%x\n", isac->name,
453 isac->state, val >> 4);
454 isac->state = val >> 4;
455 isac_ph_state_change(isac);
456 }
457 }
458
459 static void
460 isacsx_rme_irq(struct isac_hw *isac)
461 {
462 int count;
463 u8 val;
464
465 val = ReadISAC(isac, ISACX_RSTAD);
466 if ((val & (ISACX_RSTAD_VFR |
467 ISACX_RSTAD_RDO |
468 ISACX_RSTAD_CRC |
469 ISACX_RSTAD_RAB))
470 != (ISACX_RSTAD_VFR | ISACX_RSTAD_CRC)) {
471 pr_debug("%s: RSTAD %#x, dropped\n", isac->name, val);
472 #ifdef ERROR_STATISTIC
473 if (val & ISACX_RSTAD_CRC)
474 isac->dch.err_rx++;
475 else
476 isac->dch.err_crc++;
477 #endif
478 WriteISAC(isac, ISACX_CMDRD, ISACX_CMDRD_RMC);
479 if (isac->dch.rx_skb)
480 dev_kfree_skb(isac->dch.rx_skb);
481 isac->dch.rx_skb = NULL;
482 } else {
483 count = ReadISAC(isac, ISACX_RBCLD) & 0x1f;
484 if (count == 0)
485 count = 32;
486 isac_empty_fifo(isac, count);
487 if (isac->dch.rx_skb) {
488 skb_trim(isac->dch.rx_skb, isac->dch.rx_skb->len - 1);
489 pr_debug("%s: dchannel received %d\n", isac->name,
490 isac->dch.rx_skb->len);
491 recv_Dchannel(&isac->dch);
492 }
493 }
494 }
495
496 irqreturn_t
497 mISDNisac_irq(struct isac_hw *isac, u8 val)
498 {
499 if (unlikely(!val))
500 return IRQ_NONE;
501 pr_debug("%s: ISAC interrupt %02x\n", isac->name, val);
502 if (isac->type & IPAC_TYPE_ISACX) {
503 if (val & ISACX__CIC)
504 isacsx_cic_irq(isac);
505 if (val & ISACX__ICD) {
506 val = ReadISAC(isac, ISACX_ISTAD);
507 pr_debug("%s: ISTAD %02x\n", isac->name, val);
508 if (val & ISACX_D_XDU) {
509 pr_debug("%s: ISAC XDU\n", isac->name);
510 #ifdef ERROR_STATISTIC
511 isac->dch.err_tx++;
512 #endif
513 isac_retransmit(isac);
514 }
515 if (val & ISACX_D_XMR) {
516 pr_debug("%s: ISAC XMR\n", isac->name);
517 #ifdef ERROR_STATISTIC
518 isac->dch.err_tx++;
519 #endif
520 isac_retransmit(isac);
521 }
522 if (val & ISACX_D_XPR)
523 isac_xpr_irq(isac);
524 if (val & ISACX_D_RFO) {
525 pr_debug("%s: ISAC RFO\n", isac->name);
526 WriteISAC(isac, ISACX_CMDRD, ISACX_CMDRD_RMC);
527 }
528 if (val & ISACX_D_RME)
529 isacsx_rme_irq(isac);
530 if (val & ISACX_D_RPF)
531 isac_empty_fifo(isac, 0x20);
532 }
533 } else {
534 if (val & 0x80) /* RME */
535 isac_rme_irq(isac);
536 if (val & 0x40) /* RPF */
537 isac_empty_fifo(isac, 32);
538 if (val & 0x10) /* XPR */
539 isac_xpr_irq(isac);
540 if (val & 0x04) /* CISQ */
541 isac_cisq_irq(isac);
542 if (val & 0x20) /* RSC - never */
543 pr_debug("%s: ISAC RSC interrupt\n", isac->name);
544 if (val & 0x02) /* SIN - never */
545 pr_debug("%s: ISAC SIN interrupt\n", isac->name);
546 if (val & 0x01) { /* EXI */
547 val = ReadISAC(isac, ISAC_EXIR);
548 pr_debug("%s: ISAC EXIR %02x\n", isac->name, val);
549 if (val & 0x80) /* XMR */
550 pr_debug("%s: ISAC XMR\n", isac->name);
551 if (val & 0x40) { /* XDU */
552 pr_debug("%s: ISAC XDU\n", isac->name);
553 #ifdef ERROR_STATISTIC
554 isac->dch.err_tx++;
555 #endif
556 isac_retransmit(isac);
557 }
558 if (val & 0x04) /* MOS */
559 isac_mos_irq(isac);
560 }
561 }
562 return IRQ_HANDLED;
563 }
564 EXPORT_SYMBOL(mISDNisac_irq);
565
566 static int
567 isac_l1hw(struct mISDNchannel *ch, struct sk_buff *skb)
568 {
569 struct mISDNdevice *dev = container_of(ch, struct mISDNdevice, D);
570 struct dchannel *dch = container_of(dev, struct dchannel, dev);
571 struct isac_hw *isac = container_of(dch, struct isac_hw, dch);
572 int ret = -EINVAL;
573 struct mISDNhead *hh = mISDN_HEAD_P(skb);
574 u32 id;
575 u_long flags;
576
577 switch (hh->prim) {
578 case PH_DATA_REQ:
579 spin_lock_irqsave(isac->hwlock, flags);
580 ret = dchannel_senddata(dch, skb);
581 if (ret > 0) { /* direct TX */
582 id = hh->id; /* skb can be freed */
583 isac_fill_fifo(isac);
584 ret = 0;
585 spin_unlock_irqrestore(isac->hwlock, flags);
586 queue_ch_frame(ch, PH_DATA_CNF, id, NULL);
587 } else
588 spin_unlock_irqrestore(isac->hwlock, flags);
589 return ret;
590 case PH_ACTIVATE_REQ:
591 ret = l1_event(dch->l1, hh->prim);
592 break;
593 case PH_DEACTIVATE_REQ:
594 test_and_clear_bit(FLG_L2_ACTIVATED, &dch->Flags);
595 ret = l1_event(dch->l1, hh->prim);
596 break;
597 }
598
599 if (!ret)
600 dev_kfree_skb(skb);
601 return ret;
602 }
603
604 static int
605 isac_ctrl(struct isac_hw *isac, u32 cmd, u_long para)
606 {
607 u8 tl = 0;
608 u_long flags;
609
610 switch (cmd) {
611 case HW_TESTLOOP:
612 spin_lock_irqsave(isac->hwlock, flags);
613 if (!(isac->type & IPAC_TYPE_ISACX)) {
614 /* TODO: implement for IPAC_TYPE_ISACX */
615 if (para & 1) /* B1 */
616 tl |= 0x0c;
617 else if (para & 2) /* B2 */
618 tl |= 0x3;
619 /* we only support IOM2 mode */
620 WriteISAC(isac, ISAC_SPCR, tl);
621 if (tl)
622 WriteISAC(isac, ISAC_ADF1, 0x8);
623 else
624 WriteISAC(isac, ISAC_ADF1, 0x0);
625 }
626 spin_unlock_irqrestore(isac->hwlock, flags);
627 break;
628 default:
629 pr_debug("%s: %s unknown command %x %lx\n", isac->name,
630 __func__, cmd, para);
631 return -1;
632 }
633 return 0;
634 }
635
636 static int
637 isac_l1cmd(struct dchannel *dch, u32 cmd)
638 {
639 struct isac_hw *isac = container_of(dch, struct isac_hw, dch);
640 u_long flags;
641
642 pr_debug("%s: cmd(%x) state(%02x)\n", isac->name, cmd, isac->state);
643 switch (cmd) {
644 case INFO3_P8:
645 spin_lock_irqsave(isac->hwlock, flags);
646 ph_command(isac, ISAC_CMD_AR8);
647 spin_unlock_irqrestore(isac->hwlock, flags);
648 break;
649 case INFO3_P10:
650 spin_lock_irqsave(isac->hwlock, flags);
651 ph_command(isac, ISAC_CMD_AR10);
652 spin_unlock_irqrestore(isac->hwlock, flags);
653 break;
654 case HW_RESET_REQ:
655 spin_lock_irqsave(isac->hwlock, flags);
656 if ((isac->state == ISAC_IND_EI) ||
657 (isac->state == ISAC_IND_DR) ||
658 (isac->state == ISAC_IND_RS))
659 ph_command(isac, ISAC_CMD_TIM);
660 else
661 ph_command(isac, ISAC_CMD_RS);
662 spin_unlock_irqrestore(isac->hwlock, flags);
663 break;
664 case HW_DEACT_REQ:
665 skb_queue_purge(&dch->squeue);
666 if (dch->tx_skb) {
667 dev_kfree_skb(dch->tx_skb);
668 dch->tx_skb = NULL;
669 }
670 dch->tx_idx = 0;
671 if (dch->rx_skb) {
672 dev_kfree_skb(dch->rx_skb);
673 dch->rx_skb = NULL;
674 }
675 test_and_clear_bit(FLG_TX_BUSY, &dch->Flags);
676 if (test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags))
677 del_timer(&dch->timer);
678 break;
679 case HW_POWERUP_REQ:
680 spin_lock_irqsave(isac->hwlock, flags);
681 ph_command(isac, ISAC_CMD_TIM);
682 spin_unlock_irqrestore(isac->hwlock, flags);
683 break;
684 case PH_ACTIVATE_IND:
685 test_and_set_bit(FLG_ACTIVE, &dch->Flags);
686 _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL,
687 GFP_ATOMIC);
688 break;
689 case PH_DEACTIVATE_IND:
690 test_and_clear_bit(FLG_ACTIVE, &dch->Flags);
691 _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL,
692 GFP_ATOMIC);
693 break;
694 default:
695 pr_debug("%s: %s unknown command %x\n", isac->name,
696 __func__, cmd);
697 return -1;
698 }
699 return 0;
700 }
701
702 static void
703 isac_release(struct isac_hw *isac)
704 {
705 if (isac->type & IPAC_TYPE_ISACX)
706 WriteISAC(isac, ISACX_MASK, 0xff);
707 else
708 WriteISAC(isac, ISAC_MASK, 0xff);
709 if (isac->dch.timer.function != NULL) {
710 del_timer(&isac->dch.timer);
711 isac->dch.timer.function = NULL;
712 }
713 kfree(isac->mon_rx);
714 isac->mon_rx = NULL;
715 kfree(isac->mon_tx);
716 isac->mon_tx = NULL;
717 if (isac->dch.l1)
718 l1_event(isac->dch.l1, CLOSE_CHANNEL);
719 mISDN_freedchannel(&isac->dch);
720 }
721
722 static void
723 dbusy_timer_handler(struct isac_hw *isac)
724 {
725 int rbch, star;
726 u_long flags;
727
728 if (test_bit(FLG_BUSY_TIMER, &isac->dch.Flags)) {
729 spin_lock_irqsave(isac->hwlock, flags);
730 rbch = ReadISAC(isac, ISAC_RBCH);
731 star = ReadISAC(isac, ISAC_STAR);
732 pr_debug("%s: D-Channel Busy RBCH %02x STAR %02x\n",
733 isac->name, rbch, star);
734 if (rbch & ISAC_RBCH_XAC) /* D-Channel Busy */
735 test_and_set_bit(FLG_L1_BUSY, &isac->dch.Flags);
736 else {
737 /* discard frame; reset transceiver */
738 test_and_clear_bit(FLG_BUSY_TIMER, &isac->dch.Flags);
739 if (isac->dch.tx_idx)
740 isac->dch.tx_idx = 0;
741 else
742 pr_info("%s: ISAC D-Channel Busy no tx_idx\n",
743 isac->name);
744 /* Transmitter reset */
745 WriteISAC(isac, ISAC_CMDR, 0x01);
746 }
747 spin_unlock_irqrestore(isac->hwlock, flags);
748 }
749 }
750
751 static int
752 open_dchannel(struct isac_hw *isac, struct channel_req *rq)
753 {
754 pr_debug("%s: %s dev(%d) open from %p\n", isac->name, __func__,
755 isac->dch.dev.id, __builtin_return_address(1));
756 if (rq->protocol != ISDN_P_TE_S0)
757 return -EINVAL;
758 if (rq->adr.channel == 1)
759 /* E-Channel not supported */
760 return -EINVAL;
761 rq->ch = &isac->dch.dev.D;
762 rq->ch->protocol = rq->protocol;
763 if (isac->dch.state == 7)
764 _queue_data(rq->ch, PH_ACTIVATE_IND, MISDN_ID_ANY,
765 0, NULL, GFP_KERNEL);
766 return 0;
767 }
768
769 static const char *ISACVer[] =
770 {"2086/2186 V1.1", "2085 B1", "2085 B2",
771 "2085 V2.3"};
772
773 static int
774 isac_init(struct isac_hw *isac)
775 {
776 u8 val;
777 int err = 0;
778
779 if (!isac->dch.l1) {
780 err = create_l1(&isac->dch, isac_l1cmd);
781 if (err)
782 return err;
783 }
784 isac->mon_tx = NULL;
785 isac->mon_rx = NULL;
786 isac->dch.timer.function = (void *) dbusy_timer_handler;
787 isac->dch.timer.data = (long)isac;
788 init_timer(&isac->dch.timer);
789 isac->mocr = 0xaa;
790 if (isac->type & IPAC_TYPE_ISACX) {
791 /* Disable all IRQ */
792 WriteISAC(isac, ISACX_MASK, 0xff);
793 val = ReadISAC(isac, ISACX_STARD);
794 pr_debug("%s: ISACX STARD %x\n", isac->name, val);
795 val = ReadISAC(isac, ISACX_ISTAD);
796 pr_debug("%s: ISACX ISTAD %x\n", isac->name, val);
797 val = ReadISAC(isac, ISACX_ISTA);
798 pr_debug("%s: ISACX ISTA %x\n", isac->name, val);
799 /* clear LDD */
800 WriteISAC(isac, ISACX_TR_CONF0, 0x00);
801 /* enable transmitter */
802 WriteISAC(isac, ISACX_TR_CONF2, 0x00);
803 /* transparent mode 0, RAC, stop/go */
804 WriteISAC(isac, ISACX_MODED, 0xc9);
805 /* all HDLC IRQ unmasked */
806 val = ReadISAC(isac, ISACX_ID);
807 if (isac->dch.debug & DEBUG_HW)
808 pr_notice("%s: ISACX Design ID %x\n",
809 isac->name, val & 0x3f);
810 val = ReadISAC(isac, ISACX_CIR0);
811 pr_debug("%s: ISACX CIR0 %02X\n", isac->name, val);
812 isac->state = val >> 4;
813 isac_ph_state_change(isac);
814 ph_command(isac, ISAC_CMD_RS);
815 WriteISAC(isac, ISACX_MASK, IPACX__ON);
816 WriteISAC(isac, ISACX_MASKD, 0x00);
817 } else { /* old isac */
818 WriteISAC(isac, ISAC_MASK, 0xff);
819 val = ReadISAC(isac, ISAC_STAR);
820 pr_debug("%s: ISAC STAR %x\n", isac->name, val);
821 val = ReadISAC(isac, ISAC_MODE);
822 pr_debug("%s: ISAC MODE %x\n", isac->name, val);
823 val = ReadISAC(isac, ISAC_ADF2);
824 pr_debug("%s: ISAC ADF2 %x\n", isac->name, val);
825 val = ReadISAC(isac, ISAC_ISTA);
826 pr_debug("%s: ISAC ISTA %x\n", isac->name, val);
827 if (val & 0x01) {
828 val = ReadISAC(isac, ISAC_EXIR);
829 pr_debug("%s: ISAC EXIR %x\n", isac->name, val);
830 }
831 val = ReadISAC(isac, ISAC_RBCH);
832 if (isac->dch.debug & DEBUG_HW)
833 pr_notice("%s: ISAC version (%x): %s\n", isac->name,
834 val, ISACVer[(val >> 5) & 3]);
835 isac->type |= ((val >> 5) & 3);
836 if (!isac->adf2)
837 isac->adf2 = 0x80;
838 if (!(isac->adf2 & 0x80)) { /* only IOM 2 Mode */
839 pr_info("%s: only support IOM2 mode but adf2=%02x\n",
840 isac->name, isac->adf2);
841 isac_release(isac);
842 return -EINVAL;
843 }
844 WriteISAC(isac, ISAC_ADF2, isac->adf2);
845 WriteISAC(isac, ISAC_SQXR, 0x2f);
846 WriteISAC(isac, ISAC_SPCR, 0x00);
847 WriteISAC(isac, ISAC_STCR, 0x70);
848 WriteISAC(isac, ISAC_MODE, 0xc9);
849 WriteISAC(isac, ISAC_TIMR, 0x00);
850 WriteISAC(isac, ISAC_ADF1, 0x00);
851 val = ReadISAC(isac, ISAC_CIR0);
852 pr_debug("%s: ISAC CIR0 %x\n", isac->name, val);
853 isac->state = (val >> 2) & 0xf;
854 isac_ph_state_change(isac);
855 ph_command(isac, ISAC_CMD_RS);
856 WriteISAC(isac, ISAC_MASK, 0);
857 }
858 return err;
859 }
860
861 int
862 mISDNisac_init(struct isac_hw *isac, void *hw)
863 {
864 mISDN_initdchannel(&isac->dch, MAX_DFRAME_LEN_L1, isac_ph_state_bh);
865 isac->dch.hw = hw;
866 isac->dch.dev.D.send = isac_l1hw;
867 isac->init = isac_init;
868 isac->release = isac_release;
869 isac->ctrl = isac_ctrl;
870 isac->open = open_dchannel;
871 isac->dch.dev.Dprotocols = (1 << ISDN_P_TE_S0);
872 isac->dch.dev.nrbchan = 2;
873 return 0;
874 }
875 EXPORT_SYMBOL(mISDNisac_init);
876
877 static void
878 waitforCEC(struct hscx_hw *hx)
879 {
880 u8 starb, to = 50;
881
882 while (to) {
883 starb = ReadHSCX(hx, IPAC_STARB);
884 if (!(starb & 0x04))
885 break;
886 udelay(1);
887 to--;
888 }
889 if (to < 50)
890 pr_debug("%s: B%1d CEC %d us\n", hx->ip->name, hx->bch.nr,
891 50 - to);
892 if (!to)
893 pr_info("%s: B%1d CEC timeout\n", hx->ip->name, hx->bch.nr);
894 }
895
896
897 static void
898 waitforXFW(struct hscx_hw *hx)
899 {
900 u8 starb, to = 50;
901
902 while (to) {
903 starb = ReadHSCX(hx, IPAC_STARB);
904 if ((starb & 0x44) == 0x40)
905 break;
906 udelay(1);
907 to--;
908 }
909 if (to < 50)
910 pr_debug("%s: B%1d XFW %d us\n", hx->ip->name, hx->bch.nr,
911 50 - to);
912 if (!to)
913 pr_info("%s: B%1d XFW timeout\n", hx->ip->name, hx->bch.nr);
914 }
915
916 static void
917 hscx_cmdr(struct hscx_hw *hx, u8 cmd)
918 {
919 if (hx->ip->type & IPAC_TYPE_IPACX)
920 WriteHSCX(hx, IPACX_CMDRB, cmd);
921 else {
922 waitforCEC(hx);
923 WriteHSCX(hx, IPAC_CMDRB, cmd);
924 }
925 }
926
927 static void
928 hscx_empty_fifo(struct hscx_hw *hscx, u8 count)
929 {
930 u8 *p;
931
932 pr_debug("%s: B%1d %d\n", hscx->ip->name, hscx->bch.nr, count);
933 if (!hscx->bch.rx_skb) {
934 hscx->bch.rx_skb = mI_alloc_skb(hscx->bch.maxlen, GFP_ATOMIC);
935 if (!hscx->bch.rx_skb) {
936 pr_info("%s: B receive out of memory\n",
937 hscx->ip->name);
938 hscx_cmdr(hscx, 0x80); /* RMC */
939 return;
940 }
941 }
942 if ((hscx->bch.rx_skb->len + count) > hscx->bch.maxlen) {
943 pr_debug("%s: overrun %d\n", hscx->ip->name,
944 hscx->bch.rx_skb->len + count);
945 skb_trim(hscx->bch.rx_skb, 0);
946 hscx_cmdr(hscx, 0x80); /* RMC */
947 return;
948 }
949 p = skb_put(hscx->bch.rx_skb, count);
950
951 if (hscx->ip->type & IPAC_TYPE_IPACX)
952 hscx->ip->read_fifo(hscx->ip->hw,
953 hscx->off + IPACX_RFIFOB, p, count);
954 else
955 hscx->ip->read_fifo(hscx->ip->hw,
956 hscx->off, p, count);
957
958 hscx_cmdr(hscx, 0x80); /* RMC */
959
960 if (hscx->bch.debug & DEBUG_HW_BFIFO) {
961 snprintf(hscx->log, 64, "B%1d-recv %s %d ",
962 hscx->bch.nr, hscx->ip->name, count);
963 print_hex_dump_bytes(hscx->log, DUMP_PREFIX_OFFSET, p, count);
964 }
965 }
966
967 static void
968 hscx_fill_fifo(struct hscx_hw *hscx)
969 {
970 int count, more;
971 u8 *p;
972
973 if (!hscx->bch.tx_skb)
974 return;
975 count = hscx->bch.tx_skb->len - hscx->bch.tx_idx;
976 if (count <= 0)
977 return;
978 p = hscx->bch.tx_skb->data + hscx->bch.tx_idx;
979
980 more = test_bit(FLG_TRANSPARENT, &hscx->bch.Flags) ? 1 : 0;
981 if (count > hscx->fifo_size) {
982 count = hscx->fifo_size;
983 more = 1;
984 }
985 pr_debug("%s: B%1d %d/%d/%d\n", hscx->ip->name, hscx->bch.nr, count,
986 hscx->bch.tx_idx, hscx->bch.tx_skb->len);
987 hscx->bch.tx_idx += count;
988
989 if (hscx->ip->type & IPAC_TYPE_IPACX)
990 hscx->ip->write_fifo(hscx->ip->hw,
991 hscx->off + IPACX_XFIFOB, p, count);
992 else {
993 waitforXFW(hscx);
994 hscx->ip->write_fifo(hscx->ip->hw,
995 hscx->off, p, count);
996 }
997 hscx_cmdr(hscx, more ? 0x08 : 0x0a);
998
999 if (hscx->bch.debug & DEBUG_HW_BFIFO) {
1000 snprintf(hscx->log, 64, "B%1d-send %s %d ",
1001 hscx->bch.nr, hscx->ip->name, count);
1002 print_hex_dump_bytes(hscx->log, DUMP_PREFIX_OFFSET, p, count);
1003 }
1004 }
1005
1006 static void
1007 hscx_xpr(struct hscx_hw *hx)
1008 {
1009 if (hx->bch.tx_skb && hx->bch.tx_idx < hx->bch.tx_skb->len)
1010 hscx_fill_fifo(hx);
1011 else {
1012 if (hx->bch.tx_skb) {
1013 /* send confirm, on trans, free on hdlc. */
1014 if (test_bit(FLG_TRANSPARENT, &hx->bch.Flags))
1015 confirm_Bsend(&hx->bch);
1016 dev_kfree_skb(hx->bch.tx_skb);
1017 }
1018 if (get_next_bframe(&hx->bch))
1019 hscx_fill_fifo(hx);
1020 }
1021 }
1022
1023 static void
1024 ipac_rme(struct hscx_hw *hx)
1025 {
1026 int count;
1027 u8 rstab;
1028
1029 if (hx->ip->type & IPAC_TYPE_IPACX)
1030 rstab = ReadHSCX(hx, IPACX_RSTAB);
1031 else
1032 rstab = ReadHSCX(hx, IPAC_RSTAB);
1033 pr_debug("%s: B%1d RSTAB %02x\n", hx->ip->name, hx->bch.nr, rstab);
1034 if ((rstab & 0xf0) != 0xa0) {
1035 /* !(VFR && !RDO && CRC && !RAB) */
1036 if (!(rstab & 0x80)) {
1037 if (hx->bch.debug & DEBUG_HW_BCHANNEL)
1038 pr_notice("%s: B%1d invalid frame\n",
1039 hx->ip->name, hx->bch.nr);
1040 }
1041 if (rstab & 0x40) {
1042 if (hx->bch.debug & DEBUG_HW_BCHANNEL)
1043 pr_notice("%s: B%1d RDO proto=%x\n",
1044 hx->ip->name, hx->bch.nr,
1045 hx->bch.state);
1046 }
1047 if (!(rstab & 0x20)) {
1048 if (hx->bch.debug & DEBUG_HW_BCHANNEL)
1049 pr_notice("%s: B%1d CRC error\n",
1050 hx->ip->name, hx->bch.nr);
1051 }
1052 hscx_cmdr(hx, 0x80); /* Do RMC */
1053 return;
1054 }
1055 if (hx->ip->type & IPAC_TYPE_IPACX)
1056 count = ReadHSCX(hx, IPACX_RBCLB);
1057 else
1058 count = ReadHSCX(hx, IPAC_RBCLB);
1059 count &= (hx->fifo_size - 1);
1060 if (count == 0)
1061 count = hx->fifo_size;
1062 hscx_empty_fifo(hx, count);
1063 if (!hx->bch.rx_skb)
1064 return;
1065 if (hx->bch.rx_skb->len < 2) {
1066 pr_debug("%s: B%1d frame to short %d\n",
1067 hx->ip->name, hx->bch.nr, hx->bch.rx_skb->len);
1068 skb_trim(hx->bch.rx_skb, 0);
1069 } else {
1070 skb_trim(hx->bch.rx_skb, hx->bch.rx_skb->len - 1);
1071 recv_Bchannel(&hx->bch, 0);
1072 }
1073 }
1074
1075 static void
1076 ipac_irq(struct hscx_hw *hx, u8 ista)
1077 {
1078 u8 istab, m, exirb = 0;
1079
1080 if (hx->ip->type & IPAC_TYPE_IPACX)
1081 istab = ReadHSCX(hx, IPACX_ISTAB);
1082 else if (hx->ip->type & IPAC_TYPE_IPAC) {
1083 istab = ReadHSCX(hx, IPAC_ISTAB);
1084 m = (hx->bch.nr & 1) ? IPAC__EXA : IPAC__EXB;
1085 if (m & ista) {
1086 exirb = ReadHSCX(hx, IPAC_EXIRB);
1087 pr_debug("%s: B%1d EXIRB %02x\n", hx->ip->name,
1088 hx->bch.nr, exirb);
1089 }
1090 } else if (hx->bch.nr & 2) { /* HSCX B */
1091 if (ista & (HSCX__EXA | HSCX__ICA))
1092 ipac_irq(&hx->ip->hscx[0], ista);
1093 if (ista & HSCX__EXB) {
1094 exirb = ReadHSCX(hx, IPAC_EXIRB);
1095 pr_debug("%s: B%1d EXIRB %02x\n", hx->ip->name,
1096 hx->bch.nr, exirb);
1097 }
1098 istab = ista & 0xF8;
1099 } else { /* HSCX A */
1100 istab = ReadHSCX(hx, IPAC_ISTAB);
1101 if (ista & HSCX__EXA) {
1102 exirb = ReadHSCX(hx, IPAC_EXIRB);
1103 pr_debug("%s: B%1d EXIRB %02x\n", hx->ip->name,
1104 hx->bch.nr, exirb);
1105 }
1106 istab = istab & 0xF8;
1107 }
1108 if (exirb & IPAC_B_XDU)
1109 istab |= IPACX_B_XDU;
1110 if (exirb & IPAC_B_RFO)
1111 istab |= IPACX_B_RFO;
1112 pr_debug("%s: B%1d ISTAB %02x\n", hx->ip->name, hx->bch.nr, istab);
1113
1114 if (!test_bit(FLG_ACTIVE, &hx->bch.Flags))
1115 return;
1116
1117 if (istab & IPACX_B_RME)
1118 ipac_rme(hx);
1119
1120 if (istab & IPACX_B_RPF) {
1121 hscx_empty_fifo(hx, hx->fifo_size);
1122 if (test_bit(FLG_TRANSPARENT, &hx->bch.Flags)) {
1123 /* receive transparent audio data */
1124 if (hx->bch.rx_skb)
1125 recv_Bchannel(&hx->bch, 0);
1126 }
1127 }
1128
1129 if (istab & IPACX_B_RFO) {
1130 pr_debug("%s: B%1d RFO error\n", hx->ip->name, hx->bch.nr);
1131 hscx_cmdr(hx, 0x40); /* RRES */
1132 }
1133
1134 if (istab & IPACX_B_XPR)
1135 hscx_xpr(hx);
1136
1137 if (istab & IPACX_B_XDU) {
1138 if (test_bit(FLG_TRANSPARENT, &hx->bch.Flags)) {
1139 hscx_fill_fifo(hx);
1140 return;
1141 }
1142 pr_debug("%s: B%1d XDU error at len %d\n", hx->ip->name,
1143 hx->bch.nr, hx->bch.tx_idx);
1144 hx->bch.tx_idx = 0;
1145 hscx_cmdr(hx, 0x01); /* XRES */
1146 }
1147 }
1148
1149 irqreturn_t
1150 mISDNipac_irq(struct ipac_hw *ipac, int maxloop)
1151 {
1152 int cnt = maxloop + 1;
1153 u8 ista, istad;
1154 struct isac_hw *isac = &ipac->isac;
1155
1156 if (ipac->type & IPAC_TYPE_IPACX) {
1157 ista = ReadIPAC(ipac, ISACX_ISTA);
1158 while (ista && cnt--) {
1159 pr_debug("%s: ISTA %02x\n", ipac->name, ista);
1160 if (ista & IPACX__ICA)
1161 ipac_irq(&ipac->hscx[0], ista);
1162 if (ista & IPACX__ICB)
1163 ipac_irq(&ipac->hscx[1], ista);
1164 if (ista & (ISACX__ICD | ISACX__CIC))
1165 mISDNisac_irq(&ipac->isac, ista);
1166 ista = ReadIPAC(ipac, ISACX_ISTA);
1167 }
1168 } else if (ipac->type & IPAC_TYPE_IPAC) {
1169 ista = ReadIPAC(ipac, IPAC_ISTA);
1170 while (ista && cnt--) {
1171 pr_debug("%s: ISTA %02x\n", ipac->name, ista);
1172 if (ista & (IPAC__ICD | IPAC__EXD)) {
1173 istad = ReadISAC(isac, ISAC_ISTA);
1174 pr_debug("%s: ISTAD %02x\n", ipac->name, istad);
1175 if (istad & IPAC_D_TIN2)
1176 pr_debug("%s TIN2 irq\n", ipac->name);
1177 if (ista & IPAC__EXD)
1178 istad |= 1; /* ISAC EXI */
1179 mISDNisac_irq(isac, istad);
1180 }
1181 if (ista & (IPAC__ICA | IPAC__EXA))
1182 ipac_irq(&ipac->hscx[0], ista);
1183 if (ista & (IPAC__ICB | IPAC__EXB))
1184 ipac_irq(&ipac->hscx[1], ista);
1185 ista = ReadIPAC(ipac, IPAC_ISTA);
1186 }
1187 } else if (ipac->type & IPAC_TYPE_HSCX) {
1188 while (cnt) {
1189 ista = ReadIPAC(ipac, IPAC_ISTAB + ipac->hscx[1].off);
1190 pr_debug("%s: B2 ISTA %02x\n", ipac->name, ista);
1191 if (ista)
1192 ipac_irq(&ipac->hscx[1], ista);
1193 istad = ReadISAC(isac, ISAC_ISTA);
1194 pr_debug("%s: ISTAD %02x\n", ipac->name, istad);
1195 if (istad)
1196 mISDNisac_irq(isac, istad);
1197 if (0 == (ista | istad))
1198 break;
1199 cnt--;
1200 }
1201 }
1202 if (cnt > maxloop) /* only for ISAC/HSCX without PCI IRQ test */
1203 return IRQ_NONE;
1204 if (cnt < maxloop)
1205 pr_debug("%s: %d irqloops cpu%d\n", ipac->name,
1206 maxloop - cnt, smp_processor_id());
1207 if (maxloop && !cnt)
1208 pr_notice("%s: %d IRQ LOOP cpu%d\n", ipac->name,
1209 maxloop, smp_processor_id());
1210 return IRQ_HANDLED;
1211 }
1212 EXPORT_SYMBOL(mISDNipac_irq);
1213
1214 static int
1215 hscx_mode(struct hscx_hw *hscx, u32 bprotocol)
1216 {
1217 pr_debug("%s: HSCX %c protocol %x-->%x ch %d\n", hscx->ip->name,
1218 '@' + hscx->bch.nr, hscx->bch.state, bprotocol, hscx->bch.nr);
1219 if (hscx->ip->type & IPAC_TYPE_IPACX) {
1220 if (hscx->bch.nr & 1) { /* B1 and ICA */
1221 WriteIPAC(hscx->ip, ISACX_BCHA_TSDP_BC1, 0x80);
1222 WriteIPAC(hscx->ip, ISACX_BCHA_CR, 0x88);
1223 } else { /* B2 and ICB */
1224 WriteIPAC(hscx->ip, ISACX_BCHB_TSDP_BC1, 0x81);
1225 WriteIPAC(hscx->ip, ISACX_BCHB_CR, 0x88);
1226 }
1227 switch (bprotocol) {
1228 case ISDN_P_NONE: /* init */
1229 WriteHSCX(hscx, IPACX_MODEB, 0xC0); /* rec off */
1230 WriteHSCX(hscx, IPACX_EXMB, 0x30); /* std adj. */
1231 WriteHSCX(hscx, IPACX_MASKB, 0xFF); /* ints off */
1232 hscx_cmdr(hscx, 0x41);
1233 test_and_clear_bit(FLG_HDLC, &hscx->bch.Flags);
1234 test_and_clear_bit(FLG_TRANSPARENT, &hscx->bch.Flags);
1235 break;
1236 case ISDN_P_B_RAW:
1237 WriteHSCX(hscx, IPACX_MODEB, 0x88); /* ex trans */
1238 WriteHSCX(hscx, IPACX_EXMB, 0x00); /* trans */
1239 hscx_cmdr(hscx, 0x41);
1240 WriteHSCX(hscx, IPACX_MASKB, IPACX_B_ON);
1241 test_and_set_bit(FLG_TRANSPARENT, &hscx->bch.Flags);
1242 break;
1243 case ISDN_P_B_HDLC:
1244 WriteHSCX(hscx, IPACX_MODEB, 0xC0); /* trans */
1245 WriteHSCX(hscx, IPACX_EXMB, 0x00); /* hdlc,crc */
1246 hscx_cmdr(hscx, 0x41);
1247 WriteHSCX(hscx, IPACX_MASKB, IPACX_B_ON);
1248 test_and_set_bit(FLG_HDLC, &hscx->bch.Flags);
1249 break;
1250 default:
1251 pr_info("%s: protocol not known %x\n", hscx->ip->name,
1252 bprotocol);
1253 return -ENOPROTOOPT;
1254 }
1255 } else if (hscx->ip->type & IPAC_TYPE_IPAC) { /* IPAC */
1256 WriteHSCX(hscx, IPAC_CCR1, 0x82);
1257 WriteHSCX(hscx, IPAC_CCR2, 0x30);
1258 WriteHSCX(hscx, IPAC_XCCR, 0x07);
1259 WriteHSCX(hscx, IPAC_RCCR, 0x07);
1260 WriteHSCX(hscx, IPAC_TSAX, hscx->slot);
1261 WriteHSCX(hscx, IPAC_TSAR, hscx->slot);
1262 switch (bprotocol) {
1263 case ISDN_P_NONE:
1264 WriteHSCX(hscx, IPAC_TSAX, 0x1F);
1265 WriteHSCX(hscx, IPAC_TSAR, 0x1F);
1266 WriteHSCX(hscx, IPAC_MODEB, 0x84);
1267 WriteHSCX(hscx, IPAC_CCR1, 0x82);
1268 WriteHSCX(hscx, IPAC_MASKB, 0xFF); /* ints off */
1269 test_and_clear_bit(FLG_HDLC, &hscx->bch.Flags);
1270 test_and_clear_bit(FLG_TRANSPARENT, &hscx->bch.Flags);
1271 break;
1272 case ISDN_P_B_RAW:
1273 WriteHSCX(hscx, IPAC_MODEB, 0xe4); /* ex trans */
1274 WriteHSCX(hscx, IPAC_CCR1, 0x82);
1275 hscx_cmdr(hscx, 0x41);
1276 WriteHSCX(hscx, IPAC_MASKB, 0);
1277 test_and_set_bit(FLG_TRANSPARENT, &hscx->bch.Flags);
1278 break;
1279 case ISDN_P_B_HDLC:
1280 WriteHSCX(hscx, IPAC_MODEB, 0x8c);
1281 WriteHSCX(hscx, IPAC_CCR1, 0x8a);
1282 hscx_cmdr(hscx, 0x41);
1283 WriteHSCX(hscx, IPAC_MASKB, 0);
1284 test_and_set_bit(FLG_HDLC, &hscx->bch.Flags);
1285 break;
1286 default:
1287 pr_info("%s: protocol not known %x\n", hscx->ip->name,
1288 bprotocol);
1289 return -ENOPROTOOPT;
1290 }
1291 } else if (hscx->ip->type & IPAC_TYPE_HSCX) { /* HSCX */
1292 WriteHSCX(hscx, IPAC_CCR1, 0x85);
1293 WriteHSCX(hscx, IPAC_CCR2, 0x30);
1294 WriteHSCX(hscx, IPAC_XCCR, 0x07);
1295 WriteHSCX(hscx, IPAC_RCCR, 0x07);
1296 WriteHSCX(hscx, IPAC_TSAX, hscx->slot);
1297 WriteHSCX(hscx, IPAC_TSAR, hscx->slot);
1298 switch (bprotocol) {
1299 case ISDN_P_NONE:
1300 WriteHSCX(hscx, IPAC_TSAX, 0x1F);
1301 WriteHSCX(hscx, IPAC_TSAR, 0x1F);
1302 WriteHSCX(hscx, IPAC_MODEB, 0x84);
1303 WriteHSCX(hscx, IPAC_CCR1, 0x85);
1304 WriteHSCX(hscx, IPAC_MASKB, 0xFF); /* ints off */
1305 test_and_clear_bit(FLG_HDLC, &hscx->bch.Flags);
1306 test_and_clear_bit(FLG_TRANSPARENT, &hscx->bch.Flags);
1307 break;
1308 case ISDN_P_B_RAW:
1309 WriteHSCX(hscx, IPAC_MODEB, 0xe4); /* ex trans */
1310 WriteHSCX(hscx, IPAC_CCR1, 0x85);
1311 hscx_cmdr(hscx, 0x41);
1312 WriteHSCX(hscx, IPAC_MASKB, 0);
1313 test_and_set_bit(FLG_TRANSPARENT, &hscx->bch.Flags);
1314 break;
1315 case ISDN_P_B_HDLC:
1316 WriteHSCX(hscx, IPAC_MODEB, 0x8c);
1317 WriteHSCX(hscx, IPAC_CCR1, 0x8d);
1318 hscx_cmdr(hscx, 0x41);
1319 WriteHSCX(hscx, IPAC_MASKB, 0);
1320 test_and_set_bit(FLG_HDLC, &hscx->bch.Flags);
1321 break;
1322 default:
1323 pr_info("%s: protocol not known %x\n", hscx->ip->name,
1324 bprotocol);
1325 return -ENOPROTOOPT;
1326 }
1327 } else
1328 return -EINVAL;
1329 hscx->bch.state = bprotocol;
1330 return 0;
1331 }
1332
1333 static int
1334 hscx_l2l1(struct mISDNchannel *ch, struct sk_buff *skb)
1335 {
1336 struct bchannel *bch = container_of(ch, struct bchannel, ch);
1337 struct hscx_hw *hx = container_of(bch, struct hscx_hw, bch);
1338 int ret = -EINVAL;
1339 struct mISDNhead *hh = mISDN_HEAD_P(skb);
1340 u32 id;
1341 u_long flags;
1342
1343 switch (hh->prim) {
1344 case PH_DATA_REQ:
1345 spin_lock_irqsave(hx->ip->hwlock, flags);
1346 ret = bchannel_senddata(bch, skb);
1347 if (ret > 0) { /* direct TX */
1348 id = hh->id; /* skb can be freed */
1349 ret = 0;
1350 hscx_fill_fifo(hx);
1351 spin_unlock_irqrestore(hx->ip->hwlock, flags);
1352 if (!test_bit(FLG_TRANSPARENT, &bch->Flags))
1353 queue_ch_frame(ch, PH_DATA_CNF, id, NULL);
1354 } else
1355 spin_unlock_irqrestore(hx->ip->hwlock, flags);
1356 return ret;
1357 case PH_ACTIVATE_REQ:
1358 spin_lock_irqsave(hx->ip->hwlock, flags);
1359 if (!test_and_set_bit(FLG_ACTIVE, &bch->Flags))
1360 ret = hscx_mode(hx, ch->protocol);
1361 else
1362 ret = 0;
1363 spin_unlock_irqrestore(hx->ip->hwlock, flags);
1364 if (!ret)
1365 _queue_data(ch, PH_ACTIVATE_IND, MISDN_ID_ANY, 0,
1366 NULL, GFP_KERNEL);
1367 break;
1368 case PH_DEACTIVATE_REQ:
1369 spin_lock_irqsave(hx->ip->hwlock, flags);
1370 mISDN_clear_bchannel(bch);
1371 hscx_mode(hx, ISDN_P_NONE);
1372 spin_unlock_irqrestore(hx->ip->hwlock, flags);
1373 _queue_data(ch, PH_DEACTIVATE_IND, MISDN_ID_ANY, 0,
1374 NULL, GFP_KERNEL);
1375 ret = 0;
1376 break;
1377 default:
1378 pr_info("%s: %s unknown prim(%x,%x)\n",
1379 hx->ip->name, __func__, hh->prim, hh->id);
1380 ret = -EINVAL;
1381 }
1382 if (!ret)
1383 dev_kfree_skb(skb);
1384 return ret;
1385 }
1386
1387 static int
1388 channel_bctrl(struct bchannel *bch, struct mISDN_ctrl_req *cq)
1389 {
1390 int ret = 0;
1391
1392 switch (cq->op) {
1393 case MISDN_CTRL_GETOP:
1394 cq->op = 0;
1395 break;
1396 /* Nothing implemented yet */
1397 case MISDN_CTRL_FILL_EMPTY:
1398 default:
1399 pr_info("%s: unknown Op %x\n", __func__, cq->op);
1400 ret = -EINVAL;
1401 break;
1402 }
1403 return ret;
1404 }
1405
1406 static int
1407 hscx_bctrl(struct mISDNchannel *ch, u32 cmd, void *arg)
1408 {
1409 struct bchannel *bch = container_of(ch, struct bchannel, ch);
1410 struct hscx_hw *hx = container_of(bch, struct hscx_hw, bch);
1411 int ret = -EINVAL;
1412 u_long flags;
1413
1414 pr_debug("%s: %s cmd:%x %p\n", hx->ip->name, __func__, cmd, arg);
1415 switch (cmd) {
1416 case CLOSE_CHANNEL:
1417 test_and_clear_bit(FLG_OPEN, &bch->Flags);
1418 if (test_bit(FLG_ACTIVE, &bch->Flags)) {
1419 spin_lock_irqsave(hx->ip->hwlock, flags);
1420 mISDN_freebchannel(bch);
1421 hscx_mode(hx, ISDN_P_NONE);
1422 spin_unlock_irqrestore(hx->ip->hwlock, flags);
1423 } else {
1424 skb_queue_purge(&bch->rqueue);
1425 bch->rcount = 0;
1426 }
1427 ch->protocol = ISDN_P_NONE;
1428 ch->peer = NULL;
1429 module_put(hx->ip->owner);
1430 ret = 0;
1431 break;
1432 case CONTROL_CHANNEL:
1433 ret = channel_bctrl(bch, arg);
1434 break;
1435 default:
1436 pr_info("%s: %s unknown prim(%x)\n",
1437 hx->ip->name, __func__, cmd);
1438 }
1439 return ret;
1440 }
1441
1442 static void
1443 free_ipac(struct ipac_hw *ipac)
1444 {
1445 isac_release(&ipac->isac);
1446 }
1447
1448 static const char *HSCXVer[] =
1449 {"A1", "?1", "A2", "?3", "A3", "V2.1", "?6", "?7",
1450 "?8", "?9", "?10", "?11", "?12", "?13", "?14", "???"};
1451
1452
1453
1454 static void
1455 hscx_init(struct hscx_hw *hx)
1456 {
1457 u8 val;
1458
1459 WriteHSCX(hx, IPAC_RAH2, 0xFF);
1460 WriteHSCX(hx, IPAC_XBCH, 0x00);
1461 WriteHSCX(hx, IPAC_RLCR, 0x00);
1462
1463 if (hx->ip->type & IPAC_TYPE_HSCX) {
1464 WriteHSCX(hx, IPAC_CCR1, 0x85);
1465 val = ReadHSCX(hx, HSCX_VSTR);
1466 pr_debug("%s: HSCX VSTR %02x\n", hx->ip->name, val);
1467 if (hx->bch.debug & DEBUG_HW)
1468 pr_notice("%s: HSCX version %s\n", hx->ip->name,
1469 HSCXVer[val & 0x0f]);
1470 } else
1471 WriteHSCX(hx, IPAC_CCR1, 0x82);
1472 WriteHSCX(hx, IPAC_CCR2, 0x30);
1473 WriteHSCX(hx, IPAC_XCCR, 0x07);
1474 WriteHSCX(hx, IPAC_RCCR, 0x07);
1475 }
1476
1477 static int
1478 ipac_init(struct ipac_hw *ipac)
1479 {
1480 u8 val;
1481
1482 if (ipac->type & IPAC_TYPE_HSCX) {
1483 hscx_init(&ipac->hscx[0]);
1484 hscx_init(&ipac->hscx[1]);
1485 val = ReadIPAC(ipac, IPAC_ID);
1486 } else if (ipac->type & IPAC_TYPE_IPAC) {
1487 hscx_init(&ipac->hscx[0]);
1488 hscx_init(&ipac->hscx[1]);
1489 WriteIPAC(ipac, IPAC_MASK, IPAC__ON);
1490 val = ReadIPAC(ipac, IPAC_CONF);
1491 /* conf is default 0, but can be overwritten by card setup */
1492 pr_debug("%s: IPAC CONF %02x/%02x\n", ipac->name,
1493 val, ipac->conf);
1494 WriteIPAC(ipac, IPAC_CONF, ipac->conf);
1495 val = ReadIPAC(ipac, IPAC_ID);
1496 if (ipac->hscx[0].bch.debug & DEBUG_HW)
1497 pr_notice("%s: IPAC Design ID %02x\n", ipac->name, val);
1498 }
1499 /* nothing special for IPACX to do here */
1500 return isac_init(&ipac->isac);
1501 }
1502
1503 static int
1504 open_bchannel(struct ipac_hw *ipac, struct channel_req *rq)
1505 {
1506 struct bchannel *bch;
1507
1508 if (rq->adr.channel > 2)
1509 return -EINVAL;
1510 if (rq->protocol == ISDN_P_NONE)
1511 return -EINVAL;
1512 bch = &ipac->hscx[rq->adr.channel - 1].bch;
1513 if (test_and_set_bit(FLG_OPEN, &bch->Flags))
1514 return -EBUSY; /* b-channel can be only open once */
1515 test_and_clear_bit(FLG_FILLEMPTY, &bch->Flags);
1516 bch->ch.protocol = rq->protocol;
1517 rq->ch = &bch->ch;
1518 return 0;
1519 }
1520
1521 static int
1522 channel_ctrl(struct ipac_hw *ipac, struct mISDN_ctrl_req *cq)
1523 {
1524 int ret = 0;
1525
1526 switch (cq->op) {
1527 case MISDN_CTRL_GETOP:
1528 cq->op = MISDN_CTRL_LOOP;
1529 break;
1530 case MISDN_CTRL_LOOP:
1531 /* cq->channel: 0 disable, 1 B1 loop 2 B2 loop, 3 both */
1532 if (cq->channel < 0 || cq->channel > 3) {
1533 ret = -EINVAL;
1534 break;
1535 }
1536 ret = ipac->ctrl(ipac, HW_TESTLOOP, cq->channel);
1537 break;
1538 default:
1539 pr_info("%s: unknown CTRL OP %x\n", ipac->name, cq->op);
1540 ret = -EINVAL;
1541 break;
1542 }
1543 return ret;
1544 }
1545
1546 static int
1547 ipac_dctrl(struct mISDNchannel *ch, u32 cmd, void *arg)
1548 {
1549 struct mISDNdevice *dev = container_of(ch, struct mISDNdevice, D);
1550 struct dchannel *dch = container_of(dev, struct dchannel, dev);
1551 struct isac_hw *isac = container_of(dch, struct isac_hw, dch);
1552 struct ipac_hw *ipac = container_of(isac, struct ipac_hw, isac);
1553 struct channel_req *rq;
1554 int err = 0;
1555
1556 pr_debug("%s: DCTRL: %x %p\n", ipac->name, cmd, arg);
1557 switch (cmd) {
1558 case OPEN_CHANNEL:
1559 rq = arg;
1560 if (rq->protocol == ISDN_P_TE_S0)
1561 err = open_dchannel(isac, rq);
1562 else
1563 err = open_bchannel(ipac, rq);
1564 if (err)
1565 break;
1566 if (!try_module_get(ipac->owner))
1567 pr_info("%s: cannot get module\n", ipac->name);
1568 break;
1569 case CLOSE_CHANNEL:
1570 pr_debug("%s: dev(%d) close from %p\n", ipac->name,
1571 dch->dev.id, __builtin_return_address(0));
1572 module_put(ipac->owner);
1573 break;
1574 case CONTROL_CHANNEL:
1575 err = channel_ctrl(ipac, arg);
1576 break;
1577 default:
1578 pr_debug("%s: unknown DCTRL command %x\n", ipac->name, cmd);
1579 return -EINVAL;
1580 }
1581 return err;
1582 }
1583
1584 u32
1585 mISDNipac_init(struct ipac_hw *ipac, void *hw)
1586 {
1587 u32 ret;
1588 u8 i;
1589
1590 ipac->hw = hw;
1591 if (ipac->isac.dch.debug & DEBUG_HW)
1592 pr_notice("%s: ipac type %x\n", ipac->name, ipac->type);
1593 if (ipac->type & IPAC_TYPE_HSCX) {
1594 ipac->isac.type = IPAC_TYPE_ISAC;
1595 ipac->hscx[0].off = 0;
1596 ipac->hscx[1].off = 0x40;
1597 ipac->hscx[0].fifo_size = 32;
1598 ipac->hscx[1].fifo_size = 32;
1599 } else if (ipac->type & IPAC_TYPE_IPAC) {
1600 ipac->isac.type = IPAC_TYPE_IPAC | IPAC_TYPE_ISAC;
1601 ipac->hscx[0].off = 0;
1602 ipac->hscx[1].off = 0x40;
1603 ipac->hscx[0].fifo_size = 64;
1604 ipac->hscx[1].fifo_size = 64;
1605 } else if (ipac->type & IPAC_TYPE_IPACX) {
1606 ipac->isac.type = IPAC_TYPE_IPACX | IPAC_TYPE_ISACX;
1607 ipac->hscx[0].off = IPACX_OFF_ICA;
1608 ipac->hscx[1].off = IPACX_OFF_ICB;
1609 ipac->hscx[0].fifo_size = 64;
1610 ipac->hscx[1].fifo_size = 64;
1611 } else
1612 return 0;
1613
1614 mISDNisac_init(&ipac->isac, hw);
1615
1616 ipac->isac.dch.dev.D.ctrl = ipac_dctrl;
1617
1618 for (i = 0; i < 2; i++) {
1619 ipac->hscx[i].bch.nr = i + 1;
1620 set_channelmap(i + 1, ipac->isac.dch.dev.channelmap);
1621 list_add(&ipac->hscx[i].bch.ch.list,
1622 &ipac->isac.dch.dev.bchannels);
1623 mISDN_initbchannel(&ipac->hscx[i].bch, MAX_DATA_MEM);
1624 ipac->hscx[i].bch.ch.nr = i + 1;
1625 ipac->hscx[i].bch.ch.send = &hscx_l2l1;
1626 ipac->hscx[i].bch.ch.ctrl = hscx_bctrl;
1627 ipac->hscx[i].bch.hw = hw;
1628 ipac->hscx[i].ip = ipac;
1629 /* default values for IOM time slots
1630 * can be overwriten by card */
1631 ipac->hscx[i].slot = (i == 0) ? 0x2f : 0x03;
1632 }
1633
1634 ipac->init = ipac_init;
1635 ipac->release = free_ipac;
1636
1637 ret = (1 << (ISDN_P_B_RAW & ISDN_P_B_MASK)) |
1638 (1 << (ISDN_P_B_HDLC & ISDN_P_B_MASK));
1639 return ret;
1640 }
1641 EXPORT_SYMBOL(mISDNipac_init);
1642
1643 static int __init
1644 isac_mod_init(void)
1645 {
1646 pr_notice("mISDNipac module version %s\n", ISAC_REV);
1647 return 0;
1648 }
1649
1650 static void __exit
1651 isac_mod_cleanup(void)
1652 {
1653 pr_notice("mISDNipac module unloaded\n");
1654 }
1655 module_init(isac_mod_init);
1656 module_exit(isac_mod_cleanup);