drivers/net/wireless/ath/ath5k/base.h

   1 /*-
   2  * Copyright (c) 2002-2007 Sam Leffler, Errno Consulting
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer,
  10  *    without modification.
  11  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  12  *    similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
  13  *    redistribution must be conditioned upon including a substantially
  14  *    similar Disclaimer requirement for further binary redistribution.
  15  * 3. Neither the names of the above-listed copyright holders nor the names
  16  *    of any contributors may be used to endorse or promote products derived
  17  *    from this software without specific prior written permission.
  18  *
  19  * Alternatively, this software may be distributed under the terms of the
  20  * GNU General Public License ("GPL") version 2 as published by the Free
  21  * Software Foundation.
  22  *
  23  * NO WARRANTY
  24  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  25  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  26  * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
  27  * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
  28  * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
  29  * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  30  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  31  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
  32  * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  33  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  34  * THE POSSIBILITY OF SUCH DAMAGES.
  35  *
  36  */
  37
  38 /*
  39  * Definitions for the Atheros Wireless LAN controller driver.
  40  */
  41 #ifndef _DEV_ATH_ATHVAR_H
  42 #define _DEV_ATH_ATHVAR_H
  43
  44 #include <linux/interrupt.h>
  45 #include <linux/list.h>
  46 #include <linux/wireless.h>
  47 #include <linux/if_ether.h>
  48 #include <linux/leds.h>
  49 #include <linux/rfkill.h>
  50 #include <linux/workqueue.h>
  51
  52 #include "ath5k.h"
  53 #include "debug.h"
  54 #include "ani.h"
  55
  56 #include "../regd.h"
  57 #include "../ath.h"
  58
  59 #define ATH_RXBUF       40              /* number of RX buffers */
  60 #define ATH_TXBUF       200             /* number of TX buffers */
  61 #define ATH_BCBUF       4               /* number of beacon buffers */
  62 #define ATH5K_TXQ_LEN_MAX       (ATH_TXBUF / 4)         /* bufs per queue */
  63 #define ATH5K_TXQ_LEN_LOW       (ATH5K_TXQ_LEN_MAX / 2) /* low mark */
  64
  65 struct ath5k_buf {
  66         struct list_head        list;
  67         struct ath5k_desc       *desc;  /* virtual addr of desc */
  68         dma_addr_t              daddr;  /* physical addr of desc */
  69         struct sk_buff          *skb;   /* skbuff for buf */
  70         dma_addr_t              skbaddr;/* physical addr of skb data */
  71 };
  72
  73 /*
  74  * Data transmit queue state.  One of these exists for each
  75  * hardware transmit queue.  Packets sent to us from above
  76  * are assigned to queues based on their priority.  Not all
  77  * devices support a complete set of hardware transmit queues.
  78  * For those devices the array sc_ac2q will map multiple
  79  * priorities to fewer hardware queues (typically all to one
  80  * hardware queue).
  81  */
  82 struct ath5k_txq {
  83         unsigned int            qnum;   /* hardware q number */
  84         u32                     *link;  /* link ptr in last TX desc */
  85         struct list_head        q;      /* transmit queue */
  86         spinlock_t              lock;   /* lock on q and link */
  87         bool                    setup;
  88         int                     txq_len; /* number of queued buffers */
  89         int                     txq_max; /* max allowed num of queued buffers */
  90         bool                    txq_poll_mark;
  91         unsigned int            txq_stuck;      /* informational counter */
  92 };
  93
  94 #define ATH5K_LED_MAX_NAME_LEN 31
  95
  96 /*
  97  * State for LED triggers
  98  */
  99 struct ath5k_led
 100 {
 101         char name[ATH5K_LED_MAX_NAME_LEN + 1];  /* name of the LED in sysfs */
 102         struct ath5k_softc *sc;                 /* driver state */
 103         struct led_classdev led_dev;            /* led classdev */
 104 };
 105
 106 /* Rfkill */
 107 struct ath5k_rfkill {
 108         /* GPIO PIN for rfkill */
 109         u16 gpio;
 110         /* polarity of rfkill GPIO PIN */
 111         bool polarity;
 112         /* RFKILL toggle tasklet */
 113         struct tasklet_struct toggleq;
 114 };
 115
 116 /* statistics */
 117 struct ath5k_statistics {
 118         /* antenna use */
 119         unsigned int antenna_rx[5];     /* frames count per antenna RX */
 120         unsigned int antenna_tx[5];     /* frames count per antenna TX */
 121
 122         /* frame errors */
 123         unsigned int rx_all_count;      /* all RX frames, including errors */
 124         unsigned int tx_all_count;      /* all TX frames, including errors */
 125         unsigned int rx_bytes_count;    /* all RX bytes, including errored pks
 126                                          * and the MAC headers for each packet
 127                                          */
 128         unsigned int tx_bytes_count;    /* all TX bytes, including errored pkts
 129                                          * and the MAC headers and padding for
 130                                          * each packet.
 131                                          */
 132         unsigned int rxerr_crc;
 133         unsigned int rxerr_phy;
 134         unsigned int rxerr_phy_code[32];
 135         unsigned int rxerr_fifo;
 136         unsigned int rxerr_decrypt;
 137         unsigned int rxerr_mic;
 138         unsigned int rxerr_proc;
 139         unsigned int rxerr_jumbo;
 140         unsigned int txerr_retry;
 141         unsigned int txerr_fifo;
 142         unsigned int txerr_filt;
 143
 144         /* MIB counters */
 145         unsigned int ack_fail;
 146         unsigned int rts_fail;
 147         unsigned int rts_ok;
 148         unsigned int fcs_error;
 149         unsigned int beacons;
 150
 151         unsigned int mib_intr;
 152         unsigned int rxorn_intr;
 153         unsigned int rxeol_intr;
 154 };
 155
 156 #if CHAN_DEBUG
 157 #define ATH_CHAN_MAX    (26+26+26+200+200)
 158 #else
 159 #define ATH_CHAN_MAX    (14+14+14+252+20)
 160 #endif
 161
 162 struct ath5k_vif {
 163         bool                    assoc; /* are we associated or not */
 164         enum nl80211_iftype     opmode;
 165         int                     bslot;
 166         struct ath5k_buf        *bbuf; /* beacon buffer */
 167         u8                      lladdr[ETH_ALEN];
 168 };
 169
 170 /* Software Carrier, keeps track of the driver state
 171  * associated with an instance of a device */
 172 struct ath5k_softc {
 173         struct pci_dev          *pdev;
 174         struct device           *dev;           /* for dma mapping */
 175         int irq;
 176         u16 devid;
 177         void __iomem            *iobase;        /* address of the device */
 178         struct mutex            lock;           /* dev-level lock */
 179         struct ieee80211_hw     *hw;            /* IEEE 802.11 common */
 180         struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
 181         struct ieee80211_channel channels[ATH_CHAN_MAX];
 182         struct ieee80211_rate   rates[IEEE80211_NUM_BANDS][AR5K_MAX_RATES];
 183         s8                      rate_idx[IEEE80211_NUM_BANDS][AR5K_MAX_RATES];
 184         enum nl80211_iftype     opmode;
 185         struct ath5k_hw         *ah;            /* Atheros HW */
 186
 187 #ifdef CONFIG_ATH5K_DEBUG
 188         struct ath5k_dbg_info   debug;          /* debug info */
 189 #endif /* CONFIG_ATH5K_DEBUG */
 190
 191         struct ath5k_buf        *bufptr;        /* allocated buffer ptr */
 192         struct ath5k_desc       *desc;          /* TX/RX descriptors */
 193         dma_addr_t              desc_daddr;     /* DMA (physical) address */
 194         size_t                  desc_len;       /* size of TX/RX descriptors */
 195
 196         DECLARE_BITMAP(status, 6);
 197 #define ATH_STAT_INVALID        0               /* disable hardware accesses */
 198 #define ATH_STAT_MRRETRY        1               /* multi-rate retry support */
 199 #define ATH_STAT_PROMISC        2
 200 #define ATH_STAT_LEDSOFT        3               /* enable LED gpio status */
 201 #define ATH_STAT_STARTED        4               /* opened & irqs enabled */
 202 #define ATH_STAT_2G_DISABLED    5               /* multiband radio without 2G */
 203
 204         unsigned int            filter_flags;   /* HW flags, AR5K_RX_FILTER_* */
 205         struct ieee80211_channel *curchan;      /* current h/w channel */
 206
 207         u16                     nvifs;
 208
 209         enum ath5k_int          imask;          /* interrupt mask copy */
 210
 211         spinlock_t              irqlock;
 212         bool                    rx_pending;     /* rx tasklet pending */
 213         bool                    tx_pending;     /* tx tasklet pending */
 214
 215         u8                      lladdr[ETH_ALEN];
 216         u8                      bssidmask[ETH_ALEN];
 217
 218         unsigned int            led_pin,        /* GPIO pin for driving LED */
 219                                 led_on;         /* pin setting for LED on */
 220
 221         struct work_struct      reset_work;     /* deferred chip reset */
 222
 223         unsigned int            rxbufsize;      /* rx size based on mtu */
 224         struct list_head        rxbuf;          /* receive buffer */
 225         spinlock_t              rxbuflock;
 226         u32                     *rxlink;        /* link ptr in last RX desc */
 227         struct tasklet_struct   rxtq;           /* rx intr tasklet */
 228         struct ath5k_led        rx_led;         /* rx led */
 229
 230         struct list_head        txbuf;          /* transmit buffer */
 231         spinlock_t              txbuflock;
 232         unsigned int            txbuf_len;      /* buf count in txbuf list */
 233         struct ath5k_txq        txqs[AR5K_NUM_TX_QUEUES];       /* tx queues */
 234         struct tasklet_struct   txtq;           /* tx intr tasklet */
 235         struct ath5k_led        tx_led;         /* tx led */
 236
 237         struct ath5k_rfkill     rf_kill;
 238
 239         struct tasklet_struct   calib;          /* calibration tasklet */
 240
 241         spinlock_t              block;          /* protects beacon */
 242         struct tasklet_struct   beacontq;       /* beacon intr tasklet */
 243         struct list_head        bcbuf;          /* beacon buffer */
 244         struct ieee80211_vif    *bslot[ATH_BCBUF];
 245         u16                     num_ap_vifs;
 246         u16                     num_adhoc_vifs;
 247         unsigned int            bhalq,          /* SW q for outgoing beacons */
 248                                 bmisscount,     /* missed beacon transmits */
 249                                 bintval,        /* beacon interval in TU */
 250                                 bsent;
 251         unsigned int            nexttbtt;       /* next beacon time in TU */
 252         struct ath5k_txq        *cabq;          /* content after beacon */
 253
 254         int                     power_level;    /* Requested tx power in dbm */
 255         bool                    assoc;          /* associate state */
 256         bool                    enable_beacon;  /* true if beacons are on */
 257
 258         struct ath5k_statistics stats;
 259
 260         struct ath5k_ani_state  ani_state;
 261         struct tasklet_struct   ani_tasklet;    /* ANI calibration */
 262
 263         struct delayed_work     tx_complete_work;
 264
 265         struct survey_info      survey;         /* collected survey info */
 266 };
 267
 268 struct ath5k_vif_iter_data {
 269         const u8        *hw_macaddr;
 270         u8              mask[ETH_ALEN];
 271         u8              active_mac[ETH_ALEN]; /* first active MAC */
 272         bool            need_set_hw_addr;
 273         bool            found_active;
 274         bool            any_assoc;
 275         enum nl80211_iftype opmode;
 276         int n_stas;
 277 };
 278 void ath5k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif);
 279
 280
 281 #define ath5k_hw_hasbssidmask(_ah) \
 282         (ath5k_hw_get_capability(_ah, AR5K_CAP_BSSIDMASK, 0, NULL) == 0)
 283 #define ath5k_hw_hasveol(_ah) \
 284         (ath5k_hw_get_capability(_ah, AR5K_CAP_VEOL, 0, NULL) == 0)
 285
 286 #endif