| blob | ed98b9c9f389c622db6c3fc9c41c5730852be1f9 |
1 /*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
4 * Copyright 2009 Holger Schurig, hs4233@mail.mn-solutions.de
5 *
6 * This contains i.MX21-specific hardware definitions. For those
7 * hardware pieces that are common between i.MX21 and i.MX27, have a
8 * look at mx2x.h.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version 2
13 * of the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
22 * MA 02110-1301, USA.
23 */
25 #ifndef __MACH_MX21_H__
26 #define __MACH_MX21_H__
28 #define MX21_AIPI_BASE_ADDR 0x10000000
29 #define MX21_AIPI_BASE_ADDR_VIRT 0xf4000000
30 #define MX21_AIPI_SIZE SZ_1M
31 #define MX21_DMA_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x01000)
32 #define MX21_WDOG_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x02000)
33 #define MX21_GPT1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x03000)
34 #define MX21_GPT2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x04000)
35 #define MX21_GPT3_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x05000)
36 #define MX21_PWM_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x06000)
37 #define MX21_RTC_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x07000)
38 #define MX21_KPP_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x08000)
39 #define MX21_OWIRE_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x09000)
40 #define MX21_UART1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0a000)
41 #define MX21_UART2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0b000)
42 #define MX21_UART3_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0c000)
43 #define MX21_UART4_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0d000)
44 #define MX21_CSPI1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0e000)
45 #define MX21_CSPI2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0f000)
46 #define MX21_SSI1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x10000)
47 #define MX21_SSI2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x11000)
48 #define MX21_I2C_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x12000)
49 #define MX21_SDHC1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x13000)
50 #define MX21_SDHC2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x14000)
51 #define MX21_GPIO_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x15000)
52 #define MX21_AUDMUX_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x16000)
53 #define MX21_CSPI3_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x17000)
54 #define MX21_LCDC_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x21000)
55 #define MX21_SLCDC_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x22000)
56 #define MX21_USBOTG_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x24000)
57 #define MX21_EMMA_PP_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x26000)
58 #define MX21_EMMA_PRP_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x26400)
59 #define MX21_CCM_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x27000)
60 #define MX21_SYSCTRL_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x27800)
61 #define MX21_JAM_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x3e000)
62 #define MX21_MAX_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x3f000)
64 #define MX21_AVIC_BASE_ADDR 0x10040000
66 #define MX21_SAHB1_BASE_ADDR 0x80000000
67 #define MX21_SAHB1_BASE_ADDR_VIRT 0xf4100000
68 #define MX21_SAHB1_SIZE SZ_1M
69 #define MX21_CSI_BASE_ADDR (MX2x_SAHB1_BASE_ADDR + 0x0000)
71 /* Memory regions and CS */
72 #define MX21_SDRAM_BASE_ADDR 0xc0000000
73 #define MX21_CSD1_BASE_ADDR 0xc4000000
75 #define MX21_CS0_BASE_ADDR 0xc8000000
76 #define MX21_CS1_BASE_ADDR 0xcc000000
77 #define MX21_CS2_BASE_ADDR 0xd0000000
78 #define MX21_CS3_BASE_ADDR 0xd1000000
79 #define MX21_CS4_BASE_ADDR 0xd2000000
80 #define MX21_PCMCIA_MEM_BASE_ADDR 0xd4000000
81 #define MX21_CS5_BASE_ADDR 0xdd000000
83 /* NAND, SDRAM, WEIM etc controllers */
84 #define MX21_X_MEMC_BASE_ADDR 0xdf000000
85 #define MX21_X_MEMC_BASE_ADDR_VIRT 0xf4200000
86 #define MX21_X_MEMC_SIZE SZ_256K
88 #define MX21_SDRAMC_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x0000)
89 #define MX21_EIM_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x1000)
90 #define MX21_PCMCIA_CTL_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x2000)
91 #define MX21_NFC_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x3000)
95 #define MX21_IO_ADDRESS(x) ( \
96 IMX_IO_ADDRESS(x, MX21_AIPI) ?: \
97 IMX_IO_ADDRESS(x, MX21_SAHB1) ?: \
98 IMX_IO_ADDRESS(x, MX21_X_MEMC))
100 /* fixed interrupt numbers */
101 #define MX21_INT_CSPI3 6
102 #define MX21_INT_GPIO 8
103 #define MX21_INT_FIRI 9
104 #define MX21_INT_SDHC2 10
105 #define MX21_INT_SDHC1 11
106 #define MX21_INT_I2C 12
107 #define MX21_INT_SSI2 13
108 #define MX21_INT_SSI1 14
109 #define MX21_INT_CSPI2 15
110 #define MX21_INT_CSPI1 16
111 #define MX21_INT_UART4 17
112 #define MX21_INT_UART3 18
113 #define MX21_INT_UART2 19
114 #define MX21_INT_UART1 20
115 #define MX21_INT_KPP 21
116 #define MX21_INT_RTC 22
117 #define MX21_INT_PWM 23
118 #define MX21_INT_GPT3 24
119 #define MX21_INT_GPT2 25
120 #define MX21_INT_GPT1 26
121 #define MX21_INT_WDOG 27
122 #define MX21_INT_PCMCIA 28
123 #define MX21_INT_NANDFC 29
124 #define MX21_INT_BMI 30
125 #define MX21_INT_CSI 31
126 #define MX21_INT_DMACH0 32
127 #define MX21_INT_DMACH1 33
128 #define MX21_INT_DMACH2 34
129 #define MX21_INT_DMACH3 35
130 #define MX21_INT_DMACH4 36
131 #define MX21_INT_DMACH5 37
132 #define MX21_INT_DMACH6 38
133 #define MX21_INT_DMACH7 39
134 #define MX21_INT_DMACH8 40
135 #define MX21_INT_DMACH9 41
136 #define MX21_INT_DMACH10 42
137 #define MX21_INT_DMACH11 43
138 #define MX21_INT_DMACH12 44
139 #define MX21_INT_DMACH13 45
140 #define MX21_INT_DMACH14 46
141 #define MX21_INT_DMACH15 47
142 #define MX21_INT_EMMAENC 49
143 #define MX21_INT_EMMADEC 50
144 #define MX21_INT_EMMAPRP 51
145 #define MX21_INT_EMMAPP 52
146 #define MX21_INT_USBWKUP 53
147 #define MX21_INT_USBDMA 54
148 #define MX21_INT_USBHOST 55
149 #define MX21_INT_USBFUNC 56
150 #define MX21_INT_USBMNP 57
151 #define MX21_INT_USBCTRL 58
152 #define MX21_INT_SLCDC 60
153 #define MX21_INT_LCDC 61
155 /* fixed DMA request numbers */
156 #define MX21_DMA_REQ_CSPI3_RX 1
157 #define MX21_DMA_REQ_CSPI3_TX 2
158 #define MX21_DMA_REQ_EXT 3
159 #define MX21_DMA_REQ_FIRI_RX 4
160 #define MX21_DMA_REQ_SDHC2 6
161 #define MX21_DMA_REQ_SDHC1 7
162 #define MX21_DMA_REQ_SSI2_RX0 8
163 #define MX21_DMA_REQ_SSI2_TX0 9
164 #define MX21_DMA_REQ_SSI2_RX1 10
165 #define MX21_DMA_REQ_SSI2_TX1 11
166 #define MX21_DMA_REQ_SSI1_RX0 12
167 #define MX21_DMA_REQ_SSI1_TX0 13
168 #define MX21_DMA_REQ_SSI1_RX1 14
169 #define MX21_DMA_REQ_SSI1_TX1 15
170 #define MX21_DMA_REQ_CSPI2_RX 16
171 #define MX21_DMA_REQ_CSPI2_TX 17
172 #define MX21_DMA_REQ_CSPI1_RX 18
173 #define MX21_DMA_REQ_CSPI1_TX 19
174 #define MX21_DMA_REQ_UART4_RX 20
175 #define MX21_DMA_REQ_UART4_TX 21
176 #define MX21_DMA_REQ_UART3_RX 22
177 #define MX21_DMA_REQ_UART3_TX 23
178 #define MX21_DMA_REQ_UART2_RX 24
179 #define MX21_DMA_REQ_UART2_TX 25
180 #define MX21_DMA_REQ_UART1_RX 26
181 #define MX21_DMA_REQ_UART1_TX 27
182 #define MX21_DMA_REQ_BMI_TX 28
183 #define MX21_DMA_REQ_BMI_RX 29
184 #define MX21_DMA_REQ_CSI_STAT 30
185 #define MX21_DMA_REQ_CSI_RX 31
187 #ifdef IMX_NEEDS_DEPRECATED_SYMBOLS
188 /* these should go away */
189 #define SDRAM_BASE_ADDR MX21_SDRAM_BASE_ADDR
190 #define CSD1_BASE_ADDR MX21_CSD1_BASE_ADDR
191 #define CS0_BASE_ADDR MX21_CS0_BASE_ADDR
192 #define CS1_BASE_ADDR MX21_CS1_BASE_ADDR
193 #define CS2_BASE_ADDR MX21_CS2_BASE_ADDR
194 #define CS3_BASE_ADDR MX21_CS3_BASE_ADDR
195 #define CS4_BASE_ADDR MX21_CS4_BASE_ADDR
196 #define PCMCIA_MEM_BASE_ADDR MX21_PCMCIA_MEM_BASE_ADDR
197 #define CS5_BASE_ADDR MX21_CS5_BASE_ADDR
198 #define X_MEMC_BASE_ADDR MX21_X_MEMC_BASE_ADDR
199 #define X_MEMC_BASE_ADDR_VIRT MX21_X_MEMC_BASE_ADDR_VIRT
200 #define X_MEMC_SIZE MX21_X_MEMC_SIZE
201 #define SDRAMC_BASE_ADDR MX21_SDRAMC_BASE_ADDR
202 #define EIM_BASE_ADDR MX21_EIM_BASE_ADDR
203 #define PCMCIA_CTL_BASE_ADDR MX21_PCMCIA_CTL_BASE_ADDR
204 #define NFC_BASE_ADDR MX21_NFC_BASE_ADDR
205 #define IRAM_BASE_ADDR MX21_IRAM_BASE_ADDR
206 #define MXC_INT_FIRI MX21_INT_FIRI
207 #define MXC_INT_BMI MX21_INT_BMI
208 #define MXC_INT_EMMAENC MX21_INT_EMMAENC
209 #define MXC_INT_EMMADEC MX21_INT_EMMADEC
210 #define MXC_INT_USBWKUP MX21_INT_USBWKUP
211 #define MXC_INT_USBDMA MX21_INT_USBDMA
212 #define MXC_INT_USBHOST MX21_INT_USBHOST
213 #define MXC_INT_USBFUNC MX21_INT_USBFUNC
214 #define MXC_INT_USBMNP MX21_INT_USBMNP
215 #define MXC_INT_USBCTRL MX21_INT_USBCTRL
216 #define MXC_INT_USBCTRL MX21_INT_USBCTRL
217 #define DMA_REQ_FIRI_RX MX21_DMA_REQ_FIRI_RX
218 #define DMA_REQ_BMI_TX MX21_DMA_REQ_BMI_TX
219 #define DMA_REQ_BMI_RX MX21_DMA_REQ_BMI_RX
220 #endif