arch/powerpc/include/asm/mmu.h

   1 #ifndef _ASM_POWERPC_MMU_H_
   2 #define _ASM_POWERPC_MMU_H_
   3 #ifdef __KERNEL__
   4
   5 #include <linux/types.h>
   6
   7 #include <asm/asm-compat.h>
   8 #include <asm/feature-fixups.h>
   9
  10 /*
  11  * MMU features bit definitions
  12  */
  13
  14 /*
  15  * First half is MMU families
  16  */
  17 #define MMU_FTR_HPTE_TABLE              ASM_CONST(0x00000001)
  18 #define MMU_FTR_TYPE_8xx                ASM_CONST(0x00000002)
  19 #define MMU_FTR_TYPE_40x                ASM_CONST(0x00000004)
  20 #define MMU_FTR_TYPE_44x                ASM_CONST(0x00000008)
  21 #define MMU_FTR_TYPE_FSL_E              ASM_CONST(0x00000010)
  22 #define MMU_FTR_TYPE_3E                 ASM_CONST(0x00000020)
  23 #define MMU_FTR_TYPE_47x                ASM_CONST(0x00000040)
  24
  25 /*
  26  * This is individual features
  27  */
  28
  29 /* Enable use of high BAT registers */
  30 #define MMU_FTR_USE_HIGH_BATS           ASM_CONST(0x00010000)
  31
  32 /* Enable >32-bit physical addresses on 32-bit processor, only used
  33  * by CONFIG_6xx currently as BookE supports that from day 1
  34  */
  35 #define MMU_FTR_BIG_PHYS                ASM_CONST(0x00020000)
  36
  37 /* Enable use of broadcast TLB invalidations. We don't always set it
  38  * on processors that support it due to other constraints with the
  39  * use of such invalidations
  40  */
  41 #define MMU_FTR_USE_TLBIVAX_BCAST       ASM_CONST(0x00040000)
  42
  43 /* Enable use of tlbilx invalidate instructions.
  44  */
  45 #define MMU_FTR_USE_TLBILX              ASM_CONST(0x00080000)
  46
  47 /* This indicates that the processor cannot handle multiple outstanding
  48  * broadcast tlbivax or tlbsync. This makes the code use a spinlock
  49  * around such invalidate forms.
  50  */
  51 #define MMU_FTR_LOCK_BCAST_INVAL        ASM_CONST(0x00100000)
  52
  53 /* This indicates that the processor doesn't handle way selection
  54  * properly and needs SW to track and update the LRU state.  This
  55  * is specific to an errata on e300c2/c3/c4 class parts
  56  */
  57 #define MMU_FTR_NEED_DTLB_SW_LRU        ASM_CONST(0x00200000)
  58
  59 /* This indicates that the processor uses the ISA 2.06 server tlbie
  60  * mnemonics
  61  */
  62 #define MMU_FTR_TLBIE_206               ASM_CONST(0x00400000)
  63
  64 /* Enable use of TLB reservation.  Processor should support tlbsrx.
  65  * instruction and MAS0[WQ].
  66  */
  67 #define MMU_FTR_USE_TLBRSRV             ASM_CONST(0x00800000)
  68
  69 /* Use paired MAS registers (MAS7||MAS3, etc.)
  70  */
  71 #define MMU_FTR_USE_PAIRED_MAS          ASM_CONST(0x01000000)
  72
  73 #ifndef __ASSEMBLY__
  74 #include <asm/cputable.h>
  75
  76 static inline int mmu_has_feature(unsigned long feature)
  77 {
  78         return (cur_cpu_spec->mmu_features & feature);
  79 }
  80
  81 extern unsigned int __start___mmu_ftr_fixup, __stop___mmu_ftr_fixup;
  82
  83 /* MMU initialization (64-bit only fo now) */
  84 extern void early_init_mmu(void);
  85 extern void early_init_mmu_secondary(void);
  86
  87 extern void setup_initial_memory_limit(phys_addr_t first_memblock_base,
  88                                        phys_addr_t first_memblock_size);
  89
  90 #ifdef CONFIG_PPC64
  91 /* This is our real memory area size on ppc64 server, on embedded, we
  92  * make it match the size our of bolted TLB area
  93  */
  94 extern u64 ppc64_rma_size;
  95 #endif /* CONFIG_PPC64 */
  96
  97 #endif /* !__ASSEMBLY__ */
  98
  99 /* The kernel use the constants below to index in the page sizes array.
 100  * The use of fixed constants for this purpose is better for performances
 101  * of the low level hash refill handlers.
 102  *
 103  * A non supported page size has a "shift" field set to 0
 104  *
 105  * Any new page size being implemented can get a new entry in here. Whether
 106  * the kernel will use it or not is a different matter though. The actual page
 107  * size used by hugetlbfs is not defined here and may be made variable
 108  *
 109  * Note: This array ended up being a false good idea as it's growing to the
 110  * point where I wonder if we should replace it with something different,
 111  * to think about, feedback welcome. --BenH.
 112  */
 113
 114 /* There are #define as they have to be used in assembly
 115  *
 116  * WARNING: If you change this list, make sure to update the array of
 117  * names currently in arch/powerpc/mm/hugetlbpage.c or bad things will
 118  * happen
 119  */
 120 #define MMU_PAGE_4K     0
 121 #define MMU_PAGE_16K    1
 122 #define MMU_PAGE_64K    2
 123 #define MMU_PAGE_64K_AP 3       /* "Admixed pages" (hash64 only) */
 124 #define MMU_PAGE_256K   4
 125 #define MMU_PAGE_1M     5
 126 #define MMU_PAGE_8M     6
 127 #define MMU_PAGE_16M    7
 128 #define MMU_PAGE_256M   8
 129 #define MMU_PAGE_1G     9
 130 #define MMU_PAGE_16G    10
 131 #define MMU_PAGE_64G    11
 132 #define MMU_PAGE_COUNT  12
 133
 134
 135 #if defined(CONFIG_PPC_STD_MMU_64)
 136 /* 64-bit classic hash table MMU */
 137 #  include <asm/mmu-hash64.h>
 138 #elif defined(CONFIG_PPC_STD_MMU_32)
 139 /* 32-bit classic hash table MMU */
 140 #  include <asm/mmu-hash32.h>
 141 #elif defined(CONFIG_40x)
 142 /* 40x-style software loaded TLB */
 143 #  include <asm/mmu-40x.h>
 144 #elif defined(CONFIG_44x)
 145 /* 44x-style software loaded TLB */
 146 #  include <asm/mmu-44x.h>
 147 #elif defined(CONFIG_PPC_BOOK3E_MMU)
 148 /* Freescale Book-E software loaded TLB or Book-3e (ISA 2.06+) MMU */
 149 #  include <asm/mmu-book3e.h>
 150 #elif defined (CONFIG_PPC_8xx)
 151 /* Motorola/Freescale 8xx software loaded TLB */
 152 #  include <asm/mmu-8xx.h>
 153 #endif
 154
 155
 156 #endif /* __KERNEL__ */
 157 #endif /* _ASM_POWERPC_MMU_H_ */