arch/powerpc/sysdev/cpm2_pic.c

   1 /*
   2  * Platform information definitions.
   3  *
   4  * Copied from arch/ppc/syslib/cpm2_pic.c with minor subsequent updates
   5  * to make in work in arch/powerpc/. Original (c) belongs to Dan Malek.
   6  *
   7  * Author:  Vitaly Bordug <vbordug@ru.mvista.com>
   8  *
   9  * 1999-2001 (c) Dan Malek <dan@embeddedalley.com>
  10  * 2006 (c) MontaVista Software, Inc.
  11  *
  12  * This file is licensed under the terms of the GNU General Public License
  13  * version 2. This program is licensed "as is" without any warranty of any
  14  * kind, whether express or implied.
  15  */
  16
  17 /* The CPM2 internal interrupt controller.  It is usually
  18  * the only interrupt controller.
  19  * There are two 32-bit registers (high/low) for up to 64
  20  * possible interrupts.
  21  *
  22  * Now, the fun starts.....Interrupt Numbers DO NOT MAP
  23  * in a simple arithmetic fashion to mask or pending registers.
  24  * That is, interrupt 4 does not map to bit position 4.
  25  * We create two tables, indexed by vector number, to indicate
  26  * which register to use and which bit in the register to use.
  27  */
  28
  29 #include <linux/stddef.h>
  30 #include <linux/init.h>
  31 #include <linux/sched.h>
  32 #include <linux/signal.h>
  33 #include <linux/irq.h>
  34
  35 #include <asm/immap_cpm2.h>
  36 #include <asm/mpc8260.h>
  37 #include <asm/io.h>
  38 #include <asm/prom.h>
  39 #include <asm/fs_pd.h>
  40
  41 #include "cpm2_pic.h"
  42
  43 /* External IRQS */
  44 #define CPM2_IRQ_EXT1           19
  45 #define CPM2_IRQ_EXT7           25
  46
  47 /* Port C IRQS */
  48 #define CPM2_IRQ_PORTC15        48
  49 #define CPM2_IRQ_PORTC0         63
  50
  51 static intctl_cpm2_t __iomem *cpm2_intctl;
  52
  53 static struct irq_host *cpm2_pic_host;
  54 #define NR_MASK_WORDS   ((NR_IRQS + 31) / 32)
  55 static unsigned long ppc_cached_irq_mask[NR_MASK_WORDS];
  56
  57 static const u_char irq_to_siureg[] = {
  58         1, 1, 1, 1, 1, 1, 1, 1,
  59         1, 1, 1, 1, 1, 1, 1, 1,
  60         0, 0, 0, 0, 0, 0, 0, 0,
  61         0, 0, 0, 0, 0, 0, 0, 0,
  62         1, 1, 1, 1, 1, 1, 1, 1,
  63         1, 1, 1, 1, 1, 1, 1, 1,
  64         0, 0, 0, 0, 0, 0, 0, 0,
  65         0, 0, 0, 0, 0, 0, 0, 0
  66 };
  67
  68 /* bit numbers do not match the docs, these are precomputed so the bit for
  69  * a given irq is (1 << irq_to_siubit[irq]) */
  70 static const u_char irq_to_siubit[] = {
  71          0, 15, 14, 13, 12, 11, 10,  9,
  72          8,  7,  6,  5,  4,  3,  2,  1,
  73          2,  1,  0, 14, 13, 12, 11, 10,
  74          9,  8,  7,  6,  5,  4,  3,  0,
  75         31, 30, 29, 28, 27, 26, 25, 24,
  76         23, 22, 21, 20, 19, 18, 17, 16,
  77         16, 17, 18, 19, 20, 21, 22, 23,
  78         24, 25, 26, 27, 28, 29, 30, 31,
  79 };
  80
  81 static void cpm2_mask_irq(unsigned int virq)
  82 {
  83         int     bit, word;
  84         unsigned int irq_nr = virq_to_hw(virq);
  85
  86         bit = irq_to_siubit[irq_nr];
  87         word = irq_to_siureg[irq_nr];
  88
  89         ppc_cached_irq_mask[word] &= ~(1 << bit);
  90         out_be32(&cpm2_intctl->ic_simrh + word, ppc_cached_irq_mask[word]);
  91 }
  92
  93 static void cpm2_unmask_irq(unsigned int virq)
  94 {
  95         int     bit, word;
  96         unsigned int irq_nr = virq_to_hw(virq);
  97
  98         bit = irq_to_siubit[irq_nr];
  99         word = irq_to_siureg[irq_nr];
 100
 101         ppc_cached_irq_mask[word] |= 1 << bit;
 102         out_be32(&cpm2_intctl->ic_simrh + word, ppc_cached_irq_mask[word]);
 103 }
 104
 105 static void cpm2_ack(unsigned int virq)
 106 {
 107         int     bit, word;
 108         unsigned int irq_nr = virq_to_hw(virq);
 109
 110         bit = irq_to_siubit[irq_nr];
 111         word = irq_to_siureg[irq_nr];
 112
 113         out_be32(&cpm2_intctl->ic_sipnrh + word, 1 << bit);
 114 }
 115
 116 static void cpm2_end_irq(unsigned int virq)
 117 {
 118         struct irq_desc *desc;
 119         int     bit, word;
 120         unsigned int irq_nr = virq_to_hw(virq);
 121
 122         desc = irq_to_desc(irq_nr);
 123         if (!(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS))
 124                         && desc->action) {
 125
 126                 bit = irq_to_siubit[irq_nr];
 127                 word = irq_to_siureg[irq_nr];
 128
 129                 ppc_cached_irq_mask[word] |= 1 << bit;
 130                 out_be32(&cpm2_intctl->ic_simrh + word, ppc_cached_irq_mask[word]);
 131
 132                 /*
 133                  * Work around large numbers of spurious IRQs on PowerPC 82xx
 134                  * systems.
 135                  */
 136                 mb();
 137         }
 138 }
 139
 140 static int cpm2_set_irq_type(unsigned int virq, unsigned int flow_type)
 141 {
 142         unsigned int src = virq_to_hw(virq);
 143         struct irq_desc *desc = irq_to_desc(virq);
 144         unsigned int vold, vnew, edibit;
 145
 146         /* Port C interrupts are either IRQ_TYPE_EDGE_FALLING or
 147          * IRQ_TYPE_EDGE_BOTH (default).  All others are IRQ_TYPE_EDGE_FALLING
 148          * or IRQ_TYPE_LEVEL_LOW (default)
 149          */
 150         if (src >= CPM2_IRQ_PORTC15 && src <= CPM2_IRQ_PORTC0) {
 151                 if (flow_type == IRQ_TYPE_NONE)
 152                         flow_type = IRQ_TYPE_EDGE_BOTH;
 153
 154                 if (flow_type != IRQ_TYPE_EDGE_BOTH &&
 155                     flow_type != IRQ_TYPE_EDGE_FALLING)
 156                         goto err_sense;
 157         } else {
 158                 if (flow_type == IRQ_TYPE_NONE)
 159                         flow_type = IRQ_TYPE_LEVEL_LOW;
 160
 161                 if (flow_type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_LEVEL_HIGH))
 162                         goto err_sense;
 163         }
 164
 165         desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL);
 166         desc->status |= flow_type & IRQ_TYPE_SENSE_MASK;
 167         if (flow_type & IRQ_TYPE_LEVEL_LOW)  {
 168                 desc->status |= IRQ_LEVEL;
 169                 desc->handle_irq = handle_level_irq;
 170         } else
 171                 desc->handle_irq = handle_edge_irq;
 172
 173         /* internal IRQ senses are LEVEL_LOW
 174          * EXT IRQ and Port C IRQ senses are programmable
 175          */
 176         if (src >= CPM2_IRQ_EXT1 && src <= CPM2_IRQ_EXT7)
 177                         edibit = (14 - (src - CPM2_IRQ_EXT1));
 178         else
 179                 if (src >= CPM2_IRQ_PORTC15 && src <= CPM2_IRQ_PORTC0)
 180                         edibit = (31 - (CPM2_IRQ_PORTC0 - src));
 181                 else
 182                         return (flow_type & IRQ_TYPE_LEVEL_LOW) ? 0 : -EINVAL;
 183
 184         vold = in_be32(&cpm2_intctl->ic_siexr);
 185
 186         if ((flow_type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_FALLING)
 187                 vnew = vold | (1 << edibit);
 188         else
 189                 vnew = vold & ~(1 << edibit);
 190
 191         if (vold != vnew)
 192                 out_be32(&cpm2_intctl->ic_siexr, vnew);
 193         return 0;
 194
 195 err_sense:
 196         pr_err("CPM2 PIC: sense type 0x%x not supported\n", flow_type);
 197         return -EINVAL;
 198 }
 199
 200 static struct irq_chip cpm2_pic = {
 201         .name = "CPM2 SIU",
 202         .mask = cpm2_mask_irq,
 203         .unmask = cpm2_unmask_irq,
 204         .ack = cpm2_ack,
 205         .eoi = cpm2_end_irq,
 206         .set_type = cpm2_set_irq_type,
 207 };
 208
 209 unsigned int cpm2_get_irq(void)
 210 {
 211         int irq;
 212         unsigned long bits;
 213
 214        /* For CPM2, read the SIVEC register and shift the bits down
 215          * to get the irq number.         */
 216         bits = in_be32(&cpm2_intctl->ic_sivec);
 217         irq = bits >> 26;
 218
 219         if (irq == 0)
 220                 return(-1);
 221         return irq_linear_revmap(cpm2_pic_host, irq);
 222 }
 223
 224 static int cpm2_pic_host_map(struct irq_host *h, unsigned int virq,
 225                           irq_hw_number_t hw)
 226 {
 227         pr_debug("cpm2_pic_host_map(%d, 0x%lx)\n", virq, hw);
 228
 229         irq_to_desc(virq)->status |= IRQ_LEVEL;
 230         set_irq_chip_and_handler(virq, &cpm2_pic, handle_level_irq);
 231         return 0;
 232 }
 233
 234 static int cpm2_pic_host_xlate(struct irq_host *h, struct device_node *ct,
 235                             const u32 *intspec, unsigned int intsize,
 236                             irq_hw_number_t *out_hwirq, unsigned int *out_flags)
 237 {
 238         *out_hwirq = intspec[0];
 239         if (intsize > 1)
 240                 *out_flags = intspec[1];
 241         else
 242                 *out_flags = IRQ_TYPE_NONE;
 243         return 0;
 244 }
 245
 246 static struct irq_host_ops cpm2_pic_host_ops = {
 247         .map = cpm2_pic_host_map,
 248         .xlate = cpm2_pic_host_xlate,
 249 };
 250
 251 void cpm2_pic_init(struct device_node *node)
 252 {
 253         int i;
 254
 255         cpm2_intctl = cpm2_map(im_intctl);
 256
 257         /* Clear the CPM IRQ controller, in case it has any bits set
 258          * from the bootloader
 259          */
 260
 261         /* Mask out everything */
 262
 263         out_be32(&cpm2_intctl->ic_simrh, 0x00000000);
 264         out_be32(&cpm2_intctl->ic_simrl, 0x00000000);
 265
 266         wmb();
 267
 268         /* Ack everything */
 269         out_be32(&cpm2_intctl->ic_sipnrh, 0xffffffff);
 270         out_be32(&cpm2_intctl->ic_sipnrl, 0xffffffff);
 271         wmb();
 272
 273         /* Dummy read of the vector */
 274         i = in_be32(&cpm2_intctl->ic_sivec);
 275         rmb();
 276
 277         /* Initialize the default interrupt mapping priorities,
 278          * in case the boot rom changed something on us.
 279          */
 280         out_be16(&cpm2_intctl->ic_sicr, 0);
 281         out_be32(&cpm2_intctl->ic_scprrh, 0x05309770);
 282         out_be32(&cpm2_intctl->ic_scprrl, 0x05309770);
 283
 284         /* create a legacy host */
 285         cpm2_pic_host = irq_alloc_host(node, IRQ_HOST_MAP_LINEAR,
 286                                        64, &cpm2_pic_host_ops, 64);
 287         if (cpm2_pic_host == NULL) {
 288                 printk(KERN_ERR "CPM2 PIC: failed to allocate irq host!\n");
 289                 return;
 290         }
 291 }