arch/x86/pci/mmconfig-shared.c

   1 /*
   2  * mmconfig-shared.c - Low-level direct PCI config space access via
   3  *                     MMCONFIG - common code between i386 and x86-64.
   4  *
   5  * This code does:
   6  * - known chipset handling
   7  * - ACPI decoding and validation
   8  *
   9  * Per-architecture code takes care of the mappings and accesses
  10  * themselves.
  11  */
  12
  13 #include <linux/pci.h>
  14 #include <linux/init.h>
  15 #include <linux/acpi.h>
  16 #include <linux/sfi_acpi.h>
  17 #include <linux/bitmap.h>
  18 #include <linux/dmi.h>
  19 #include <linux/sort.h>
  20 #include <asm/e820.h>
  21 #include <asm/pci_x86.h>
  22 #include <asm/acpi.h>
  23
  24 #define PREFIX "PCI: "
  25
  26 /* Indicate if the mmcfg resources have been placed into the resource table. */
  27 static int __initdata pci_mmcfg_resources_inserted;
  28
  29 static __init void free_all_mmcfg(void)
  30 {
  31         pci_mmcfg_arch_free();
  32         pci_mmcfg_config_num = 0;
  33         kfree(pci_mmcfg_config);
  34         pci_mmcfg_config = NULL;
  35 }
  36
  37 static __init struct acpi_mcfg_allocation *pci_mmconfig_add(int segment,
  38         int start, int end, u64 addr)
  39 {
  40         struct acpi_mcfg_allocation *new;
  41         int new_num = pci_mmcfg_config_num + 1;
  42         int i = pci_mmcfg_config_num;
  43
  44         new = kzalloc(sizeof(pci_mmcfg_config[0]) * new_num, GFP_KERNEL);
  45         if (!new)
  46                 return NULL;
  47
  48         if (pci_mmcfg_config) {
  49                 memcpy(new, pci_mmcfg_config,
  50                          sizeof(pci_mmcfg_config[0]) * new_num);
  51                 kfree(pci_mmcfg_config);
  52         }
  53         pci_mmcfg_config = new;
  54
  55         pci_mmcfg_config_num++;
  56         pci_mmcfg_config[i].address = addr;
  57         pci_mmcfg_config[i].pci_segment = segment;
  58         pci_mmcfg_config[i].start_bus_number = start;
  59         pci_mmcfg_config[i].end_bus_number = end;
  60
  61         return &pci_mmcfg_config[i];
  62 }
  63
  64 static const char __init *pci_mmcfg_e7520(void)
  65 {
  66         u32 win;
  67         raw_pci_ops->read(0, 0, PCI_DEVFN(0, 0), 0xce, 2, &win);
  68
  69         win = win & 0xf000;
  70         if (win == 0x0000 || win == 0xf000)
  71                 return NULL;
  72
  73         if (pci_mmconfig_add(0, 0, 255, win << 16) == NULL)
  74                 return NULL;
  75
  76         return "Intel Corporation E7520 Memory Controller Hub";
  77 }
  78
  79 static const char __init *pci_mmcfg_intel_945(void)
  80 {
  81         u32 pciexbar, mask = 0, len = 0;
  82
  83         raw_pci_ops->read(0, 0, PCI_DEVFN(0, 0), 0x48, 4, &pciexbar);
  84
  85         /* Enable bit */
  86         if (!(pciexbar & 1))
  87                 return NULL;
  88
  89         /* Size bits */
  90         switch ((pciexbar >> 1) & 3) {
  91         case 0:
  92                 mask = 0xf0000000U;
  93                 len  = 0x10000000U;
  94                 break;
  95         case 1:
  96                 mask = 0xf8000000U;
  97                 len  = 0x08000000U;
  98                 break;
  99         case 2:
 100                 mask = 0xfc000000U;
 101                 len  = 0x04000000U;
 102                 break;
 103         default:
 104                 return NULL;
 105         }
 106
 107         /* Errata #2, things break when not aligned on a 256Mb boundary */
 108         /* Can only happen in 64M/128M mode */
 109
 110         if ((pciexbar & mask) & 0x0fffffffU)
 111                 return NULL;
 112
 113         /* Don't hit the APIC registers and their friends */
 114         if ((pciexbar & mask) >= 0xf0000000U)
 115                 return NULL;
 116
 117         if (pci_mmconfig_add(0, 0, (len >> 20) - 1, pciexbar & mask) == NULL)
 118                 return NULL;
 119
 120         return "Intel Corporation 945G/GZ/P/PL Express Memory Controller Hub";
 121 }
 122
 123 static const char __init *pci_mmcfg_amd_fam10h(void)
 124 {
 125         u32 low, high, address;
 126         u64 base, msr;
 127         int i;
 128         unsigned segnbits = 0, busnbits, end_bus;
 129
 130         if (!(pci_probe & PCI_CHECK_ENABLE_AMD_MMCONF))
 131                 return NULL;
 132
 133         address = MSR_FAM10H_MMIO_CONF_BASE;
 134         if (rdmsr_safe(address, &low, &high))
 135                 return NULL;
 136
 137         msr = high;
 138         msr <<= 32;
 139         msr |= low;
 140
 141         /* mmconfig is not enable */
 142         if (!(msr & FAM10H_MMIO_CONF_ENABLE))
 143                 return NULL;
 144
 145         base = msr & (FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT);
 146
 147         busnbits = (msr >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) &
 148                          FAM10H_MMIO_CONF_BUSRANGE_MASK;
 149
 150         /*
 151          * only handle bus 0 ?
 152          * need to skip it
 153          */
 154         if (!busnbits)
 155                 return NULL;
 156
 157         if (busnbits > 8) {
 158                 segnbits = busnbits - 8;
 159                 busnbits = 8;
 160         }
 161
 162         end_bus = (1 << busnbits) - 1;
 163         for (i = 0; i < (1 << segnbits); i++)
 164                 if (pci_mmconfig_add(i, 0, end_bus,
 165                                      base + (1<<28) * i) == NULL) {
 166                         free_all_mmcfg();
 167                         return NULL;
 168                 }
 169
 170         return "AMD Family 10h NB";
 171 }
 172
 173 static bool __initdata mcp55_checked;
 174 static const char __init *pci_mmcfg_nvidia_mcp55(void)
 175 {
 176         int bus;
 177         int mcp55_mmconf_found = 0;
 178
 179         static const u32 extcfg_regnum          = 0x90;
 180         static const u32 extcfg_regsize         = 4;
 181         static const u32 extcfg_enable_mask     = 1<<31;
 182         static const u32 extcfg_start_mask      = 0xff<<16;
 183         static const int extcfg_start_shift     = 16;
 184         static const u32 extcfg_size_mask       = 0x3<<28;
 185         static const int extcfg_size_shift      = 28;
 186         static const int extcfg_sizebus[]       = {0x100, 0x80, 0x40, 0x20};
 187         static const u32 extcfg_base_mask[]     = {0x7ff8, 0x7ffc, 0x7ffe, 0x7fff};
 188         static const int extcfg_base_lshift     = 25;
 189
 190         /*
 191          * do check if amd fam10h already took over
 192          */
 193         if (!acpi_disabled || pci_mmcfg_config_num || mcp55_checked)
 194                 return NULL;
 195
 196         mcp55_checked = true;
 197         for (bus = 0; bus < 256; bus++) {
 198                 u64 base;
 199                 u32 l, extcfg;
 200                 u16 vendor, device;
 201                 int start, size_index, end;
 202
 203                 raw_pci_ops->read(0, bus, PCI_DEVFN(0, 0), 0, 4, &l);
 204                 vendor = l & 0xffff;
 205                 device = (l >> 16) & 0xffff;
 206
 207                 if (PCI_VENDOR_ID_NVIDIA != vendor || 0x0369 != device)
 208                         continue;
 209
 210                 raw_pci_ops->read(0, bus, PCI_DEVFN(0, 0), extcfg_regnum,
 211                                   extcfg_regsize, &extcfg);
 212
 213                 if (!(extcfg & extcfg_enable_mask))
 214                         continue;
 215
 216                 size_index = (extcfg & extcfg_size_mask) >> extcfg_size_shift;
 217                 base = extcfg & extcfg_base_mask[size_index];
 218                 /* base could > 4G */
 219                 base <<= extcfg_base_lshift;
 220                 start = (extcfg & extcfg_start_mask) >> extcfg_start_shift;
 221                 end = start + extcfg_sizebus[size_index] - 1;
 222                 if (pci_mmconfig_add(0, start, end, base) == NULL)
 223                         continue;
 224                 mcp55_mmconf_found++;
 225         }
 226
 227         if (!mcp55_mmconf_found)
 228                 return NULL;
 229
 230         return "nVidia MCP55";
 231 }
 232
 233 struct pci_mmcfg_hostbridge_probe {
 234         u32 bus;
 235         u32 devfn;
 236         u32 vendor;
 237         u32 device;
 238         const char *(*probe)(void);
 239 };
 240
 241 static struct pci_mmcfg_hostbridge_probe pci_mmcfg_probes[] __initdata = {
 242         { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL,
 243           PCI_DEVICE_ID_INTEL_E7520_MCH, pci_mmcfg_e7520 },
 244         { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL,
 245           PCI_DEVICE_ID_INTEL_82945G_HB, pci_mmcfg_intel_945 },
 246         { 0, PCI_DEVFN(0x18, 0), PCI_VENDOR_ID_AMD,
 247           0x1200, pci_mmcfg_amd_fam10h },
 248         { 0xff, PCI_DEVFN(0, 0), PCI_VENDOR_ID_AMD,
 249           0x1200, pci_mmcfg_amd_fam10h },
 250         { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_NVIDIA,
 251           0x0369, pci_mmcfg_nvidia_mcp55 },
 252 };
 253
 254 static int __init cmp_mmcfg(const void *x1, const void *x2)
 255 {
 256         const typeof(pci_mmcfg_config[0]) *m1 = x1;
 257         const typeof(pci_mmcfg_config[0]) *m2 = x2;
 258         int start1, start2;
 259
 260         start1 = m1->start_bus_number;
 261         start2 = m2->start_bus_number;
 262
 263         return start1 - start2;
 264 }
 265
 266 static void __init pci_mmcfg_check_end_bus_number(void)
 267 {
 268         int i;
 269         typeof(pci_mmcfg_config[0]) *cfg, *cfgx;
 270
 271         /* sort them at first */
 272         sort(pci_mmcfg_config, pci_mmcfg_config_num,
 273                  sizeof(pci_mmcfg_config[0]), cmp_mmcfg, NULL);
 274
 275         /* last one*/
 276         if (pci_mmcfg_config_num > 0) {
 277                 i = pci_mmcfg_config_num - 1;
 278                 cfg = &pci_mmcfg_config[i];
 279                 if (cfg->end_bus_number < cfg->start_bus_number)
 280                         cfg->end_bus_number = 255;
 281         }
 282
 283         /* don't overlap please */
 284         for (i = 0; i < pci_mmcfg_config_num - 1; i++) {
 285                 cfg = &pci_mmcfg_config[i];
 286                 cfgx = &pci_mmcfg_config[i+1];
 287
 288                 if (cfg->end_bus_number < cfg->start_bus_number)
 289                         cfg->end_bus_number = 255;
 290
 291                 if (cfg->end_bus_number >= cfgx->start_bus_number)
 292                         cfg->end_bus_number = cfgx->start_bus_number - 1;
 293         }
 294 }
 295
 296 static int __init pci_mmcfg_check_hostbridge(void)
 297 {
 298         u32 l;
 299         u32 bus, devfn;
 300         u16 vendor, device;
 301         int i;
 302         const char *name;
 303
 304         if (!raw_pci_ops)
 305                 return 0;
 306
 307         free_all_mmcfg();
 308
 309         for (i = 0; i < ARRAY_SIZE(pci_mmcfg_probes); i++) {
 310                 bus =  pci_mmcfg_probes[i].bus;
 311                 devfn = pci_mmcfg_probes[i].devfn;
 312                 raw_pci_ops->read(0, bus, devfn, 0, 4, &l);
 313                 vendor = l & 0xffff;
 314                 device = (l >> 16) & 0xffff;
 315
 316                 name = NULL;
 317                 if (pci_mmcfg_probes[i].vendor == vendor &&
 318                     pci_mmcfg_probes[i].device == device)
 319                         name = pci_mmcfg_probes[i].probe();
 320
 321                 if (name)
 322                         printk(KERN_INFO "PCI: Found %s with MMCONFIG support.\n",
 323                                name);
 324         }
 325
 326         /* some end_bus_number is crazy, fix it */
 327         pci_mmcfg_check_end_bus_number();
 328
 329         return pci_mmcfg_config_num != 0;
 330 }
 331
 332 static void __init pci_mmcfg_insert_resources(void)
 333 {
 334 #define PCI_MMCFG_RESOURCE_NAME_LEN 24
 335         int i;
 336         struct resource *res;
 337         char *names;
 338         unsigned num_buses;
 339
 340         res = kcalloc(PCI_MMCFG_RESOURCE_NAME_LEN + sizeof(*res),
 341                         pci_mmcfg_config_num, GFP_KERNEL);
 342         if (!res) {
 343                 printk(KERN_ERR "PCI: Unable to allocate MMCONFIG resources\n");
 344                 return;
 345         }
 346
 347         names = (void *)&res[pci_mmcfg_config_num];
 348         for (i = 0; i < pci_mmcfg_config_num; i++, res++) {
 349                 struct acpi_mcfg_allocation *cfg = &pci_mmcfg_config[i];
 350                 num_buses = cfg->end_bus_number - cfg->start_bus_number + 1;
 351                 res->name = names;
 352                 snprintf(names, PCI_MMCFG_RESOURCE_NAME_LEN,
 353                          "PCI MMCONFIG %u [%02x-%02x]", cfg->pci_segment,
 354                          cfg->start_bus_number, cfg->end_bus_number);
 355                 res->start = cfg->address + (cfg->start_bus_number << 20);
 356                 res->end = res->start + (num_buses << 20) - 1;
 357                 res->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
 358                 insert_resource(&iomem_resource, res);
 359                 names += PCI_MMCFG_RESOURCE_NAME_LEN;
 360         }
 361
 362         /* Mark that the resources have been inserted. */
 363         pci_mmcfg_resources_inserted = 1;
 364 }
 365
 366 static acpi_status __init check_mcfg_resource(struct acpi_resource *res,
 367                                               void *data)
 368 {
 369         struct resource *mcfg_res = data;
 370         struct acpi_resource_address64 address;
 371         acpi_status status;
 372
 373         if (res->type == ACPI_RESOURCE_TYPE_FIXED_MEMORY32) {
 374                 struct acpi_resource_fixed_memory32 *fixmem32 =
 375                         &res->data.fixed_memory32;
 376                 if (!fixmem32)
 377                         return AE_OK;
 378                 if ((mcfg_res->start >= fixmem32->address) &&
 379                     (mcfg_res->end < (fixmem32->address +
 380                                       fixmem32->address_length))) {
 381                         mcfg_res->flags = 1;
 382                         return AE_CTRL_TERMINATE;
 383                 }
 384         }
 385         if ((res->type != ACPI_RESOURCE_TYPE_ADDRESS32) &&
 386             (res->type != ACPI_RESOURCE_TYPE_ADDRESS64))
 387                 return AE_OK;
 388
 389         status = acpi_resource_to_address64(res, &address);
 390         if (ACPI_FAILURE(status) ||
 391            (address.address_length <= 0) ||
 392            (address.resource_type != ACPI_MEMORY_RANGE))
 393                 return AE_OK;
 394
 395         if ((mcfg_res->start >= address.minimum) &&
 396             (mcfg_res->end < (address.minimum + address.address_length))) {
 397                 mcfg_res->flags = 1;
 398                 return AE_CTRL_TERMINATE;
 399         }
 400         return AE_OK;
 401 }
 402
 403 static acpi_status __init find_mboard_resource(acpi_handle handle, u32 lvl,
 404                 void *context, void **rv)
 405 {
 406         struct resource *mcfg_res = context;
 407
 408         acpi_walk_resources(handle, METHOD_NAME__CRS,
 409                             check_mcfg_resource, context);
 410
 411         if (mcfg_res->flags)
 412                 return AE_CTRL_TERMINATE;
 413
 414         return AE_OK;
 415 }
 416
 417 static int __init is_acpi_reserved(u64 start, u64 end, unsigned not_used)
 418 {
 419         struct resource mcfg_res;
 420
 421         mcfg_res.start = start;
 422         mcfg_res.end = end - 1;
 423         mcfg_res.flags = 0;
 424
 425         acpi_get_devices("PNP0C01", find_mboard_resource, &mcfg_res, NULL);
 426
 427         if (!mcfg_res.flags)
 428                 acpi_get_devices("PNP0C02", find_mboard_resource, &mcfg_res,
 429                                  NULL);
 430
 431         return mcfg_res.flags;
 432 }
 433
 434 typedef int (*check_reserved_t)(u64 start, u64 end, unsigned type);
 435
 436 static int __init is_mmconf_reserved(check_reserved_t is_reserved,
 437                 u64 addr, u64 size, int i,
 438                 typeof(pci_mmcfg_config[0]) *cfg, int with_e820)
 439 {
 440         u64 old_size = size;
 441         int valid = 0;
 442
 443         while (!is_reserved(addr, addr + size, E820_RESERVED)) {
 444                 size >>= 1;
 445                 if (size < (16UL<<20))
 446                         break;
 447         }
 448
 449         if (size >= (16UL<<20) || size == old_size) {
 450                 printk(KERN_NOTICE
 451                        "PCI: MCFG area at %Lx reserved in %s\n",
 452                         addr, with_e820?"E820":"ACPI motherboard resources");
 453                 valid = 1;
 454
 455                 if (old_size != size) {
 456                         /* update end_bus_number */
 457                         cfg->end_bus_number = cfg->start_bus_number + ((size>>20) - 1);
 458                         printk(KERN_NOTICE "PCI: updated MCFG configuration %d: base %lx "
 459                                "segment %hu buses %u - %u\n",
 460                                i, (unsigned long)cfg->address, cfg->pci_segment,
 461                                (unsigned int)cfg->start_bus_number,
 462                                (unsigned int)cfg->end_bus_number);
 463                 }
 464         }
 465
 466         return valid;
 467 }
 468
 469 static void __init pci_mmcfg_reject_broken(int early)
 470 {
 471         typeof(pci_mmcfg_config[0]) *cfg;
 472         int i;
 473
 474         if ((pci_mmcfg_config_num == 0) ||
 475             (pci_mmcfg_config == NULL) ||
 476             (pci_mmcfg_config[0].address == 0))
 477                 return;
 478
 479         for (i = 0; i < pci_mmcfg_config_num; i++) {
 480                 int valid = 0;
 481                 u64 addr, size;
 482
 483                 cfg = &pci_mmcfg_config[i];
 484                 addr = cfg->start_bus_number;
 485                 addr <<= 20;
 486                 addr += cfg->address;
 487                 size = cfg->end_bus_number + 1 - cfg->start_bus_number;
 488                 size <<= 20;
 489                 printk(KERN_NOTICE "PCI: MCFG configuration %d: base %lx "
 490                        "segment %hu buses %u - %u\n",
 491                        i, (unsigned long)cfg->address, cfg->pci_segment,
 492                        (unsigned int)cfg->start_bus_number,
 493                        (unsigned int)cfg->end_bus_number);
 494
 495                 if (!early && !acpi_disabled)
 496                         valid = is_mmconf_reserved(is_acpi_reserved, addr, size, i, cfg, 0);
 497
 498                 if (valid)
 499                         continue;
 500
 501                 if (!early)
 502                         printk(KERN_ERR "PCI: BIOS Bug: MCFG area at %Lx is not"
 503                                " reserved in ACPI motherboard resources\n",
 504                                cfg->address);
 505
 506                 /* Don't try to do this check unless configuration
 507                    type 1 is available. how about type 2 ?*/
 508                 if (raw_pci_ops)
 509                         valid = is_mmconf_reserved(e820_all_mapped, addr, size, i, cfg, 1);
 510
 511                 if (!valid)
 512                         goto reject;
 513         }
 514
 515         return;
 516
 517 reject:
 518         printk(KERN_INFO "PCI: Not using MMCONFIG.\n");
 519         free_all_mmcfg();
 520 }
 521
 522 static int __initdata known_bridge;
 523
 524 /* The physical address of the MMCONFIG aperture.  Set from ACPI tables. */
 525 struct acpi_mcfg_allocation *pci_mmcfg_config;
 526 int pci_mmcfg_config_num;
 527
 528 static int __init acpi_mcfg_check_entry(struct acpi_table_mcfg *mcfg,
 529                                         struct acpi_mcfg_allocation *cfg)
 530 {
 531         int year;
 532
 533         if (cfg->address < 0xFFFFFFFF)
 534                 return 0;
 535
 536         if (!strcmp(mcfg->header.oem_id, "SGI"))
 537                 return 0;
 538
 539         if (mcfg->header.revision >= 1) {
 540                 if (dmi_get_date(DMI_BIOS_DATE, &year, NULL, NULL) &&
 541                     year >= 2010)
 542                         return 0;
 543         }
 544
 545         printk(KERN_ERR PREFIX "MCFG region for %04x:%02x-%02x at %#llx "
 546                "is above 4GB, ignored\n", cfg->pci_segment,
 547                cfg->start_bus_number, cfg->end_bus_number, cfg->address);
 548         return -EINVAL;
 549 }
 550
 551 static int __init pci_parse_mcfg(struct acpi_table_header *header)
 552 {
 553         struct acpi_table_mcfg *mcfg;
 554         struct acpi_mcfg_allocation *cfg_table, *cfg;
 555         unsigned long i;
 556         int entries;
 557
 558         if (!header)
 559                 return -EINVAL;
 560
 561         mcfg = (struct acpi_table_mcfg *)header;
 562
 563         /* how many config structures do we have */
 564         free_all_mmcfg();
 565         entries = 0;
 566         i = header->length - sizeof(struct acpi_table_mcfg);
 567         while (i >= sizeof(struct acpi_mcfg_allocation)) {
 568                 entries++;
 569                 i -= sizeof(struct acpi_mcfg_allocation);
 570         };
 571         if (entries == 0) {
 572                 printk(KERN_ERR PREFIX "MMCONFIG has no entries\n");
 573                 return -ENODEV;
 574         }
 575
 576         cfg_table = (struct acpi_mcfg_allocation *) &mcfg[1];
 577         for (i = 0; i < entries; i++) {
 578                 cfg = &cfg_table[i];
 579                 if (acpi_mcfg_check_entry(mcfg, cfg)) {
 580                         free_all_mmcfg();
 581                         return -ENODEV;
 582                 }
 583
 584                 if (pci_mmconfig_add(cfg->pci_segment, cfg->start_bus_number,
 585                                    cfg->end_bus_number, cfg->address) == NULL) {
 586                         printk(KERN_WARNING PREFIX
 587                                "no memory for MCFG entries\n");
 588                         free_all_mmcfg();
 589                         return -ENOMEM;
 590                 }
 591         }
 592
 593         return 0;
 594 }
 595
 596 static void __init __pci_mmcfg_init(int early)
 597 {
 598         /* MMCONFIG disabled */
 599         if ((pci_probe & PCI_PROBE_MMCONF) == 0)
 600                 return;
 601
 602         /* MMCONFIG already enabled */
 603         if (!early && !(pci_probe & PCI_PROBE_MASK & ~PCI_PROBE_MMCONF))
 604                 return;
 605
 606         /* for late to exit */
 607         if (known_bridge)
 608                 return;
 609
 610         if (early) {
 611                 if (pci_mmcfg_check_hostbridge())
 612                         known_bridge = 1;
 613         }
 614
 615         if (!known_bridge)
 616                 acpi_sfi_table_parse(ACPI_SIG_MCFG, pci_parse_mcfg);
 617
 618         pci_mmcfg_reject_broken(early);
 619
 620         if ((pci_mmcfg_config_num == 0) ||
 621             (pci_mmcfg_config == NULL) ||
 622             (pci_mmcfg_config[0].address == 0))
 623                 return;
 624
 625         if (pci_mmcfg_arch_init())
 626                 pci_probe = (pci_probe & ~PCI_PROBE_MASK) | PCI_PROBE_MMCONF;
 627         else {
 628                 /*
 629                  * Signal not to attempt to insert mmcfg resources because
 630                  * the architecture mmcfg setup could not initialize.
 631                  */
 632                 pci_mmcfg_resources_inserted = 1;
 633         }
 634 }
 635
 636 void __init pci_mmcfg_early_init(void)
 637 {
 638         __pci_mmcfg_init(1);
 639 }
 640
 641 void __init pci_mmcfg_late_init(void)
 642 {
 643         __pci_mmcfg_init(0);
 644 }
 645
 646 static int __init pci_mmcfg_late_insert_resources(void)
 647 {
 648         /*
 649          * If resources are already inserted or we are not using MMCONFIG,
 650          * don't insert the resources.
 651          */
 652         if ((pci_mmcfg_resources_inserted == 1) ||
 653             (pci_probe & PCI_PROBE_MMCONF) == 0 ||
 654             (pci_mmcfg_config_num == 0) ||
 655             (pci_mmcfg_config == NULL) ||
 656             (pci_mmcfg_config[0].address == 0))
 657                 return 1;
 658
 659         /*
 660          * Attempt to insert the mmcfg resources but not with the busy flag
 661          * marked so it won't cause request errors when __request_region is
 662          * called.
 663          */
 664         pci_mmcfg_insert_resources();
 665
 666         return 0;
 667 }
 668
 669 /*
 670  * Perform MMCONFIG resource insertion after PCI initialization to allow for
 671  * misprogrammed MCFG tables that state larger sizes but actually conflict
 672  * with other system resources.
 673  */
 674 late_initcall(pci_mmcfg_late_insert_resources);