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usb: gadget: m66592-udc: add pullup function
[zen-stable.git] / drivers / net / tulip / dmfe.c
blob4685127319669eadb65aa596ffed7ce8caa3b506
1 /*
2 A Davicom DM9102/DM9102A/DM9102A+DM9801/DM9102A+DM9802 NIC fast
3 ethernet driver for Linux.
4 Copyright (C) 1997 Sten Wang
5
6 This program is free software; you can redistribute it and/or
7 modify it under the terms of the GNU General Public License
8 as published by the Free Software Foundation; either version 2
9 of the License, or (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 DAVICOM Web-Site: www.davicom.com.tw
17
18 Author: Sten Wang, 886-3-5798797-8517, E-mail: sten_wang@davicom.com.tw
19 Maintainer: Tobias Ringstrom <tori@unhappy.mine.nu>
20
21 (C)Copyright 1997-1998 DAVICOM Semiconductor,Inc. All Rights Reserved.
22
23 Marcelo Tosatti <marcelo@conectiva.com.br> :
24 Made it compile in 2.3 (device to net_device)
25
26 Alan Cox <alan@lxorguk.ukuu.org.uk> :
27 Cleaned up for kernel merge.
28 Removed the back compatibility support
29 Reformatted, fixing spelling etc as I went
30 Removed IRQ 0-15 assumption
31
32 Jeff Garzik <jgarzik@pobox.com> :
33 Updated to use new PCI driver API.
34 Resource usage cleanups.
35 Report driver version to user.
36
37 Tobias Ringstrom <tori@unhappy.mine.nu> :
38 Cleaned up and added SMP safety. Thanks go to Jeff Garzik,
39 Andrew Morton and Frank Davis for the SMP safety fixes.
40
41 Vojtech Pavlik <vojtech@suse.cz> :
42 Cleaned up pointer arithmetics.
43 Fixed a lot of 64bit issues.
44 Cleaned up printk()s a bit.
45 Fixed some obvious big endian problems.
46
47 Tobias Ringstrom <tori@unhappy.mine.nu> :
48 Use time_after for jiffies calculation. Added ethtool
49 support. Updated PCI resource allocation. Do not
50 forget to unmap PCI mapped skbs.
51
52 Alan Cox <alan@lxorguk.ukuu.org.uk>
53 Added new PCI identifiers provided by Clear Zhang at ALi
54 for their 1563 ethernet device.
55
56 TODO
57
58 Check on 64 bit boxes.
59 Check and fix on big endian boxes.
60
61 Test and make sure PCI latency is now correct for all cases.
62 */
63
64 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
65
66 #define DRV_NAME "dmfe"
67 #define DRV_VERSION "1.36.4"
68 #define DRV_RELDATE "2002-01-17"
69
70 #include <linux/module.h>
71 #include <linux/kernel.h>
72 #include <linux/string.h>
73 #include <linux/timer.h>
74 #include <linux/ptrace.h>
75 #include <linux/errno.h>
76 #include <linux/ioport.h>
77 #include <linux/interrupt.h>
78 #include <linux/pci.h>
79 #include <linux/dma-mapping.h>
80 #include <linux/init.h>
81 #include <linux/netdevice.h>
82 #include <linux/etherdevice.h>
83 #include <linux/ethtool.h>
84 #include <linux/skbuff.h>
85 #include <linux/delay.h>
86 #include <linux/spinlock.h>
87 #include <linux/crc32.h>
88 #include <linux/bitops.h>
89
90 #include <asm/processor.h>
91 #include <asm/io.h>
92 #include <asm/dma.h>
93 #include <asm/uaccess.h>
94 #include <asm/irq.h>
95
96 #ifdef CONFIG_TULIP_DM910X
97 #include <linux/of.h>
98 #endif
99
100
101 /* Board/System/Debug information/definition ---------------- */
102 #define PCI_DM9132_ID 0x91321282 /* Davicom DM9132 ID */
103 #define PCI_DM9102_ID 0x91021282 /* Davicom DM9102 ID */
104 #define PCI_DM9100_ID 0x91001282 /* Davicom DM9100 ID */
105 #define PCI_DM9009_ID 0x90091282 /* Davicom DM9009 ID */
106
107 #define DM9102_IO_SIZE 0x80
108 #define DM9102A_IO_SIZE 0x100
109 #define TX_MAX_SEND_CNT 0x1 /* Maximum tx packet per time */
110 #define TX_DESC_CNT 0x10 /* Allocated Tx descriptors */
111 #define RX_DESC_CNT 0x20 /* Allocated Rx descriptors */
112 #define TX_FREE_DESC_CNT (TX_DESC_CNT - 2) /* Max TX packet count */
113 #define TX_WAKE_DESC_CNT (TX_DESC_CNT - 3) /* TX wakeup count */
114 #define DESC_ALL_CNT (TX_DESC_CNT + RX_DESC_CNT)
115 #define TX_BUF_ALLOC 0x600
116 #define RX_ALLOC_SIZE 0x620
117 #define DM910X_RESET 1
118 #define CR0_DEFAULT 0x00E00000 /* TX & RX burst mode */
119 #define CR6_DEFAULT 0x00080000 /* HD */
120 #define CR7_DEFAULT 0x180c1
121 #define CR15_DEFAULT 0x06 /* TxJabber RxWatchdog */
122 #define TDES0_ERR_MASK 0x4302 /* TXJT, LC, EC, FUE */
123 #define MAX_PACKET_SIZE 1514
124 #define DMFE_MAX_MULTICAST 14
125 #define RX_COPY_SIZE 100
126 #define MAX_CHECK_PACKET 0x8000
127 #define DM9801_NOISE_FLOOR 8
128 #define DM9802_NOISE_FLOOR 5
129
130 #define DMFE_WOL_LINKCHANGE 0x20000000
131 #define DMFE_WOL_SAMPLEPACKET 0x10000000
132 #define DMFE_WOL_MAGICPACKET 0x08000000
133
134
135 #define DMFE_10MHF 0
136 #define DMFE_100MHF 1
137 #define DMFE_10MFD 4
138 #define DMFE_100MFD 5
139 #define DMFE_AUTO 8
140 #define DMFE_1M_HPNA 0x10
141
142 #define DMFE_TXTH_72 0x400000 /* TX TH 72 byte */
143 #define DMFE_TXTH_96 0x404000 /* TX TH 96 byte */
144 #define DMFE_TXTH_128 0x0000 /* TX TH 128 byte */
145 #define DMFE_TXTH_256 0x4000 /* TX TH 256 byte */
146 #define DMFE_TXTH_512 0x8000 /* TX TH 512 byte */
147 #define DMFE_TXTH_1K 0xC000 /* TX TH 1K byte */
148
149 #define DMFE_TIMER_WUT (jiffies + HZ * 1)/* timer wakeup time : 1 second */
150 #define DMFE_TX_TIMEOUT ((3*HZ)/2) /* tx packet time-out time 1.5 s" */
151 #define DMFE_TX_KICK (HZ/2) /* tx packet Kick-out time 0.5 s" */
152
153 #define DMFE_DBUG(dbug_now, msg, value) \
154 do { \
155 if (dmfe_debug || (dbug_now)) \
156 pr_err("%s %lx\n", \
157 (msg), (long) (value)); \
158 } while (0)
159
160 #define SHOW_MEDIA_TYPE(mode) \
161 pr_info("Change Speed to %sMhz %s duplex\n" , \
162 (mode & 1) ? "100":"10", \
163 (mode & 4) ? "full":"half");
164
165
166 /* CR9 definition: SROM/MII */
167 #define CR9_SROM_READ 0x4800
168 #define CR9_SRCS 0x1
169 #define CR9_SRCLK 0x2
170 #define CR9_CRDOUT 0x8
171 #define SROM_DATA_0 0x0
172 #define SROM_DATA_1 0x4
173 #define PHY_DATA_1 0x20000
174 #define PHY_DATA_0 0x00000
175 #define MDCLKH 0x10000
176
177 #define PHY_POWER_DOWN 0x800
178
179 #define SROM_V41_CODE 0x14
180
181 #define SROM_CLK_WRITE(data, ioaddr) \
182 outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr); \
183 udelay(5); \
184 outl(data|CR9_SROM_READ|CR9_SRCS|CR9_SRCLK,ioaddr); \
185 udelay(5); \
186 outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr); \
187 udelay(5);
188
189 #define __CHK_IO_SIZE(pci_id, dev_rev) \
190 (( ((pci_id)==PCI_DM9132_ID) || ((dev_rev) >= 0x30) ) ? \
191 DM9102A_IO_SIZE: DM9102_IO_SIZE)
192
193 #define CHK_IO_SIZE(pci_dev) \
194 (__CHK_IO_SIZE(((pci_dev)->device << 16) | (pci_dev)->vendor, \
195 (pci_dev)->revision))
196
197 /* Sten Check */
198 #define DEVICE net_device
199
200 /* Structure/enum declaration ------------------------------- */
201 struct tx_desc {
202 __le32 tdes0, tdes1, tdes2, tdes3; /* Data for the card */
203 char *tx_buf_ptr; /* Data for us */
204 struct tx_desc *next_tx_desc;
205 } __attribute__(( aligned(32) ));
206
207 struct rx_desc {
208 __le32 rdes0, rdes1, rdes2, rdes3; /* Data for the card */
209 struct sk_buff *rx_skb_ptr; /* Data for us */
210 struct rx_desc *next_rx_desc;
211 } __attribute__(( aligned(32) ));
212
213 struct dmfe_board_info {
214 u32 chip_id; /* Chip vendor/Device ID */
215 u8 chip_revision; /* Chip revision */
216 struct DEVICE *next_dev; /* next device */
217 struct pci_dev *pdev; /* PCI device */
218 spinlock_t lock;
219
220 long ioaddr; /* I/O base address */
221 u32 cr0_data;
222 u32 cr5_data;
223 u32 cr6_data;
224 u32 cr7_data;
225 u32 cr15_data;
226
227 /* pointer for memory physical address */
228 dma_addr_t buf_pool_dma_ptr; /* Tx buffer pool memory */
229 dma_addr_t buf_pool_dma_start; /* Tx buffer pool align dword */
230 dma_addr_t desc_pool_dma_ptr; /* descriptor pool memory */
231 dma_addr_t first_tx_desc_dma;
232 dma_addr_t first_rx_desc_dma;
233
234 /* descriptor pointer */
235 unsigned char *buf_pool_ptr; /* Tx buffer pool memory */
236 unsigned char *buf_pool_start; /* Tx buffer pool align dword */
237 unsigned char *desc_pool_ptr; /* descriptor pool memory */
238 struct tx_desc *first_tx_desc;
239 struct tx_desc *tx_insert_ptr;
240 struct tx_desc *tx_remove_ptr;
241 struct rx_desc *first_rx_desc;
242 struct rx_desc *rx_insert_ptr;
243 struct rx_desc *rx_ready_ptr; /* packet come pointer */
244 unsigned long tx_packet_cnt; /* transmitted packet count */
245 unsigned long tx_queue_cnt; /* wait to send packet count */
246 unsigned long rx_avail_cnt; /* available rx descriptor count */
247 unsigned long interval_rx_cnt; /* rx packet count a callback time */
248
249 u16 HPNA_command; /* For HPNA register 16 */
250 u16 HPNA_timer; /* For HPNA remote device check */
251 u16 dbug_cnt;
252 u16 NIC_capability; /* NIC media capability */
253 u16 PHY_reg4; /* Saved Phyxcer register 4 value */
254
255 u8 HPNA_present; /* 0:none, 1:DM9801, 2:DM9802 */
256 u8 chip_type; /* Keep DM9102A chip type */
257 u8 media_mode; /* user specify media mode */
258 u8 op_mode; /* real work media mode */
259 u8 phy_addr;
260 u8 wait_reset; /* Hardware failed, need to reset */
261 u8 dm910x_chk_mode; /* Operating mode check */
262 u8 first_in_callback; /* Flag to record state */
263 u8 wol_mode; /* user WOL settings */
264 struct timer_list timer;
265
266 /* Driver defined statistic counter */
267 unsigned long tx_fifo_underrun;
268 unsigned long tx_loss_carrier;
269 unsigned long tx_no_carrier;
270 unsigned long tx_late_collision;
271 unsigned long tx_excessive_collision;
272 unsigned long tx_jabber_timeout;
273 unsigned long reset_count;
274 unsigned long reset_cr8;
275 unsigned long reset_fatal;
276 unsigned long reset_TXtimeout;
277
278 /* NIC SROM data */
279 unsigned char srom[128];
280 };
281
282 enum dmfe_offsets {
283 DCR0 = 0x00, DCR1 = 0x08, DCR2 = 0x10, DCR3 = 0x18, DCR4 = 0x20,
284 DCR5 = 0x28, DCR6 = 0x30, DCR7 = 0x38, DCR8 = 0x40, DCR9 = 0x48,
285 DCR10 = 0x50, DCR11 = 0x58, DCR12 = 0x60, DCR13 = 0x68, DCR14 = 0x70,
286 DCR15 = 0x78
287 };
288
289 enum dmfe_CR6_bits {
290 CR6_RXSC = 0x2, CR6_PBF = 0x8, CR6_PM = 0x40, CR6_PAM = 0x80,
291 CR6_FDM = 0x200, CR6_TXSC = 0x2000, CR6_STI = 0x100000,
292 CR6_SFT = 0x200000, CR6_RXA = 0x40000000, CR6_NO_PURGE = 0x20000000
293 };
294
295 /* Global variable declaration ----------------------------- */
296 static int __devinitdata printed_version;
297 static const char version[] __devinitconst =
298 "Davicom DM9xxx net driver, version " DRV_VERSION " (" DRV_RELDATE ")";
299
300 static int dmfe_debug;
301 static unsigned char dmfe_media_mode = DMFE_AUTO;
302 static u32 dmfe_cr6_user_set;
303
304 /* For module input parameter */
305 static int debug;
306 static u32 cr6set;
307 static unsigned char mode = 8;
308 static u8 chkmode = 1;
309 static u8 HPNA_mode; /* Default: Low Power/High Speed */
310 static u8 HPNA_rx_cmd; /* Default: Disable Rx remote command */
311 static u8 HPNA_tx_cmd; /* Default: Don't issue remote command */
312 static u8 HPNA_NoiseFloor; /* Default: HPNA NoiseFloor */
313 static u8 SF_mode; /* Special Function: 1:VLAN, 2:RX Flow Control
314 4: TX pause packet */
315
316
317 /* function declaration ------------------------------------- */
318 static int dmfe_open(struct DEVICE *);
319 static netdev_tx_t dmfe_start_xmit(struct sk_buff *, struct DEVICE *);
320 static int dmfe_stop(struct DEVICE *);
321 static void dmfe_set_filter_mode(struct DEVICE *);
322 static const struct ethtool_ops netdev_ethtool_ops;
323 static u16 read_srom_word(long ,int);
324 static irqreturn_t dmfe_interrupt(int , void *);
325 #ifdef CONFIG_NET_POLL_CONTROLLER
326 static void poll_dmfe (struct net_device *dev);
327 #endif
328 static void dmfe_descriptor_init(struct dmfe_board_info *, unsigned long);
329 static void allocate_rx_buffer(struct dmfe_board_info *);
330 static void update_cr6(u32, unsigned long);
331 static void send_filter_frame(struct DEVICE *);
332 static void dm9132_id_table(struct DEVICE *);
333 static u16 phy_read(unsigned long, u8, u8, u32);
334 static void phy_write(unsigned long, u8, u8, u16, u32);
335 static void phy_write_1bit(unsigned long, u32);
336 static u16 phy_read_1bit(unsigned long);
337 static u8 dmfe_sense_speed(struct dmfe_board_info *);
338 static void dmfe_process_mode(struct dmfe_board_info *);
339 static void dmfe_timer(unsigned long);
340 static inline u32 cal_CRC(unsigned char *, unsigned int, u8);
341 static void dmfe_rx_packet(struct DEVICE *, struct dmfe_board_info *);
342 static void dmfe_free_tx_pkt(struct DEVICE *, struct dmfe_board_info *);
343 static void dmfe_reuse_skb(struct dmfe_board_info *, struct sk_buff *);
344 static void dmfe_dynamic_reset(struct DEVICE *);
345 static void dmfe_free_rxbuffer(struct dmfe_board_info *);
346 static void dmfe_init_dm910x(struct DEVICE *);
347 static void dmfe_parse_srom(struct dmfe_board_info *);
348 static void dmfe_program_DM9801(struct dmfe_board_info *, int);
349 static void dmfe_program_DM9802(struct dmfe_board_info *);
350 static void dmfe_HPNA_remote_cmd_chk(struct dmfe_board_info * );
351 static void dmfe_set_phyxcer(struct dmfe_board_info *);
352
353 /* DM910X network board routine ---------------------------- */
354
355 static const struct net_device_ops netdev_ops = {
356 .ndo_open = dmfe_open,
357 .ndo_stop = dmfe_stop,
358 .ndo_start_xmit = dmfe_start_xmit,
359 .ndo_set_multicast_list = dmfe_set_filter_mode,
360 .ndo_change_mtu = eth_change_mtu,
361 .ndo_set_mac_address = eth_mac_addr,
362 .ndo_validate_addr = eth_validate_addr,
363 #ifdef CONFIG_NET_POLL_CONTROLLER
364 .ndo_poll_controller = poll_dmfe,
365 #endif
366 };
367
368 /*
369 * Search DM910X board ,allocate space and register it
370 */
371
372 static int __devinit dmfe_init_one (struct pci_dev *pdev,
373 const struct pci_device_id *ent)
374 {
375 struct dmfe_board_info *db; /* board information structure */
376 struct net_device *dev;
377 u32 pci_pmr;
378 int i, err;
379
380 DMFE_DBUG(0, "dmfe_init_one()", 0);
381
382 if (!printed_version++)
383 pr_info("%s\n", version);
384
385 /*
386 * SPARC on-board DM910x chips should be handled by the main
387 * tulip driver, except for early DM9100s.
388 */
389 #ifdef CONFIG_TULIP_DM910X
390 if ((ent->driver_data == PCI_DM9100_ID && pdev->revision >= 0x30) ||
391 ent->driver_data == PCI_DM9102_ID) {
392 struct device_node *dp = pci_device_to_OF_node(pdev);
393
394 if (dp && of_get_property(dp, "local-mac-address", NULL)) {
395 pr_info("skipping on-board DM910x (use tulip)\n");
396 return -ENODEV;
397 }
398 }
399 #endif
400
401 /* Init network device */
402 dev = alloc_etherdev(sizeof(*db));
403 if (dev == NULL)
404 return -ENOMEM;
405 SET_NETDEV_DEV(dev, &pdev->dev);
406
407 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
408 pr_warn("32-bit PCI DMA not available\n");
409 err = -ENODEV;
410 goto err_out_free;
411 }
412
413 /* Enable Master/IO access, Disable memory access */
414 err = pci_enable_device(pdev);
415 if (err)
416 goto err_out_free;
417
418 if (!pci_resource_start(pdev, 0)) {
419 pr_err("I/O base is zero\n");
420 err = -ENODEV;
421 goto err_out_disable;
422 }
423
424 if (pci_resource_len(pdev, 0) < (CHK_IO_SIZE(pdev)) ) {
425 pr_err("Allocated I/O size too small\n");
426 err = -ENODEV;
427 goto err_out_disable;
428 }
429
430 #if 0 /* pci_{enable_device,set_master} sets minimum latency for us now */
431
432 /* Set Latency Timer 80h */
433 /* FIXME: setting values > 32 breaks some SiS 559x stuff.
434 Need a PCI quirk.. */
435
436 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80);
437 #endif
438
439 if (pci_request_regions(pdev, DRV_NAME)) {
440 pr_err("Failed to request PCI regions\n");
441 err = -ENODEV;
442 goto err_out_disable;
443 }
444
445 /* Init system & device */
446 db = netdev_priv(dev);
447
448 /* Allocate Tx/Rx descriptor memory */
449 db->desc_pool_ptr = pci_alloc_consistent(pdev, sizeof(struct tx_desc) *
450 DESC_ALL_CNT + 0x20, &db->desc_pool_dma_ptr);
451 if (!db->desc_pool_ptr)
452 goto err_out_res;
453
454 db->buf_pool_ptr = pci_alloc_consistent(pdev, TX_BUF_ALLOC *
455 TX_DESC_CNT + 4, &db->buf_pool_dma_ptr);
456 if (!db->buf_pool_ptr)
457 goto err_out_free_desc;
458
459 db->first_tx_desc = (struct tx_desc *) db->desc_pool_ptr;
460 db->first_tx_desc_dma = db->desc_pool_dma_ptr;
461 db->buf_pool_start = db->buf_pool_ptr;
462 db->buf_pool_dma_start = db->buf_pool_dma_ptr;
463
464 db->chip_id = ent->driver_data;
465 db->ioaddr = pci_resource_start(pdev, 0);
466 db->chip_revision = pdev->revision;
467 db->wol_mode = 0;
468
469 db->pdev = pdev;
470
471 dev->base_addr = db->ioaddr;
472 dev->irq = pdev->irq;
473 pci_set_drvdata(pdev, dev);
474 dev->netdev_ops = &netdev_ops;
475 dev->ethtool_ops = &netdev_ethtool_ops;
476 netif_carrier_off(dev);
477 spin_lock_init(&db->lock);
478
479 pci_read_config_dword(pdev, 0x50, &pci_pmr);
480 pci_pmr &= 0x70000;
481 if ( (pci_pmr == 0x10000) && (db->chip_revision == 0x31) )
482 db->chip_type = 1; /* DM9102A E3 */
483 else
484 db->chip_type = 0;
485
486 /* read 64 word srom data */
487 for (i = 0; i < 64; i++)
488 ((__le16 *) db->srom)[i] =
489 cpu_to_le16(read_srom_word(db->ioaddr, i));
490
491 /* Set Node address */
492 for (i = 0; i < 6; i++)
493 dev->dev_addr[i] = db->srom[20 + i];
494
495 err = register_netdev (dev);
496 if (err)
497 goto err_out_free_buf;
498
499 dev_info(&dev->dev, "Davicom DM%04lx at pci%s, %pM, irq %d\n",
500 ent->driver_data >> 16,
501 pci_name(pdev), dev->dev_addr, dev->irq);
502
503 pci_set_master(pdev);
504
505 return 0;
506
507 err_out_free_buf:
508 pci_free_consistent(pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4,
509 db->buf_pool_ptr, db->buf_pool_dma_ptr);
510 err_out_free_desc:
511 pci_free_consistent(pdev, sizeof(struct tx_desc) * DESC_ALL_CNT + 0x20,
512 db->desc_pool_ptr, db->desc_pool_dma_ptr);
513 err_out_res:
514 pci_release_regions(pdev);
515 err_out_disable:
516 pci_disable_device(pdev);
517 err_out_free:
518 pci_set_drvdata(pdev, NULL);
519 free_netdev(dev);
520
521 return err;
522 }
523
524
525 static void __devexit dmfe_remove_one (struct pci_dev *pdev)
526 {
527 struct net_device *dev = pci_get_drvdata(pdev);
528 struct dmfe_board_info *db = netdev_priv(dev);
529
530 DMFE_DBUG(0, "dmfe_remove_one()", 0);
531
532 if (dev) {
533
534 unregister_netdev(dev);
535
536 pci_free_consistent(db->pdev, sizeof(struct tx_desc) *
537 DESC_ALL_CNT + 0x20, db->desc_pool_ptr,
538 db->desc_pool_dma_ptr);
539 pci_free_consistent(db->pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4,
540 db->buf_pool_ptr, db->buf_pool_dma_ptr);
541 pci_release_regions(pdev);
542 free_netdev(dev); /* free board information */
543
544 pci_set_drvdata(pdev, NULL);
545 }
546
547 DMFE_DBUG(0, "dmfe_remove_one() exit", 0);
548 }
549
550
551 /*
552 * Open the interface.
553 * The interface is opened whenever "ifconfig" actives it.
554 */
555
556 static int dmfe_open(struct DEVICE *dev)
557 {
558 int ret;
559 struct dmfe_board_info *db = netdev_priv(dev);
560
561 DMFE_DBUG(0, "dmfe_open", 0);
562
563 ret = request_irq(dev->irq, dmfe_interrupt,
564 IRQF_SHARED, dev->name, dev);
565 if (ret)
566 return ret;
567
568 /* system variable init */
569 db->cr6_data = CR6_DEFAULT | dmfe_cr6_user_set;
570 db->tx_packet_cnt = 0;
571 db->tx_queue_cnt = 0;
572 db->rx_avail_cnt = 0;
573 db->wait_reset = 0;
574
575 db->first_in_callback = 0;
576 db->NIC_capability = 0xf; /* All capability*/
577 db->PHY_reg4 = 0x1e0;
578
579 /* CR6 operation mode decision */
580 if ( !chkmode || (db->chip_id == PCI_DM9132_ID) ||
581 (db->chip_revision >= 0x30) ) {
582 db->cr6_data |= DMFE_TXTH_256;
583 db->cr0_data = CR0_DEFAULT;
584 db->dm910x_chk_mode=4; /* Enter the normal mode */
585 } else {
586 db->cr6_data |= CR6_SFT; /* Store & Forward mode */
587 db->cr0_data = 0;
588 db->dm910x_chk_mode = 1; /* Enter the check mode */
589 }
590
591 /* Initialize DM910X board */
592 dmfe_init_dm910x(dev);
593
594 /* Active System Interface */
595 netif_wake_queue(dev);
596
597 /* set and active a timer process */
598 init_timer(&db->timer);
599 db->timer.expires = DMFE_TIMER_WUT + HZ * 2;
600 db->timer.data = (unsigned long)dev;
601 db->timer.function = dmfe_timer;
602 add_timer(&db->timer);
603
604 return 0;
605 }
606
607
608 /* Initialize DM910X board
609 * Reset DM910X board
610 * Initialize TX/Rx descriptor chain structure
611 * Send the set-up frame
612 * Enable Tx/Rx machine
613 */
614
615 static void dmfe_init_dm910x(struct DEVICE *dev)
616 {
617 struct dmfe_board_info *db = netdev_priv(dev);
618 unsigned long ioaddr = db->ioaddr;
619
620 DMFE_DBUG(0, "dmfe_init_dm910x()", 0);
621
622 /* Reset DM910x MAC controller */
623 outl(DM910X_RESET, ioaddr + DCR0); /* RESET MAC */
624 udelay(100);
625 outl(db->cr0_data, ioaddr + DCR0);
626 udelay(5);
627
628 /* Phy addr : DM910(A)2/DM9132/9801, phy address = 1 */
629 db->phy_addr = 1;
630
631 /* Parser SROM and media mode */
632 dmfe_parse_srom(db);
633 db->media_mode = dmfe_media_mode;
634
635 /* RESET Phyxcer Chip by GPR port bit 7 */
636 outl(0x180, ioaddr + DCR12); /* Let bit 7 output port */
637 if (db->chip_id == PCI_DM9009_ID) {
638 outl(0x80, ioaddr + DCR12); /* Issue RESET signal */
639 mdelay(300); /* Delay 300 ms */
640 }
641 outl(0x0, ioaddr + DCR12); /* Clear RESET signal */
642
643 /* Process Phyxcer Media Mode */
644 if ( !(db->media_mode & 0x10) ) /* Force 1M mode */
645 dmfe_set_phyxcer(db);
646
647 /* Media Mode Process */
648 if ( !(db->media_mode & DMFE_AUTO) )
649 db->op_mode = db->media_mode; /* Force Mode */
650
651 /* Initialize Transmit/Receive decriptor and CR3/4 */
652 dmfe_descriptor_init(db, ioaddr);
653
654 /* Init CR6 to program DM910x operation */
655 update_cr6(db->cr6_data, ioaddr);
656
657 /* Send setup frame */
658 if (db->chip_id == PCI_DM9132_ID)
659 dm9132_id_table(dev); /* DM9132 */
660 else
661 send_filter_frame(dev); /* DM9102/DM9102A */
662
663 /* Init CR7, interrupt active bit */
664 db->cr7_data = CR7_DEFAULT;
665 outl(db->cr7_data, ioaddr + DCR7);
666
667 /* Init CR15, Tx jabber and Rx watchdog timer */
668 outl(db->cr15_data, ioaddr + DCR15);
669
670 /* Enable DM910X Tx/Rx function */
671 db->cr6_data |= CR6_RXSC | CR6_TXSC | 0x40000;
672 update_cr6(db->cr6_data, ioaddr);
673 }
674
675
676 /*
677 * Hardware start transmission.
678 * Send a packet to media from the upper layer.
679 */
680
681 static netdev_tx_t dmfe_start_xmit(struct sk_buff *skb,
682 struct DEVICE *dev)
683 {
684 struct dmfe_board_info *db = netdev_priv(dev);
685 struct tx_desc *txptr;
686 unsigned long flags;
687
688 DMFE_DBUG(0, "dmfe_start_xmit", 0);
689
690 /* Too large packet check */
691 if (skb->len > MAX_PACKET_SIZE) {
692 pr_err("big packet = %d\n", (u16)skb->len);
693 dev_kfree_skb(skb);
694 return NETDEV_TX_OK;
695 }
696
697 /* Resource flag check */
698 netif_stop_queue(dev);
699
700 spin_lock_irqsave(&db->lock, flags);
701
702 /* No Tx resource check, it never happen nromally */
703 if (db->tx_queue_cnt >= TX_FREE_DESC_CNT) {
704 spin_unlock_irqrestore(&db->lock, flags);
705 pr_err("No Tx resource %ld\n", db->tx_queue_cnt);
706 return NETDEV_TX_BUSY;
707 }
708
709 /* Disable NIC interrupt */
710 outl(0, dev->base_addr + DCR7);
711
712 /* transmit this packet */
713 txptr = db->tx_insert_ptr;
714 skb_copy_from_linear_data(skb, txptr->tx_buf_ptr, skb->len);
715 txptr->tdes1 = cpu_to_le32(0xe1000000 | skb->len);
716
717 /* Point to next transmit free descriptor */
718 db->tx_insert_ptr = txptr->next_tx_desc;
719
720 /* Transmit Packet Process */
721 if ( (!db->tx_queue_cnt) && (db->tx_packet_cnt < TX_MAX_SEND_CNT) ) {
722 txptr->tdes0 = cpu_to_le32(0x80000000); /* Set owner bit */
723 db->tx_packet_cnt++; /* Ready to send */
724 outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */
725 dev->trans_start = jiffies; /* saved time stamp */
726 } else {
727 db->tx_queue_cnt++; /* queue TX packet */
728 outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */
729 }
730
731 /* Tx resource check */
732 if ( db->tx_queue_cnt < TX_FREE_DESC_CNT )
733 netif_wake_queue(dev);
734
735 /* Restore CR7 to enable interrupt */
736 spin_unlock_irqrestore(&db->lock, flags);
737 outl(db->cr7_data, dev->base_addr + DCR7);
738
739 /* free this SKB */
740 dev_kfree_skb(skb);
741
742 return NETDEV_TX_OK;
743 }
744
745
746 /*
747 * Stop the interface.
748 * The interface is stopped when it is brought.
749 */
750
751 static int dmfe_stop(struct DEVICE *dev)
752 {
753 struct dmfe_board_info *db = netdev_priv(dev);
754 unsigned long ioaddr = dev->base_addr;
755
756 DMFE_DBUG(0, "dmfe_stop", 0);
757
758 /* disable system */
759 netif_stop_queue(dev);
760
761 /* deleted timer */
762 del_timer_sync(&db->timer);
763
764 /* Reset & stop DM910X board */
765 outl(DM910X_RESET, ioaddr + DCR0);
766 udelay(5);
767 phy_write(db->ioaddr, db->phy_addr, 0, 0x8000, db->chip_id);
768
769 /* free interrupt */
770 free_irq(dev->irq, dev);
771
772 /* free allocated rx buffer */
773 dmfe_free_rxbuffer(db);
774
775 #if 0
776 /* show statistic counter */
777 printk("FU:%lx EC:%lx LC:%lx NC:%lx LOC:%lx TXJT:%lx RESET:%lx RCR8:%lx FAL:%lx TT:%lx\n",
778 db->tx_fifo_underrun, db->tx_excessive_collision,
779 db->tx_late_collision, db->tx_no_carrier, db->tx_loss_carrier,
780 db->tx_jabber_timeout, db->reset_count, db->reset_cr8,
781 db->reset_fatal, db->reset_TXtimeout);
782 #endif
783
784 return 0;
785 }
786
787
788 /*
789 * DM9102 insterrupt handler
790 * receive the packet to upper layer, free the transmitted packet
791 */
792
793 static irqreturn_t dmfe_interrupt(int irq, void *dev_id)
794 {
795 struct DEVICE *dev = dev_id;
796 struct dmfe_board_info *db = netdev_priv(dev);
797 unsigned long ioaddr = dev->base_addr;
798 unsigned long flags;
799
800 DMFE_DBUG(0, "dmfe_interrupt()", 0);
801
802 spin_lock_irqsave(&db->lock, flags);
803
804 /* Got DM910X status */
805 db->cr5_data = inl(ioaddr + DCR5);
806 outl(db->cr5_data, ioaddr + DCR5);
807 if ( !(db->cr5_data & 0xc1) ) {
808 spin_unlock_irqrestore(&db->lock, flags);
809 return IRQ_HANDLED;
810 }
811
812 /* Disable all interrupt in CR7 to solve the interrupt edge problem */
813 outl(0, ioaddr + DCR7);
814
815 /* Check system status */
816 if (db->cr5_data & 0x2000) {
817 /* system bus error happen */
818 DMFE_DBUG(1, "System bus error happen. CR5=", db->cr5_data);
819 db->reset_fatal++;
820 db->wait_reset = 1; /* Need to RESET */
821 spin_unlock_irqrestore(&db->lock, flags);
822 return IRQ_HANDLED;
823 }
824
825 /* Received the coming packet */
826 if ( (db->cr5_data & 0x40) && db->rx_avail_cnt )
827 dmfe_rx_packet(dev, db);
828
829 /* reallocate rx descriptor buffer */
830 if (db->rx_avail_cnt<RX_DESC_CNT)
831 allocate_rx_buffer(db);
832
833 /* Free the transmitted descriptor */
834 if ( db->cr5_data & 0x01)
835 dmfe_free_tx_pkt(dev, db);
836
837 /* Mode Check */
838 if (db->dm910x_chk_mode & 0x2) {
839 db->dm910x_chk_mode = 0x4;
840 db->cr6_data |= 0x100;
841 update_cr6(db->cr6_data, db->ioaddr);
842 }
843
844 /* Restore CR7 to enable interrupt mask */
845 outl(db->cr7_data, ioaddr + DCR7);
846
847 spin_unlock_irqrestore(&db->lock, flags);
848 return IRQ_HANDLED;
849 }
850
851
852 #ifdef CONFIG_NET_POLL_CONTROLLER
853 /*
854 * Polling 'interrupt' - used by things like netconsole to send skbs
855 * without having to re-enable interrupts. It's not called while
856 * the interrupt routine is executing.
857 */
858
859 static void poll_dmfe (struct net_device *dev)
860 {
861 /* disable_irq here is not very nice, but with the lockless
862 interrupt handler we have no other choice. */
863 disable_irq(dev->irq);
864 dmfe_interrupt (dev->irq, dev);
865 enable_irq(dev->irq);
866 }
867 #endif
868
869 /*
870 * Free TX resource after TX complete
871 */
872
873 static void dmfe_free_tx_pkt(struct DEVICE *dev, struct dmfe_board_info * db)
874 {
875 struct tx_desc *txptr;
876 unsigned long ioaddr = dev->base_addr;
877 u32 tdes0;
878
879 txptr = db->tx_remove_ptr;
880 while(db->tx_packet_cnt) {
881 tdes0 = le32_to_cpu(txptr->tdes0);
882 pr_debug("tdes0=%x\n", tdes0);
883 if (tdes0 & 0x80000000)
884 break;
885
886 /* A packet sent completed */
887 db->tx_packet_cnt--;
888 dev->stats.tx_packets++;
889
890 /* Transmit statistic counter */
891 if ( tdes0 != 0x7fffffff ) {
892 pr_debug("tdes0=%x\n", tdes0);
893 dev->stats.collisions += (tdes0 >> 3) & 0xf;
894 dev->stats.tx_bytes += le32_to_cpu(txptr->tdes1) & 0x7ff;
895 if (tdes0 & TDES0_ERR_MASK) {
896 dev->stats.tx_errors++;
897
898 if (tdes0 & 0x0002) { /* UnderRun */
899 db->tx_fifo_underrun++;
900 if ( !(db->cr6_data & CR6_SFT) ) {
901 db->cr6_data = db->cr6_data | CR6_SFT;
902 update_cr6(db->cr6_data, db->ioaddr);
903 }
904 }
905 if (tdes0 & 0x0100)
906 db->tx_excessive_collision++;
907 if (tdes0 & 0x0200)
908 db->tx_late_collision++;
909 if (tdes0 & 0x0400)
910 db->tx_no_carrier++;
911 if (tdes0 & 0x0800)
912 db->tx_loss_carrier++;
913 if (tdes0 & 0x4000)
914 db->tx_jabber_timeout++;
915 }
916 }
917
918 txptr = txptr->next_tx_desc;
919 }/* End of while */
920
921 /* Update TX remove pointer to next */
922 db->tx_remove_ptr = txptr;
923
924 /* Send the Tx packet in queue */
925 if ( (db->tx_packet_cnt < TX_MAX_SEND_CNT) && db->tx_queue_cnt ) {
926 txptr->tdes0 = cpu_to_le32(0x80000000); /* Set owner bit */
927 db->tx_packet_cnt++; /* Ready to send */
928 db->tx_queue_cnt--;
929 outl(0x1, ioaddr + DCR1); /* Issue Tx polling */
930 dev->trans_start = jiffies; /* saved time stamp */
931 }
932
933 /* Resource available check */
934 if ( db->tx_queue_cnt < TX_WAKE_DESC_CNT )
935 netif_wake_queue(dev); /* Active upper layer, send again */
936 }
937
938
939 /*
940 * Calculate the CRC valude of the Rx packet
941 * flag = 1 : return the reverse CRC (for the received packet CRC)
942 * 0 : return the normal CRC (for Hash Table index)
943 */
944
945 static inline u32 cal_CRC(unsigned char * Data, unsigned int Len, u8 flag)
946 {
947 u32 crc = crc32(~0, Data, Len);
948 if (flag) crc = ~crc;
949 return crc;
950 }
951
952
953 /*
954 * Receive the come packet and pass to upper layer
955 */
956
957 static void dmfe_rx_packet(struct DEVICE *dev, struct dmfe_board_info * db)
958 {
959 struct rx_desc *rxptr;
960 struct sk_buff *skb, *newskb;
961 int rxlen;
962 u32 rdes0;
963
964 rxptr = db->rx_ready_ptr;
965
966 while(db->rx_avail_cnt) {
967 rdes0 = le32_to_cpu(rxptr->rdes0);
968 if (rdes0 & 0x80000000) /* packet owner check */
969 break;
970
971 db->rx_avail_cnt--;
972 db->interval_rx_cnt++;
973
974 pci_unmap_single(db->pdev, le32_to_cpu(rxptr->rdes2),
975 RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
976
977 if ( (rdes0 & 0x300) != 0x300) {
978 /* A packet without First/Last flag */
979 /* reuse this SKB */
980 DMFE_DBUG(0, "Reuse SK buffer, rdes0", rdes0);
981 dmfe_reuse_skb(db, rxptr->rx_skb_ptr);
982 } else {
983 /* A packet with First/Last flag */
984 rxlen = ( (rdes0 >> 16) & 0x3fff) - 4;
985
986 /* error summary bit check */
987 if (rdes0 & 0x8000) {
988 /* This is a error packet */
989 pr_debug("rdes0: %x\n", rdes0);
990 dev->stats.rx_errors++;
991 if (rdes0 & 1)
992 dev->stats.rx_fifo_errors++;
993 if (rdes0 & 2)
994 dev->stats.rx_crc_errors++;
995 if (rdes0 & 0x80)
996 dev->stats.rx_length_errors++;
997 }
998
999 if ( !(rdes0 & 0x8000) ||
1000 ((db->cr6_data & CR6_PM) && (rxlen>6)) ) {
1001 skb = rxptr->rx_skb_ptr;
1002
1003 /* Received Packet CRC check need or not */
1004 if ( (db->dm910x_chk_mode & 1) &&
1005 (cal_CRC(skb->data, rxlen, 1) !=
1006 (*(u32 *) (skb->data+rxlen) ))) { /* FIXME (?) */
1007 /* Found a error received packet */
1008 dmfe_reuse_skb(db, rxptr->rx_skb_ptr);
1009 db->dm910x_chk_mode = 3;
1010 } else {
1011 /* Good packet, send to upper layer */
1012 /* Shorst packet used new SKB */
1013 if ((rxlen < RX_COPY_SIZE) &&
1014 ((newskb = dev_alloc_skb(rxlen + 2))
1015 != NULL)) {
1016
1017 skb = newskb;
1018 /* size less than COPY_SIZE, allocate a rxlen SKB */
1019 skb_reserve(skb, 2); /* 16byte align */
1020 skb_copy_from_linear_data(rxptr->rx_skb_ptr,
1021 skb_put(skb, rxlen),
1022 rxlen);
1023 dmfe_reuse_skb(db, rxptr->rx_skb_ptr);
1024 } else
1025 skb_put(skb, rxlen);
1026
1027 skb->protocol = eth_type_trans(skb, dev);
1028 netif_rx(skb);
1029 dev->stats.rx_packets++;
1030 dev->stats.rx_bytes += rxlen;
1031 }
1032 } else {
1033 /* Reuse SKB buffer when the packet is error */
1034 DMFE_DBUG(0, "Reuse SK buffer, rdes0", rdes0);
1035 dmfe_reuse_skb(db, rxptr->rx_skb_ptr);
1036 }
1037 }
1038
1039 rxptr = rxptr->next_rx_desc;
1040 }
1041
1042 db->rx_ready_ptr = rxptr;
1043 }
1044
1045 /*
1046 * Set DM910X multicast address
1047 */
1048
1049 static void dmfe_set_filter_mode(struct DEVICE * dev)
1050 {
1051 struct dmfe_board_info *db = netdev_priv(dev);
1052 unsigned long flags;
1053 int mc_count = netdev_mc_count(dev);
1054
1055 DMFE_DBUG(0, "dmfe_set_filter_mode()", 0);
1056 spin_lock_irqsave(&db->lock, flags);
1057
1058 if (dev->flags & IFF_PROMISC) {
1059 DMFE_DBUG(0, "Enable PROM Mode", 0);
1060 db->cr6_data |= CR6_PM | CR6_PBF;
1061 update_cr6(db->cr6_data, db->ioaddr);
1062 spin_unlock_irqrestore(&db->lock, flags);
1063 return;
1064 }
1065
1066 if (dev->flags & IFF_ALLMULTI || mc_count > DMFE_MAX_MULTICAST) {
1067 DMFE_DBUG(0, "Pass all multicast address", mc_count);
1068 db->cr6_data &= ~(CR6_PM | CR6_PBF);
1069 db->cr6_data |= CR6_PAM;
1070 spin_unlock_irqrestore(&db->lock, flags);
1071 return;
1072 }
1073
1074 DMFE_DBUG(0, "Set multicast address", mc_count);
1075 if (db->chip_id == PCI_DM9132_ID)
1076 dm9132_id_table(dev); /* DM9132 */
1077 else
1078 send_filter_frame(dev); /* DM9102/DM9102A */
1079 spin_unlock_irqrestore(&db->lock, flags);
1080 }
1081
1082 /*
1083 * Ethtool interace
1084 */
1085
1086 static void dmfe_ethtool_get_drvinfo(struct net_device *dev,
1087 struct ethtool_drvinfo *info)
1088 {
1089 struct dmfe_board_info *np = netdev_priv(dev);
1090
1091 strcpy(info->driver, DRV_NAME);
1092 strcpy(info->version, DRV_VERSION);
1093 if (np->pdev)
1094 strcpy(info->bus_info, pci_name(np->pdev));
1095 else
1096 sprintf(info->bus_info, "EISA 0x%lx %d",
1097 dev->base_addr, dev->irq);
1098 }
1099
1100 static int dmfe_ethtool_set_wol(struct net_device *dev,
1101 struct ethtool_wolinfo *wolinfo)
1102 {
1103 struct dmfe_board_info *db = netdev_priv(dev);
1104
1105 if (wolinfo->wolopts & (WAKE_UCAST | WAKE_MCAST | WAKE_BCAST |
1106 WAKE_ARP | WAKE_MAGICSECURE))
1107 return -EOPNOTSUPP;
1108
1109 db->wol_mode = wolinfo->wolopts;
1110 return 0;
1111 }
1112
1113 static void dmfe_ethtool_get_wol(struct net_device *dev,
1114 struct ethtool_wolinfo *wolinfo)
1115 {
1116 struct dmfe_board_info *db = netdev_priv(dev);
1117
1118 wolinfo->supported = WAKE_PHY | WAKE_MAGIC;
1119 wolinfo->wolopts = db->wol_mode;
1120 }
1121
1122
1123 static const struct ethtool_ops netdev_ethtool_ops = {
1124 .get_drvinfo = dmfe_ethtool_get_drvinfo,
1125 .get_link = ethtool_op_get_link,
1126 .set_wol = dmfe_ethtool_set_wol,
1127 .get_wol = dmfe_ethtool_get_wol,
1128 };
1129
1130 /*
1131 * A periodic timer routine
1132 * Dynamic media sense, allocate Rx buffer...
1133 */
1134
1135 static void dmfe_timer(unsigned long data)
1136 {
1137 u32 tmp_cr8;
1138 unsigned char tmp_cr12;
1139 struct DEVICE *dev = (struct DEVICE *) data;
1140 struct dmfe_board_info *db = netdev_priv(dev);
1141 unsigned long flags;
1142
1143 int link_ok, link_ok_phy;
1144
1145 DMFE_DBUG(0, "dmfe_timer()", 0);
1146 spin_lock_irqsave(&db->lock, flags);
1147
1148 /* Media mode process when Link OK before enter this route */
1149 if (db->first_in_callback == 0) {
1150 db->first_in_callback = 1;
1151 if (db->chip_type && (db->chip_id==PCI_DM9102_ID)) {
1152 db->cr6_data &= ~0x40000;
1153 update_cr6(db->cr6_data, db->ioaddr);
1154 phy_write(db->ioaddr,
1155 db->phy_addr, 0, 0x1000, db->chip_id);
1156 db->cr6_data |= 0x40000;
1157 update_cr6(db->cr6_data, db->ioaddr);
1158 db->timer.expires = DMFE_TIMER_WUT + HZ * 2;
1159 add_timer(&db->timer);
1160 spin_unlock_irqrestore(&db->lock, flags);
1161 return;
1162 }
1163 }
1164
1165
1166 /* Operating Mode Check */
1167 if ( (db->dm910x_chk_mode & 0x1) &&
1168 (dev->stats.rx_packets > MAX_CHECK_PACKET) )
1169 db->dm910x_chk_mode = 0x4;
1170
1171 /* Dynamic reset DM910X : system error or transmit time-out */
1172 tmp_cr8 = inl(db->ioaddr + DCR8);
1173 if ( (db->interval_rx_cnt==0) && (tmp_cr8) ) {
1174 db->reset_cr8++;
1175 db->wait_reset = 1;
1176 }
1177 db->interval_rx_cnt = 0;
1178
1179 /* TX polling kick monitor */
1180 if ( db->tx_packet_cnt &&
1181 time_after(jiffies, dev_trans_start(dev) + DMFE_TX_KICK) ) {
1182 outl(0x1, dev->base_addr + DCR1); /* Tx polling again */
1183
1184 /* TX Timeout */
1185 if (time_after(jiffies, dev_trans_start(dev) + DMFE_TX_TIMEOUT) ) {
1186 db->reset_TXtimeout++;
1187 db->wait_reset = 1;
1188 dev_warn(&dev->dev, "Tx timeout - resetting\n");
1189 }
1190 }
1191
1192 if (db->wait_reset) {
1193 DMFE_DBUG(0, "Dynamic Reset device", db->tx_packet_cnt);
1194 db->reset_count++;
1195 dmfe_dynamic_reset(dev);
1196 db->first_in_callback = 0;
1197 db->timer.expires = DMFE_TIMER_WUT;
1198 add_timer(&db->timer);
1199 spin_unlock_irqrestore(&db->lock, flags);
1200 return;
1201 }
1202
1203 /* Link status check, Dynamic media type change */
1204 if (db->chip_id == PCI_DM9132_ID)
1205 tmp_cr12 = inb(db->ioaddr + DCR9 + 3); /* DM9132 */
1206 else
1207 tmp_cr12 = inb(db->ioaddr + DCR12); /* DM9102/DM9102A */
1208
1209 if ( ((db->chip_id == PCI_DM9102_ID) &&
1210 (db->chip_revision == 0x30)) ||
1211 ((db->chip_id == PCI_DM9132_ID) &&
1212 (db->chip_revision == 0x10)) ) {
1213 /* DM9102A Chip */
1214 if (tmp_cr12 & 2)
1215 link_ok = 0;
1216 else
1217 link_ok = 1;
1218 }
1219 else
1220 /*0x43 is used instead of 0x3 because bit 6 should represent
1221 link status of external PHY */
1222 link_ok = (tmp_cr12 & 0x43) ? 1 : 0;
1223
1224
1225 /* If chip reports that link is failed it could be because external
1226 PHY link status pin is not connected correctly to chip
1227 To be sure ask PHY too.
1228 */
1229
1230 /* need a dummy read because of PHY's register latch*/
1231 phy_read (db->ioaddr, db->phy_addr, 1, db->chip_id);
1232 link_ok_phy = (phy_read (db->ioaddr,
1233 db->phy_addr, 1, db->chip_id) & 0x4) ? 1 : 0;
1234
1235 if (link_ok_phy != link_ok) {
1236 DMFE_DBUG (0, "PHY and chip report different link status", 0);
1237 link_ok = link_ok | link_ok_phy;
1238 }
1239
1240 if ( !link_ok && netif_carrier_ok(dev)) {
1241 /* Link Failed */
1242 DMFE_DBUG(0, "Link Failed", tmp_cr12);
1243 netif_carrier_off(dev);
1244
1245 /* For Force 10/100M Half/Full mode: Enable Auto-Nego mode */
1246 /* AUTO or force 1M Homerun/Longrun don't need */
1247 if ( !(db->media_mode & 0x38) )
1248 phy_write(db->ioaddr, db->phy_addr,
1249 0, 0x1000, db->chip_id);
1250
1251 /* AUTO mode, if INT phyxcer link failed, select EXT device */
1252 if (db->media_mode & DMFE_AUTO) {
1253 /* 10/100M link failed, used 1M Home-Net */
1254 db->cr6_data|=0x00040000; /* bit18=1, MII */
1255 db->cr6_data&=~0x00000200; /* bit9=0, HD mode */
1256 update_cr6(db->cr6_data, db->ioaddr);
1257 }
1258 } else if (!netif_carrier_ok(dev)) {
1259
1260 DMFE_DBUG(0, "Link link OK", tmp_cr12);
1261
1262 /* Auto Sense Speed */
1263 if ( !(db->media_mode & DMFE_AUTO) || !dmfe_sense_speed(db)) {
1264 netif_carrier_on(dev);
1265 SHOW_MEDIA_TYPE(db->op_mode);
1266 }
1267
1268 dmfe_process_mode(db);
1269 }
1270
1271 /* HPNA remote command check */
1272 if (db->HPNA_command & 0xf00) {
1273 db->HPNA_timer--;
1274 if (!db->HPNA_timer)
1275 dmfe_HPNA_remote_cmd_chk(db);
1276 }
1277
1278 /* Timer active again */
1279 db->timer.expires = DMFE_TIMER_WUT;
1280 add_timer(&db->timer);
1281 spin_unlock_irqrestore(&db->lock, flags);
1282 }
1283
1284
1285 /*
1286 * Dynamic reset the DM910X board
1287 * Stop DM910X board
1288 * Free Tx/Rx allocated memory
1289 * Reset DM910X board
1290 * Re-initialize DM910X board
1291 */
1292
1293 static void dmfe_dynamic_reset(struct DEVICE *dev)
1294 {
1295 struct dmfe_board_info *db = netdev_priv(dev);
1296
1297 DMFE_DBUG(0, "dmfe_dynamic_reset()", 0);
1298
1299 /* Sopt MAC controller */
1300 db->cr6_data &= ~(CR6_RXSC | CR6_TXSC); /* Disable Tx/Rx */
1301 update_cr6(db->cr6_data, dev->base_addr);
1302 outl(0, dev->base_addr + DCR7); /* Disable Interrupt */
1303 outl(inl(dev->base_addr + DCR5), dev->base_addr + DCR5);
1304
1305 /* Disable upper layer interface */
1306 netif_stop_queue(dev);
1307
1308 /* Free Rx Allocate buffer */
1309 dmfe_free_rxbuffer(db);
1310
1311 /* system variable init */
1312 db->tx_packet_cnt = 0;
1313 db->tx_queue_cnt = 0;
1314 db->rx_avail_cnt = 0;
1315 netif_carrier_off(dev);
1316 db->wait_reset = 0;
1317
1318 /* Re-initialize DM910X board */
1319 dmfe_init_dm910x(dev);
1320
1321 /* Restart upper layer interface */
1322 netif_wake_queue(dev);
1323 }
1324
1325
1326 /*
1327 * free all allocated rx buffer
1328 */
1329
1330 static void dmfe_free_rxbuffer(struct dmfe_board_info * db)
1331 {
1332 DMFE_DBUG(0, "dmfe_free_rxbuffer()", 0);
1333
1334 /* free allocated rx buffer */
1335 while (db->rx_avail_cnt) {
1336 dev_kfree_skb(db->rx_ready_ptr->rx_skb_ptr);
1337 db->rx_ready_ptr = db->rx_ready_ptr->next_rx_desc;
1338 db->rx_avail_cnt--;
1339 }
1340 }
1341
1342
1343 /*
1344 * Reuse the SK buffer
1345 */
1346
1347 static void dmfe_reuse_skb(struct dmfe_board_info *db, struct sk_buff * skb)
1348 {
1349 struct rx_desc *rxptr = db->rx_insert_ptr;
1350
1351 if (!(rxptr->rdes0 & cpu_to_le32(0x80000000))) {
1352 rxptr->rx_skb_ptr = skb;
1353 rxptr->rdes2 = cpu_to_le32( pci_map_single(db->pdev,
1354 skb->data, RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE) );
1355 wmb();
1356 rxptr->rdes0 = cpu_to_le32(0x80000000);
1357 db->rx_avail_cnt++;
1358 db->rx_insert_ptr = rxptr->next_rx_desc;
1359 } else
1360 DMFE_DBUG(0, "SK Buffer reuse method error", db->rx_avail_cnt);
1361 }
1362
1363
1364 /*
1365 * Initialize transmit/Receive descriptor
1366 * Using Chain structure, and allocate Tx/Rx buffer
1367 */
1368
1369 static void dmfe_descriptor_init(struct dmfe_board_info *db, unsigned long ioaddr)
1370 {
1371 struct tx_desc *tmp_tx;
1372 struct rx_desc *tmp_rx;
1373 unsigned char *tmp_buf;
1374 dma_addr_t tmp_tx_dma, tmp_rx_dma;
1375 dma_addr_t tmp_buf_dma;
1376 int i;
1377
1378 DMFE_DBUG(0, "dmfe_descriptor_init()", 0);
1379
1380 /* tx descriptor start pointer */
1381 db->tx_insert_ptr = db->first_tx_desc;
1382 db->tx_remove_ptr = db->first_tx_desc;
1383 outl(db->first_tx_desc_dma, ioaddr + DCR4); /* TX DESC address */
1384
1385 /* rx descriptor start pointer */
1386 db->first_rx_desc = (void *)db->first_tx_desc +
1387 sizeof(struct tx_desc) * TX_DESC_CNT;
1388
1389 db->first_rx_desc_dma = db->first_tx_desc_dma +
1390 sizeof(struct tx_desc) * TX_DESC_CNT;
1391 db->rx_insert_ptr = db->first_rx_desc;
1392 db->rx_ready_ptr = db->first_rx_desc;
1393 outl(db->first_rx_desc_dma, ioaddr + DCR3); /* RX DESC address */
1394
1395 /* Init Transmit chain */
1396 tmp_buf = db->buf_pool_start;
1397 tmp_buf_dma = db->buf_pool_dma_start;
1398 tmp_tx_dma = db->first_tx_desc_dma;
1399 for (tmp_tx = db->first_tx_desc, i = 0; i < TX_DESC_CNT; i++, tmp_tx++) {
1400 tmp_tx->tx_buf_ptr = tmp_buf;
1401 tmp_tx->tdes0 = cpu_to_le32(0);
1402 tmp_tx->tdes1 = cpu_to_le32(0x81000000); /* IC, chain */
1403 tmp_tx->tdes2 = cpu_to_le32(tmp_buf_dma);
1404 tmp_tx_dma += sizeof(struct tx_desc);
1405 tmp_tx->tdes3 = cpu_to_le32(tmp_tx_dma);
1406 tmp_tx->next_tx_desc = tmp_tx + 1;
1407 tmp_buf = tmp_buf + TX_BUF_ALLOC;
1408 tmp_buf_dma = tmp_buf_dma + TX_BUF_ALLOC;
1409 }
1410 (--tmp_tx)->tdes3 = cpu_to_le32(db->first_tx_desc_dma);
1411 tmp_tx->next_tx_desc = db->first_tx_desc;
1412
1413 /* Init Receive descriptor chain */
1414 tmp_rx_dma=db->first_rx_desc_dma;
1415 for (tmp_rx = db->first_rx_desc, i = 0; i < RX_DESC_CNT; i++, tmp_rx++) {
1416 tmp_rx->rdes0 = cpu_to_le32(0);
1417 tmp_rx->rdes1 = cpu_to_le32(0x01000600);
1418 tmp_rx_dma += sizeof(struct rx_desc);
1419 tmp_rx->rdes3 = cpu_to_le32(tmp_rx_dma);
1420 tmp_rx->next_rx_desc = tmp_rx + 1;
1421 }
1422 (--tmp_rx)->rdes3 = cpu_to_le32(db->first_rx_desc_dma);
1423 tmp_rx->next_rx_desc = db->first_rx_desc;
1424
1425 /* pre-allocate Rx buffer */
1426 allocate_rx_buffer(db);
1427 }
1428
1429
1430 /*
1431 * Update CR6 value
1432 * Firstly stop DM910X , then written value and start
1433 */
1434
1435 static void update_cr6(u32 cr6_data, unsigned long ioaddr)
1436 {
1437 u32 cr6_tmp;
1438
1439 cr6_tmp = cr6_data & ~0x2002; /* stop Tx/Rx */
1440 outl(cr6_tmp, ioaddr + DCR6);
1441 udelay(5);
1442 outl(cr6_data, ioaddr + DCR6);
1443 udelay(5);
1444 }
1445
1446
1447 /*
1448 * Send a setup frame for DM9132
1449 * This setup frame initialize DM910X address filter mode
1450 */
1451
1452 static void dm9132_id_table(struct DEVICE *dev)
1453 {
1454 struct netdev_hw_addr *ha;
1455 u16 * addrptr;
1456 unsigned long ioaddr = dev->base_addr+0xc0; /* ID Table */
1457 u32 hash_val;
1458 u16 i, hash_table[4];
1459
1460 DMFE_DBUG(0, "dm9132_id_table()", 0);
1461
1462 /* Node address */
1463 addrptr = (u16 *) dev->dev_addr;
1464 outw(addrptr[0], ioaddr);
1465 ioaddr += 4;
1466 outw(addrptr[1], ioaddr);
1467 ioaddr += 4;
1468 outw(addrptr[2], ioaddr);
1469 ioaddr += 4;
1470
1471 /* Clear Hash Table */
1472 memset(hash_table, 0, sizeof(hash_table));
1473
1474 /* broadcast address */
1475 hash_table[3] = 0x8000;
1476
1477 /* the multicast address in Hash Table : 64 bits */
1478 netdev_for_each_mc_addr(ha, dev) {
1479 hash_val = cal_CRC((char *) ha->addr, 6, 0) & 0x3f;
1480 hash_table[hash_val / 16] |= (u16) 1 << (hash_val % 16);
1481 }
1482
1483 /* Write the hash table to MAC MD table */
1484 for (i = 0; i < 4; i++, ioaddr += 4)
1485 outw(hash_table[i], ioaddr);
1486 }
1487
1488
1489 /*
1490 * Send a setup frame for DM9102/DM9102A
1491 * This setup frame initialize DM910X address filter mode
1492 */
1493
1494 static void send_filter_frame(struct DEVICE *dev)
1495 {
1496 struct dmfe_board_info *db = netdev_priv(dev);
1497 struct netdev_hw_addr *ha;
1498 struct tx_desc *txptr;
1499 u16 * addrptr;
1500 u32 * suptr;
1501 int i;
1502
1503 DMFE_DBUG(0, "send_filter_frame()", 0);
1504
1505 txptr = db->tx_insert_ptr;
1506 suptr = (u32 *) txptr->tx_buf_ptr;
1507
1508 /* Node address */
1509 addrptr = (u16 *) dev->dev_addr;
1510 *suptr++ = addrptr[0];
1511 *suptr++ = addrptr[1];
1512 *suptr++ = addrptr[2];
1513
1514 /* broadcast address */
1515 *suptr++ = 0xffff;
1516 *suptr++ = 0xffff;
1517 *suptr++ = 0xffff;
1518
1519 /* fit the multicast address */
1520 netdev_for_each_mc_addr(ha, dev) {
1521 addrptr = (u16 *) ha->addr;
1522 *suptr++ = addrptr[0];
1523 *suptr++ = addrptr[1];
1524 *suptr++ = addrptr[2];
1525 }
1526
1527 for (i = netdev_mc_count(dev); i < 14; i++) {
1528 *suptr++ = 0xffff;
1529 *suptr++ = 0xffff;
1530 *suptr++ = 0xffff;
1531 }
1532
1533 /* prepare the setup frame */
1534 db->tx_insert_ptr = txptr->next_tx_desc;
1535 txptr->tdes1 = cpu_to_le32(0x890000c0);
1536
1537 /* Resource Check and Send the setup packet */
1538 if (!db->tx_packet_cnt) {
1539 /* Resource Empty */
1540 db->tx_packet_cnt++;
1541 txptr->tdes0 = cpu_to_le32(0x80000000);
1542 update_cr6(db->cr6_data | 0x2000, dev->base_addr);
1543 outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */
1544 update_cr6(db->cr6_data, dev->base_addr);
1545 dev->trans_start = jiffies;
1546 } else
1547 db->tx_queue_cnt++; /* Put in TX queue */
1548 }
1549
1550
1551 /*
1552 * Allocate rx buffer,
1553 * As possible as allocate maxiumn Rx buffer
1554 */
1555
1556 static void allocate_rx_buffer(struct dmfe_board_info *db)
1557 {
1558 struct rx_desc *rxptr;
1559 struct sk_buff *skb;
1560
1561 rxptr = db->rx_insert_ptr;
1562
1563 while(db->rx_avail_cnt < RX_DESC_CNT) {
1564 if ( ( skb = dev_alloc_skb(RX_ALLOC_SIZE) ) == NULL )
1565 break;
1566 rxptr->rx_skb_ptr = skb; /* FIXME (?) */
1567 rxptr->rdes2 = cpu_to_le32( pci_map_single(db->pdev, skb->data,
1568 RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE) );
1569 wmb();
1570 rxptr->rdes0 = cpu_to_le32(0x80000000);
1571 rxptr = rxptr->next_rx_desc;
1572 db->rx_avail_cnt++;
1573 }
1574
1575 db->rx_insert_ptr = rxptr;
1576 }
1577
1578
1579 /*
1580 * Read one word data from the serial ROM
1581 */
1582
1583 static u16 read_srom_word(long ioaddr, int offset)
1584 {
1585 int i;
1586 u16 srom_data = 0;
1587 long cr9_ioaddr = ioaddr + DCR9;
1588
1589 outl(CR9_SROM_READ, cr9_ioaddr);
1590 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1591
1592 /* Send the Read Command 110b */
1593 SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
1594 SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
1595 SROM_CLK_WRITE(SROM_DATA_0, cr9_ioaddr);
1596
1597 /* Send the offset */
1598 for (i = 5; i >= 0; i--) {
1599 srom_data = (offset & (1 << i)) ? SROM_DATA_1 : SROM_DATA_0;
1600 SROM_CLK_WRITE(srom_data, cr9_ioaddr);
1601 }
1602
1603 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1604
1605 for (i = 16; i > 0; i--) {
1606 outl(CR9_SROM_READ | CR9_SRCS | CR9_SRCLK, cr9_ioaddr);
1607 udelay(5);
1608 srom_data = (srom_data << 1) |
1609 ((inl(cr9_ioaddr) & CR9_CRDOUT) ? 1 : 0);
1610 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1611 udelay(5);
1612 }
1613
1614 outl(CR9_SROM_READ, cr9_ioaddr);
1615 return srom_data;
1616 }
1617
1618
1619 /*
1620 * Auto sense the media mode
1621 */
1622
1623 static u8 dmfe_sense_speed(struct dmfe_board_info * db)
1624 {
1625 u8 ErrFlag = 0;
1626 u16 phy_mode;
1627
1628 /* CR6 bit18=0, select 10/100M */
1629 update_cr6( (db->cr6_data & ~0x40000), db->ioaddr);
1630
1631 phy_mode = phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id);
1632 phy_mode = phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id);
1633
1634 if ( (phy_mode & 0x24) == 0x24 ) {
1635 if (db->chip_id == PCI_DM9132_ID) /* DM9132 */
1636 phy_mode = phy_read(db->ioaddr,
1637 db->phy_addr, 7, db->chip_id) & 0xf000;
1638 else /* DM9102/DM9102A */
1639 phy_mode = phy_read(db->ioaddr,
1640 db->phy_addr, 17, db->chip_id) & 0xf000;
1641 pr_debug("Phy_mode %x\n", phy_mode);
1642 switch (phy_mode) {
1643 case 0x1000: db->op_mode = DMFE_10MHF; break;
1644 case 0x2000: db->op_mode = DMFE_10MFD; break;
1645 case 0x4000: db->op_mode = DMFE_100MHF; break;
1646 case 0x8000: db->op_mode = DMFE_100MFD; break;
1647 default: db->op_mode = DMFE_10MHF;
1648 ErrFlag = 1;
1649 break;
1650 }
1651 } else {
1652 db->op_mode = DMFE_10MHF;
1653 DMFE_DBUG(0, "Link Failed :", phy_mode);
1654 ErrFlag = 1;
1655 }
1656
1657 return ErrFlag;
1658 }
1659
1660
1661 /*
1662 * Set 10/100 phyxcer capability
1663 * AUTO mode : phyxcer register4 is NIC capability
1664 * Force mode: phyxcer register4 is the force media
1665 */
1666
1667 static void dmfe_set_phyxcer(struct dmfe_board_info *db)
1668 {
1669 u16 phy_reg;
1670
1671 /* Select 10/100M phyxcer */
1672 db->cr6_data &= ~0x40000;
1673 update_cr6(db->cr6_data, db->ioaddr);
1674
1675 /* DM9009 Chip: Phyxcer reg18 bit12=0 */
1676 if (db->chip_id == PCI_DM9009_ID) {
1677 phy_reg = phy_read(db->ioaddr,
1678 db->phy_addr, 18, db->chip_id) & ~0x1000;
1679
1680 phy_write(db->ioaddr,
1681 db->phy_addr, 18, phy_reg, db->chip_id);
1682 }
1683
1684 /* Phyxcer capability setting */
1685 phy_reg = phy_read(db->ioaddr, db->phy_addr, 4, db->chip_id) & ~0x01e0;
1686
1687 if (db->media_mode & DMFE_AUTO) {
1688 /* AUTO Mode */
1689 phy_reg |= db->PHY_reg4;
1690 } else {
1691 /* Force Mode */
1692 switch(db->media_mode) {
1693 case DMFE_10MHF: phy_reg |= 0x20; break;
1694 case DMFE_10MFD: phy_reg |= 0x40; break;
1695 case DMFE_100MHF: phy_reg |= 0x80; break;
1696 case DMFE_100MFD: phy_reg |= 0x100; break;
1697 }
1698 if (db->chip_id == PCI_DM9009_ID) phy_reg &= 0x61;
1699 }
1700
1701 /* Write new capability to Phyxcer Reg4 */
1702 if ( !(phy_reg & 0x01e0)) {
1703 phy_reg|=db->PHY_reg4;
1704 db->media_mode|=DMFE_AUTO;
1705 }
1706 phy_write(db->ioaddr, db->phy_addr, 4, phy_reg, db->chip_id);
1707
1708 /* Restart Auto-Negotiation */
1709 if ( db->chip_type && (db->chip_id == PCI_DM9102_ID) )
1710 phy_write(db->ioaddr, db->phy_addr, 0, 0x1800, db->chip_id);
1711 if ( !db->chip_type )
1712 phy_write(db->ioaddr, db->phy_addr, 0, 0x1200, db->chip_id);
1713 }
1714
1715
1716 /*
1717 * Process op-mode
1718 * AUTO mode : PHY controller in Auto-negotiation Mode
1719 * Force mode: PHY controller in force mode with HUB
1720 * N-way force capability with SWITCH
1721 */
1722
1723 static void dmfe_process_mode(struct dmfe_board_info *db)
1724 {
1725 u16 phy_reg;
1726
1727 /* Full Duplex Mode Check */
1728 if (db->op_mode & 0x4)
1729 db->cr6_data |= CR6_FDM; /* Set Full Duplex Bit */
1730 else
1731 db->cr6_data &= ~CR6_FDM; /* Clear Full Duplex Bit */
1732
1733 /* Transciver Selection */
1734 if (db->op_mode & 0x10) /* 1M HomePNA */
1735 db->cr6_data |= 0x40000;/* External MII select */
1736 else
1737 db->cr6_data &= ~0x40000;/* Internal 10/100 transciver */
1738
1739 update_cr6(db->cr6_data, db->ioaddr);
1740
1741 /* 10/100M phyxcer force mode need */
1742 if ( !(db->media_mode & 0x18)) {
1743 /* Forece Mode */
1744 phy_reg = phy_read(db->ioaddr, db->phy_addr, 6, db->chip_id);
1745 if ( !(phy_reg & 0x1) ) {
1746 /* parter without N-Way capability */
1747 phy_reg = 0x0;
1748 switch(db->op_mode) {
1749 case DMFE_10MHF: phy_reg = 0x0; break;
1750 case DMFE_10MFD: phy_reg = 0x100; break;
1751 case DMFE_100MHF: phy_reg = 0x2000; break;
1752 case DMFE_100MFD: phy_reg = 0x2100; break;
1753 }
1754 phy_write(db->ioaddr,
1755 db->phy_addr, 0, phy_reg, db->chip_id);
1756 if ( db->chip_type && (db->chip_id == PCI_DM9102_ID) )
1757 mdelay(20);
1758 phy_write(db->ioaddr,
1759 db->phy_addr, 0, phy_reg, db->chip_id);
1760 }
1761 }
1762 }
1763
1764
1765 /*
1766 * Write a word to Phy register
1767 */
1768
1769 static void phy_write(unsigned long iobase, u8 phy_addr, u8 offset,
1770 u16 phy_data, u32 chip_id)
1771 {
1772 u16 i;
1773 unsigned long ioaddr;
1774
1775 if (chip_id == PCI_DM9132_ID) {
1776 ioaddr = iobase + 0x80 + offset * 4;
1777 outw(phy_data, ioaddr);
1778 } else {
1779 /* DM9102/DM9102A Chip */
1780 ioaddr = iobase + DCR9;
1781
1782 /* Send 33 synchronization clock to Phy controller */
1783 for (i = 0; i < 35; i++)
1784 phy_write_1bit(ioaddr, PHY_DATA_1);
1785
1786 /* Send start command(01) to Phy */
1787 phy_write_1bit(ioaddr, PHY_DATA_0);
1788 phy_write_1bit(ioaddr, PHY_DATA_1);
1789
1790 /* Send write command(01) to Phy */
1791 phy_write_1bit(ioaddr, PHY_DATA_0);
1792 phy_write_1bit(ioaddr, PHY_DATA_1);
1793
1794 /* Send Phy address */
1795 for (i = 0x10; i > 0; i = i >> 1)
1796 phy_write_1bit(ioaddr,
1797 phy_addr & i ? PHY_DATA_1 : PHY_DATA_0);
1798
1799 /* Send register address */
1800 for (i = 0x10; i > 0; i = i >> 1)
1801 phy_write_1bit(ioaddr,
1802 offset & i ? PHY_DATA_1 : PHY_DATA_0);
1803
1804 /* written trasnition */
1805 phy_write_1bit(ioaddr, PHY_DATA_1);
1806 phy_write_1bit(ioaddr, PHY_DATA_0);
1807
1808 /* Write a word data to PHY controller */
1809 for ( i = 0x8000; i > 0; i >>= 1)
1810 phy_write_1bit(ioaddr,
1811 phy_data & i ? PHY_DATA_1 : PHY_DATA_0);
1812 }
1813 }
1814
1815
1816 /*
1817 * Read a word data from phy register
1818 */
1819
1820 static u16 phy_read(unsigned long iobase, u8 phy_addr, u8 offset, u32 chip_id)
1821 {
1822 int i;
1823 u16 phy_data;
1824 unsigned long ioaddr;
1825
1826 if (chip_id == PCI_DM9132_ID) {
1827 /* DM9132 Chip */
1828 ioaddr = iobase + 0x80 + offset * 4;
1829 phy_data = inw(ioaddr);
1830 } else {
1831 /* DM9102/DM9102A Chip */
1832 ioaddr = iobase + DCR9;
1833
1834 /* Send 33 synchronization clock to Phy controller */
1835 for (i = 0; i < 35; i++)
1836 phy_write_1bit(ioaddr, PHY_DATA_1);
1837
1838 /* Send start command(01) to Phy */
1839 phy_write_1bit(ioaddr, PHY_DATA_0);
1840 phy_write_1bit(ioaddr, PHY_DATA_1);
1841
1842 /* Send read command(10) to Phy */
1843 phy_write_1bit(ioaddr, PHY_DATA_1);
1844 phy_write_1bit(ioaddr, PHY_DATA_0);
1845
1846 /* Send Phy address */
1847 for (i = 0x10; i > 0; i = i >> 1)
1848 phy_write_1bit(ioaddr,
1849 phy_addr & i ? PHY_DATA_1 : PHY_DATA_0);
1850
1851 /* Send register address */
1852 for (i = 0x10; i > 0; i = i >> 1)
1853 phy_write_1bit(ioaddr,
1854 offset & i ? PHY_DATA_1 : PHY_DATA_0);
1855
1856 /* Skip transition state */
1857 phy_read_1bit(ioaddr);
1858
1859 /* read 16bit data */
1860 for (phy_data = 0, i = 0; i < 16; i++) {
1861 phy_data <<= 1;
1862 phy_data |= phy_read_1bit(ioaddr);
1863 }
1864 }
1865
1866 return phy_data;
1867 }
1868
1869
1870 /*
1871 * Write one bit data to Phy Controller
1872 */
1873
1874 static void phy_write_1bit(unsigned long ioaddr, u32 phy_data)
1875 {
1876 outl(phy_data, ioaddr); /* MII Clock Low */
1877 udelay(1);
1878 outl(phy_data | MDCLKH, ioaddr); /* MII Clock High */
1879 udelay(1);
1880 outl(phy_data, ioaddr); /* MII Clock Low */
1881 udelay(1);
1882 }
1883
1884
1885 /*
1886 * Read one bit phy data from PHY controller
1887 */
1888
1889 static u16 phy_read_1bit(unsigned long ioaddr)
1890 {
1891 u16 phy_data;
1892
1893 outl(0x50000, ioaddr);
1894 udelay(1);
1895 phy_data = ( inl(ioaddr) >> 19 ) & 0x1;
1896 outl(0x40000, ioaddr);
1897 udelay(1);
1898
1899 return phy_data;
1900 }
1901
1902
1903 /*
1904 * Parser SROM and media mode
1905 */
1906
1907 static void dmfe_parse_srom(struct dmfe_board_info * db)
1908 {
1909 char * srom = db->srom;
1910 int dmfe_mode, tmp_reg;
1911
1912 DMFE_DBUG(0, "dmfe_parse_srom() ", 0);
1913
1914 /* Init CR15 */
1915 db->cr15_data = CR15_DEFAULT;
1916
1917 /* Check SROM Version */
1918 if ( ( (int) srom[18] & 0xff) == SROM_V41_CODE) {
1919 /* SROM V4.01 */
1920 /* Get NIC support media mode */
1921 db->NIC_capability = le16_to_cpup((__le16 *) (srom + 34));
1922 db->PHY_reg4 = 0;
1923 for (tmp_reg = 1; tmp_reg < 0x10; tmp_reg <<= 1) {
1924 switch( db->NIC_capability & tmp_reg ) {
1925 case 0x1: db->PHY_reg4 |= 0x0020; break;
1926 case 0x2: db->PHY_reg4 |= 0x0040; break;
1927 case 0x4: db->PHY_reg4 |= 0x0080; break;
1928 case 0x8: db->PHY_reg4 |= 0x0100; break;
1929 }
1930 }
1931
1932 /* Media Mode Force or not check */
1933 dmfe_mode = (le32_to_cpup((__le32 *) (srom + 34)) &
1934 le32_to_cpup((__le32 *) (srom + 36)));
1935 switch(dmfe_mode) {
1936 case 0x4: dmfe_media_mode = DMFE_100MHF; break; /* 100MHF */
1937 case 0x2: dmfe_media_mode = DMFE_10MFD; break; /* 10MFD */
1938 case 0x8: dmfe_media_mode = DMFE_100MFD; break; /* 100MFD */
1939 case 0x100:
1940 case 0x200: dmfe_media_mode = DMFE_1M_HPNA; break;/* HomePNA */
1941 }
1942
1943 /* Special Function setting */
1944 /* VLAN function */
1945 if ( (SF_mode & 0x1) || (srom[43] & 0x80) )
1946 db->cr15_data |= 0x40;
1947
1948 /* Flow Control */
1949 if ( (SF_mode & 0x2) || (srom[40] & 0x1) )
1950 db->cr15_data |= 0x400;
1951
1952 /* TX pause packet */
1953 if ( (SF_mode & 0x4) || (srom[40] & 0xe) )
1954 db->cr15_data |= 0x9800;
1955 }
1956
1957 /* Parse HPNA parameter */
1958 db->HPNA_command = 1;
1959
1960 /* Accept remote command or not */
1961 if (HPNA_rx_cmd == 0)
1962 db->HPNA_command |= 0x8000;
1963
1964 /* Issue remote command & operation mode */
1965 if (HPNA_tx_cmd == 1)
1966 switch(HPNA_mode) { /* Issue Remote Command */
1967 case 0: db->HPNA_command |= 0x0904; break;
1968 case 1: db->HPNA_command |= 0x0a00; break;
1969 case 2: db->HPNA_command |= 0x0506; break;
1970 case 3: db->HPNA_command |= 0x0602; break;
1971 }
1972 else
1973 switch(HPNA_mode) { /* Don't Issue */
1974 case 0: db->HPNA_command |= 0x0004; break;
1975 case 1: db->HPNA_command |= 0x0000; break;
1976 case 2: db->HPNA_command |= 0x0006; break;
1977 case 3: db->HPNA_command |= 0x0002; break;
1978 }
1979
1980 /* Check DM9801 or DM9802 present or not */
1981 db->HPNA_present = 0;
1982 update_cr6(db->cr6_data|0x40000, db->ioaddr);
1983 tmp_reg = phy_read(db->ioaddr, db->phy_addr, 3, db->chip_id);
1984 if ( ( tmp_reg & 0xfff0 ) == 0xb900 ) {
1985 /* DM9801 or DM9802 present */
1986 db->HPNA_timer = 8;
1987 if ( phy_read(db->ioaddr, db->phy_addr, 31, db->chip_id) == 0x4404) {
1988 /* DM9801 HomeRun */
1989 db->HPNA_present = 1;
1990 dmfe_program_DM9801(db, tmp_reg);
1991 } else {
1992 /* DM9802 LongRun */
1993 db->HPNA_present = 2;
1994 dmfe_program_DM9802(db);
1995 }
1996 }
1997
1998 }
1999
2000
2001 /*
2002 * Init HomeRun DM9801
2003 */
2004
2005 static void dmfe_program_DM9801(struct dmfe_board_info * db, int HPNA_rev)
2006 {
2007 uint reg17, reg25;
2008
2009 if ( !HPNA_NoiseFloor ) HPNA_NoiseFloor = DM9801_NOISE_FLOOR;
2010 switch(HPNA_rev) {
2011 case 0xb900: /* DM9801 E3 */
2012 db->HPNA_command |= 0x1000;
2013 reg25 = phy_read(db->ioaddr, db->phy_addr, 24, db->chip_id);
2014 reg25 = ( (reg25 + HPNA_NoiseFloor) & 0xff) | 0xf000;
2015 reg17 = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id);
2016 break;
2017 case 0xb901: /* DM9801 E4 */
2018 reg25 = phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id);
2019 reg25 = (reg25 & 0xff00) + HPNA_NoiseFloor;
2020 reg17 = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id);
2021 reg17 = (reg17 & 0xfff0) + HPNA_NoiseFloor + 3;
2022 break;
2023 case 0xb902: /* DM9801 E5 */
2024 case 0xb903: /* DM9801 E6 */
2025 default:
2026 db->HPNA_command |= 0x1000;
2027 reg25 = phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id);
2028 reg25 = (reg25 & 0xff00) + HPNA_NoiseFloor - 5;
2029 reg17 = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id);
2030 reg17 = (reg17 & 0xfff0) + HPNA_NoiseFloor;
2031 break;
2032 }
2033 phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command, db->chip_id);
2034 phy_write(db->ioaddr, db->phy_addr, 17, reg17, db->chip_id);
2035 phy_write(db->ioaddr, db->phy_addr, 25, reg25, db->chip_id);
2036 }
2037
2038
2039 /*
2040 * Init HomeRun DM9802
2041 */
2042
2043 static void dmfe_program_DM9802(struct dmfe_board_info * db)
2044 {
2045 uint phy_reg;
2046
2047 if ( !HPNA_NoiseFloor ) HPNA_NoiseFloor = DM9802_NOISE_FLOOR;
2048 phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command, db->chip_id);
2049 phy_reg = phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id);
2050 phy_reg = ( phy_reg & 0xff00) + HPNA_NoiseFloor;
2051 phy_write(db->ioaddr, db->phy_addr, 25, phy_reg, db->chip_id);
2052 }
2053
2054
2055 /*
2056 * Check remote HPNA power and speed status. If not correct,
2057 * issue command again.
2058 */
2059
2060 static void dmfe_HPNA_remote_cmd_chk(struct dmfe_board_info * db)
2061 {
2062 uint phy_reg;
2063
2064 /* Got remote device status */
2065 phy_reg = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id) & 0x60;
2066 switch(phy_reg) {
2067 case 0x00: phy_reg = 0x0a00;break; /* LP/LS */
2068 case 0x20: phy_reg = 0x0900;break; /* LP/HS */
2069 case 0x40: phy_reg = 0x0600;break; /* HP/LS */
2070 case 0x60: phy_reg = 0x0500;break; /* HP/HS */
2071 }
2072
2073 /* Check remote device status match our setting ot not */
2074 if ( phy_reg != (db->HPNA_command & 0x0f00) ) {
2075 phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command,
2076 db->chip_id);
2077 db->HPNA_timer=8;
2078 } else
2079 db->HPNA_timer=600; /* Match, every 10 minutes, check */
2080 }
2081
2082
2083
2084 static DEFINE_PCI_DEVICE_TABLE(dmfe_pci_tbl) = {
2085 { 0x1282, 0x9132, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9132_ID },
2086 { 0x1282, 0x9102, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9102_ID },
2087 { 0x1282, 0x9100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9100_ID },
2088 { 0x1282, 0x9009, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9009_ID },
2089 { 0, }
2090 };
2091 MODULE_DEVICE_TABLE(pci, dmfe_pci_tbl);
2092
2093
2094 #ifdef CONFIG_PM
2095 static int dmfe_suspend(struct pci_dev *pci_dev, pm_message_t state)
2096 {
2097 struct net_device *dev = pci_get_drvdata(pci_dev);
2098 struct dmfe_board_info *db = netdev_priv(dev);
2099 u32 tmp;
2100
2101 /* Disable upper layer interface */
2102 netif_device_detach(dev);
2103
2104 /* Disable Tx/Rx */
2105 db->cr6_data &= ~(CR6_RXSC | CR6_TXSC);
2106 update_cr6(db->cr6_data, dev->base_addr);
2107
2108 /* Disable Interrupt */
2109 outl(0, dev->base_addr + DCR7);
2110 outl(inl (dev->base_addr + DCR5), dev->base_addr + DCR5);
2111
2112 /* Fre RX buffers */
2113 dmfe_free_rxbuffer(db);
2114
2115 /* Enable WOL */
2116 pci_read_config_dword(pci_dev, 0x40, &tmp);
2117 tmp &= ~(DMFE_WOL_LINKCHANGE|DMFE_WOL_MAGICPACKET);
2118
2119 if (db->wol_mode & WAKE_PHY)
2120 tmp |= DMFE_WOL_LINKCHANGE;
2121 if (db->wol_mode & WAKE_MAGIC)
2122 tmp |= DMFE_WOL_MAGICPACKET;
2123
2124 pci_write_config_dword(pci_dev, 0x40, tmp);
2125
2126 pci_enable_wake(pci_dev, PCI_D3hot, 1);
2127 pci_enable_wake(pci_dev, PCI_D3cold, 1);
2128
2129 /* Power down device*/
2130 pci_save_state(pci_dev);
2131 pci_set_power_state(pci_dev, pci_choose_state (pci_dev, state));
2132
2133 return 0;
2134 }
2135
2136 static int dmfe_resume(struct pci_dev *pci_dev)
2137 {
2138 struct net_device *dev = pci_get_drvdata(pci_dev);
2139 u32 tmp;
2140
2141 pci_set_power_state(pci_dev, PCI_D0);
2142 pci_restore_state(pci_dev);
2143
2144 /* Re-initialize DM910X board */
2145 dmfe_init_dm910x(dev);
2146
2147 /* Disable WOL */
2148 pci_read_config_dword(pci_dev, 0x40, &tmp);
2149
2150 tmp &= ~(DMFE_WOL_LINKCHANGE | DMFE_WOL_MAGICPACKET);
2151 pci_write_config_dword(pci_dev, 0x40, tmp);
2152
2153 pci_enable_wake(pci_dev, PCI_D3hot, 0);
2154 pci_enable_wake(pci_dev, PCI_D3cold, 0);
2155
2156 /* Restart upper layer interface */
2157 netif_device_attach(dev);
2158
2159 return 0;
2160 }
2161 #else
2162 #define dmfe_suspend NULL
2163 #define dmfe_resume NULL
2164 #endif
2165
2166 static struct pci_driver dmfe_driver = {
2167 .name = "dmfe",
2168 .id_table = dmfe_pci_tbl,
2169 .probe = dmfe_init_one,
2170 .remove = __devexit_p(dmfe_remove_one),
2171 .suspend = dmfe_suspend,
2172 .resume = dmfe_resume
2173 };
2174
2175 MODULE_AUTHOR("Sten Wang, sten_wang@davicom.com.tw");
2176 MODULE_DESCRIPTION("Davicom DM910X fast ethernet driver");
2177 MODULE_LICENSE("GPL");
2178 MODULE_VERSION(DRV_VERSION);
2179
2180 module_param(debug, int, 0);
2181 module_param(mode, byte, 0);
2182 module_param(cr6set, int, 0);
2183 module_param(chkmode, byte, 0);
2184 module_param(HPNA_mode, byte, 0);
2185 module_param(HPNA_rx_cmd, byte, 0);
2186 module_param(HPNA_tx_cmd, byte, 0);
2187 module_param(HPNA_NoiseFloor, byte, 0);
2188 module_param(SF_mode, byte, 0);
2189 MODULE_PARM_DESC(debug, "Davicom DM9xxx enable debugging (0-1)");
2190 MODULE_PARM_DESC(mode, "Davicom DM9xxx: "
2191 "Bit 0: 10/100Mbps, bit 2: duplex, bit 8: HomePNA");
2192
2193 MODULE_PARM_DESC(SF_mode, "Davicom DM9xxx special function "
2194 "(bit 0: VLAN, bit 1 Flow Control, bit 2: TX pause packet)");
2195
2196 /* Description:
2197 * when user used insmod to add module, system invoked init_module()
2198 * to initialize and register.
2199 */
2200
2201 static int __init dmfe_init_module(void)
2202 {
2203 int rc;
2204
2205 pr_info("%s\n", version);
2206 printed_version = 1;
2207
2208 DMFE_DBUG(0, "init_module() ", debug);
2209
2210 if (debug)
2211 dmfe_debug = debug; /* set debug flag */
2212 if (cr6set)
2213 dmfe_cr6_user_set = cr6set;
2214
2215 switch(mode) {
2216 case DMFE_10MHF:
2217 case DMFE_100MHF:
2218 case DMFE_10MFD:
2219 case DMFE_100MFD:
2220 case DMFE_1M_HPNA:
2221 dmfe_media_mode = mode;
2222 break;
2223 default:dmfe_media_mode = DMFE_AUTO;
2224 break;
2225 }
2226
2227 if (HPNA_mode > 4)
2228 HPNA_mode = 0; /* Default: LP/HS */
2229 if (HPNA_rx_cmd > 1)
2230 HPNA_rx_cmd = 0; /* Default: Ignored remote cmd */
2231 if (HPNA_tx_cmd > 1)
2232 HPNA_tx_cmd = 0; /* Default: Don't issue remote cmd */
2233 if (HPNA_NoiseFloor > 15)
2234 HPNA_NoiseFloor = 0;
2235
2236 rc = pci_register_driver(&dmfe_driver);
2237 if (rc < 0)
2238 return rc;
2239
2240 return 0;
2241 }
2242
2243
2244 /*
2245 * Description:
2246 * when user used rmmod to delete module, system invoked clean_module()
2247 * to un-register all registered services.
2248 */
2249
2250 static void __exit dmfe_cleanup_module(void)
2251 {
2252 DMFE_DBUG(0, "dmfe_clean_module() ", debug);
2253 pci_unregister_driver(&dmfe_driver);
2254 }
2255
2256 module_init(dmfe_init_module);
2257 module_exit(dmfe_cleanup_module);