drivers/staging/brcm80211/include/aidmp.h

   1 /*
   2  * Copyright (c) 2010 Broadcom Corporation
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  11  * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
  13  * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
  14  * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #ifndef _AIDMP_H
  18 #define _AIDMP_H
  19
  20 /* Manufacturer Ids */
  21 #define MFGID_ARM               0x43b
  22 #define MFGID_BRCM              0x4bf
  23 #define MFGID_MIPS              0x4a7
  24
  25 /* Component Classes */
  26 #define CC_SIM                  0
  27 #define CC_EROM                 1
  28 #define CC_CORESIGHT            9
  29 #define CC_VERIF                0xb
  30 #define CC_OPTIMO               0xd
  31 #define CC_GEN                  0xe
  32 #define CC_PRIMECELL            0xf
  33
  34 /* Enumeration ROM registers */
  35 #define ER_EROMENTRY            0x000
  36 #define ER_REMAPCONTROL         0xe00
  37 #define ER_REMAPSELECT          0xe04
  38 #define ER_MASTERSELECT         0xe10
  39 #define ER_ITCR                 0xf00
  40 #define ER_ITIP                 0xf04
  41
  42 /* Erom entries */
  43 #define ER_TAG                  0xe
  44 #define ER_TAG1                 0x6
  45 #define ER_VALID                1
  46 #define ER_CI                   0
  47 #define ER_MP                   2
  48 #define ER_ADD                  4
  49 #define ER_END                  0xe
  50 #define ER_BAD                  0xffffffff
  51
  52 /* EROM CompIdentA */
  53 #define CIA_MFG_MASK            0xfff00000
  54 #define CIA_MFG_SHIFT           20
  55 #define CIA_CID_MASK            0x000fff00
  56 #define CIA_CID_SHIFT           8
  57 #define CIA_CCL_MASK            0x000000f0
  58 #define CIA_CCL_SHIFT           4
  59
  60 /* EROM CompIdentB */
  61 #define CIB_REV_MASK            0xff000000
  62 #define CIB_REV_SHIFT           24
  63 #define CIB_NSW_MASK            0x00f80000
  64 #define CIB_NSW_SHIFT           19
  65 #define CIB_NMW_MASK            0x0007c000
  66 #define CIB_NMW_SHIFT           14
  67 #define CIB_NSP_MASK            0x00003e00
  68 #define CIB_NSP_SHIFT           9
  69 #define CIB_NMP_MASK            0x000001f0
  70 #define CIB_NMP_SHIFT           4
  71
  72 /* EROM MasterPortDesc */
  73 #define MPD_MUI_MASK            0x0000ff00
  74 #define MPD_MUI_SHIFT           8
  75 #define MPD_MP_MASK             0x000000f0
  76 #define MPD_MP_SHIFT            4
  77
  78 /* EROM AddrDesc */
  79 #define AD_ADDR_MASK            0xfffff000
  80 #define AD_SP_MASK              0x00000f00
  81 #define AD_SP_SHIFT             8
  82 #define AD_ST_MASK              0x000000c0
  83 #define AD_ST_SHIFT             6
  84 #define AD_ST_SLAVE             0x00000000
  85 #define AD_ST_BRIDGE            0x00000040
  86 #define AD_ST_SWRAP             0x00000080
  87 #define AD_ST_MWRAP             0x000000c0
  88 #define AD_SZ_MASK              0x00000030
  89 #define AD_SZ_SHIFT             4
  90 #define AD_SZ_4K                0x00000000
  91 #define AD_SZ_8K                0x00000010
  92 #define AD_SZ_16K               0x00000020
  93 #define AD_SZ_SZD               0x00000030
  94 #define AD_AG32                 0x00000008
  95 #define AD_ADDR_ALIGN           0x00000fff
  96 #define AD_SZ_BASE              0x00001000      /* 4KB */
  97
  98 /* EROM SizeDesc */
  99 #define SD_SZ_MASK              0xfffff000
 100 #define SD_SG32                 0x00000008
 101 #define SD_SZ_ALIGN             0x00000fff
 102
 103 #ifndef _LANGUAGE_ASSEMBLY
 104
 105 typedef volatile struct _aidmp {
 106         u32 oobselina30;        /* 0x000 */
 107         u32 oobselina74;        /* 0x004 */
 108         u32 PAD[6];
 109         u32 oobselinb30;        /* 0x020 */
 110         u32 oobselinb74;        /* 0x024 */
 111         u32 PAD[6];
 112         u32 oobselinc30;        /* 0x040 */
 113         u32 oobselinc74;        /* 0x044 */
 114         u32 PAD[6];
 115         u32 oobselind30;        /* 0x060 */
 116         u32 oobselind74;        /* 0x064 */
 117         u32 PAD[38];
 118         u32 oobselouta30;       /* 0x100 */
 119         u32 oobselouta74;       /* 0x104 */
 120         u32 PAD[6];
 121         u32 oobseloutb30;       /* 0x120 */
 122         u32 oobseloutb74;       /* 0x124 */
 123         u32 PAD[6];
 124         u32 oobseloutc30;       /* 0x140 */
 125         u32 oobseloutc74;       /* 0x144 */
 126         u32 PAD[6];
 127         u32 oobseloutd30;       /* 0x160 */
 128         u32 oobseloutd74;       /* 0x164 */
 129         u32 PAD[38];
 130         u32 oobsynca;   /* 0x200 */
 131         u32 oobseloutaen;       /* 0x204 */
 132         u32 PAD[6];
 133         u32 oobsyncb;   /* 0x220 */
 134         u32 oobseloutben;       /* 0x224 */
 135         u32 PAD[6];
 136         u32 oobsyncc;   /* 0x240 */
 137         u32 oobseloutcen;       /* 0x244 */
 138         u32 PAD[6];
 139         u32 oobsyncd;   /* 0x260 */
 140         u32 oobseloutden;       /* 0x264 */
 141         u32 PAD[38];
 142         u32 oobaextwidth;       /* 0x300 */
 143         u32 oobainwidth;        /* 0x304 */
 144         u32 oobaoutwidth;       /* 0x308 */
 145         u32 PAD[5];
 146         u32 oobbextwidth;       /* 0x320 */
 147         u32 oobbinwidth;        /* 0x324 */
 148         u32 oobboutwidth;       /* 0x328 */
 149         u32 PAD[5];
 150         u32 oobcextwidth;       /* 0x340 */
 151         u32 oobcinwidth;        /* 0x344 */
 152         u32 oobcoutwidth;       /* 0x348 */
 153         u32 PAD[5];
 154         u32 oobdextwidth;       /* 0x360 */
 155         u32 oobdinwidth;        /* 0x364 */
 156         u32 oobdoutwidth;       /* 0x368 */
 157         u32 PAD[37];
 158         u32 ioctrlset;  /* 0x400 */
 159         u32 ioctrlclear;        /* 0x404 */
 160         u32 ioctrl;             /* 0x408 */
 161         u32 PAD[61];
 162         u32 iostatus;   /* 0x500 */
 163         u32 PAD[127];
 164         u32 ioctrlwidth;        /* 0x700 */
 165         u32 iostatuswidth;      /* 0x704 */
 166         u32 PAD[62];
 167         u32 resetctrl;  /* 0x800 */
 168         u32 resetstatus;        /* 0x804 */
 169         u32 resetreadid;        /* 0x808 */
 170         u32 resetwriteid;       /* 0x80c */
 171         u32 PAD[60];
 172         u32 errlogctrl; /* 0x900 */
 173         u32 errlogdone; /* 0x904 */
 174         u32 errlogstatus;       /* 0x908 */
 175         u32 errlogaddrlo;       /* 0x90c */
 176         u32 errlogaddrhi;       /* 0x910 */
 177         u32 errlogid;   /* 0x914 */
 178         u32 errloguser; /* 0x918 */
 179         u32 errlogflags;        /* 0x91c */
 180         u32 PAD[56];
 181         u32 intstatus;  /* 0xa00 */
 182         u32 PAD[127];
 183         u32 config;             /* 0xe00 */
 184         u32 PAD[63];
 185         u32 itcr;               /* 0xf00 */
 186         u32 PAD[3];
 187         u32 itipooba;   /* 0xf10 */
 188         u32 itipoobb;   /* 0xf14 */
 189         u32 itipoobc;   /* 0xf18 */
 190         u32 itipoobd;   /* 0xf1c */
 191         u32 PAD[4];
 192         u32 itipoobaout;        /* 0xf30 */
 193         u32 itipoobbout;        /* 0xf34 */
 194         u32 itipoobcout;        /* 0xf38 */
 195         u32 itipoobdout;        /* 0xf3c */
 196         u32 PAD[4];
 197         u32 itopooba;   /* 0xf50 */
 198         u32 itopoobb;   /* 0xf54 */
 199         u32 itopoobc;   /* 0xf58 */
 200         u32 itopoobd;   /* 0xf5c */
 201         u32 PAD[4];
 202         u32 itopoobain; /* 0xf70 */
 203         u32 itopoobbin; /* 0xf74 */
 204         u32 itopoobcin; /* 0xf78 */
 205         u32 itopoobdin; /* 0xf7c */
 206         u32 PAD[4];
 207         u32 itopreset;  /* 0xf90 */
 208         u32 PAD[15];
 209         u32 peripherialid4;     /* 0xfd0 */
 210         u32 peripherialid5;     /* 0xfd4 */
 211         u32 peripherialid6;     /* 0xfd8 */
 212         u32 peripherialid7;     /* 0xfdc */
 213         u32 peripherialid0;     /* 0xfe0 */
 214         u32 peripherialid1;     /* 0xfe4 */
 215         u32 peripherialid2;     /* 0xfe8 */
 216         u32 peripherialid3;     /* 0xfec */
 217         u32 componentid0;       /* 0xff0 */
 218         u32 componentid1;       /* 0xff4 */
 219         u32 componentid2;       /* 0xff8 */
 220         u32 componentid3;       /* 0xffc */
 221 } aidmp_t;
 222
 223 #endif                          /* _LANGUAGE_ASSEMBLY */
 224
 225 /* Out-of-band Router registers */
 226 #define OOB_BUSCONFIG           0x020
 227 #define OOB_STATUSA             0x100
 228 #define OOB_STATUSB             0x104
 229 #define OOB_STATUSC             0x108
 230 #define OOB_STATUSD             0x10c
 231 #define OOB_ENABLEA0            0x200
 232 #define OOB_ENABLEA1            0x204
 233 #define OOB_ENABLEA2            0x208
 234 #define OOB_ENABLEA3            0x20c
 235 #define OOB_ENABLEB0            0x280
 236 #define OOB_ENABLEB1            0x284
 237 #define OOB_ENABLEB2            0x288
 238 #define OOB_ENABLEB3            0x28c
 239 #define OOB_ENABLEC0            0x300
 240 #define OOB_ENABLEC1            0x304
 241 #define OOB_ENABLEC2            0x308
 242 #define OOB_ENABLEC3            0x30c
 243 #define OOB_ENABLED0            0x380
 244 #define OOB_ENABLED1            0x384
 245 #define OOB_ENABLED2            0x388
 246 #define OOB_ENABLED3            0x38c
 247 #define OOB_ITCR                0xf00
 248 #define OOB_ITIPOOBA            0xf10
 249 #define OOB_ITIPOOBB            0xf14
 250 #define OOB_ITIPOOBC            0xf18
 251 #define OOB_ITIPOOBD            0xf1c
 252 #define OOB_ITOPOOBA            0xf30
 253 #define OOB_ITOPOOBB            0xf34
 254 #define OOB_ITOPOOBC            0xf38
 255 #define OOB_ITOPOOBD            0xf3c
 256
 257 /* DMP wrapper registers */
 258 #define AI_OOBSELINA30          0x000
 259 #define AI_OOBSELINA74          0x004
 260 #define AI_OOBSELINB30          0x020
 261 #define AI_OOBSELINB74          0x024
 262 #define AI_OOBSELINC30          0x040
 263 #define AI_OOBSELINC74          0x044
 264 #define AI_OOBSELIND30          0x060
 265 #define AI_OOBSELIND74          0x064
 266 #define AI_OOBSELOUTA30         0x100
 267 #define AI_OOBSELOUTA74         0x104
 268 #define AI_OOBSELOUTB30         0x120
 269 #define AI_OOBSELOUTB74         0x124
 270 #define AI_OOBSELOUTC30         0x140
 271 #define AI_OOBSELOUTC74         0x144
 272 #define AI_OOBSELOUTD30         0x160
 273 #define AI_OOBSELOUTD74         0x164
 274 #define AI_OOBSYNCA             0x200
 275 #define AI_OOBSELOUTAEN         0x204
 276 #define AI_OOBSYNCB             0x220
 277 #define AI_OOBSELOUTBEN         0x224
 278 #define AI_OOBSYNCC             0x240
 279 #define AI_OOBSELOUTCEN         0x244
 280 #define AI_OOBSYNCD             0x260
 281 #define AI_OOBSELOUTDEN         0x264
 282 #define AI_OOBAEXTWIDTH         0x300
 283 #define AI_OOBAINWIDTH          0x304
 284 #define AI_OOBAOUTWIDTH         0x308
 285 #define AI_OOBBEXTWIDTH         0x320
 286 #define AI_OOBBINWIDTH          0x324
 287 #define AI_OOBBOUTWIDTH         0x328
 288 #define AI_OOBCEXTWIDTH         0x340
 289 #define AI_OOBCINWIDTH          0x344
 290 #define AI_OOBCOUTWIDTH         0x348
 291 #define AI_OOBDEXTWIDTH         0x360
 292 #define AI_OOBDINWIDTH          0x364
 293 #define AI_OOBDOUTWIDTH         0x368
 294
 295 #if     defined(__BIG_ENDIAN) && defined(BCMHND74K)
 296 /* Selective swapped defines for those registers we need in
 297  * big-endian code.
 298  */
 299 #define AI_IOCTRLSET            0x404
 300 #define AI_IOCTRLCLEAR          0x400
 301 #define AI_IOCTRL               0x40c
 302 #define AI_IOSTATUS             0x504
 303 #define AI_RESETCTRL            0x804
 304 #define AI_RESETSTATUS          0x800
 305
 306 #else                           /* !__BIG_ENDIAN || !BCMHND74K */
 307
 308 #define AI_IOCTRLSET            0x400
 309 #define AI_IOCTRLCLEAR          0x404
 310 #define AI_IOCTRL               0x408
 311 #define AI_IOSTATUS             0x500
 312 #define AI_RESETCTRL            0x800
 313 #define AI_RESETSTATUS          0x804
 314
 315 #endif                          /* __BIG_ENDIAN && BCMHND74K */
 316
 317 #define AI_IOCTRLWIDTH          0x700
 318 #define AI_IOSTATUSWIDTH        0x704
 319
 320 #define AI_RESETREADID          0x808
 321 #define AI_RESETWRITEID         0x80c
 322 #define AI_ERRLOGCTRL           0xa00
 323 #define AI_ERRLOGDONE           0xa04
 324 #define AI_ERRLOGSTATUS         0xa08
 325 #define AI_ERRLOGADDRLO         0xa0c
 326 #define AI_ERRLOGADDRHI         0xa10
 327 #define AI_ERRLOGID             0xa14
 328 #define AI_ERRLOGUSER           0xa18
 329 #define AI_ERRLOGFLAGS          0xa1c
 330 #define AI_INTSTATUS            0xa00
 331 #define AI_CONFIG               0xe00
 332 #define AI_ITCR                 0xf00
 333 #define AI_ITIPOOBA             0xf10
 334 #define AI_ITIPOOBB             0xf14
 335 #define AI_ITIPOOBC             0xf18
 336 #define AI_ITIPOOBD             0xf1c
 337 #define AI_ITIPOOBAOUT          0xf30
 338 #define AI_ITIPOOBBOUT          0xf34
 339 #define AI_ITIPOOBCOUT          0xf38
 340 #define AI_ITIPOOBDOUT          0xf3c
 341 #define AI_ITOPOOBA             0xf50
 342 #define AI_ITOPOOBB             0xf54
 343 #define AI_ITOPOOBC             0xf58
 344 #define AI_ITOPOOBD             0xf5c
 345 #define AI_ITOPOOBAIN           0xf70
 346 #define AI_ITOPOOBBIN           0xf74
 347 #define AI_ITOPOOBCIN           0xf78
 348 #define AI_ITOPOOBDIN           0xf7c
 349 #define AI_ITOPRESET            0xf90
 350 #define AI_PERIPHERIALID4       0xfd0
 351 #define AI_PERIPHERIALID5       0xfd4
 352 #define AI_PERIPHERIALID6       0xfd8
 353 #define AI_PERIPHERIALID7       0xfdc
 354 #define AI_PERIPHERIALID0       0xfe0
 355 #define AI_PERIPHERIALID1       0xfe4
 356 #define AI_PERIPHERIALID2       0xfe8
 357 #define AI_PERIPHERIALID3       0xfec
 358 #define AI_COMPONENTID0         0xff0
 359 #define AI_COMPONENTID1         0xff4
 360 #define AI_COMPONENTID2         0xff8
 361 #define AI_COMPONENTID3         0xffc
 362
 363 /* resetctrl */
 364 #define AIRC_RESET              1
 365
 366 /* config */
 367 #define AICFG_OOB               0x00000020
 368 #define AICFG_IOS               0x00000010
 369 #define AICFG_IOC               0x00000008
 370 #define AICFG_TO                0x00000004
 371 #define AICFG_ERRL              0x00000002
 372 #define AICFG_RST               0x00000001
 373
 374 #endif                          /* _AIDMP_H */