drivers/staging/brcm80211/include/bcmdevs.h

   1 /*
   2  * Copyright (c) 2010 Broadcom Corporation
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  11  * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
  13  * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
  14  * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #ifndef _BCMDEVS_H
  18 #define _BCMDEVS_H
  19
  20 #define BCM4325_D11DUAL_ID      0x431b
  21 #define BCM4325_D11G_ID         0x431c
  22 #define BCM4325_D11A_ID         0x431d
  23
  24 #define BCM4329_D11N2G_ID       0x432f  /* 4329 802.11n 2.4G device */
  25 #define BCM4329_D11N5G_ID       0x4330  /* 4329 802.11n 5G device */
  26 #define BCM4329_D11NDUAL_ID     0x432e
  27
  28 #define BCM4319_D11N_ID         0x4337  /* 4319 802.11n dualband device */
  29 #define BCM4319_D11N2G_ID       0x4338  /* 4319 802.11n 2.4G device */
  30 #define BCM4319_D11N5G_ID       0x4339  /* 4319 802.11n 5G device */
  31
  32 #define BCM43224_D11N_ID        0x4353  /* 43224 802.11n dualband device */
  33
  34 #define BCM43225_D11N2G_ID      0x4357  /* 43225 802.11n 2.4GHz device */
  35
  36 #define BCM43236_D11N_ID        0x4346  /* 43236 802.11n dualband device */
  37 #define BCM43236_D11N2G_ID      0x4347  /* 43236 802.11n 2.4GHz device */
  38
  39 #define BCM4313_D11N2G_ID       0x4727  /* 4313 802.11n 2.4G device */
  40
  41 /* Chip IDs */
  42 #define BCM4313_CHIP_ID         0x4313  /* 4313 chip id */
  43 #define BCM4319_CHIP_ID         0x4319  /* 4319 chip id */
  44
  45 #define BCM43224_CHIP_ID        43224   /* 43224 chipcommon chipid */
  46 #define BCM43225_CHIP_ID        43225   /* 43225 chipcommon chipid */
  47 #define BCM43421_CHIP_ID        43421   /* 43421 chipcommon chipid */
  48 #define BCM43235_CHIP_ID        43235   /* 43235 chipcommon chipid */
  49 #define BCM43236_CHIP_ID        43236   /* 43236 chipcommon chipid */
  50 #define BCM43238_CHIP_ID        43238   /* 43238 chipcommon chipid */
  51 #define BCM4329_CHIP_ID         0x4329  /* 4329 chipcommon chipid */
  52 #define BCM4325_CHIP_ID         0x4325  /* 4325 chipcommon chipid */
  53 #define BCM4331_CHIP_ID         0x4331  /* 4331 chipcommon chipid */
  54 #define BCM4336_CHIP_ID         0x4336  /* 4336 chipcommon chipid */
  55 #define BCM4330_CHIP_ID         0x4330  /* 4330 chipcommon chipid */
  56 #define BCM6362_CHIP_ID         0x6362  /* 6362 chipcommon chipid */
  57
  58 /* these are router chips */
  59 #define BCM4716_CHIP_ID         0x4716  /* 4716 chipcommon chipid */
  60 #define BCM47162_CHIP_ID        47162   /* 47162 chipcommon chipid */
  61 #define BCM4748_CHIP_ID         0x4748  /* 4716 chipcommon chipid (OTP, RBBU) */
  62 #define BCM5356_CHIP_ID         0x5356  /* 5356 chipcommon chipid */
  63 #define BCM5357_CHIP_ID         0x5357  /* 5357 chipcommon chipid */
  64
  65 /* Package IDs */
  66 #define BCM4329_289PIN_PKG_ID   0       /* 4329 289-pin package id */
  67 #define BCM4329_182PIN_PKG_ID   1       /* 4329N 182-pin package id */
  68 #define BCM4717_PKG_ID          9       /* 4717 package id */
  69 #define BCM4718_PKG_ID          10      /* 4718 package id */
  70 #define HDLSIM_PKG_ID           14      /* HDL simulator package id */
  71 #define HWSIM_PKG_ID            15      /* Hardware simulator package id */
  72 #define BCM43224_FAB_SMIC       0xa     /* the chip is manufactured by SMIC */
  73
  74 /* boardflags */
  75 #define BFL_PACTRL              0x00000002      /* Board has gpio 9 controlling the PA */
  76 #define BFL_NOPLLDOWN           0x00000020      /* Not ok to power down the chip pll and oscillator */
  77 #define BFL_FEM                 0x00000800      /* Board supports the Front End Module */
  78 #define BFL_EXTLNA              0x00001000      /* Board has an external LNA in 2.4GHz band */
  79 #define BFL_NOPA                0x00010000      /* Board has no PA */
  80 #define BFL_BUCKBOOST           0x00200000      /* Power topology uses BUCKBOOST */
  81 #define BFL_FEM_BT              0x00400000      /* Board has FEM and switch to share antenna w/ BT */
  82 #define BFL_NOCBUCK             0x00800000      /* Power topology doesn't use CBUCK */
  83 #define BFL_PALDO               0x02000000      /* Power topology uses PALDO */
  84 #define BFL_EXTLNA_5GHz         0x10000000      /* Board has an external LNA in 5GHz band */
  85
  86 /* boardflags2 */
  87 #define BFL2_RXBB_INT_REG_DIS   0x00000001      /* Board has an external rxbb regulator */
  88 #define BFL2_APLL_WAR           0x00000002      /* Flag to implement alternative A-band PLL settings */
  89 #define BFL2_TXPWRCTRL_EN       0x00000004      /* Board permits enabling TX Power Control */
  90 #define BFL2_2X4_DIV            0x00000008      /* Board supports the 2X4 diversity switch */
  91 #define BFL2_5G_PWRGAIN         0x00000010      /* Board supports 5G band power gain */
  92 #define BFL2_PCIEWAR_OVR        0x00000020      /* Board overrides ASPM and Clkreq settings */
  93 #define BFL2_LEGACY             0x00000080
  94 #define BFL2_SKWRKFEM_BRD       0x00000100      /* 4321mcm93 board uses Skyworks FEM */
  95 #define BFL2_SPUR_WAR           0x00000200      /* Board has a WAR for clock-harmonic spurs */
  96 #define BFL2_GPLL_WAR           0x00000400      /* Flag to narrow G-band PLL loop b/w */
  97 #define BFL2_SINGLEANT_CCK      0x00001000      /* Tx CCK pkts on Ant 0 only */
  98 #define BFL2_2G_SPUR_WAR        0x00002000      /* WAR to reduce and avoid clock-harmonic spurs in 2G */
  99 #define BFL2_GPLL_WAR2          0x00010000      /* Flag to widen G-band PLL loop b/w */
 100 #define BFL2_IPALVLSHIFT_3P3    0x00020000
 101 #define BFL2_INTERNDET_TXIQCAL  0x00040000      /* Use internal envelope detector for TX IQCAL */
 102 #define BFL2_XTALBUFOUTEN       0x00080000      /* Keep the buffered Xtal output from radio "ON"
 103                                                  * Most drivers will turn it off without this flag
 104                                                  * to save power.
 105                                                  */
 106
 107 /* board specific GPIO assignment, gpio 0-3 are also customer-configurable led */
 108 #define BOARD_GPIO_PACTRL       0x200   /* bit 9 controls the PA on new 4306 boards */
 109 #define BOARD_GPIO_12           0x1000  /* gpio 12 */
 110 #define BOARD_GPIO_13           0x2000  /* gpio 13 */
 111
 112 #define PCI_CFG_GPIO_SCS        0x10    /* PCI config space bit 4 for 4306c0 slow clock source */
 113 #define PCI_CFG_GPIO_XTAL       0x40    /* PCI config space GPIO 14 for Xtal power-up */
 114 #define PCI_CFG_GPIO_PLL        0x80    /* PCI config space GPIO 15 for PLL power-down */
 115
 116 /* power control defines */
 117 #define PLL_DELAY               150     /* us pll on delay */
 118 #define FREF_DELAY              200     /* us fref change delay */
 119 #define XTAL_ON_DELAY           1000    /* us crystal power-on delay */
 120
 121 /* Reference board types */
 122 #define SPI_BOARD               0x0402
 123
 124 #endif                          /* _BCMDEVS_H */