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spi-topcliff-pch: Modify pci-bus number dynamically to get DMA device info
[zen-stable.git] / drivers / gpio / gpio-omap.c
bloba6c10e849e61d21060f024e603eedb38ccea1a70
1 /*
2 * Support functions for OMAP GPIO
3 *
4 * Copyright (C) 2003-2005 Nokia Corporation
5 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
6 *
7 * Copyright (C) 2009 Texas Instruments
8 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/interrupt.h>
18 #include <linux/syscore_ops.h>
19 #include <linux/err.h>
20 #include <linux/clk.h>
21 #include <linux/io.h>
22 #include <linux/slab.h>
23 #include <linux/pm_runtime.h>
24
25 #include <mach/hardware.h>
26 #include <asm/irq.h>
27 #include <mach/irqs.h>
28 #include <asm/gpio.h>
29 #include <asm/mach/irq.h>
30
31 struct gpio_bank {
32 unsigned long pbase;
33 void __iomem *base;
34 u16 irq;
35 u16 virtual_irq_start;
36 int method;
37 u32 suspend_wakeup;
38 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
39 u32 saved_wakeup;
40 #endif
41 u32 non_wakeup_gpios;
42 u32 enabled_non_wakeup_gpios;
43
44 u32 saved_datain;
45 u32 saved_fallingdetect;
46 u32 saved_risingdetect;
47 u32 level_mask;
48 u32 toggle_mask;
49 spinlock_t lock;
50 struct gpio_chip chip;
51 struct clk *dbck;
52 u32 mod_usage;
53 u32 dbck_enable_mask;
54 struct device *dev;
55 bool dbck_flag;
56 int stride;
57 u32 width;
58
59 void (*set_dataout)(struct gpio_bank *bank, int gpio, int enable);
60
61 struct omap_gpio_reg_offs *regs;
62 };
63
64 #ifdef CONFIG_ARCH_OMAP3
65 struct omap3_gpio_regs {
66 u32 irqenable1;
67 u32 irqenable2;
68 u32 wake_en;
69 u32 ctrl;
70 u32 oe;
71 u32 leveldetect0;
72 u32 leveldetect1;
73 u32 risingdetect;
74 u32 fallingdetect;
75 u32 dataout;
76 };
77
78 static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS];
79 #endif
80
81 /*
82 * TODO: Cleanup gpio_bank usage as it is having information
83 * related to all instances of the device
84 */
85 static struct gpio_bank *gpio_bank;
86
87 /* TODO: Analyze removing gpio_bank_count usage from driver code */
88 int gpio_bank_count;
89
90 #define GPIO_INDEX(bank, gpio) (gpio % bank->width)
91 #define GPIO_BIT(bank, gpio) (1 << GPIO_INDEX(bank, gpio))
92
93 static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
94 {
95 void __iomem *reg = bank->base;
96 u32 l;
97
98 reg += bank->regs->direction;
99 l = __raw_readl(reg);
100 if (is_input)
101 l |= 1 << gpio;
102 else
103 l &= ~(1 << gpio);
104 __raw_writel(l, reg);
105 }
106
107
108 /* set data out value using dedicate set/clear register */
109 static void _set_gpio_dataout_reg(struct gpio_bank *bank, int gpio, int enable)
110 {
111 void __iomem *reg = bank->base;
112 u32 l = GPIO_BIT(bank, gpio);
113
114 if (enable)
115 reg += bank->regs->set_dataout;
116 else
117 reg += bank->regs->clr_dataout;
118
119 __raw_writel(l, reg);
120 }
121
122 /* set data out value using mask register */
123 static void _set_gpio_dataout_mask(struct gpio_bank *bank, int gpio, int enable)
124 {
125 void __iomem *reg = bank->base + bank->regs->dataout;
126 u32 gpio_bit = GPIO_BIT(bank, gpio);
127 u32 l;
128
129 l = __raw_readl(reg);
130 if (enable)
131 l |= gpio_bit;
132 else
133 l &= ~gpio_bit;
134 __raw_writel(l, reg);
135 }
136
137 static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
138 {
139 void __iomem *reg = bank->base + bank->regs->datain;
140
141 return (__raw_readl(reg) & GPIO_BIT(bank, gpio)) != 0;
142 }
143
144 static int _get_gpio_dataout(struct gpio_bank *bank, int gpio)
145 {
146 void __iomem *reg = bank->base + bank->regs->dataout;
147
148 return (__raw_readl(reg) & GPIO_BIT(bank, gpio)) != 0;
149 }
150
151 static inline void _gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set)
152 {
153 int l = __raw_readl(base + reg);
154
155 if (set)
156 l |= mask;
157 else
158 l &= ~mask;
159
160 __raw_writel(l, base + reg);
161 }
162
163 /**
164 * _set_gpio_debounce - low level gpio debounce time
165 * @bank: the gpio bank we're acting upon
166 * @gpio: the gpio number on this @gpio
167 * @debounce: debounce time to use
168 *
169 * OMAP's debounce time is in 31us steps so we need
170 * to convert and round up to the closest unit.
171 */
172 static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
173 unsigned debounce)
174 {
175 void __iomem *reg;
176 u32 val;
177 u32 l;
178
179 if (!bank->dbck_flag)
180 return;
181
182 if (debounce < 32)
183 debounce = 0x01;
184 else if (debounce > 7936)
185 debounce = 0xff;
186 else
187 debounce = (debounce / 0x1f) - 1;
188
189 l = GPIO_BIT(bank, gpio);
190
191 reg = bank->base + bank->regs->debounce;
192 __raw_writel(debounce, reg);
193
194 reg = bank->base + bank->regs->debounce_en;
195 val = __raw_readl(reg);
196
197 if (debounce) {
198 val |= l;
199 clk_enable(bank->dbck);
200 } else {
201 val &= ~l;
202 clk_disable(bank->dbck);
203 }
204 bank->dbck_enable_mask = val;
205
206 __raw_writel(val, reg);
207 }
208
209 #ifdef CONFIG_ARCH_OMAP2PLUS
210 static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
211 int trigger)
212 {
213 void __iomem *base = bank->base;
214 u32 gpio_bit = 1 << gpio;
215
216 if (cpu_is_omap44xx()) {
217 _gpio_rmw(base, OMAP4_GPIO_LEVELDETECT0, gpio_bit,
218 trigger & IRQ_TYPE_LEVEL_LOW);
219 _gpio_rmw(base, OMAP4_GPIO_LEVELDETECT1, gpio_bit,
220 trigger & IRQ_TYPE_LEVEL_HIGH);
221 _gpio_rmw(base, OMAP4_GPIO_RISINGDETECT, gpio_bit,
222 trigger & IRQ_TYPE_EDGE_RISING);
223 _gpio_rmw(base, OMAP4_GPIO_FALLINGDETECT, gpio_bit,
224 trigger & IRQ_TYPE_EDGE_FALLING);
225 } else {
226 _gpio_rmw(base, OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
227 trigger & IRQ_TYPE_LEVEL_LOW);
228 _gpio_rmw(base, OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
229 trigger & IRQ_TYPE_LEVEL_HIGH);
230 _gpio_rmw(base, OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
231 trigger & IRQ_TYPE_EDGE_RISING);
232 _gpio_rmw(base, OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
233 trigger & IRQ_TYPE_EDGE_FALLING);
234 }
235 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
236 if (cpu_is_omap44xx()) {
237 _gpio_rmw(base, OMAP4_GPIO_IRQWAKEN0, gpio_bit,
238 trigger != 0);
239 } else {
240 /*
241 * GPIO wakeup request can only be generated on edge
242 * transitions
243 */
244 if (trigger & IRQ_TYPE_EDGE_BOTH)
245 __raw_writel(1 << gpio, bank->base
246 + OMAP24XX_GPIO_SETWKUENA);
247 else
248 __raw_writel(1 << gpio, bank->base
249 + OMAP24XX_GPIO_CLEARWKUENA);
250 }
251 }
252 /* This part needs to be executed always for OMAP{34xx, 44xx} */
253 if (cpu_is_omap34xx() || cpu_is_omap44xx() ||
254 (bank->non_wakeup_gpios & gpio_bit)) {
255 /*
256 * Log the edge gpio and manually trigger the IRQ
257 * after resume if the input level changes
258 * to avoid irq lost during PER RET/OFF mode
259 * Applies for omap2 non-wakeup gpio and all omap3 gpios
260 */
261 if (trigger & IRQ_TYPE_EDGE_BOTH)
262 bank->enabled_non_wakeup_gpios |= gpio_bit;
263 else
264 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
265 }
266
267 if (cpu_is_omap44xx()) {
268 bank->level_mask =
269 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT0) |
270 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT1);
271 } else {
272 bank->level_mask =
273 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
274 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
275 }
276 }
277 #endif
278
279 #ifdef CONFIG_ARCH_OMAP1
280 /*
281 * This only applies to chips that can't do both rising and falling edge
282 * detection at once. For all other chips, this function is a noop.
283 */
284 static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
285 {
286 void __iomem *reg = bank->base;
287 u32 l = 0;
288
289 switch (bank->method) {
290 case METHOD_MPUIO:
291 reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride;
292 break;
293 #ifdef CONFIG_ARCH_OMAP15XX
294 case METHOD_GPIO_1510:
295 reg += OMAP1510_GPIO_INT_CONTROL;
296 break;
297 #endif
298 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
299 case METHOD_GPIO_7XX:
300 reg += OMAP7XX_GPIO_INT_CONTROL;
301 break;
302 #endif
303 default:
304 return;
305 }
306
307 l = __raw_readl(reg);
308 if ((l >> gpio) & 1)
309 l &= ~(1 << gpio);
310 else
311 l |= 1 << gpio;
312
313 __raw_writel(l, reg);
314 }
315 #endif
316
317 static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
318 {
319 void __iomem *reg = bank->base;
320 u32 l = 0;
321
322 switch (bank->method) {
323 #ifdef CONFIG_ARCH_OMAP1
324 case METHOD_MPUIO:
325 reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride;
326 l = __raw_readl(reg);
327 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
328 bank->toggle_mask |= 1 << gpio;
329 if (trigger & IRQ_TYPE_EDGE_RISING)
330 l |= 1 << gpio;
331 else if (trigger & IRQ_TYPE_EDGE_FALLING)
332 l &= ~(1 << gpio);
333 else
334 goto bad;
335 break;
336 #endif
337 #ifdef CONFIG_ARCH_OMAP15XX
338 case METHOD_GPIO_1510:
339 reg += OMAP1510_GPIO_INT_CONTROL;
340 l = __raw_readl(reg);
341 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
342 bank->toggle_mask |= 1 << gpio;
343 if (trigger & IRQ_TYPE_EDGE_RISING)
344 l |= 1 << gpio;
345 else if (trigger & IRQ_TYPE_EDGE_FALLING)
346 l &= ~(1 << gpio);
347 else
348 goto bad;
349 break;
350 #endif
351 #ifdef CONFIG_ARCH_OMAP16XX
352 case METHOD_GPIO_1610:
353 if (gpio & 0x08)
354 reg += OMAP1610_GPIO_EDGE_CTRL2;
355 else
356 reg += OMAP1610_GPIO_EDGE_CTRL1;
357 gpio &= 0x07;
358 l = __raw_readl(reg);
359 l &= ~(3 << (gpio << 1));
360 if (trigger & IRQ_TYPE_EDGE_RISING)
361 l |= 2 << (gpio << 1);
362 if (trigger & IRQ_TYPE_EDGE_FALLING)
363 l |= 1 << (gpio << 1);
364 if (trigger)
365 /* Enable wake-up during idle for dynamic tick */
366 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
367 else
368 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
369 break;
370 #endif
371 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
372 case METHOD_GPIO_7XX:
373 reg += OMAP7XX_GPIO_INT_CONTROL;
374 l = __raw_readl(reg);
375 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
376 bank->toggle_mask |= 1 << gpio;
377 if (trigger & IRQ_TYPE_EDGE_RISING)
378 l |= 1 << gpio;
379 else if (trigger & IRQ_TYPE_EDGE_FALLING)
380 l &= ~(1 << gpio);
381 else
382 goto bad;
383 break;
384 #endif
385 #ifdef CONFIG_ARCH_OMAP2PLUS
386 case METHOD_GPIO_24XX:
387 case METHOD_GPIO_44XX:
388 set_24xx_gpio_triggering(bank, gpio, trigger);
389 return 0;
390 #endif
391 default:
392 goto bad;
393 }
394 __raw_writel(l, reg);
395 return 0;
396 bad:
397 return -EINVAL;
398 }
399
400 static int gpio_irq_type(struct irq_data *d, unsigned type)
401 {
402 struct gpio_bank *bank;
403 unsigned gpio;
404 int retval;
405 unsigned long flags;
406
407 if (!cpu_class_is_omap2() && d->irq > IH_MPUIO_BASE)
408 gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
409 else
410 gpio = d->irq - IH_GPIO_BASE;
411
412 if (type & ~IRQ_TYPE_SENSE_MASK)
413 return -EINVAL;
414
415 /* OMAP1 allows only only edge triggering */
416 if (!cpu_class_is_omap2()
417 && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
418 return -EINVAL;
419
420 bank = irq_data_get_irq_chip_data(d);
421 spin_lock_irqsave(&bank->lock, flags);
422 retval = _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), type);
423 spin_unlock_irqrestore(&bank->lock, flags);
424
425 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
426 __irq_set_handler_locked(d->irq, handle_level_irq);
427 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
428 __irq_set_handler_locked(d->irq, handle_edge_irq);
429
430 return retval;
431 }
432
433 static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
434 {
435 void __iomem *reg = bank->base;
436
437 reg += bank->regs->irqstatus;
438 __raw_writel(gpio_mask, reg);
439
440 /* Workaround for clearing DSP GPIO interrupts to allow retention */
441 if (bank->regs->irqstatus2) {
442 reg = bank->base + bank->regs->irqstatus2;
443 __raw_writel(gpio_mask, reg);
444 }
445
446 /* Flush posted write for the irq status to avoid spurious interrupts */
447 __raw_readl(reg);
448 }
449
450 static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
451 {
452 _clear_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
453 }
454
455 static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
456 {
457 void __iomem *reg = bank->base;
458 u32 l;
459 u32 mask = (1 << bank->width) - 1;
460
461 reg += bank->regs->irqenable;
462 l = __raw_readl(reg);
463 if (bank->regs->irqenable_inv)
464 l = ~l;
465 l &= mask;
466 return l;
467 }
468
469 static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
470 {
471 void __iomem *reg = bank->base;
472 u32 l;
473
474 if (bank->regs->set_irqenable) {
475 reg += bank->regs->set_irqenable;
476 l = gpio_mask;
477 } else {
478 reg += bank->regs->irqenable;
479 l = __raw_readl(reg);
480 if (bank->regs->irqenable_inv)
481 l &= ~gpio_mask;
482 else
483 l |= gpio_mask;
484 }
485
486 __raw_writel(l, reg);
487 }
488
489 static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
490 {
491 void __iomem *reg = bank->base;
492 u32 l;
493
494 if (bank->regs->clr_irqenable) {
495 reg += bank->regs->clr_irqenable;
496 l = gpio_mask;
497 } else {
498 reg += bank->regs->irqenable;
499 l = __raw_readl(reg);
500 if (bank->regs->irqenable_inv)
501 l |= gpio_mask;
502 else
503 l &= ~gpio_mask;
504 }
505
506 __raw_writel(l, reg);
507 }
508
509 static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
510 {
511 if (enable)
512 _enable_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
513 else
514 _disable_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
515 }
516
517 /*
518 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
519 * 1510 does not seem to have a wake-up register. If JTAG is connected
520 * to the target, system will wake up always on GPIO events. While
521 * system is running all registered GPIO interrupts need to have wake-up
522 * enabled. When system is suspended, only selected GPIO interrupts need
523 * to have wake-up enabled.
524 */
525 static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
526 {
527 u32 gpio_bit = GPIO_BIT(bank, gpio);
528 unsigned long flags;
529
530 if (bank->non_wakeup_gpios & gpio_bit) {
531 dev_err(bank->dev,
532 "Unable to modify wakeup on non-wakeup GPIO%d\n", gpio);
533 return -EINVAL;
534 }
535
536 spin_lock_irqsave(&bank->lock, flags);
537 if (enable)
538 bank->suspend_wakeup |= gpio_bit;
539 else
540 bank->suspend_wakeup &= ~gpio_bit;
541
542 spin_unlock_irqrestore(&bank->lock, flags);
543
544 return 0;
545 }
546
547 static void _reset_gpio(struct gpio_bank *bank, int gpio)
548 {
549 _set_gpio_direction(bank, GPIO_INDEX(bank, gpio), 1);
550 _set_gpio_irqenable(bank, gpio, 0);
551 _clear_gpio_irqstatus(bank, gpio);
552 _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE);
553 }
554
555 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
556 static int gpio_wake_enable(struct irq_data *d, unsigned int enable)
557 {
558 unsigned int gpio = d->irq - IH_GPIO_BASE;
559 struct gpio_bank *bank;
560 int retval;
561
562 bank = irq_data_get_irq_chip_data(d);
563 retval = _set_gpio_wakeup(bank, gpio, enable);
564
565 return retval;
566 }
567
568 static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
569 {
570 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
571 unsigned long flags;
572
573 spin_lock_irqsave(&bank->lock, flags);
574
575 /* Set trigger to none. You need to enable the desired trigger with
576 * request_irq() or set_irq_type().
577 */
578 _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
579
580 #ifdef CONFIG_ARCH_OMAP15XX
581 if (bank->method == METHOD_GPIO_1510) {
582 void __iomem *reg;
583
584 /* Claim the pin for MPU */
585 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
586 __raw_writel(__raw_readl(reg) | (1 << offset), reg);
587 }
588 #endif
589 if (!cpu_class_is_omap1()) {
590 if (!bank->mod_usage) {
591 void __iomem *reg = bank->base;
592 u32 ctrl;
593
594 if (cpu_is_omap24xx() || cpu_is_omap34xx())
595 reg += OMAP24XX_GPIO_CTRL;
596 else if (cpu_is_omap44xx())
597 reg += OMAP4_GPIO_CTRL;
598 ctrl = __raw_readl(reg);
599 /* Module is enabled, clocks are not gated */
600 ctrl &= 0xFFFFFFFE;
601 __raw_writel(ctrl, reg);
602 }
603 bank->mod_usage |= 1 << offset;
604 }
605 spin_unlock_irqrestore(&bank->lock, flags);
606
607 return 0;
608 }
609
610 static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
611 {
612 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
613 unsigned long flags;
614
615 spin_lock_irqsave(&bank->lock, flags);
616 #ifdef CONFIG_ARCH_OMAP16XX
617 if (bank->method == METHOD_GPIO_1610) {
618 /* Disable wake-up during idle for dynamic tick */
619 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
620 __raw_writel(1 << offset, reg);
621 }
622 #endif
623 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
624 if (bank->method == METHOD_GPIO_24XX) {
625 /* Disable wake-up during idle for dynamic tick */
626 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
627 __raw_writel(1 << offset, reg);
628 }
629 #endif
630 #ifdef CONFIG_ARCH_OMAP4
631 if (bank->method == METHOD_GPIO_44XX) {
632 /* Disable wake-up during idle for dynamic tick */
633 void __iomem *reg = bank->base + OMAP4_GPIO_IRQWAKEN0;
634 __raw_writel(1 << offset, reg);
635 }
636 #endif
637 if (!cpu_class_is_omap1()) {
638 bank->mod_usage &= ~(1 << offset);
639 if (!bank->mod_usage) {
640 void __iomem *reg = bank->base;
641 u32 ctrl;
642
643 if (cpu_is_omap24xx() || cpu_is_omap34xx())
644 reg += OMAP24XX_GPIO_CTRL;
645 else if (cpu_is_omap44xx())
646 reg += OMAP4_GPIO_CTRL;
647 ctrl = __raw_readl(reg);
648 /* Module is disabled, clocks are gated */
649 ctrl |= 1;
650 __raw_writel(ctrl, reg);
651 }
652 }
653 _reset_gpio(bank, bank->chip.base + offset);
654 spin_unlock_irqrestore(&bank->lock, flags);
655 }
656
657 /*
658 * We need to unmask the GPIO bank interrupt as soon as possible to
659 * avoid missing GPIO interrupts for other lines in the bank.
660 * Then we need to mask-read-clear-unmask the triggered GPIO lines
661 * in the bank to avoid missing nested interrupts for a GPIO line.
662 * If we wait to unmask individual GPIO lines in the bank after the
663 * line's interrupt handler has been run, we may miss some nested
664 * interrupts.
665 */
666 static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
667 {
668 void __iomem *isr_reg = NULL;
669 u32 isr;
670 unsigned int gpio_irq, gpio_index;
671 struct gpio_bank *bank;
672 u32 retrigger = 0;
673 int unmasked = 0;
674 struct irq_chip *chip = irq_desc_get_chip(desc);
675
676 chained_irq_enter(chip, desc);
677
678 bank = irq_get_handler_data(irq);
679 isr_reg = bank->base + bank->regs->irqstatus;
680
681 if (WARN_ON(!isr_reg))
682 goto exit;
683
684 while(1) {
685 u32 isr_saved, level_mask = 0;
686 u32 enabled;
687
688 enabled = _get_gpio_irqbank_mask(bank);
689 isr_saved = isr = __raw_readl(isr_reg) & enabled;
690
691 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
692 isr &= 0x0000ffff;
693
694 if (cpu_class_is_omap2()) {
695 level_mask = bank->level_mask & enabled;
696 }
697
698 /* clear edge sensitive interrupts before handler(s) are
699 called so that we don't miss any interrupt occurred while
700 executing them */
701 _disable_gpio_irqbank(bank, isr_saved & ~level_mask);
702 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
703 _enable_gpio_irqbank(bank, isr_saved & ~level_mask);
704
705 /* if there is only edge sensitive GPIO pin interrupts
706 configured, we could unmask GPIO bank interrupt immediately */
707 if (!level_mask && !unmasked) {
708 unmasked = 1;
709 chained_irq_exit(chip, desc);
710 }
711
712 isr |= retrigger;
713 retrigger = 0;
714 if (!isr)
715 break;
716
717 gpio_irq = bank->virtual_irq_start;
718 for (; isr != 0; isr >>= 1, gpio_irq++) {
719 gpio_index = GPIO_INDEX(bank, irq_to_gpio(gpio_irq));
720
721 if (!(isr & 1))
722 continue;
723
724 #ifdef CONFIG_ARCH_OMAP1
725 /*
726 * Some chips can't respond to both rising and falling
727 * at the same time. If this irq was requested with
728 * both flags, we need to flip the ICR data for the IRQ
729 * to respond to the IRQ for the opposite direction.
730 * This will be indicated in the bank toggle_mask.
731 */
732 if (bank->toggle_mask & (1 << gpio_index))
733 _toggle_gpio_edge_triggering(bank, gpio_index);
734 #endif
735
736 generic_handle_irq(gpio_irq);
737 }
738 }
739 /* if bank has any level sensitive GPIO pin interrupt
740 configured, we must unmask the bank interrupt only after
741 handler(s) are executed in order to avoid spurious bank
742 interrupt */
743 exit:
744 if (!unmasked)
745 chained_irq_exit(chip, desc);
746 }
747
748 static void gpio_irq_shutdown(struct irq_data *d)
749 {
750 unsigned int gpio = d->irq - IH_GPIO_BASE;
751 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
752 unsigned long flags;
753
754 spin_lock_irqsave(&bank->lock, flags);
755 _reset_gpio(bank, gpio);
756 spin_unlock_irqrestore(&bank->lock, flags);
757 }
758
759 static void gpio_ack_irq(struct irq_data *d)
760 {
761 unsigned int gpio = d->irq - IH_GPIO_BASE;
762 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
763
764 _clear_gpio_irqstatus(bank, gpio);
765 }
766
767 static void gpio_mask_irq(struct irq_data *d)
768 {
769 unsigned int gpio = d->irq - IH_GPIO_BASE;
770 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
771 unsigned long flags;
772
773 spin_lock_irqsave(&bank->lock, flags);
774 _set_gpio_irqenable(bank, gpio, 0);
775 _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE);
776 spin_unlock_irqrestore(&bank->lock, flags);
777 }
778
779 static void gpio_unmask_irq(struct irq_data *d)
780 {
781 unsigned int gpio = d->irq - IH_GPIO_BASE;
782 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
783 unsigned int irq_mask = GPIO_BIT(bank, gpio);
784 u32 trigger = irqd_get_trigger_type(d);
785 unsigned long flags;
786
787 spin_lock_irqsave(&bank->lock, flags);
788 if (trigger)
789 _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), trigger);
790
791 /* For level-triggered GPIOs, the clearing must be done after
792 * the HW source is cleared, thus after the handler has run */
793 if (bank->level_mask & irq_mask) {
794 _set_gpio_irqenable(bank, gpio, 0);
795 _clear_gpio_irqstatus(bank, gpio);
796 }
797
798 _set_gpio_irqenable(bank, gpio, 1);
799 spin_unlock_irqrestore(&bank->lock, flags);
800 }
801
802 static struct irq_chip gpio_irq_chip = {
803 .name = "GPIO",
804 .irq_shutdown = gpio_irq_shutdown,
805 .irq_ack = gpio_ack_irq,
806 .irq_mask = gpio_mask_irq,
807 .irq_unmask = gpio_unmask_irq,
808 .irq_set_type = gpio_irq_type,
809 .irq_set_wake = gpio_wake_enable,
810 };
811
812 /*---------------------------------------------------------------------*/
813
814 #ifdef CONFIG_ARCH_OMAP1
815
816 #define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
817
818 #ifdef CONFIG_ARCH_OMAP16XX
819
820 #include <linux/platform_device.h>
821
822 static int omap_mpuio_suspend_noirq(struct device *dev)
823 {
824 struct platform_device *pdev = to_platform_device(dev);
825 struct gpio_bank *bank = platform_get_drvdata(pdev);
826 void __iomem *mask_reg = bank->base +
827 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
828 unsigned long flags;
829
830 spin_lock_irqsave(&bank->lock, flags);
831 bank->saved_wakeup = __raw_readl(mask_reg);
832 __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
833 spin_unlock_irqrestore(&bank->lock, flags);
834
835 return 0;
836 }
837
838 static int omap_mpuio_resume_noirq(struct device *dev)
839 {
840 struct platform_device *pdev = to_platform_device(dev);
841 struct gpio_bank *bank = platform_get_drvdata(pdev);
842 void __iomem *mask_reg = bank->base +
843 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
844 unsigned long flags;
845
846 spin_lock_irqsave(&bank->lock, flags);
847 __raw_writel(bank->saved_wakeup, mask_reg);
848 spin_unlock_irqrestore(&bank->lock, flags);
849
850 return 0;
851 }
852
853 static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
854 .suspend_noirq = omap_mpuio_suspend_noirq,
855 .resume_noirq = omap_mpuio_resume_noirq,
856 };
857
858 /* use platform_driver for this. */
859 static struct platform_driver omap_mpuio_driver = {
860 .driver = {
861 .name = "mpuio",
862 .pm = &omap_mpuio_dev_pm_ops,
863 },
864 };
865
866 static struct platform_device omap_mpuio_device = {
867 .name = "mpuio",
868 .id = -1,
869 .dev = {
870 .driver = &omap_mpuio_driver.driver,
871 }
872 /* could list the /proc/iomem resources */
873 };
874
875 static inline void mpuio_init(void)
876 {
877 struct gpio_bank *bank = &gpio_bank[0];
878 platform_set_drvdata(&omap_mpuio_device, bank);
879
880 if (platform_driver_register(&omap_mpuio_driver) == 0)
881 (void) platform_device_register(&omap_mpuio_device);
882 }
883
884 #else
885 static inline void mpuio_init(void) {}
886 #endif /* 16xx */
887
888 #else
889
890 #define bank_is_mpuio(bank) 0
891 static inline void mpuio_init(void) {}
892
893 #endif
894
895 /*---------------------------------------------------------------------*/
896
897 /* REVISIT these are stupid implementations! replace by ones that
898 * don't switch on METHOD_* and which mostly avoid spinlocks
899 */
900
901 static int gpio_input(struct gpio_chip *chip, unsigned offset)
902 {
903 struct gpio_bank *bank;
904 unsigned long flags;
905
906 bank = container_of(chip, struct gpio_bank, chip);
907 spin_lock_irqsave(&bank->lock, flags);
908 _set_gpio_direction(bank, offset, 1);
909 spin_unlock_irqrestore(&bank->lock, flags);
910 return 0;
911 }
912
913 static int gpio_is_input(struct gpio_bank *bank, int mask)
914 {
915 void __iomem *reg = bank->base + bank->regs->direction;
916
917 return __raw_readl(reg) & mask;
918 }
919
920 static int gpio_get(struct gpio_chip *chip, unsigned offset)
921 {
922 struct gpio_bank *bank;
923 void __iomem *reg;
924 int gpio;
925 u32 mask;
926
927 gpio = chip->base + offset;
928 bank = container_of(chip, struct gpio_bank, chip);
929 reg = bank->base;
930 mask = GPIO_BIT(bank, gpio);
931
932 if (gpio_is_input(bank, mask))
933 return _get_gpio_datain(bank, gpio);
934 else
935 return _get_gpio_dataout(bank, gpio);
936 }
937
938 static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
939 {
940 struct gpio_bank *bank;
941 unsigned long flags;
942
943 bank = container_of(chip, struct gpio_bank, chip);
944 spin_lock_irqsave(&bank->lock, flags);
945 bank->set_dataout(bank, offset, value);
946 _set_gpio_direction(bank, offset, 0);
947 spin_unlock_irqrestore(&bank->lock, flags);
948 return 0;
949 }
950
951 static int gpio_debounce(struct gpio_chip *chip, unsigned offset,
952 unsigned debounce)
953 {
954 struct gpio_bank *bank;
955 unsigned long flags;
956
957 bank = container_of(chip, struct gpio_bank, chip);
958
959 if (!bank->dbck) {
960 bank->dbck = clk_get(bank->dev, "dbclk");
961 if (IS_ERR(bank->dbck))
962 dev_err(bank->dev, "Could not get gpio dbck\n");
963 }
964
965 spin_lock_irqsave(&bank->lock, flags);
966 _set_gpio_debounce(bank, offset, debounce);
967 spin_unlock_irqrestore(&bank->lock, flags);
968
969 return 0;
970 }
971
972 static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
973 {
974 struct gpio_bank *bank;
975 unsigned long flags;
976
977 bank = container_of(chip, struct gpio_bank, chip);
978 spin_lock_irqsave(&bank->lock, flags);
979 bank->set_dataout(bank, offset, value);
980 spin_unlock_irqrestore(&bank->lock, flags);
981 }
982
983 static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
984 {
985 struct gpio_bank *bank;
986
987 bank = container_of(chip, struct gpio_bank, chip);
988 return bank->virtual_irq_start + offset;
989 }
990
991 /*---------------------------------------------------------------------*/
992
993 static void __init omap_gpio_show_rev(struct gpio_bank *bank)
994 {
995 static bool called;
996 u32 rev;
997
998 if (called || bank->regs->revision == USHRT_MAX)
999 return;
1000
1001 rev = __raw_readw(bank->base + bank->regs->revision);
1002 pr_info("OMAP GPIO hardware version %d.%d\n",
1003 (rev >> 4) & 0x0f, rev & 0x0f);
1004
1005 called = true;
1006 }
1007
1008 /* This lock class tells lockdep that GPIO irqs are in a different
1009 * category than their parents, so it won't report false recursion.
1010 */
1011 static struct lock_class_key gpio_lock_class;
1012
1013 static inline int init_gpio_info(struct platform_device *pdev)
1014 {
1015 /* TODO: Analyze removing gpio_bank_count usage from driver code */
1016 gpio_bank = kzalloc(gpio_bank_count * sizeof(struct gpio_bank),
1017 GFP_KERNEL);
1018 if (!gpio_bank) {
1019 dev_err(&pdev->dev, "Memory alloc failed for gpio_bank\n");
1020 return -ENOMEM;
1021 }
1022 return 0;
1023 }
1024
1025 /* TODO: Cleanup cpu_is_* checks */
1026 static void omap_gpio_mod_init(struct gpio_bank *bank, int id)
1027 {
1028 if (cpu_class_is_omap2()) {
1029 if (cpu_is_omap44xx()) {
1030 __raw_writel(0xffffffff, bank->base +
1031 OMAP4_GPIO_IRQSTATUSCLR0);
1032 __raw_writel(0x00000000, bank->base +
1033 OMAP4_GPIO_DEBOUNCENABLE);
1034 /* Initialize interface clk ungated, module enabled */
1035 __raw_writel(0, bank->base + OMAP4_GPIO_CTRL);
1036 } else if (cpu_is_omap34xx()) {
1037 __raw_writel(0x00000000, bank->base +
1038 OMAP24XX_GPIO_IRQENABLE1);
1039 __raw_writel(0xffffffff, bank->base +
1040 OMAP24XX_GPIO_IRQSTATUS1);
1041 __raw_writel(0x00000000, bank->base +
1042 OMAP24XX_GPIO_DEBOUNCE_EN);
1043
1044 /* Initialize interface clk ungated, module enabled */
1045 __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
1046 } else if (cpu_is_omap24xx()) {
1047 static const u32 non_wakeup_gpios[] = {
1048 0xe203ffc0, 0x08700040
1049 };
1050 if (id < ARRAY_SIZE(non_wakeup_gpios))
1051 bank->non_wakeup_gpios = non_wakeup_gpios[id];
1052 }
1053 } else if (cpu_class_is_omap1()) {
1054 if (bank_is_mpuio(bank))
1055 __raw_writew(0xffff, bank->base +
1056 OMAP_MPUIO_GPIO_MASKIT / bank->stride);
1057 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
1058 __raw_writew(0xffff, bank->base
1059 + OMAP1510_GPIO_INT_MASK);
1060 __raw_writew(0x0000, bank->base
1061 + OMAP1510_GPIO_INT_STATUS);
1062 }
1063 if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
1064 __raw_writew(0x0000, bank->base
1065 + OMAP1610_GPIO_IRQENABLE1);
1066 __raw_writew(0xffff, bank->base
1067 + OMAP1610_GPIO_IRQSTATUS1);
1068 __raw_writew(0x0014, bank->base
1069 + OMAP1610_GPIO_SYSCONFIG);
1070
1071 /*
1072 * Enable system clock for GPIO module.
1073 * The CAM_CLK_CTRL *is* really the right place.
1074 */
1075 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04,
1076 ULPD_CAM_CLK_CTRL);
1077 }
1078 if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) {
1079 __raw_writel(0xffffffff, bank->base
1080 + OMAP7XX_GPIO_INT_MASK);
1081 __raw_writel(0x00000000, bank->base
1082 + OMAP7XX_GPIO_INT_STATUS);
1083 }
1084 }
1085 }
1086
1087 static __init void
1088 omap_mpuio_alloc_gc(struct gpio_bank *bank, unsigned int irq_start,
1089 unsigned int num)
1090 {
1091 struct irq_chip_generic *gc;
1092 struct irq_chip_type *ct;
1093
1094 gc = irq_alloc_generic_chip("MPUIO", 1, irq_start, bank->base,
1095 handle_simple_irq);
1096 if (!gc) {
1097 dev_err(bank->dev, "Memory alloc failed for gc\n");
1098 return;
1099 }
1100
1101 ct = gc->chip_types;
1102
1103 /* NOTE: No ack required, reading IRQ status clears it. */
1104 ct->chip.irq_mask = irq_gc_mask_set_bit;
1105 ct->chip.irq_unmask = irq_gc_mask_clr_bit;
1106 ct->chip.irq_set_type = gpio_irq_type;
1107 /* REVISIT: assuming only 16xx supports MPUIO wake events */
1108 if (cpu_is_omap16xx())
1109 ct->chip.irq_set_wake = gpio_wake_enable,
1110
1111 ct->regs.mask = OMAP_MPUIO_GPIO_INT / bank->stride;
1112 irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
1113 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
1114 }
1115
1116 static void __devinit omap_gpio_chip_init(struct gpio_bank *bank)
1117 {
1118 int j;
1119 static int gpio;
1120
1121 bank->mod_usage = 0;
1122 /*
1123 * REVISIT eventually switch from OMAP-specific gpio structs
1124 * over to the generic ones
1125 */
1126 bank->chip.request = omap_gpio_request;
1127 bank->chip.free = omap_gpio_free;
1128 bank->chip.direction_input = gpio_input;
1129 bank->chip.get = gpio_get;
1130 bank->chip.direction_output = gpio_output;
1131 bank->chip.set_debounce = gpio_debounce;
1132 bank->chip.set = gpio_set;
1133 bank->chip.to_irq = gpio_2irq;
1134 if (bank_is_mpuio(bank)) {
1135 bank->chip.label = "mpuio";
1136 #ifdef CONFIG_ARCH_OMAP16XX
1137 bank->chip.dev = &omap_mpuio_device.dev;
1138 #endif
1139 bank->chip.base = OMAP_MPUIO(0);
1140 } else {
1141 bank->chip.label = "gpio";
1142 bank->chip.base = gpio;
1143 gpio += bank->width;
1144 }
1145 bank->chip.ngpio = bank->width;
1146
1147 gpiochip_add(&bank->chip);
1148
1149 for (j = bank->virtual_irq_start;
1150 j < bank->virtual_irq_start + bank->width; j++) {
1151 irq_set_lockdep_class(j, &gpio_lock_class);
1152 irq_set_chip_data(j, bank);
1153 if (bank_is_mpuio(bank)) {
1154 omap_mpuio_alloc_gc(bank, j, bank->width);
1155 } else {
1156 irq_set_chip(j, &gpio_irq_chip);
1157 irq_set_handler(j, handle_simple_irq);
1158 set_irq_flags(j, IRQF_VALID);
1159 }
1160 }
1161 irq_set_chained_handler(bank->irq, gpio_irq_handler);
1162 irq_set_handler_data(bank->irq, bank);
1163 }
1164
1165 static int __devinit omap_gpio_probe(struct platform_device *pdev)
1166 {
1167 static int gpio_init_done;
1168 struct omap_gpio_platform_data *pdata;
1169 struct resource *res;
1170 int id;
1171 struct gpio_bank *bank;
1172
1173 if (!pdev->dev.platform_data)
1174 return -EINVAL;
1175
1176 pdata = pdev->dev.platform_data;
1177
1178 if (!gpio_init_done) {
1179 int ret;
1180
1181 ret = init_gpio_info(pdev);
1182 if (ret)
1183 return ret;
1184 }
1185
1186 id = pdev->id;
1187 bank = &gpio_bank[id];
1188
1189 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1190 if (unlikely(!res)) {
1191 dev_err(&pdev->dev, "GPIO Bank %i Invalid IRQ resource\n", id);
1192 return -ENODEV;
1193 }
1194
1195 bank->irq = res->start;
1196 bank->virtual_irq_start = pdata->virtual_irq_start;
1197 bank->method = pdata->bank_type;
1198 bank->dev = &pdev->dev;
1199 bank->dbck_flag = pdata->dbck_flag;
1200 bank->stride = pdata->bank_stride;
1201 bank->width = pdata->bank_width;
1202
1203 bank->regs = pdata->regs;
1204
1205 if (bank->regs->set_dataout && bank->regs->clr_dataout)
1206 bank->set_dataout = _set_gpio_dataout_reg;
1207 else
1208 bank->set_dataout = _set_gpio_dataout_mask;
1209
1210 spin_lock_init(&bank->lock);
1211
1212 /* Static mapping, never released */
1213 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1214 if (unlikely(!res)) {
1215 dev_err(&pdev->dev, "GPIO Bank %i Invalid mem resource\n", id);
1216 return -ENODEV;
1217 }
1218
1219 bank->base = ioremap(res->start, resource_size(res));
1220 if (!bank->base) {
1221 dev_err(&pdev->dev, "Could not ioremap gpio bank%i\n", id);
1222 return -ENOMEM;
1223 }
1224
1225 pm_runtime_enable(bank->dev);
1226 pm_runtime_get_sync(bank->dev);
1227
1228 omap_gpio_mod_init(bank, id);
1229 omap_gpio_chip_init(bank);
1230 omap_gpio_show_rev(bank);
1231
1232 if (!gpio_init_done)
1233 gpio_init_done = 1;
1234
1235 return 0;
1236 }
1237
1238 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
1239 static int omap_gpio_suspend(void)
1240 {
1241 int i;
1242
1243 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1244 return 0;
1245
1246 for (i = 0; i < gpio_bank_count; i++) {
1247 struct gpio_bank *bank = &gpio_bank[i];
1248 void __iomem *wake_status;
1249 void __iomem *wake_clear;
1250 void __iomem *wake_set;
1251 unsigned long flags;
1252
1253 switch (bank->method) {
1254 #ifdef CONFIG_ARCH_OMAP16XX
1255 case METHOD_GPIO_1610:
1256 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1257 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1258 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1259 break;
1260 #endif
1261 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1262 case METHOD_GPIO_24XX:
1263 wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN;
1264 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1265 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1266 break;
1267 #endif
1268 #ifdef CONFIG_ARCH_OMAP4
1269 case METHOD_GPIO_44XX:
1270 wake_status = bank->base + OMAP4_GPIO_IRQWAKEN0;
1271 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
1272 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
1273 break;
1274 #endif
1275 default:
1276 continue;
1277 }
1278
1279 spin_lock_irqsave(&bank->lock, flags);
1280 bank->saved_wakeup = __raw_readl(wake_status);
1281 __raw_writel(0xffffffff, wake_clear);
1282 __raw_writel(bank->suspend_wakeup, wake_set);
1283 spin_unlock_irqrestore(&bank->lock, flags);
1284 }
1285
1286 return 0;
1287 }
1288
1289 static void omap_gpio_resume(void)
1290 {
1291 int i;
1292
1293 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1294 return;
1295
1296 for (i = 0; i < gpio_bank_count; i++) {
1297 struct gpio_bank *bank = &gpio_bank[i];
1298 void __iomem *wake_clear;
1299 void __iomem *wake_set;
1300 unsigned long flags;
1301
1302 switch (bank->method) {
1303 #ifdef CONFIG_ARCH_OMAP16XX
1304 case METHOD_GPIO_1610:
1305 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1306 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1307 break;
1308 #endif
1309 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1310 case METHOD_GPIO_24XX:
1311 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1312 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1313 break;
1314 #endif
1315 #ifdef CONFIG_ARCH_OMAP4
1316 case METHOD_GPIO_44XX:
1317 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
1318 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
1319 break;
1320 #endif
1321 default:
1322 continue;
1323 }
1324
1325 spin_lock_irqsave(&bank->lock, flags);
1326 __raw_writel(0xffffffff, wake_clear);
1327 __raw_writel(bank->saved_wakeup, wake_set);
1328 spin_unlock_irqrestore(&bank->lock, flags);
1329 }
1330 }
1331
1332 static struct syscore_ops omap_gpio_syscore_ops = {
1333 .suspend = omap_gpio_suspend,
1334 .resume = omap_gpio_resume,
1335 };
1336
1337 #endif
1338
1339 #ifdef CONFIG_ARCH_OMAP2PLUS
1340
1341 static int workaround_enabled;
1342
1343 void omap2_gpio_prepare_for_idle(int off_mode)
1344 {
1345 int i, c = 0;
1346 int min = 0;
1347
1348 if (cpu_is_omap34xx())
1349 min = 1;
1350
1351 for (i = min; i < gpio_bank_count; i++) {
1352 struct gpio_bank *bank = &gpio_bank[i];
1353 u32 l1 = 0, l2 = 0;
1354 int j;
1355
1356 for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
1357 clk_disable(bank->dbck);
1358
1359 if (!off_mode)
1360 continue;
1361
1362 /* If going to OFF, remove triggering for all
1363 * non-wakeup GPIOs. Otherwise spurious IRQs will be
1364 * generated. See OMAP2420 Errata item 1.101. */
1365 if (!(bank->enabled_non_wakeup_gpios))
1366 continue;
1367
1368 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1369 bank->saved_datain = __raw_readl(bank->base +
1370 OMAP24XX_GPIO_DATAIN);
1371 l1 = __raw_readl(bank->base +
1372 OMAP24XX_GPIO_FALLINGDETECT);
1373 l2 = __raw_readl(bank->base +
1374 OMAP24XX_GPIO_RISINGDETECT);
1375 }
1376
1377 if (cpu_is_omap44xx()) {
1378 bank->saved_datain = __raw_readl(bank->base +
1379 OMAP4_GPIO_DATAIN);
1380 l1 = __raw_readl(bank->base +
1381 OMAP4_GPIO_FALLINGDETECT);
1382 l2 = __raw_readl(bank->base +
1383 OMAP4_GPIO_RISINGDETECT);
1384 }
1385
1386 bank->saved_fallingdetect = l1;
1387 bank->saved_risingdetect = l2;
1388 l1 &= ~bank->enabled_non_wakeup_gpios;
1389 l2 &= ~bank->enabled_non_wakeup_gpios;
1390
1391 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1392 __raw_writel(l1, bank->base +
1393 OMAP24XX_GPIO_FALLINGDETECT);
1394 __raw_writel(l2, bank->base +
1395 OMAP24XX_GPIO_RISINGDETECT);
1396 }
1397
1398 if (cpu_is_omap44xx()) {
1399 __raw_writel(l1, bank->base + OMAP4_GPIO_FALLINGDETECT);
1400 __raw_writel(l2, bank->base + OMAP4_GPIO_RISINGDETECT);
1401 }
1402
1403 c++;
1404 }
1405 if (!c) {
1406 workaround_enabled = 0;
1407 return;
1408 }
1409 workaround_enabled = 1;
1410 }
1411
1412 void omap2_gpio_resume_after_idle(void)
1413 {
1414 int i;
1415 int min = 0;
1416
1417 if (cpu_is_omap34xx())
1418 min = 1;
1419 for (i = min; i < gpio_bank_count; i++) {
1420 struct gpio_bank *bank = &gpio_bank[i];
1421 u32 l = 0, gen, gen0, gen1;
1422 int j;
1423
1424 for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
1425 clk_enable(bank->dbck);
1426
1427 if (!workaround_enabled)
1428 continue;
1429
1430 if (!(bank->enabled_non_wakeup_gpios))
1431 continue;
1432
1433 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1434 __raw_writel(bank->saved_fallingdetect,
1435 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1436 __raw_writel(bank->saved_risingdetect,
1437 bank->base + OMAP24XX_GPIO_RISINGDETECT);
1438 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1439 }
1440
1441 if (cpu_is_omap44xx()) {
1442 __raw_writel(bank->saved_fallingdetect,
1443 bank->base + OMAP4_GPIO_FALLINGDETECT);
1444 __raw_writel(bank->saved_risingdetect,
1445 bank->base + OMAP4_GPIO_RISINGDETECT);
1446 l = __raw_readl(bank->base + OMAP4_GPIO_DATAIN);
1447 }
1448
1449 /* Check if any of the non-wakeup interrupt GPIOs have changed
1450 * state. If so, generate an IRQ by software. This is
1451 * horribly racy, but it's the best we can do to work around
1452 * this silicon bug. */
1453 l ^= bank->saved_datain;
1454 l &= bank->enabled_non_wakeup_gpios;
1455
1456 /*
1457 * No need to generate IRQs for the rising edge for gpio IRQs
1458 * configured with falling edge only; and vice versa.
1459 */
1460 gen0 = l & bank->saved_fallingdetect;
1461 gen0 &= bank->saved_datain;
1462
1463 gen1 = l & bank->saved_risingdetect;
1464 gen1 &= ~(bank->saved_datain);
1465
1466 /* FIXME: Consider GPIO IRQs with level detections properly! */
1467 gen = l & (~(bank->saved_fallingdetect) &
1468 ~(bank->saved_risingdetect));
1469 /* Consider all GPIO IRQs needed to be updated */
1470 gen |= gen0 | gen1;
1471
1472 if (gen) {
1473 u32 old0, old1;
1474
1475 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1476 old0 = __raw_readl(bank->base +
1477 OMAP24XX_GPIO_LEVELDETECT0);
1478 old1 = __raw_readl(bank->base +
1479 OMAP24XX_GPIO_LEVELDETECT1);
1480 __raw_writel(old0 | gen, bank->base +
1481 OMAP24XX_GPIO_LEVELDETECT0);
1482 __raw_writel(old1 | gen, bank->base +
1483 OMAP24XX_GPIO_LEVELDETECT1);
1484 __raw_writel(old0, bank->base +
1485 OMAP24XX_GPIO_LEVELDETECT0);
1486 __raw_writel(old1, bank->base +
1487 OMAP24XX_GPIO_LEVELDETECT1);
1488 }
1489
1490 if (cpu_is_omap44xx()) {
1491 old0 = __raw_readl(bank->base +
1492 OMAP4_GPIO_LEVELDETECT0);
1493 old1 = __raw_readl(bank->base +
1494 OMAP4_GPIO_LEVELDETECT1);
1495 __raw_writel(old0 | l, bank->base +
1496 OMAP4_GPIO_LEVELDETECT0);
1497 __raw_writel(old1 | l, bank->base +
1498 OMAP4_GPIO_LEVELDETECT1);
1499 __raw_writel(old0, bank->base +
1500 OMAP4_GPIO_LEVELDETECT0);
1501 __raw_writel(old1, bank->base +
1502 OMAP4_GPIO_LEVELDETECT1);
1503 }
1504 }
1505 }
1506
1507 }
1508
1509 #endif
1510
1511 #ifdef CONFIG_ARCH_OMAP3
1512 /* save the registers of bank 2-6 */
1513 void omap_gpio_save_context(void)
1514 {
1515 int i;
1516
1517 /* saving banks from 2-6 only since GPIO1 is in WKUP */
1518 for (i = 1; i < gpio_bank_count; i++) {
1519 struct gpio_bank *bank = &gpio_bank[i];
1520 gpio_context[i].irqenable1 =
1521 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE1);
1522 gpio_context[i].irqenable2 =
1523 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE2);
1524 gpio_context[i].wake_en =
1525 __raw_readl(bank->base + OMAP24XX_GPIO_WAKE_EN);
1526 gpio_context[i].ctrl =
1527 __raw_readl(bank->base + OMAP24XX_GPIO_CTRL);
1528 gpio_context[i].oe =
1529 __raw_readl(bank->base + OMAP24XX_GPIO_OE);
1530 gpio_context[i].leveldetect0 =
1531 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1532 gpio_context[i].leveldetect1 =
1533 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1534 gpio_context[i].risingdetect =
1535 __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
1536 gpio_context[i].fallingdetect =
1537 __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1538 gpio_context[i].dataout =
1539 __raw_readl(bank->base + OMAP24XX_GPIO_DATAOUT);
1540 }
1541 }
1542
1543 /* restore the required registers of bank 2-6 */
1544 void omap_gpio_restore_context(void)
1545 {
1546 int i;
1547
1548 for (i = 1; i < gpio_bank_count; i++) {
1549 struct gpio_bank *bank = &gpio_bank[i];
1550 __raw_writel(gpio_context[i].irqenable1,
1551 bank->base + OMAP24XX_GPIO_IRQENABLE1);
1552 __raw_writel(gpio_context[i].irqenable2,
1553 bank->base + OMAP24XX_GPIO_IRQENABLE2);
1554 __raw_writel(gpio_context[i].wake_en,
1555 bank->base + OMAP24XX_GPIO_WAKE_EN);
1556 __raw_writel(gpio_context[i].ctrl,
1557 bank->base + OMAP24XX_GPIO_CTRL);
1558 __raw_writel(gpio_context[i].oe,
1559 bank->base + OMAP24XX_GPIO_OE);
1560 __raw_writel(gpio_context[i].leveldetect0,
1561 bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1562 __raw_writel(gpio_context[i].leveldetect1,
1563 bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1564 __raw_writel(gpio_context[i].risingdetect,
1565 bank->base + OMAP24XX_GPIO_RISINGDETECT);
1566 __raw_writel(gpio_context[i].fallingdetect,
1567 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1568 __raw_writel(gpio_context[i].dataout,
1569 bank->base + OMAP24XX_GPIO_DATAOUT);
1570 }
1571 }
1572 #endif
1573
1574 static struct platform_driver omap_gpio_driver = {
1575 .probe = omap_gpio_probe,
1576 .driver = {
1577 .name = "omap_gpio",
1578 },
1579 };
1580
1581 /*
1582 * gpio driver register needs to be done before
1583 * machine_init functions access gpio APIs.
1584 * Hence omap_gpio_drv_reg() is a postcore_initcall.
1585 */
1586 static int __init omap_gpio_drv_reg(void)
1587 {
1588 return platform_driver_register(&omap_gpio_driver);
1589 }
1590 postcore_initcall(omap_gpio_drv_reg);
1591
1592 static int __init omap_gpio_sysinit(void)
1593 {
1594 mpuio_init();
1595
1596 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
1597 if (cpu_is_omap16xx() || cpu_class_is_omap2())
1598 register_syscore_ops(&omap_gpio_syscore_ops);
1599 #endif
1600
1601 return 0;
1602 }
1603
1604 arch_initcall(omap_gpio_sysinit);