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aufs: possible bugfix, allow the nested aufsd between several aufs mounts
[zen-stable.git] / sound / sparc / dbri.c
bloba6b0deb77746c11646e42dd9f5f6353311e94656
1 /*
2 * Driver for DBRI sound chip found on Sparcs.
3 * Copyright (C) 2004, 2005 Martin Habets (mhabets@users.sourceforge.net)
4 *
5 * Converted to ring buffered version by Krzysztof Helt (krzysztof.h1@wp.pl)
6 *
7 * Based entirely upon drivers/sbus/audio/dbri.c which is:
8 * Copyright (C) 1997 Rudolf Koenig (rfkoenig@immd4.informatik.uni-erlangen.de)
9 * Copyright (C) 1998, 1999 Brent Baccala (baccala@freesoft.org)
10 *
11 * This is the low level driver for the DBRI & MMCODEC duo used for ISDN & AUDIO
12 * on Sun SPARCStation 10, 20, LX and Voyager models.
13 *
14 * - DBRI: AT&T T5900FX Dual Basic Rates ISDN Interface. It is a 32 channel
15 * data time multiplexer with ISDN support (aka T7259)
16 * Interfaces: SBus,ISDN NT & TE, CHI, 4 bits parallel.
17 * CHI: (spelled ki) Concentration Highway Interface (AT&T or Intel bus ?).
18 * Documentation:
19 * - "STP 4000SBus Dual Basic Rate ISDN (DBRI) Transceiver" from
20 * Sparc Technology Business (courtesy of Sun Support)
21 * - Data sheet of the T7903, a newer but very similar ISA bus equivalent
22 * available from the Lucent (formerly AT&T microelectronics) home
23 * page.
24 * - http://www.freesoft.org/Linux/DBRI/
25 * - MMCODEC: Crystal Semiconductor CS4215 16 bit Multimedia Audio Codec
26 * Interfaces: CHI, Audio In & Out, 2 bits parallel
27 * Documentation: from the Crystal Semiconductor home page.
28 *
29 * The DBRI is a 32 pipe machine, each pipe can transfer some bits between
30 * memory and a serial device (long pipes, no. 0-15) or between two serial
31 * devices (short pipes, no. 16-31), or simply send a fixed data to a serial
32 * device (short pipes).
33 * A timeslot defines the bit-offset and no. of bits read from a serial device.
34 * The timeslots are linked to 6 circular lists, one for each direction for
35 * each serial device (NT,TE,CHI). A timeslot is associated to 1 or 2 pipes
36 * (the second one is a monitor/tee pipe, valid only for serial input).
37 *
38 * The mmcodec is connected via the CHI bus and needs the data & some
39 * parameters (volume, output selection) time multiplexed in 8 byte
40 * chunks. It also has a control mode, which serves for audio format setting.
41 *
42 * Looking at the CS4215 data sheet it is easy to set up 2 or 4 codecs on
43 * the same CHI bus, so I thought perhaps it is possible to use the on-board
44 * & the speakerbox codec simultaneously, giving 2 (not very independent :-)
45 * audio devices. But the SUN HW group decided against it, at least on my
46 * LX the speakerbox connector has at least 1 pin missing and 1 wrongly
47 * connected.
48 *
49 * I've tried to stick to the following function naming conventions:
50 * snd_* ALSA stuff
51 * cs4215_* CS4215 codec specific stuff
52 * dbri_* DBRI high-level stuff
53 * other DBRI low-level stuff
54 */
55
56 #include <linux/interrupt.h>
57 #include <linux/delay.h>
58 #include <linux/irq.h>
59 #include <linux/io.h>
60 #include <linux/dma-mapping.h>
61 #include <linux/gfp.h>
62
63 #include <sound/core.h>
64 #include <sound/pcm.h>
65 #include <sound/pcm_params.h>
66 #include <sound/info.h>
67 #include <sound/control.h>
68 #include <sound/initval.h>
69
70 #include <linux/of.h>
71 #include <linux/of_device.h>
72 #include <linux/atomic.h>
73 #include <linux/module.h>
74
75 MODULE_AUTHOR("Rudolf Koenig, Brent Baccala and Martin Habets");
76 MODULE_DESCRIPTION("Sun DBRI");
77 MODULE_LICENSE("GPL");
78 MODULE_SUPPORTED_DEVICE("{{Sun,DBRI}}");
79
80 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
81 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
82 /* Enable this card */
83 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
84
85 module_param_array(index, int, NULL, 0444);
86 MODULE_PARM_DESC(index, "Index value for Sun DBRI soundcard.");
87 module_param_array(id, charp, NULL, 0444);
88 MODULE_PARM_DESC(id, "ID string for Sun DBRI soundcard.");
89 module_param_array(enable, bool, NULL, 0444);
90 MODULE_PARM_DESC(enable, "Enable Sun DBRI soundcard.");
91
92 #undef DBRI_DEBUG
93
94 #define D_INT (1<<0)
95 #define D_GEN (1<<1)
96 #define D_CMD (1<<2)
97 #define D_MM (1<<3)
98 #define D_USR (1<<4)
99 #define D_DESC (1<<5)
100
101 static int dbri_debug;
102 module_param(dbri_debug, int, 0644);
103 MODULE_PARM_DESC(dbri_debug, "Debug value for Sun DBRI soundcard.");
104
105 #ifdef DBRI_DEBUG
106 static char *cmds[] = {
107 "WAIT", "PAUSE", "JUMP", "IIQ", "REX", "SDP", "CDP", "DTS",
108 "SSP", "CHI", "NT", "TE", "CDEC", "TEST", "CDM", "RESRV"
109 };
110
111 #define dprintk(a, x...) if (dbri_debug & a) printk(KERN_DEBUG x)
112
113 #else
114 #define dprintk(a, x...) do { } while (0)
115
116 #endif /* DBRI_DEBUG */
117
118 #define DBRI_CMD(cmd, intr, value) ((cmd << 28) | \
119 (intr << 27) | \
120 value)
121
122 /***************************************************************************
123 CS4215 specific definitions and structures
124 ****************************************************************************/
125
126 struct cs4215 {
127 __u8 data[4]; /* Data mode: Time slots 5-8 */
128 __u8 ctrl[4]; /* Ctrl mode: Time slots 1-4 */
129 __u8 onboard;
130 __u8 offset; /* Bit offset from frame sync to time slot 1 */
131 volatile __u32 status;
132 volatile __u32 version;
133 __u8 precision; /* In bits, either 8 or 16 */
134 __u8 channels; /* 1 or 2 */
135 };
136
137 /*
138 * Control mode first
139 */
140
141 /* Time Slot 1, Status register */
142 #define CS4215_CLB (1<<2) /* Control Latch Bit */
143 #define CS4215_OLB (1<<3) /* 1: line: 2.0V, speaker 4V */
144 /* 0: line: 2.8V, speaker 8V */
145 #define CS4215_MLB (1<<4) /* 1: Microphone: 20dB gain disabled */
146 #define CS4215_RSRVD_1 (1<<5)
147
148 /* Time Slot 2, Data Format Register */
149 #define CS4215_DFR_LINEAR16 0
150 #define CS4215_DFR_ULAW 1
151 #define CS4215_DFR_ALAW 2
152 #define CS4215_DFR_LINEAR8 3
153 #define CS4215_DFR_STEREO (1<<2)
154 static struct {
155 unsigned short freq;
156 unsigned char xtal;
157 unsigned char csval;
158 } CS4215_FREQ[] = {
159 { 8000, (1 << 4), (0 << 3) },
160 { 16000, (1 << 4), (1 << 3) },
161 { 27429, (1 << 4), (2 << 3) }, /* Actually 24428.57 */
162 { 32000, (1 << 4), (3 << 3) },
163 /* { NA, (1 << 4), (4 << 3) }, */
164 /* { NA, (1 << 4), (5 << 3) }, */
165 { 48000, (1 << 4), (6 << 3) },
166 { 9600, (1 << 4), (7 << 3) },
167 { 5512, (2 << 4), (0 << 3) }, /* Actually 5512.5 */
168 { 11025, (2 << 4), (1 << 3) },
169 { 18900, (2 << 4), (2 << 3) },
170 { 22050, (2 << 4), (3 << 3) },
171 { 37800, (2 << 4), (4 << 3) },
172 { 44100, (2 << 4), (5 << 3) },
173 { 33075, (2 << 4), (6 << 3) },
174 { 6615, (2 << 4), (7 << 3) },
175 { 0, 0, 0}
176 };
177
178 #define CS4215_HPF (1<<7) /* High Pass Filter, 1: Enabled */
179
180 #define CS4215_12_MASK 0xfcbf /* Mask off reserved bits in slot 1 & 2 */
181
182 /* Time Slot 3, Serial Port Control register */
183 #define CS4215_XEN (1<<0) /* 0: Enable serial output */
184 #define CS4215_XCLK (1<<1) /* 1: Master mode: Generate SCLK */
185 #define CS4215_BSEL_64 (0<<2) /* Bitrate: 64 bits per frame */
186 #define CS4215_BSEL_128 (1<<2)
187 #define CS4215_BSEL_256 (2<<2)
188 #define CS4215_MCK_MAST (0<<4) /* Master clock */
189 #define CS4215_MCK_XTL1 (1<<4) /* 24.576 MHz clock source */
190 #define CS4215_MCK_XTL2 (2<<4) /* 16.9344 MHz clock source */
191 #define CS4215_MCK_CLK1 (3<<4) /* Clockin, 256 x Fs */
192 #define CS4215_MCK_CLK2 (4<<4) /* Clockin, see DFR */
193
194 /* Time Slot 4, Test Register */
195 #define CS4215_DAD (1<<0) /* 0:Digital-Dig loop, 1:Dig-Analog-Dig loop */
196 #define CS4215_ENL (1<<1) /* Enable Loopback Testing */
197
198 /* Time Slot 5, Parallel Port Register */
199 /* Read only here and the same as the in data mode */
200
201 /* Time Slot 6, Reserved */
202
203 /* Time Slot 7, Version Register */
204 #define CS4215_VERSION_MASK 0xf /* Known versions 0/C, 1/D, 2/E */
205
206 /* Time Slot 8, Reserved */
207
208 /*
209 * Data mode
210 */
211 /* Time Slot 1-2: Left Channel Data, 2-3: Right Channel Data */
212
213 /* Time Slot 5, Output Setting */
214 #define CS4215_LO(v) v /* Left Output Attenuation 0x3f: -94.5 dB */
215 #define CS4215_LE (1<<6) /* Line Out Enable */
216 #define CS4215_HE (1<<7) /* Headphone Enable */
217
218 /* Time Slot 6, Output Setting */
219 #define CS4215_RO(v) v /* Right Output Attenuation 0x3f: -94.5 dB */
220 #define CS4215_SE (1<<6) /* Speaker Enable */
221 #define CS4215_ADI (1<<7) /* A/D Data Invalid: Busy in calibration */
222
223 /* Time Slot 7, Input Setting */
224 #define CS4215_LG(v) v /* Left Gain Setting 0xf: 22.5 dB */
225 #define CS4215_IS (1<<4) /* Input Select: 1=Microphone, 0=Line */
226 #define CS4215_OVR (1<<5) /* 1: Over range condition occurred */
227 #define CS4215_PIO0 (1<<6) /* Parallel I/O 0 */
228 #define CS4215_PIO1 (1<<7)
229
230 /* Time Slot 8, Input Setting */
231 #define CS4215_RG(v) v /* Right Gain Setting 0xf: 22.5 dB */
232 #define CS4215_MA(v) (v<<4) /* Monitor Path Attenuation 0xf: mute */
233
234 /***************************************************************************
235 DBRI specific definitions and structures
236 ****************************************************************************/
237
238 /* DBRI main registers */
239 #define REG0 0x00 /* Status and Control */
240 #define REG1 0x04 /* Mode and Interrupt */
241 #define REG2 0x08 /* Parallel IO */
242 #define REG3 0x0c /* Test */
243 #define REG8 0x20 /* Command Queue Pointer */
244 #define REG9 0x24 /* Interrupt Queue Pointer */
245
246 #define DBRI_NO_CMDS 64
247 #define DBRI_INT_BLK 64
248 #define DBRI_NO_DESCS 64
249 #define DBRI_NO_PIPES 32
250 #define DBRI_MAX_PIPE (DBRI_NO_PIPES - 1)
251
252 #define DBRI_REC 0
253 #define DBRI_PLAY 1
254 #define DBRI_NO_STREAMS 2
255
256 /* One transmit/receive descriptor */
257 /* When ba != 0 descriptor is used */
258 struct dbri_mem {
259 volatile __u32 word1;
260 __u32 ba; /* Transmit/Receive Buffer Address */
261 __u32 nda; /* Next Descriptor Address */
262 volatile __u32 word4;
263 };
264
265 /* This structure is in a DMA region where it can accessed by both
266 * the CPU and the DBRI
267 */
268 struct dbri_dma {
269 s32 cmd[DBRI_NO_CMDS]; /* Place for commands */
270 volatile s32 intr[DBRI_INT_BLK]; /* Interrupt field */
271 struct dbri_mem desc[DBRI_NO_DESCS]; /* Xmit/receive descriptors */
272 };
273
274 #define dbri_dma_off(member, elem) \
275 ((u32)(unsigned long) \
276 (&(((struct dbri_dma *)0)->member[elem])))
277
278 enum in_or_out { PIPEinput, PIPEoutput };
279
280 struct dbri_pipe {
281 u32 sdp; /* SDP command word */
282 int nextpipe; /* Next pipe in linked list */
283 int length; /* Length of timeslot (bits) */
284 int first_desc; /* Index of first descriptor */
285 int desc; /* Index of active descriptor */
286 volatile __u32 *recv_fixed_ptr; /* Ptr to receive fixed data */
287 };
288
289 /* Per stream (playback or record) information */
290 struct dbri_streaminfo {
291 struct snd_pcm_substream *substream;
292 u32 dvma_buffer; /* Device view of ALSA DMA buffer */
293 int size; /* Size of DMA buffer */
294 size_t offset; /* offset in user buffer */
295 int pipe; /* Data pipe used */
296 int left_gain; /* mixer elements */
297 int right_gain;
298 };
299
300 /* This structure holds the information for both chips (DBRI & CS4215) */
301 struct snd_dbri {
302 int regs_size, irq; /* Needed for unload */
303 struct platform_device *op; /* OF device info */
304 spinlock_t lock;
305
306 struct dbri_dma *dma; /* Pointer to our DMA block */
307 u32 dma_dvma; /* DBRI visible DMA address */
308
309 void __iomem *regs; /* dbri HW regs */
310 int dbri_irqp; /* intr queue pointer */
311
312 struct dbri_pipe pipes[DBRI_NO_PIPES]; /* DBRI's 32 data pipes */
313 int next_desc[DBRI_NO_DESCS]; /* Index of next desc, or -1 */
314 spinlock_t cmdlock; /* Protects cmd queue accesses */
315 s32 *cmdptr; /* Pointer to the last queued cmd */
316
317 int chi_bpf;
318
319 struct cs4215 mm; /* mmcodec special info */
320 /* per stream (playback/record) info */
321 struct dbri_streaminfo stream_info[DBRI_NO_STREAMS];
322 };
323
324 #define DBRI_MAX_VOLUME 63 /* Output volume */
325 #define DBRI_MAX_GAIN 15 /* Input gain */
326
327 /* DBRI Reg0 - Status Control Register - defines. (Page 17) */
328 #define D_P (1<<15) /* Program command & queue pointer valid */
329 #define D_G (1<<14) /* Allow 4-Word SBus Burst */
330 #define D_S (1<<13) /* Allow 16-Word SBus Burst */
331 #define D_E (1<<12) /* Allow 8-Word SBus Burst */
332 #define D_X (1<<7) /* Sanity Timer Disable */
333 #define D_T (1<<6) /* Permit activation of the TE interface */
334 #define D_N (1<<5) /* Permit activation of the NT interface */
335 #define D_C (1<<4) /* Permit activation of the CHI interface */
336 #define D_F (1<<3) /* Force Sanity Timer Time-Out */
337 #define D_D (1<<2) /* Disable Master Mode */
338 #define D_H (1<<1) /* Halt for Analysis */
339 #define D_R (1<<0) /* Soft Reset */
340
341 /* DBRI Reg1 - Mode and Interrupt Register - defines. (Page 18) */
342 #define D_LITTLE_END (1<<8) /* Byte Order */
343 #define D_BIG_END (0<<8) /* Byte Order */
344 #define D_MRR (1<<4) /* Multiple Error Ack on SBus (read only) */
345 #define D_MLE (1<<3) /* Multiple Late Error on SBus (read only) */
346 #define D_LBG (1<<2) /* Lost Bus Grant on SBus (read only) */
347 #define D_MBE (1<<1) /* Burst Error on SBus (read only) */
348 #define D_IR (1<<0) /* Interrupt Indicator (read only) */
349
350 /* DBRI Reg2 - Parallel IO Register - defines. (Page 18) */
351 #define D_ENPIO3 (1<<7) /* Enable Pin 3 */
352 #define D_ENPIO2 (1<<6) /* Enable Pin 2 */
353 #define D_ENPIO1 (1<<5) /* Enable Pin 1 */
354 #define D_ENPIO0 (1<<4) /* Enable Pin 0 */
355 #define D_ENPIO (0xf0) /* Enable all the pins */
356 #define D_PIO3 (1<<3) /* Pin 3: 1: Data mode, 0: Ctrl mode */
357 #define D_PIO2 (1<<2) /* Pin 2: 1: Onboard PDN */
358 #define D_PIO1 (1<<1) /* Pin 1: 0: Reset */
359 #define D_PIO0 (1<<0) /* Pin 0: 1: Speakerbox PDN */
360
361 /* DBRI Commands (Page 20) */
362 #define D_WAIT 0x0 /* Stop execution */
363 #define D_PAUSE 0x1 /* Flush long pipes */
364 #define D_JUMP 0x2 /* New command queue */
365 #define D_IIQ 0x3 /* Initialize Interrupt Queue */
366 #define D_REX 0x4 /* Report command execution via interrupt */
367 #define D_SDP 0x5 /* Setup Data Pipe */
368 #define D_CDP 0x6 /* Continue Data Pipe (reread NULL Pointer) */
369 #define D_DTS 0x7 /* Define Time Slot */
370 #define D_SSP 0x8 /* Set short Data Pipe */
371 #define D_CHI 0x9 /* Set CHI Global Mode */
372 #define D_NT 0xa /* NT Command */
373 #define D_TE 0xb /* TE Command */
374 #define D_CDEC 0xc /* Codec setup */
375 #define D_TEST 0xd /* No comment */
376 #define D_CDM 0xe /* CHI Data mode command */
377
378 /* Special bits for some commands */
379 #define D_PIPE(v) ((v)<<0) /* Pipe No.: 0-15 long, 16-21 short */
380
381 /* Setup Data Pipe */
382 /* IRM */
383 #define D_SDP_2SAME (1<<18) /* Report 2nd time in a row value received */
384 #define D_SDP_CHANGE (2<<18) /* Report any changes */
385 #define D_SDP_EVERY (3<<18) /* Report any changes */
386 #define D_SDP_EOL (1<<17) /* EOL interrupt enable */
387 #define D_SDP_IDLE (1<<16) /* HDLC idle interrupt enable */
388
389 /* Pipe data MODE */
390 #define D_SDP_MEM (0<<13) /* To/from memory */
391 #define D_SDP_HDLC (2<<13)
392 #define D_SDP_HDLC_D (3<<13) /* D Channel (prio control) */
393 #define D_SDP_SER (4<<13) /* Serial to serial */
394 #define D_SDP_FIXED (6<<13) /* Short only */
395 #define D_SDP_MODE(v) ((v)&(7<<13))
396
397 #define D_SDP_TO_SER (1<<12) /* Direction */
398 #define D_SDP_FROM_SER (0<<12) /* Direction */
399 #define D_SDP_MSB (1<<11) /* Bit order within Byte */
400 #define D_SDP_LSB (0<<11) /* Bit order within Byte */
401 #define D_SDP_P (1<<10) /* Pointer Valid */
402 #define D_SDP_A (1<<8) /* Abort */
403 #define D_SDP_C (1<<7) /* Clear */
404
405 /* Define Time Slot */
406 #define D_DTS_VI (1<<17) /* Valid Input Time-Slot Descriptor */
407 #define D_DTS_VO (1<<16) /* Valid Output Time-Slot Descriptor */
408 #define D_DTS_INS (1<<15) /* Insert Time Slot */
409 #define D_DTS_DEL (0<<15) /* Delete Time Slot */
410 #define D_DTS_PRVIN(v) ((v)<<10) /* Previous In Pipe */
411 #define D_DTS_PRVOUT(v) ((v)<<5) /* Previous Out Pipe */
412
413 /* Time Slot defines */
414 #define D_TS_LEN(v) ((v)<<24) /* Number of bits in this time slot */
415 #define D_TS_CYCLE(v) ((v)<<14) /* Bit Count at start of TS */
416 #define D_TS_DI (1<<13) /* Data Invert */
417 #define D_TS_1CHANNEL (0<<10) /* Single Channel / Normal mode */
418 #define D_TS_MONITOR (2<<10) /* Monitor pipe */
419 #define D_TS_NONCONTIG (3<<10) /* Non contiguous mode */
420 #define D_TS_ANCHOR (7<<10) /* Starting short pipes */
421 #define D_TS_MON(v) ((v)<<5) /* Monitor Pipe */
422 #define D_TS_NEXT(v) ((v)<<0) /* Pipe no.: 0-15 long, 16-21 short */
423
424 /* Concentration Highway Interface Modes */
425 #define D_CHI_CHICM(v) ((v)<<16) /* Clock mode */
426 #define D_CHI_IR (1<<15) /* Immediate Interrupt Report */
427 #define D_CHI_EN (1<<14) /* CHIL Interrupt enabled */
428 #define D_CHI_OD (1<<13) /* Open Drain Enable */
429 #define D_CHI_FE (1<<12) /* Sample CHIFS on Rising Frame Edge */
430 #define D_CHI_FD (1<<11) /* Frame Drive */
431 #define D_CHI_BPF(v) ((v)<<0) /* Bits per Frame */
432
433 /* NT: These are here for completeness */
434 #define D_NT_FBIT (1<<17) /* Frame Bit */
435 #define D_NT_NBF (1<<16) /* Number of bad frames to loose framing */
436 #define D_NT_IRM_IMM (1<<15) /* Interrupt Report & Mask: Immediate */
437 #define D_NT_IRM_EN (1<<14) /* Interrupt Report & Mask: Enable */
438 #define D_NT_ISNT (1<<13) /* Configure interface as NT */
439 #define D_NT_FT (1<<12) /* Fixed Timing */
440 #define D_NT_EZ (1<<11) /* Echo Channel is Zeros */
441 #define D_NT_IFA (1<<10) /* Inhibit Final Activation */
442 #define D_NT_ACT (1<<9) /* Activate Interface */
443 #define D_NT_MFE (1<<8) /* Multiframe Enable */
444 #define D_NT_RLB(v) ((v)<<5) /* Remote Loopback */
445 #define D_NT_LLB(v) ((v)<<2) /* Local Loopback */
446 #define D_NT_FACT (1<<1) /* Force Activation */
447 #define D_NT_ABV (1<<0) /* Activate Bipolar Violation */
448
449 /* Codec Setup */
450 #define D_CDEC_CK(v) ((v)<<24) /* Clock Select */
451 #define D_CDEC_FED(v) ((v)<<12) /* FSCOD Falling Edge Delay */
452 #define D_CDEC_RED(v) ((v)<<0) /* FSCOD Rising Edge Delay */
453
454 /* Test */
455 #define D_TEST_RAM(v) ((v)<<16) /* RAM Pointer */
456 #define D_TEST_SIZE(v) ((v)<<11) /* */
457 #define D_TEST_ROMONOFF 0x5 /* Toggle ROM opcode monitor on/off */
458 #define D_TEST_PROC 0x6 /* Microprocessor test */
459 #define D_TEST_SER 0x7 /* Serial-Controller test */
460 #define D_TEST_RAMREAD 0x8 /* Copy from Ram to system memory */
461 #define D_TEST_RAMWRITE 0x9 /* Copy into Ram from system memory */
462 #define D_TEST_RAMBIST 0xa /* RAM Built-In Self Test */
463 #define D_TEST_MCBIST 0xb /* Microcontroller Built-In Self Test */
464 #define D_TEST_DUMP 0xe /* ROM Dump */
465
466 /* CHI Data Mode */
467 #define D_CDM_THI (1 << 8) /* Transmit Data on CHIDR Pin */
468 #define D_CDM_RHI (1 << 7) /* Receive Data on CHIDX Pin */
469 #define D_CDM_RCE (1 << 6) /* Receive on Rising Edge of CHICK */
470 #define D_CDM_XCE (1 << 2) /* Transmit Data on Rising Edge of CHICK */
471 #define D_CDM_XEN (1 << 1) /* Transmit Highway Enable */
472 #define D_CDM_REN (1 << 0) /* Receive Highway Enable */
473
474 /* The Interrupts */
475 #define D_INTR_BRDY 1 /* Buffer Ready for processing */
476 #define D_INTR_MINT 2 /* Marked Interrupt in RD/TD */
477 #define D_INTR_IBEG 3 /* Flag to idle transition detected (HDLC) */
478 #define D_INTR_IEND 4 /* Idle to flag transition detected (HDLC) */
479 #define D_INTR_EOL 5 /* End of List */
480 #define D_INTR_CMDI 6 /* Command has bean read */
481 #define D_INTR_XCMP 8 /* Transmission of frame complete */
482 #define D_INTR_SBRI 9 /* BRI status change info */
483 #define D_INTR_FXDT 10 /* Fixed data change */
484 #define D_INTR_CHIL 11 /* CHI lost frame sync (channel 36 only) */
485 #define D_INTR_COLL 11 /* Unrecoverable D-Channel collision */
486 #define D_INTR_DBYT 12 /* Dropped by frame slip */
487 #define D_INTR_RBYT 13 /* Repeated by frame slip */
488 #define D_INTR_LINT 14 /* Lost Interrupt */
489 #define D_INTR_UNDR 15 /* DMA underrun */
490
491 #define D_INTR_TE 32
492 #define D_INTR_NT 34
493 #define D_INTR_CHI 36
494 #define D_INTR_CMD 38
495
496 #define D_INTR_GETCHAN(v) (((v) >> 24) & 0x3f)
497 #define D_INTR_GETCODE(v) (((v) >> 20) & 0xf)
498 #define D_INTR_GETCMD(v) (((v) >> 16) & 0xf)
499 #define D_INTR_GETVAL(v) ((v) & 0xffff)
500 #define D_INTR_GETRVAL(v) ((v) & 0xfffff)
501
502 #define D_P_0 0 /* TE receive anchor */
503 #define D_P_1 1 /* TE transmit anchor */
504 #define D_P_2 2 /* NT transmit anchor */
505 #define D_P_3 3 /* NT receive anchor */
506 #define D_P_4 4 /* CHI send data */
507 #define D_P_5 5 /* CHI receive data */
508 #define D_P_6 6 /* */
509 #define D_P_7 7 /* */
510 #define D_P_8 8 /* */
511 #define D_P_9 9 /* */
512 #define D_P_10 10 /* */
513 #define D_P_11 11 /* */
514 #define D_P_12 12 /* */
515 #define D_P_13 13 /* */
516 #define D_P_14 14 /* */
517 #define D_P_15 15 /* */
518 #define D_P_16 16 /* CHI anchor pipe */
519 #define D_P_17 17 /* CHI send */
520 #define D_P_18 18 /* CHI receive */
521 #define D_P_19 19 /* CHI receive */
522 #define D_P_20 20 /* CHI receive */
523 #define D_P_21 21 /* */
524 #define D_P_22 22 /* */
525 #define D_P_23 23 /* */
526 #define D_P_24 24 /* */
527 #define D_P_25 25 /* */
528 #define D_P_26 26 /* */
529 #define D_P_27 27 /* */
530 #define D_P_28 28 /* */
531 #define D_P_29 29 /* */
532 #define D_P_30 30 /* */
533 #define D_P_31 31 /* */
534
535 /* Transmit descriptor defines */
536 #define DBRI_TD_F (1 << 31) /* End of Frame */
537 #define DBRI_TD_D (1 << 30) /* Do not append CRC */
538 #define DBRI_TD_CNT(v) ((v) << 16) /* Number of valid bytes in the buffer */
539 #define DBRI_TD_B (1 << 15) /* Final interrupt */
540 #define DBRI_TD_M (1 << 14) /* Marker interrupt */
541 #define DBRI_TD_I (1 << 13) /* Transmit Idle Characters */
542 #define DBRI_TD_FCNT(v) (v) /* Flag Count */
543 #define DBRI_TD_UNR (1 << 3) /* Underrun: transmitter is out of data */
544 #define DBRI_TD_ABT (1 << 2) /* Abort: frame aborted */
545 #define DBRI_TD_TBC (1 << 0) /* Transmit buffer Complete */
546 #define DBRI_TD_STATUS(v) ((v) & 0xff) /* Transmit status */
547 /* Maximum buffer size per TD: almost 8KB */
548 #define DBRI_TD_MAXCNT ((1 << 13) - 4)
549
550 /* Receive descriptor defines */
551 #define DBRI_RD_F (1 << 31) /* End of Frame */
552 #define DBRI_RD_C (1 << 30) /* Completed buffer */
553 #define DBRI_RD_B (1 << 15) /* Final interrupt */
554 #define DBRI_RD_M (1 << 14) /* Marker interrupt */
555 #define DBRI_RD_BCNT(v) (v) /* Buffer size */
556 #define DBRI_RD_CRC (1 << 7) /* 0: CRC is correct */
557 #define DBRI_RD_BBC (1 << 6) /* 1: Bad Byte received */
558 #define DBRI_RD_ABT (1 << 5) /* Abort: frame aborted */
559 #define DBRI_RD_OVRN (1 << 3) /* Overrun: data lost */
560 #define DBRI_RD_STATUS(v) ((v) & 0xff) /* Receive status */
561 #define DBRI_RD_CNT(v) (((v) >> 16) & 0x1fff) /* Valid bytes in the buffer */
562
563 /* stream_info[] access */
564 /* Translate the ALSA direction into the array index */
565 #define DBRI_STREAMNO(substream) \
566 (substream->stream == \
567 SNDRV_PCM_STREAM_PLAYBACK ? DBRI_PLAY: DBRI_REC)
568
569 /* Return a pointer to dbri_streaminfo */
570 #define DBRI_STREAM(dbri, substream) \
571 &dbri->stream_info[DBRI_STREAMNO(substream)]
572
573 /*
574 * Short data pipes transmit LSB first. The CS4215 receives MSB first. Grrr.
575 * So we have to reverse the bits. Note: not all bit lengths are supported
576 */
577 static __u32 reverse_bytes(__u32 b, int len)
578 {
579 switch (len) {
580 case 32:
581 b = ((b & 0xffff0000) >> 16) | ((b & 0x0000ffff) << 16);
582 case 16:
583 b = ((b & 0xff00ff00) >> 8) | ((b & 0x00ff00ff) << 8);
584 case 8:
585 b = ((b & 0xf0f0f0f0) >> 4) | ((b & 0x0f0f0f0f) << 4);
586 case 4:
587 b = ((b & 0xcccccccc) >> 2) | ((b & 0x33333333) << 2);
588 case 2:
589 b = ((b & 0xaaaaaaaa) >> 1) | ((b & 0x55555555) << 1);
590 case 1:
591 case 0:
592 break;
593 default:
594 printk(KERN_ERR "DBRI reverse_bytes: unsupported length\n");
595 };
596
597 return b;
598 }
599
600 /*
601 ****************************************************************************
602 ************** DBRI initialization and command synchronization *************
603 ****************************************************************************
604
605 Commands are sent to the DBRI by building a list of them in memory,
606 then writing the address of the first list item to DBRI register 8.
607 The list is terminated with a WAIT command, which generates a
608 CPU interrupt to signal completion.
609
610 Since the DBRI can run in parallel with the CPU, several means of
611 synchronization present themselves. The method implemented here uses
612 the dbri_cmdwait() to wait for execution of batch of sent commands.
613
614 A circular command buffer is used here. A new command is being added
615 while another can be executed. The scheme works by adding two WAIT commands
616 after each sent batch of commands. When the next batch is prepared it is
617 added after the WAIT commands then the WAITs are replaced with single JUMP
618 command to the new batch. The the DBRI is forced to reread the last WAIT
619 command (replaced by the JUMP by then). If the DBRI is still executing
620 previous commands the request to reread the WAIT command is ignored.
621
622 Every time a routine wants to write commands to the DBRI, it must
623 first call dbri_cmdlock() and get pointer to a free space in
624 dbri->dma->cmd buffer. After this, the commands can be written to
625 the buffer, and dbri_cmdsend() is called with the final pointer value
626 to send them to the DBRI.
627
628 */
629
630 #define MAXLOOPS 20
631 /*
632 * Wait for the current command string to execute
633 */
634 static void dbri_cmdwait(struct snd_dbri *dbri)
635 {
636 int maxloops = MAXLOOPS;
637 unsigned long flags;
638
639 /* Delay if previous commands are still being processed */
640 spin_lock_irqsave(&dbri->lock, flags);
641 while ((--maxloops) > 0 && (sbus_readl(dbri->regs + REG0) & D_P)) {
642 spin_unlock_irqrestore(&dbri->lock, flags);
643 msleep_interruptible(1);
644 spin_lock_irqsave(&dbri->lock, flags);
645 }
646 spin_unlock_irqrestore(&dbri->lock, flags);
647
648 if (maxloops == 0)
649 printk(KERN_ERR "DBRI: Chip never completed command buffer\n");
650 else
651 dprintk(D_CMD, "Chip completed command buffer (%d)\n",
652 MAXLOOPS - maxloops - 1);
653 }
654 /*
655 * Lock the command queue and return pointer to space for len cmd words
656 * It locks the cmdlock spinlock.
657 */
658 static s32 *dbri_cmdlock(struct snd_dbri *dbri, int len)
659 {
660 /* Space for 2 WAIT cmds (replaced later by 1 JUMP cmd) */
661 len += 2;
662 spin_lock(&dbri->cmdlock);
663 if (dbri->cmdptr - dbri->dma->cmd + len < DBRI_NO_CMDS - 2)
664 return dbri->cmdptr + 2;
665 else if (len < sbus_readl(dbri->regs + REG8) - dbri->dma_dvma)
666 return dbri->dma->cmd;
667 else
668 printk(KERN_ERR "DBRI: no space for commands.");
669
670 return NULL;
671 }
672
673 /*
674 * Send prepared cmd string. It works by writing a JUMP cmd into
675 * the last WAIT cmd and force DBRI to reread the cmd.
676 * The JUMP cmd points to the new cmd string.
677 * It also releases the cmdlock spinlock.
678 *
679 * Lock must be held before calling this.
680 */
681 static void dbri_cmdsend(struct snd_dbri *dbri, s32 *cmd, int len)
682 {
683 s32 tmp, addr;
684 static int wait_id = 0;
685
686 wait_id++;
687 wait_id &= 0xffff; /* restrict it to a 16 bit counter. */
688 *(cmd) = DBRI_CMD(D_WAIT, 1, wait_id);
689 *(cmd+1) = DBRI_CMD(D_WAIT, 1, wait_id);
690
691 /* Replace the last command with JUMP */
692 addr = dbri->dma_dvma + (cmd - len - dbri->dma->cmd) * sizeof(s32);
693 *(dbri->cmdptr+1) = addr;
694 *(dbri->cmdptr) = DBRI_CMD(D_JUMP, 0, 0);
695
696 #ifdef DBRI_DEBUG
697 if (cmd > dbri->cmdptr) {
698 s32 *ptr;
699
700 for (ptr = dbri->cmdptr; ptr < cmd+2; ptr++)
701 dprintk(D_CMD, "cmd: %lx:%08x\n",
702 (unsigned long)ptr, *ptr);
703 } else {
704 s32 *ptr = dbri->cmdptr;
705
706 dprintk(D_CMD, "cmd: %lx:%08x\n", (unsigned long)ptr, *ptr);
707 ptr++;
708 dprintk(D_CMD, "cmd: %lx:%08x\n", (unsigned long)ptr, *ptr);
709 for (ptr = dbri->dma->cmd; ptr < cmd+2; ptr++)
710 dprintk(D_CMD, "cmd: %lx:%08x\n",
711 (unsigned long)ptr, *ptr);
712 }
713 #endif
714
715 /* Reread the last command */
716 tmp = sbus_readl(dbri->regs + REG0);
717 tmp |= D_P;
718 sbus_writel(tmp, dbri->regs + REG0);
719
720 dbri->cmdptr = cmd;
721 spin_unlock(&dbri->cmdlock);
722 }
723
724 /* Lock must be held when calling this */
725 static void dbri_reset(struct snd_dbri *dbri)
726 {
727 int i;
728 u32 tmp;
729
730 dprintk(D_GEN, "reset 0:%x 2:%x 8:%x 9:%x\n",
731 sbus_readl(dbri->regs + REG0),
732 sbus_readl(dbri->regs + REG2),
733 sbus_readl(dbri->regs + REG8), sbus_readl(dbri->regs + REG9));
734
735 sbus_writel(D_R, dbri->regs + REG0); /* Soft Reset */
736 for (i = 0; (sbus_readl(dbri->regs + REG0) & D_R) && i < 64; i++)
737 udelay(10);
738
739 /* A brute approach - DBRI falls back to working burst size by itself
740 * On SS20 D_S does not work, so do not try so high. */
741 tmp = sbus_readl(dbri->regs + REG0);
742 tmp |= D_G | D_E;
743 tmp &= ~D_S;
744 sbus_writel(tmp, dbri->regs + REG0);
745 }
746
747 /* Lock must not be held before calling this */
748 static void __devinit dbri_initialize(struct snd_dbri *dbri)
749 {
750 s32 *cmd;
751 u32 dma_addr;
752 unsigned long flags;
753 int n;
754
755 spin_lock_irqsave(&dbri->lock, flags);
756
757 dbri_reset(dbri);
758
759 /* Initialize pipes */
760 for (n = 0; n < DBRI_NO_PIPES; n++)
761 dbri->pipes[n].desc = dbri->pipes[n].first_desc = -1;
762
763 spin_lock_init(&dbri->cmdlock);
764 /*
765 * Initialize the interrupt ring buffer.
766 */
767 dma_addr = dbri->dma_dvma + dbri_dma_off(intr, 0);
768 dbri->dma->intr[0] = dma_addr;
769 dbri->dbri_irqp = 1;
770 /*
771 * Set up the interrupt queue
772 */
773 spin_lock(&dbri->cmdlock);
774 cmd = dbri->cmdptr = dbri->dma->cmd;
775 *(cmd++) = DBRI_CMD(D_IIQ, 0, 0);
776 *(cmd++) = dma_addr;
777 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
778 dbri->cmdptr = cmd;
779 *(cmd++) = DBRI_CMD(D_WAIT, 1, 0);
780 *(cmd++) = DBRI_CMD(D_WAIT, 1, 0);
781 dma_addr = dbri->dma_dvma + dbri_dma_off(cmd, 0);
782 sbus_writel(dma_addr, dbri->regs + REG8);
783 spin_unlock(&dbri->cmdlock);
784
785 spin_unlock_irqrestore(&dbri->lock, flags);
786 dbri_cmdwait(dbri);
787 }
788
789 /*
790 ****************************************************************************
791 ************************** DBRI data pipe management ***********************
792 ****************************************************************************
793
794 While DBRI control functions use the command and interrupt buffers, the
795 main data path takes the form of data pipes, which can be short (command
796 and interrupt driven), or long (attached to DMA buffers). These functions
797 provide a rudimentary means of setting up and managing the DBRI's pipes,
798 but the calling functions have to make sure they respect the pipes' linked
799 list ordering, among other things. The transmit and receive functions
800 here interface closely with the transmit and receive interrupt code.
801
802 */
803 static inline int pipe_active(struct snd_dbri *dbri, int pipe)
804 {
805 return ((pipe >= 0) && (dbri->pipes[pipe].desc != -1));
806 }
807
808 /* reset_pipe(dbri, pipe)
809 *
810 * Called on an in-use pipe to clear anything being transmitted or received
811 * Lock must be held before calling this.
812 */
813 static void reset_pipe(struct snd_dbri *dbri, int pipe)
814 {
815 int sdp;
816 int desc;
817 s32 *cmd;
818
819 if (pipe < 0 || pipe > DBRI_MAX_PIPE) {
820 printk(KERN_ERR "DBRI: reset_pipe called with "
821 "illegal pipe number\n");
822 return;
823 }
824
825 sdp = dbri->pipes[pipe].sdp;
826 if (sdp == 0) {
827 printk(KERN_ERR "DBRI: reset_pipe called "
828 "on uninitialized pipe\n");
829 return;
830 }
831
832 cmd = dbri_cmdlock(dbri, 3);
833 *(cmd++) = DBRI_CMD(D_SDP, 0, sdp | D_SDP_C | D_SDP_P);
834 *(cmd++) = 0;
835 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
836 dbri_cmdsend(dbri, cmd, 3);
837
838 desc = dbri->pipes[pipe].first_desc;
839 if (desc >= 0)
840 do {
841 dbri->dma->desc[desc].ba = 0;
842 dbri->dma->desc[desc].nda = 0;
843 desc = dbri->next_desc[desc];
844 } while (desc != -1 && desc != dbri->pipes[pipe].first_desc);
845
846 dbri->pipes[pipe].desc = -1;
847 dbri->pipes[pipe].first_desc = -1;
848 }
849
850 /*
851 * Lock must be held before calling this.
852 */
853 static void setup_pipe(struct snd_dbri *dbri, int pipe, int sdp)
854 {
855 if (pipe < 0 || pipe > DBRI_MAX_PIPE) {
856 printk(KERN_ERR "DBRI: setup_pipe called "
857 "with illegal pipe number\n");
858 return;
859 }
860
861 if ((sdp & 0xf800) != sdp) {
862 printk(KERN_ERR "DBRI: setup_pipe called "
863 "with strange SDP value\n");
864 /* sdp &= 0xf800; */
865 }
866
867 /* If this is a fixed receive pipe, arrange for an interrupt
868 * every time its data changes
869 */
870 if (D_SDP_MODE(sdp) == D_SDP_FIXED && !(sdp & D_SDP_TO_SER))
871 sdp |= D_SDP_CHANGE;
872
873 sdp |= D_PIPE(pipe);
874 dbri->pipes[pipe].sdp = sdp;
875 dbri->pipes[pipe].desc = -1;
876 dbri->pipes[pipe].first_desc = -1;
877
878 reset_pipe(dbri, pipe);
879 }
880
881 /*
882 * Lock must be held before calling this.
883 */
884 static void link_time_slot(struct snd_dbri *dbri, int pipe,
885 int prevpipe, int nextpipe,
886 int length, int cycle)
887 {
888 s32 *cmd;
889 int val;
890
891 if (pipe < 0 || pipe > DBRI_MAX_PIPE
892 || prevpipe < 0 || prevpipe > DBRI_MAX_PIPE
893 || nextpipe < 0 || nextpipe > DBRI_MAX_PIPE) {
894 printk(KERN_ERR
895 "DBRI: link_time_slot called with illegal pipe number\n");
896 return;
897 }
898
899 if (dbri->pipes[pipe].sdp == 0
900 || dbri->pipes[prevpipe].sdp == 0
901 || dbri->pipes[nextpipe].sdp == 0) {
902 printk(KERN_ERR "DBRI: link_time_slot called "
903 "on uninitialized pipe\n");
904 return;
905 }
906
907 dbri->pipes[prevpipe].nextpipe = pipe;
908 dbri->pipes[pipe].nextpipe = nextpipe;
909 dbri->pipes[pipe].length = length;
910
911 cmd = dbri_cmdlock(dbri, 4);
912
913 if (dbri->pipes[pipe].sdp & D_SDP_TO_SER) {
914 /* Deal with CHI special case:
915 * "If transmission on edges 0 or 1 is desired, then cycle n
916 * (where n = # of bit times per frame...) must be used."
917 * - DBRI data sheet, page 11
918 */
919 if (prevpipe == 16 && cycle == 0)
920 cycle = dbri->chi_bpf;
921
922 val = D_DTS_VO | D_DTS_INS | D_DTS_PRVOUT(prevpipe) | pipe;
923 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
924 *(cmd++) = 0;
925 *(cmd++) =
926 D_TS_LEN(length) | D_TS_CYCLE(cycle) | D_TS_NEXT(nextpipe);
927 } else {
928 val = D_DTS_VI | D_DTS_INS | D_DTS_PRVIN(prevpipe) | pipe;
929 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
930 *(cmd++) =
931 D_TS_LEN(length) | D_TS_CYCLE(cycle) | D_TS_NEXT(nextpipe);
932 *(cmd++) = 0;
933 }
934 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
935
936 dbri_cmdsend(dbri, cmd, 4);
937 }
938
939 #if 0
940 /*
941 * Lock must be held before calling this.
942 */
943 static void unlink_time_slot(struct snd_dbri *dbri, int pipe,
944 enum in_or_out direction, int prevpipe,
945 int nextpipe)
946 {
947 s32 *cmd;
948 int val;
949
950 if (pipe < 0 || pipe > DBRI_MAX_PIPE
951 || prevpipe < 0 || prevpipe > DBRI_MAX_PIPE
952 || nextpipe < 0 || nextpipe > DBRI_MAX_PIPE) {
953 printk(KERN_ERR
954 "DBRI: unlink_time_slot called with illegal pipe number\n");
955 return;
956 }
957
958 cmd = dbri_cmdlock(dbri, 4);
959
960 if (direction == PIPEinput) {
961 val = D_DTS_VI | D_DTS_DEL | D_DTS_PRVIN(prevpipe) | pipe;
962 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
963 *(cmd++) = D_TS_NEXT(nextpipe);
964 *(cmd++) = 0;
965 } else {
966 val = D_DTS_VO | D_DTS_DEL | D_DTS_PRVOUT(prevpipe) | pipe;
967 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
968 *(cmd++) = 0;
969 *(cmd++) = D_TS_NEXT(nextpipe);
970 }
971 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
972
973 dbri_cmdsend(dbri, cmd, 4);
974 }
975 #endif
976
977 /* xmit_fixed() / recv_fixed()
978 *
979 * Transmit/receive data on a "fixed" pipe - i.e, one whose contents are not
980 * expected to change much, and which we don't need to buffer.
981 * The DBRI only interrupts us when the data changes (receive pipes),
982 * or only changes the data when this function is called (transmit pipes).
983 * Only short pipes (numbers 16-31) can be used in fixed data mode.
984 *
985 * These function operate on a 32-bit field, no matter how large
986 * the actual time slot is. The interrupt handler takes care of bit
987 * ordering and alignment. An 8-bit time slot will always end up
988 * in the low-order 8 bits, filled either MSB-first or LSB-first,
989 * depending on the settings passed to setup_pipe().
990 *
991 * Lock must not be held before calling it.
992 */
993 static void xmit_fixed(struct snd_dbri *dbri, int pipe, unsigned int data)
994 {
995 s32 *cmd;
996 unsigned long flags;
997
998 if (pipe < 16 || pipe > DBRI_MAX_PIPE) {
999 printk(KERN_ERR "DBRI: xmit_fixed: Illegal pipe number\n");
1000 return;
1001 }
1002
1003 if (D_SDP_MODE(dbri->pipes[pipe].sdp) == 0) {
1004 printk(KERN_ERR "DBRI: xmit_fixed: "
1005 "Uninitialized pipe %d\n", pipe);
1006 return;
1007 }
1008
1009 if (D_SDP_MODE(dbri->pipes[pipe].sdp) != D_SDP_FIXED) {
1010 printk(KERN_ERR "DBRI: xmit_fixed: Non-fixed pipe %d\n", pipe);
1011 return;
1012 }
1013
1014 if (!(dbri->pipes[pipe].sdp & D_SDP_TO_SER)) {
1015 printk(KERN_ERR "DBRI: xmit_fixed: Called on receive pipe %d\n",
1016 pipe);
1017 return;
1018 }
1019
1020 /* DBRI short pipes always transmit LSB first */
1021
1022 if (dbri->pipes[pipe].sdp & D_SDP_MSB)
1023 data = reverse_bytes(data, dbri->pipes[pipe].length);
1024
1025 cmd = dbri_cmdlock(dbri, 3);
1026
1027 *(cmd++) = DBRI_CMD(D_SSP, 0, pipe);
1028 *(cmd++) = data;
1029 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
1030
1031 spin_lock_irqsave(&dbri->lock, flags);
1032 dbri_cmdsend(dbri, cmd, 3);
1033 spin_unlock_irqrestore(&dbri->lock, flags);
1034 dbri_cmdwait(dbri);
1035
1036 }
1037
1038 static void recv_fixed(struct snd_dbri *dbri, int pipe, volatile __u32 *ptr)
1039 {
1040 if (pipe < 16 || pipe > DBRI_MAX_PIPE) {
1041 printk(KERN_ERR "DBRI: recv_fixed called with "
1042 "illegal pipe number\n");
1043 return;
1044 }
1045
1046 if (D_SDP_MODE(dbri->pipes[pipe].sdp) != D_SDP_FIXED) {
1047 printk(KERN_ERR "DBRI: recv_fixed called on "
1048 "non-fixed pipe %d\n", pipe);
1049 return;
1050 }
1051
1052 if (dbri->pipes[pipe].sdp & D_SDP_TO_SER) {
1053 printk(KERN_ERR "DBRI: recv_fixed called on "
1054 "transmit pipe %d\n", pipe);
1055 return;
1056 }
1057
1058 dbri->pipes[pipe].recv_fixed_ptr = ptr;
1059 }
1060
1061 /* setup_descs()
1062 *
1063 * Setup transmit/receive data on a "long" pipe - i.e, one associated
1064 * with a DMA buffer.
1065 *
1066 * Only pipe numbers 0-15 can be used in this mode.
1067 *
1068 * This function takes a stream number pointing to a data buffer,
1069 * and work by building chains of descriptors which identify the
1070 * data buffers. Buffers too large for a single descriptor will
1071 * be spread across multiple descriptors.
1072 *
1073 * All descriptors create a ring buffer.
1074 *
1075 * Lock must be held before calling this.
1076 */
1077 static int setup_descs(struct snd_dbri *dbri, int streamno, unsigned int period)
1078 {
1079 struct dbri_streaminfo *info = &dbri->stream_info[streamno];
1080 __u32 dvma_buffer;
1081 int desc;
1082 int len;
1083 int first_desc = -1;
1084 int last_desc = -1;
1085
1086 if (info->pipe < 0 || info->pipe > 15) {
1087 printk(KERN_ERR "DBRI: setup_descs: Illegal pipe number\n");
1088 return -2;
1089 }
1090
1091 if (dbri->pipes[info->pipe].sdp == 0) {
1092 printk(KERN_ERR "DBRI: setup_descs: Uninitialized pipe %d\n",
1093 info->pipe);
1094 return -2;
1095 }
1096
1097 dvma_buffer = info->dvma_buffer;
1098 len = info->size;
1099
1100 if (streamno == DBRI_PLAY) {
1101 if (!(dbri->pipes[info->pipe].sdp & D_SDP_TO_SER)) {
1102 printk(KERN_ERR "DBRI: setup_descs: "
1103 "Called on receive pipe %d\n", info->pipe);
1104 return -2;
1105 }
1106 } else {
1107 if (dbri->pipes[info->pipe].sdp & D_SDP_TO_SER) {
1108 printk(KERN_ERR
1109 "DBRI: setup_descs: Called on transmit pipe %d\n",
1110 info->pipe);
1111 return -2;
1112 }
1113 /* Should be able to queue multiple buffers
1114 * to receive on a pipe
1115 */
1116 if (pipe_active(dbri, info->pipe)) {
1117 printk(KERN_ERR "DBRI: recv_on_pipe: "
1118 "Called on active pipe %d\n", info->pipe);
1119 return -2;
1120 }
1121
1122 /* Make sure buffer size is multiple of four */
1123 len &= ~3;
1124 }
1125
1126 /* Free descriptors if pipe has any */
1127 desc = dbri->pipes[info->pipe].first_desc;
1128 if (desc >= 0)
1129 do {
1130 dbri->dma->desc[desc].ba = 0;
1131 dbri->dma->desc[desc].nda = 0;
1132 desc = dbri->next_desc[desc];
1133 } while (desc != -1 &&
1134 desc != dbri->pipes[info->pipe].first_desc);
1135
1136 dbri->pipes[info->pipe].desc = -1;
1137 dbri->pipes[info->pipe].first_desc = -1;
1138
1139 desc = 0;
1140 while (len > 0) {
1141 int mylen;
1142
1143 for (; desc < DBRI_NO_DESCS; desc++) {
1144 if (!dbri->dma->desc[desc].ba)
1145 break;
1146 }
1147
1148 if (desc == DBRI_NO_DESCS) {
1149 printk(KERN_ERR "DBRI: setup_descs: No descriptors\n");
1150 return -1;
1151 }
1152
1153 if (len > DBRI_TD_MAXCNT)
1154 mylen = DBRI_TD_MAXCNT; /* 8KB - 4 */
1155 else
1156 mylen = len;
1157
1158 if (mylen > period)
1159 mylen = period;
1160
1161 dbri->next_desc[desc] = -1;
1162 dbri->dma->desc[desc].ba = dvma_buffer;
1163 dbri->dma->desc[desc].nda = 0;
1164
1165 if (streamno == DBRI_PLAY) {
1166 dbri->dma->desc[desc].word1 = DBRI_TD_CNT(mylen);
1167 dbri->dma->desc[desc].word4 = 0;
1168 dbri->dma->desc[desc].word1 |= DBRI_TD_F | DBRI_TD_B;
1169 } else {
1170 dbri->dma->desc[desc].word1 = 0;
1171 dbri->dma->desc[desc].word4 =
1172 DBRI_RD_B | DBRI_RD_BCNT(mylen);
1173 }
1174
1175 if (first_desc == -1)
1176 first_desc = desc;
1177 else {
1178 dbri->next_desc[last_desc] = desc;
1179 dbri->dma->desc[last_desc].nda =
1180 dbri->dma_dvma + dbri_dma_off(desc, desc);
1181 }
1182
1183 last_desc = desc;
1184 dvma_buffer += mylen;
1185 len -= mylen;
1186 }
1187
1188 if (first_desc == -1 || last_desc == -1) {
1189 printk(KERN_ERR "DBRI: setup_descs: "
1190 " Not enough descriptors available\n");
1191 return -1;
1192 }
1193
1194 dbri->dma->desc[last_desc].nda =
1195 dbri->dma_dvma + dbri_dma_off(desc, first_desc);
1196 dbri->next_desc[last_desc] = first_desc;
1197 dbri->pipes[info->pipe].first_desc = first_desc;
1198 dbri->pipes[info->pipe].desc = first_desc;
1199
1200 #ifdef DBRI_DEBUG
1201 for (desc = first_desc; desc != -1;) {
1202 dprintk(D_DESC, "DESC %d: %08x %08x %08x %08x\n",
1203 desc,
1204 dbri->dma->desc[desc].word1,
1205 dbri->dma->desc[desc].ba,
1206 dbri->dma->desc[desc].nda, dbri->dma->desc[desc].word4);
1207 desc = dbri->next_desc[desc];
1208 if (desc == first_desc)
1209 break;
1210 }
1211 #endif
1212 return 0;
1213 }
1214
1215 /*
1216 ****************************************************************************
1217 ************************** DBRI - CHI interface ****************************
1218 ****************************************************************************
1219
1220 The CHI is a four-wire (clock, frame sync, data in, data out) time-division
1221 multiplexed serial interface which the DBRI can operate in either master
1222 (give clock/frame sync) or slave (take clock/frame sync) mode.
1223
1224 */
1225
1226 enum master_or_slave { CHImaster, CHIslave };
1227
1228 /*
1229 * Lock must not be held before calling it.
1230 */
1231 static void reset_chi(struct snd_dbri *dbri,
1232 enum master_or_slave master_or_slave,
1233 int bits_per_frame)
1234 {
1235 s32 *cmd;
1236 int val;
1237
1238 /* Set CHI Anchor: Pipe 16 */
1239
1240 cmd = dbri_cmdlock(dbri, 4);
1241 val = D_DTS_VO | D_DTS_VI | D_DTS_INS
1242 | D_DTS_PRVIN(16) | D_PIPE(16) | D_DTS_PRVOUT(16);
1243 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
1244 *(cmd++) = D_TS_ANCHOR | D_TS_NEXT(16);
1245 *(cmd++) = D_TS_ANCHOR | D_TS_NEXT(16);
1246 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
1247 dbri_cmdsend(dbri, cmd, 4);
1248
1249 dbri->pipes[16].sdp = 1;
1250 dbri->pipes[16].nextpipe = 16;
1251
1252 cmd = dbri_cmdlock(dbri, 4);
1253
1254 if (master_or_slave == CHIslave) {
1255 /* Setup DBRI for CHI Slave - receive clock, frame sync (FS)
1256 *
1257 * CHICM = 0 (slave mode, 8 kHz frame rate)
1258 * IR = give immediate CHI status interrupt
1259 * EN = give CHI status interrupt upon change
1260 */
1261 *(cmd++) = DBRI_CMD(D_CHI, 0, D_CHI_CHICM(0));
1262 } else {
1263 /* Setup DBRI for CHI Master - generate clock, FS
1264 *
1265 * BPF = bits per 8 kHz frame
1266 * 12.288 MHz / CHICM_divisor = clock rate
1267 * FD = 1 - drive CHIFS on rising edge of CHICK
1268 */
1269 int clockrate = bits_per_frame * 8;
1270 int divisor = 12288 / clockrate;
1271
1272 if (divisor > 255 || divisor * clockrate != 12288)
1273 printk(KERN_ERR "DBRI: illegal bits_per_frame "
1274 "in setup_chi\n");
1275
1276 *(cmd++) = DBRI_CMD(D_CHI, 0, D_CHI_CHICM(divisor) | D_CHI_FD
1277 | D_CHI_BPF(bits_per_frame));
1278 }
1279
1280 dbri->chi_bpf = bits_per_frame;
1281
1282 /* CHI Data Mode
1283 *
1284 * RCE = 0 - receive on falling edge of CHICK
1285 * XCE = 1 - transmit on rising edge of CHICK
1286 * XEN = 1 - enable transmitter
1287 * REN = 1 - enable receiver
1288 */
1289
1290 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
1291 *(cmd++) = DBRI_CMD(D_CDM, 0, D_CDM_XCE | D_CDM_XEN | D_CDM_REN);
1292 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
1293
1294 dbri_cmdsend(dbri, cmd, 4);
1295 }
1296
1297 /*
1298 ****************************************************************************
1299 *********************** CS4215 audio codec management **********************
1300 ****************************************************************************
1301
1302 In the standard SPARC audio configuration, the CS4215 codec is attached
1303 to the DBRI via the CHI interface and few of the DBRI's PIO pins.
1304
1305 * Lock must not be held before calling it.
1306
1307 */
1308 static __devinit void cs4215_setup_pipes(struct snd_dbri *dbri)
1309 {
1310 unsigned long flags;
1311
1312 spin_lock_irqsave(&dbri->lock, flags);
1313 /*
1314 * Data mode:
1315 * Pipe 4: Send timeslots 1-4 (audio data)
1316 * Pipe 20: Send timeslots 5-8 (part of ctrl data)
1317 * Pipe 6: Receive timeslots 1-4 (audio data)
1318 * Pipe 21: Receive timeslots 6-7. We can only receive 20 bits via
1319 * interrupt, and the rest of the data (slot 5 and 8) is
1320 * not relevant for us (only for doublechecking).
1321 *
1322 * Control mode:
1323 * Pipe 17: Send timeslots 1-4 (slots 5-8 are read only)
1324 * Pipe 18: Receive timeslot 1 (clb).
1325 * Pipe 19: Receive timeslot 7 (version).
1326 */
1327
1328 setup_pipe(dbri, 4, D_SDP_MEM | D_SDP_TO_SER | D_SDP_MSB);
1329 setup_pipe(dbri, 20, D_SDP_FIXED | D_SDP_TO_SER | D_SDP_MSB);
1330 setup_pipe(dbri, 6, D_SDP_MEM | D_SDP_FROM_SER | D_SDP_MSB);
1331 setup_pipe(dbri, 21, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
1332
1333 setup_pipe(dbri, 17, D_SDP_FIXED | D_SDP_TO_SER | D_SDP_MSB);
1334 setup_pipe(dbri, 18, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
1335 setup_pipe(dbri, 19, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
1336 spin_unlock_irqrestore(&dbri->lock, flags);
1337
1338 dbri_cmdwait(dbri);
1339 }
1340
1341 static __devinit int cs4215_init_data(struct cs4215 *mm)
1342 {
1343 /*
1344 * No action, memory resetting only.
1345 *
1346 * Data Time Slot 5-8
1347 * Speaker,Line and Headphone enable. Gain set to the half.
1348 * Input is mike.
1349 */
1350 mm->data[0] = CS4215_LO(0x20) | CS4215_HE | CS4215_LE;
1351 mm->data[1] = CS4215_RO(0x20) | CS4215_SE;
1352 mm->data[2] = CS4215_LG(0x8) | CS4215_IS | CS4215_PIO0 | CS4215_PIO1;
1353 mm->data[3] = CS4215_RG(0x8) | CS4215_MA(0xf);
1354
1355 /*
1356 * Control Time Slot 1-4
1357 * 0: Default I/O voltage scale
1358 * 1: 8 bit ulaw, 8kHz, mono, high pass filter disabled
1359 * 2: Serial enable, CHI master, 128 bits per frame, clock 1
1360 * 3: Tests disabled
1361 */
1362 mm->ctrl[0] = CS4215_RSRVD_1 | CS4215_MLB;
1363 mm->ctrl[1] = CS4215_DFR_ULAW | CS4215_FREQ[0].csval;
1364 mm->ctrl[2] = CS4215_XCLK | CS4215_BSEL_128 | CS4215_FREQ[0].xtal;
1365 mm->ctrl[3] = 0;
1366
1367 mm->status = 0;
1368 mm->version = 0xff;
1369 mm->precision = 8; /* For ULAW */
1370 mm->channels = 1;
1371
1372 return 0;
1373 }
1374
1375 static void cs4215_setdata(struct snd_dbri *dbri, int muted)
1376 {
1377 if (muted) {
1378 dbri->mm.data[0] |= 63;
1379 dbri->mm.data[1] |= 63;
1380 dbri->mm.data[2] &= ~15;
1381 dbri->mm.data[3] &= ~15;
1382 } else {
1383 /* Start by setting the playback attenuation. */
1384 struct dbri_streaminfo *info = &dbri->stream_info[DBRI_PLAY];
1385 int left_gain = info->left_gain & 0x3f;
1386 int right_gain = info->right_gain & 0x3f;
1387
1388 dbri->mm.data[0] &= ~0x3f; /* Reset the volume bits */
1389 dbri->mm.data[1] &= ~0x3f;
1390 dbri->mm.data[0] |= (DBRI_MAX_VOLUME - left_gain);
1391 dbri->mm.data[1] |= (DBRI_MAX_VOLUME - right_gain);
1392
1393 /* Now set the recording gain. */
1394 info = &dbri->stream_info[DBRI_REC];
1395 left_gain = info->left_gain & 0xf;
1396 right_gain = info->right_gain & 0xf;
1397 dbri->mm.data[2] |= CS4215_LG(left_gain);
1398 dbri->mm.data[3] |= CS4215_RG(right_gain);
1399 }
1400
1401 xmit_fixed(dbri, 20, *(int *)dbri->mm.data);
1402 }
1403
1404 /*
1405 * Set the CS4215 to data mode.
1406 */
1407 static void cs4215_open(struct snd_dbri *dbri)
1408 {
1409 int data_width;
1410 u32 tmp;
1411 unsigned long flags;
1412
1413 dprintk(D_MM, "cs4215_open: %d channels, %d bits\n",
1414 dbri->mm.channels, dbri->mm.precision);
1415
1416 /* Temporarily mute outputs, and wait 1/8000 sec (125 us)
1417 * to make sure this takes. This avoids clicking noises.
1418 */
1419
1420 cs4215_setdata(dbri, 1);
1421 udelay(125);
1422
1423 /*
1424 * Data mode:
1425 * Pipe 4: Send timeslots 1-4 (audio data)
1426 * Pipe 20: Send timeslots 5-8 (part of ctrl data)
1427 * Pipe 6: Receive timeslots 1-4 (audio data)
1428 * Pipe 21: Receive timeslots 6-7. We can only receive 20 bits via
1429 * interrupt, and the rest of the data (slot 5 and 8) is
1430 * not relevant for us (only for doublechecking).
1431 *
1432 * Just like in control mode, the time slots are all offset by eight
1433 * bits. The CS4215, it seems, observes TSIN (the delayed signal)
1434 * even if it's the CHI master. Don't ask me...
1435 */
1436 spin_lock_irqsave(&dbri->lock, flags);
1437 tmp = sbus_readl(dbri->regs + REG0);
1438 tmp &= ~(D_C); /* Disable CHI */
1439 sbus_writel(tmp, dbri->regs + REG0);
1440
1441 /* Switch CS4215 to data mode - set PIO3 to 1 */
1442 sbus_writel(D_ENPIO | D_PIO1 | D_PIO3 |
1443 (dbri->mm.onboard ? D_PIO0 : D_PIO2), dbri->regs + REG2);
1444
1445 reset_chi(dbri, CHIslave, 128);
1446
1447 /* Note: this next doesn't work for 8-bit stereo, because the two
1448 * channels would be on timeslots 1 and 3, with 2 and 4 idle.
1449 * (See CS4215 datasheet Fig 15)
1450 *
1451 * DBRI non-contiguous mode would be required to make this work.
1452 */
1453 data_width = dbri->mm.channels * dbri->mm.precision;
1454
1455 link_time_slot(dbri, 4, 16, 16, data_width, dbri->mm.offset);
1456 link_time_slot(dbri, 20, 4, 16, 32, dbri->mm.offset + 32);
1457 link_time_slot(dbri, 6, 16, 16, data_width, dbri->mm.offset);
1458 link_time_slot(dbri, 21, 6, 16, 16, dbri->mm.offset + 40);
1459
1460 /* FIXME: enable CHI after _setdata? */
1461 tmp = sbus_readl(dbri->regs + REG0);
1462 tmp |= D_C; /* Enable CHI */
1463 sbus_writel(tmp, dbri->regs + REG0);
1464 spin_unlock_irqrestore(&dbri->lock, flags);
1465
1466 cs4215_setdata(dbri, 0);
1467 }
1468
1469 /*
1470 * Send the control information (i.e. audio format)
1471 */
1472 static int cs4215_setctrl(struct snd_dbri *dbri)
1473 {
1474 int i, val;
1475 u32 tmp;
1476 unsigned long flags;
1477
1478 /* FIXME - let the CPU do something useful during these delays */
1479
1480 /* Temporarily mute outputs, and wait 1/8000 sec (125 us)
1481 * to make sure this takes. This avoids clicking noises.
1482 */
1483 cs4215_setdata(dbri, 1);
1484 udelay(125);
1485
1486 /*
1487 * Enable Control mode: Set DBRI's PIO3 (4215's D/~C) to 0, then wait
1488 * 12 cycles <= 12/(5512.5*64) sec = 34.01 usec
1489 */
1490 val = D_ENPIO | D_PIO1 | (dbri->mm.onboard ? D_PIO0 : D_PIO2);
1491 sbus_writel(val, dbri->regs + REG2);
1492 dprintk(D_MM, "cs4215_setctrl: reg2=0x%x\n", val);
1493 udelay(34);
1494
1495 /* In Control mode, the CS4215 is a slave device, so the DBRI must
1496 * operate as CHI master, supplying clocking and frame synchronization.
1497 *
1498 * In Data mode, however, the CS4215 must be CHI master to insure
1499 * that its data stream is synchronous with its codec.
1500 *
1501 * The upshot of all this? We start by putting the DBRI into master
1502 * mode, program the CS4215 in Control mode, then switch the CS4215
1503 * into Data mode and put the DBRI into slave mode. Various timing
1504 * requirements must be observed along the way.
1505 *
1506 * Oh, and one more thing, on a SPARCStation 20 (and maybe
1507 * others?), the addressing of the CS4215's time slots is
1508 * offset by eight bits, so we add eight to all the "cycle"
1509 * values in the Define Time Slot (DTS) commands. This is
1510 * done in hardware by a TI 248 that delays the DBRI->4215
1511 * frame sync signal by eight clock cycles. Anybody know why?
1512 */
1513 spin_lock_irqsave(&dbri->lock, flags);
1514 tmp = sbus_readl(dbri->regs + REG0);
1515 tmp &= ~D_C; /* Disable CHI */
1516 sbus_writel(tmp, dbri->regs + REG0);
1517
1518 reset_chi(dbri, CHImaster, 128);
1519
1520 /*
1521 * Control mode:
1522 * Pipe 17: Send timeslots 1-4 (slots 5-8 are read only)
1523 * Pipe 18: Receive timeslot 1 (clb).
1524 * Pipe 19: Receive timeslot 7 (version).
1525 */
1526
1527 link_time_slot(dbri, 17, 16, 16, 32, dbri->mm.offset);
1528 link_time_slot(dbri, 18, 16, 16, 8, dbri->mm.offset);
1529 link_time_slot(dbri, 19, 18, 16, 8, dbri->mm.offset + 48);
1530 spin_unlock_irqrestore(&dbri->lock, flags);
1531
1532 /* Wait for the chip to echo back CLB (Control Latch Bit) as zero */
1533 dbri->mm.ctrl[0] &= ~CS4215_CLB;
1534 xmit_fixed(dbri, 17, *(int *)dbri->mm.ctrl);
1535
1536 spin_lock_irqsave(&dbri->lock, flags);
1537 tmp = sbus_readl(dbri->regs + REG0);
1538 tmp |= D_C; /* Enable CHI */
1539 sbus_writel(tmp, dbri->regs + REG0);
1540 spin_unlock_irqrestore(&dbri->lock, flags);
1541
1542 for (i = 10; ((dbri->mm.status & 0xe4) != 0x20); --i)
1543 msleep_interruptible(1);
1544
1545 if (i == 0) {
1546 dprintk(D_MM, "CS4215 didn't respond to CLB (0x%02x)\n",
1547 dbri->mm.status);
1548 return -1;
1549 }
1550
1551 /* Disable changes to our copy of the version number, as we are about
1552 * to leave control mode.
1553 */
1554 recv_fixed(dbri, 19, NULL);
1555
1556 /* Terminate CS4215 control mode - data sheet says
1557 * "Set CLB=1 and send two more frames of valid control info"
1558 */
1559 dbri->mm.ctrl[0] |= CS4215_CLB;
1560 xmit_fixed(dbri, 17, *(int *)dbri->mm.ctrl);
1561
1562 /* Two frames of control info @ 8kHz frame rate = 250 us delay */
1563 udelay(250);
1564
1565 cs4215_setdata(dbri, 0);
1566
1567 return 0;
1568 }
1569
1570 /*
1571 * Setup the codec with the sampling rate, audio format and number of
1572 * channels.
1573 * As part of the process we resend the settings for the data
1574 * timeslots as well.
1575 */
1576 static int cs4215_prepare(struct snd_dbri *dbri, unsigned int rate,
1577 snd_pcm_format_t format, unsigned int channels)
1578 {
1579 int freq_idx;
1580 int ret = 0;
1581
1582 /* Lookup index for this rate */
1583 for (freq_idx = 0; CS4215_FREQ[freq_idx].freq != 0; freq_idx++) {
1584 if (CS4215_FREQ[freq_idx].freq == rate)
1585 break;
1586 }
1587 if (CS4215_FREQ[freq_idx].freq != rate) {
1588 printk(KERN_WARNING "DBRI: Unsupported rate %d Hz\n", rate);
1589 return -1;
1590 }
1591
1592 switch (format) {
1593 case SNDRV_PCM_FORMAT_MU_LAW:
1594 dbri->mm.ctrl[1] = CS4215_DFR_ULAW;
1595 dbri->mm.precision = 8;
1596 break;
1597 case SNDRV_PCM_FORMAT_A_LAW:
1598 dbri->mm.ctrl[1] = CS4215_DFR_ALAW;
1599 dbri->mm.precision = 8;
1600 break;
1601 case SNDRV_PCM_FORMAT_U8:
1602 dbri->mm.ctrl[1] = CS4215_DFR_LINEAR8;
1603 dbri->mm.precision = 8;
1604 break;
1605 case SNDRV_PCM_FORMAT_S16_BE:
1606 dbri->mm.ctrl[1] = CS4215_DFR_LINEAR16;
1607 dbri->mm.precision = 16;
1608 break;
1609 default:
1610 printk(KERN_WARNING "DBRI: Unsupported format %d\n", format);
1611 return -1;
1612 }
1613
1614 /* Add rate parameters */
1615 dbri->mm.ctrl[1] |= CS4215_FREQ[freq_idx].csval;
1616 dbri->mm.ctrl[2] = CS4215_XCLK |
1617 CS4215_BSEL_128 | CS4215_FREQ[freq_idx].xtal;
1618
1619 dbri->mm.channels = channels;
1620 if (channels == 2)
1621 dbri->mm.ctrl[1] |= CS4215_DFR_STEREO;
1622
1623 ret = cs4215_setctrl(dbri);
1624 if (ret == 0)
1625 cs4215_open(dbri); /* set codec to data mode */
1626
1627 return ret;
1628 }
1629
1630 /*
1631 *
1632 */
1633 static __devinit int cs4215_init(struct snd_dbri *dbri)
1634 {
1635 u32 reg2 = sbus_readl(dbri->regs + REG2);
1636 dprintk(D_MM, "cs4215_init: reg2=0x%x\n", reg2);
1637
1638 /* Look for the cs4215 chips */
1639 if (reg2 & D_PIO2) {
1640 dprintk(D_MM, "Onboard CS4215 detected\n");
1641 dbri->mm.onboard = 1;
1642 }
1643 if (reg2 & D_PIO0) {
1644 dprintk(D_MM, "Speakerbox detected\n");
1645 dbri->mm.onboard = 0;
1646
1647 if (reg2 & D_PIO2) {
1648 printk(KERN_INFO "DBRI: Using speakerbox / "
1649 "ignoring onboard mmcodec.\n");
1650 sbus_writel(D_ENPIO2, dbri->regs + REG2);
1651 }
1652 }
1653
1654 if (!(reg2 & (D_PIO0 | D_PIO2))) {
1655 printk(KERN_ERR "DBRI: no mmcodec found.\n");
1656 return -EIO;
1657 }
1658
1659 cs4215_setup_pipes(dbri);
1660 cs4215_init_data(&dbri->mm);
1661
1662 /* Enable capture of the status & version timeslots. */
1663 recv_fixed(dbri, 18, &dbri->mm.status);
1664 recv_fixed(dbri, 19, &dbri->mm.version);
1665
1666 dbri->mm.offset = dbri->mm.onboard ? 0 : 8;
1667 if (cs4215_setctrl(dbri) == -1 || dbri->mm.version == 0xff) {
1668 dprintk(D_MM, "CS4215 failed probe at offset %d\n",
1669 dbri->mm.offset);
1670 return -EIO;
1671 }
1672 dprintk(D_MM, "Found CS4215 at offset %d\n", dbri->mm.offset);
1673
1674 return 0;
1675 }
1676
1677 /*
1678 ****************************************************************************
1679 *************************** DBRI interrupt handler *************************
1680 ****************************************************************************
1681
1682 The DBRI communicates with the CPU mainly via a circular interrupt
1683 buffer. When an interrupt is signaled, the CPU walks through the
1684 buffer and calls dbri_process_one_interrupt() for each interrupt word.
1685 Complicated interrupts are handled by dedicated functions (which
1686 appear first in this file). Any pending interrupts can be serviced by
1687 calling dbri_process_interrupt_buffer(), which works even if the CPU's
1688 interrupts are disabled.
1689
1690 */
1691
1692 /* xmit_descs()
1693 *
1694 * Starts transmitting the current TD's for recording/playing.
1695 * For playback, ALSA has filled the DMA memory with new data (we hope).
1696 */
1697 static void xmit_descs(struct snd_dbri *dbri)
1698 {
1699 struct dbri_streaminfo *info;
1700 s32 *cmd;
1701 unsigned long flags;
1702 int first_td;
1703
1704 if (dbri == NULL)
1705 return; /* Disabled */
1706
1707 info = &dbri->stream_info[DBRI_REC];
1708 spin_lock_irqsave(&dbri->lock, flags);
1709
1710 if (info->pipe >= 0) {
1711 first_td = dbri->pipes[info->pipe].first_desc;
1712
1713 dprintk(D_DESC, "xmit_descs rec @ TD %d\n", first_td);
1714
1715 /* Stream could be closed by the time we run. */
1716 if (first_td >= 0) {
1717 cmd = dbri_cmdlock(dbri, 2);
1718 *(cmd++) = DBRI_CMD(D_SDP, 0,
1719 dbri->pipes[info->pipe].sdp
1720 | D_SDP_P | D_SDP_EVERY | D_SDP_C);
1721 *(cmd++) = dbri->dma_dvma +
1722 dbri_dma_off(desc, first_td);
1723 dbri_cmdsend(dbri, cmd, 2);
1724
1725 /* Reset our admin of the pipe. */
1726 dbri->pipes[info->pipe].desc = first_td;
1727 }
1728 }
1729
1730 info = &dbri->stream_info[DBRI_PLAY];
1731
1732 if (info->pipe >= 0) {
1733 first_td = dbri->pipes[info->pipe].first_desc;
1734
1735 dprintk(D_DESC, "xmit_descs play @ TD %d\n", first_td);
1736
1737 /* Stream could be closed by the time we run. */
1738 if (first_td >= 0) {
1739 cmd = dbri_cmdlock(dbri, 2);
1740 *(cmd++) = DBRI_CMD(D_SDP, 0,
1741 dbri->pipes[info->pipe].sdp
1742 | D_SDP_P | D_SDP_EVERY | D_SDP_C);
1743 *(cmd++) = dbri->dma_dvma +
1744 dbri_dma_off(desc, first_td);
1745 dbri_cmdsend(dbri, cmd, 2);
1746
1747 /* Reset our admin of the pipe. */
1748 dbri->pipes[info->pipe].desc = first_td;
1749 }
1750 }
1751
1752 spin_unlock_irqrestore(&dbri->lock, flags);
1753 }
1754
1755 /* transmission_complete_intr()
1756 *
1757 * Called by main interrupt handler when DBRI signals transmission complete
1758 * on a pipe (interrupt triggered by the B bit in a transmit descriptor).
1759 *
1760 * Walks through the pipe's list of transmit buffer descriptors and marks
1761 * them as available. Stops when the first descriptor is found without
1762 * TBC (Transmit Buffer Complete) set, or we've run through them all.
1763 *
1764 * The DMA buffers are not released. They form a ring buffer and
1765 * they are filled by ALSA while others are transmitted by DMA.
1766 *
1767 */
1768
1769 static void transmission_complete_intr(struct snd_dbri *dbri, int pipe)
1770 {
1771 struct dbri_streaminfo *info = &dbri->stream_info[DBRI_PLAY];
1772 int td = dbri->pipes[pipe].desc;
1773 int status;
1774
1775 while (td >= 0) {
1776 if (td >= DBRI_NO_DESCS) {
1777 printk(KERN_ERR "DBRI: invalid td on pipe %d\n", pipe);
1778 return;
1779 }
1780
1781 status = DBRI_TD_STATUS(dbri->dma->desc[td].word4);
1782 if (!(status & DBRI_TD_TBC))
1783 break;
1784
1785 dprintk(D_INT, "TD %d, status 0x%02x\n", td, status);
1786
1787 dbri->dma->desc[td].word4 = 0; /* Reset it for next time. */
1788 info->offset += DBRI_RD_CNT(dbri->dma->desc[td].word1);
1789
1790 td = dbri->next_desc[td];
1791 dbri->pipes[pipe].desc = td;
1792 }
1793
1794 /* Notify ALSA */
1795 spin_unlock(&dbri->lock);
1796 snd_pcm_period_elapsed(info->substream);
1797 spin_lock(&dbri->lock);
1798 }
1799
1800 static void reception_complete_intr(struct snd_dbri *dbri, int pipe)
1801 {
1802 struct dbri_streaminfo *info;
1803 int rd = dbri->pipes[pipe].desc;
1804 s32 status;
1805
1806 if (rd < 0 || rd >= DBRI_NO_DESCS) {
1807 printk(KERN_ERR "DBRI: invalid rd on pipe %d\n", pipe);
1808 return;
1809 }
1810
1811 dbri->pipes[pipe].desc = dbri->next_desc[rd];
1812 status = dbri->dma->desc[rd].word1;
1813 dbri->dma->desc[rd].word1 = 0; /* Reset it for next time. */
1814
1815 info = &dbri->stream_info[DBRI_REC];
1816 info->offset += DBRI_RD_CNT(status);
1817
1818 /* FIXME: Check status */
1819
1820 dprintk(D_INT, "Recv RD %d, status 0x%02x, len %d\n",
1821 rd, DBRI_RD_STATUS(status), DBRI_RD_CNT(status));
1822
1823 /* Notify ALSA */
1824 spin_unlock(&dbri->lock);
1825 snd_pcm_period_elapsed(info->substream);
1826 spin_lock(&dbri->lock);
1827 }
1828
1829 static void dbri_process_one_interrupt(struct snd_dbri *dbri, int x)
1830 {
1831 int val = D_INTR_GETVAL(x);
1832 int channel = D_INTR_GETCHAN(x);
1833 int command = D_INTR_GETCMD(x);
1834 int code = D_INTR_GETCODE(x);
1835 #ifdef DBRI_DEBUG
1836 int rval = D_INTR_GETRVAL(x);
1837 #endif
1838
1839 if (channel == D_INTR_CMD) {
1840 dprintk(D_CMD, "INTR: Command: %-5s Value:%d\n",
1841 cmds[command], val);
1842 } else {
1843 dprintk(D_INT, "INTR: Chan:%d Code:%d Val:%#x\n",
1844 channel, code, rval);
1845 }
1846
1847 switch (code) {
1848 case D_INTR_CMDI:
1849 if (command != D_WAIT)
1850 printk(KERN_ERR "DBRI: Command read interrupt\n");
1851 break;
1852 case D_INTR_BRDY:
1853 reception_complete_intr(dbri, channel);
1854 break;
1855 case D_INTR_XCMP:
1856 case D_INTR_MINT:
1857 transmission_complete_intr(dbri, channel);
1858 break;
1859 case D_INTR_UNDR:
1860 /* UNDR - Transmission underrun
1861 * resend SDP command with clear pipe bit (C) set
1862 */
1863 {
1864 /* FIXME: do something useful in case of underrun */
1865 printk(KERN_ERR "DBRI: Underrun error\n");
1866 #if 0
1867 s32 *cmd;
1868 int pipe = channel;
1869 int td = dbri->pipes[pipe].desc;
1870
1871 dbri->dma->desc[td].word4 = 0;
1872 cmd = dbri_cmdlock(dbri, NoGetLock);
1873 *(cmd++) = DBRI_CMD(D_SDP, 0,
1874 dbri->pipes[pipe].sdp
1875 | D_SDP_P | D_SDP_C | D_SDP_2SAME);
1876 *(cmd++) = dbri->dma_dvma + dbri_dma_off(desc, td);
1877 dbri_cmdsend(dbri, cmd);
1878 #endif
1879 }
1880 break;
1881 case D_INTR_FXDT:
1882 /* FXDT - Fixed data change */
1883 if (dbri->pipes[channel].sdp & D_SDP_MSB)
1884 val = reverse_bytes(val, dbri->pipes[channel].length);
1885
1886 if (dbri->pipes[channel].recv_fixed_ptr)
1887 *(dbri->pipes[channel].recv_fixed_ptr) = val;
1888 break;
1889 default:
1890 if (channel != D_INTR_CMD)
1891 printk(KERN_WARNING
1892 "DBRI: Ignored Interrupt: %d (0x%x)\n", code, x);
1893 }
1894 }
1895
1896 /* dbri_process_interrupt_buffer advances through the DBRI's interrupt
1897 * buffer until it finds a zero word (indicating nothing more to do
1898 * right now). Non-zero words require processing and are handed off
1899 * to dbri_process_one_interrupt AFTER advancing the pointer.
1900 */
1901 static void dbri_process_interrupt_buffer(struct snd_dbri *dbri)
1902 {
1903 s32 x;
1904
1905 while ((x = dbri->dma->intr[dbri->dbri_irqp]) != 0) {
1906 dbri->dma->intr[dbri->dbri_irqp] = 0;
1907 dbri->dbri_irqp++;
1908 if (dbri->dbri_irqp == DBRI_INT_BLK)
1909 dbri->dbri_irqp = 1;
1910
1911 dbri_process_one_interrupt(dbri, x);
1912 }
1913 }
1914
1915 static irqreturn_t snd_dbri_interrupt(int irq, void *dev_id)
1916 {
1917 struct snd_dbri *dbri = dev_id;
1918 static int errcnt = 0;
1919 int x;
1920
1921 if (dbri == NULL)
1922 return IRQ_NONE;
1923 spin_lock(&dbri->lock);
1924
1925 /*
1926 * Read it, so the interrupt goes away.
1927 */
1928 x = sbus_readl(dbri->regs + REG1);
1929
1930 if (x & (D_MRR | D_MLE | D_LBG | D_MBE)) {
1931 u32 tmp;
1932
1933 if (x & D_MRR)
1934 printk(KERN_ERR
1935 "DBRI: Multiple Error Ack on SBus reg1=0x%x\n",
1936 x);
1937 if (x & D_MLE)
1938 printk(KERN_ERR
1939 "DBRI: Multiple Late Error on SBus reg1=0x%x\n",
1940 x);
1941 if (x & D_LBG)
1942 printk(KERN_ERR
1943 "DBRI: Lost Bus Grant on SBus reg1=0x%x\n", x);
1944 if (x & D_MBE)
1945 printk(KERN_ERR
1946 "DBRI: Burst Error on SBus reg1=0x%x\n", x);
1947
1948 /* Some of these SBus errors cause the chip's SBus circuitry
1949 * to be disabled, so just re-enable and try to keep going.
1950 *
1951 * The only one I've seen is MRR, which will be triggered
1952 * if you let a transmit pipe underrun, then try to CDP it.
1953 *
1954 * If these things persist, we reset the chip.
1955 */
1956 if ((++errcnt) % 10 == 0) {
1957 dprintk(D_INT, "Interrupt errors exceeded.\n");
1958 dbri_reset(dbri);
1959 } else {
1960 tmp = sbus_readl(dbri->regs + REG0);
1961 tmp &= ~(D_D);
1962 sbus_writel(tmp, dbri->regs + REG0);
1963 }
1964 }
1965
1966 dbri_process_interrupt_buffer(dbri);
1967
1968 spin_unlock(&dbri->lock);
1969
1970 return IRQ_HANDLED;
1971 }
1972
1973 /****************************************************************************
1974 PCM Interface
1975 ****************************************************************************/
1976 static struct snd_pcm_hardware snd_dbri_pcm_hw = {
1977 .info = SNDRV_PCM_INFO_MMAP |
1978 SNDRV_PCM_INFO_INTERLEAVED |
1979 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1980 SNDRV_PCM_INFO_MMAP_VALID |
1981 SNDRV_PCM_INFO_BATCH,
1982 .formats = SNDRV_PCM_FMTBIT_MU_LAW |
1983 SNDRV_PCM_FMTBIT_A_LAW |
1984 SNDRV_PCM_FMTBIT_U8 |
1985 SNDRV_PCM_FMTBIT_S16_BE,
1986 .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_5512,
1987 .rate_min = 5512,
1988 .rate_max = 48000,
1989 .channels_min = 1,
1990 .channels_max = 2,
1991 .buffer_bytes_max = 64 * 1024,
1992 .period_bytes_min = 1,
1993 .period_bytes_max = DBRI_TD_MAXCNT,
1994 .periods_min = 1,
1995 .periods_max = 1024,
1996 };
1997
1998 static int snd_hw_rule_format(struct snd_pcm_hw_params *params,
1999 struct snd_pcm_hw_rule *rule)
2000 {
2001 struct snd_interval *c = hw_param_interval(params,
2002 SNDRV_PCM_HW_PARAM_CHANNELS);
2003 struct snd_mask *f = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
2004 struct snd_mask fmt;
2005
2006 snd_mask_any(&fmt);
2007 if (c->min > 1) {
2008 fmt.bits[0] &= SNDRV_PCM_FMTBIT_S16_BE;
2009 return snd_mask_refine(f, &fmt);
2010 }
2011 return 0;
2012 }
2013
2014 static int snd_hw_rule_channels(struct snd_pcm_hw_params *params,
2015 struct snd_pcm_hw_rule *rule)
2016 {
2017 struct snd_interval *c = hw_param_interval(params,
2018 SNDRV_PCM_HW_PARAM_CHANNELS);
2019 struct snd_mask *f = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
2020 struct snd_interval ch;
2021
2022 snd_interval_any(&ch);
2023 if (!(f->bits[0] & SNDRV_PCM_FMTBIT_S16_BE)) {
2024 ch.min = 1;
2025 ch.max = 1;
2026 ch.integer = 1;
2027 return snd_interval_refine(c, &ch);
2028 }
2029 return 0;
2030 }
2031
2032 static int snd_dbri_open(struct snd_pcm_substream *substream)
2033 {
2034 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2035 struct snd_pcm_runtime *runtime = substream->runtime;
2036 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2037 unsigned long flags;
2038
2039 dprintk(D_USR, "open audio output.\n");
2040 runtime->hw = snd_dbri_pcm_hw;
2041
2042 spin_lock_irqsave(&dbri->lock, flags);
2043 info->substream = substream;
2044 info->offset = 0;
2045 info->dvma_buffer = 0;
2046 info->pipe = -1;
2047 spin_unlock_irqrestore(&dbri->lock, flags);
2048
2049 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
2050 snd_hw_rule_format, NULL, SNDRV_PCM_HW_PARAM_FORMAT,
2051 -1);
2052 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_FORMAT,
2053 snd_hw_rule_channels, NULL,
2054 SNDRV_PCM_HW_PARAM_CHANNELS,
2055 -1);
2056
2057 cs4215_open(dbri);
2058
2059 return 0;
2060 }
2061
2062 static int snd_dbri_close(struct snd_pcm_substream *substream)
2063 {
2064 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2065 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2066
2067 dprintk(D_USR, "close audio output.\n");
2068 info->substream = NULL;
2069 info->offset = 0;
2070
2071 return 0;
2072 }
2073
2074 static int snd_dbri_hw_params(struct snd_pcm_substream *substream,
2075 struct snd_pcm_hw_params *hw_params)
2076 {
2077 struct snd_pcm_runtime *runtime = substream->runtime;
2078 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2079 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2080 int direction;
2081 int ret;
2082
2083 /* set sampling rate, audio format and number of channels */
2084 ret = cs4215_prepare(dbri, params_rate(hw_params),
2085 params_format(hw_params),
2086 params_channels(hw_params));
2087 if (ret != 0)
2088 return ret;
2089
2090 if ((ret = snd_pcm_lib_malloc_pages(substream,
2091 params_buffer_bytes(hw_params))) < 0) {
2092 printk(KERN_ERR "malloc_pages failed with %d\n", ret);
2093 return ret;
2094 }
2095
2096 /* hw_params can get called multiple times. Only map the DMA once.
2097 */
2098 if (info->dvma_buffer == 0) {
2099 if (DBRI_STREAMNO(substream) == DBRI_PLAY)
2100 direction = DMA_TO_DEVICE;
2101 else
2102 direction = DMA_FROM_DEVICE;
2103
2104 info->dvma_buffer =
2105 dma_map_single(&dbri->op->dev,
2106 runtime->dma_area,
2107 params_buffer_bytes(hw_params),
2108 direction);
2109 }
2110
2111 direction = params_buffer_bytes(hw_params);
2112 dprintk(D_USR, "hw_params: %d bytes, dvma=%x\n",
2113 direction, info->dvma_buffer);
2114 return 0;
2115 }
2116
2117 static int snd_dbri_hw_free(struct snd_pcm_substream *substream)
2118 {
2119 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2120 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2121 int direction;
2122
2123 dprintk(D_USR, "hw_free.\n");
2124
2125 /* hw_free can get called multiple times. Only unmap the DMA once.
2126 */
2127 if (info->dvma_buffer) {
2128 if (DBRI_STREAMNO(substream) == DBRI_PLAY)
2129 direction = DMA_TO_DEVICE;
2130 else
2131 direction = DMA_FROM_DEVICE;
2132
2133 dma_unmap_single(&dbri->op->dev, info->dvma_buffer,
2134 substream->runtime->buffer_size, direction);
2135 info->dvma_buffer = 0;
2136 }
2137 if (info->pipe != -1) {
2138 reset_pipe(dbri, info->pipe);
2139 info->pipe = -1;
2140 }
2141
2142 return snd_pcm_lib_free_pages(substream);
2143 }
2144
2145 static int snd_dbri_prepare(struct snd_pcm_substream *substream)
2146 {
2147 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2148 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2149 int ret;
2150
2151 info->size = snd_pcm_lib_buffer_bytes(substream);
2152 if (DBRI_STREAMNO(substream) == DBRI_PLAY)
2153 info->pipe = 4; /* Send pipe */
2154 else
2155 info->pipe = 6; /* Receive pipe */
2156
2157 spin_lock_irq(&dbri->lock);
2158 info->offset = 0;
2159
2160 /* Setup the all the transmit/receive descriptors to cover the
2161 * whole DMA buffer.
2162 */
2163 ret = setup_descs(dbri, DBRI_STREAMNO(substream),
2164 snd_pcm_lib_period_bytes(substream));
2165
2166 spin_unlock_irq(&dbri->lock);
2167
2168 dprintk(D_USR, "prepare audio output. %d bytes\n", info->size);
2169 return ret;
2170 }
2171
2172 static int snd_dbri_trigger(struct snd_pcm_substream *substream, int cmd)
2173 {
2174 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2175 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2176 int ret = 0;
2177
2178 switch (cmd) {
2179 case SNDRV_PCM_TRIGGER_START:
2180 dprintk(D_USR, "start audio, period is %d bytes\n",
2181 (int)snd_pcm_lib_period_bytes(substream));
2182 /* Re-submit the TDs. */
2183 xmit_descs(dbri);
2184 break;
2185 case SNDRV_PCM_TRIGGER_STOP:
2186 dprintk(D_USR, "stop audio.\n");
2187 reset_pipe(dbri, info->pipe);
2188 break;
2189 default:
2190 ret = -EINVAL;
2191 }
2192
2193 return ret;
2194 }
2195
2196 static snd_pcm_uframes_t snd_dbri_pointer(struct snd_pcm_substream *substream)
2197 {
2198 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2199 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2200 snd_pcm_uframes_t ret;
2201
2202 ret = bytes_to_frames(substream->runtime, info->offset)
2203 % substream->runtime->buffer_size;
2204 dprintk(D_USR, "I/O pointer: %ld frames of %ld.\n",
2205 ret, substream->runtime->buffer_size);
2206 return ret;
2207 }
2208
2209 static struct snd_pcm_ops snd_dbri_ops = {
2210 .open = snd_dbri_open,
2211 .close = snd_dbri_close,
2212 .ioctl = snd_pcm_lib_ioctl,
2213 .hw_params = snd_dbri_hw_params,
2214 .hw_free = snd_dbri_hw_free,
2215 .prepare = snd_dbri_prepare,
2216 .trigger = snd_dbri_trigger,
2217 .pointer = snd_dbri_pointer,
2218 };
2219
2220 static int __devinit snd_dbri_pcm(struct snd_card *card)
2221 {
2222 struct snd_pcm *pcm;
2223 int err;
2224
2225 if ((err = snd_pcm_new(card,
2226 /* ID */ "sun_dbri",
2227 /* device */ 0,
2228 /* playback count */ 1,
2229 /* capture count */ 1, &pcm)) < 0)
2230 return err;
2231
2232 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_dbri_ops);
2233 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_dbri_ops);
2234
2235 pcm->private_data = card->private_data;
2236 pcm->info_flags = 0;
2237 strcpy(pcm->name, card->shortname);
2238
2239 if ((err = snd_pcm_lib_preallocate_pages_for_all(pcm,
2240 SNDRV_DMA_TYPE_CONTINUOUS,
2241 snd_dma_continuous_data(GFP_KERNEL),
2242 64 * 1024, 64 * 1024)) < 0)
2243 return err;
2244
2245 return 0;
2246 }
2247
2248 /*****************************************************************************
2249 Mixer interface
2250 *****************************************************************************/
2251
2252 static int snd_cs4215_info_volume(struct snd_kcontrol *kcontrol,
2253 struct snd_ctl_elem_info *uinfo)
2254 {
2255 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2256 uinfo->count = 2;
2257 uinfo->value.integer.min = 0;
2258 if (kcontrol->private_value == DBRI_PLAY)
2259 uinfo->value.integer.max = DBRI_MAX_VOLUME;
2260 else
2261 uinfo->value.integer.max = DBRI_MAX_GAIN;
2262 return 0;
2263 }
2264
2265 static int snd_cs4215_get_volume(struct snd_kcontrol *kcontrol,
2266 struct snd_ctl_elem_value *ucontrol)
2267 {
2268 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol);
2269 struct dbri_streaminfo *info;
2270
2271 if (snd_BUG_ON(!dbri))
2272 return -EINVAL;
2273 info = &dbri->stream_info[kcontrol->private_value];
2274
2275 ucontrol->value.integer.value[0] = info->left_gain;
2276 ucontrol->value.integer.value[1] = info->right_gain;
2277 return 0;
2278 }
2279
2280 static int snd_cs4215_put_volume(struct snd_kcontrol *kcontrol,
2281 struct snd_ctl_elem_value *ucontrol)
2282 {
2283 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol);
2284 struct dbri_streaminfo *info =
2285 &dbri->stream_info[kcontrol->private_value];
2286 unsigned int vol[2];
2287 int changed = 0;
2288
2289 vol[0] = ucontrol->value.integer.value[0];
2290 vol[1] = ucontrol->value.integer.value[1];
2291 if (kcontrol->private_value == DBRI_PLAY) {
2292 if (vol[0] > DBRI_MAX_VOLUME || vol[1] > DBRI_MAX_VOLUME)
2293 return -EINVAL;
2294 } else {
2295 if (vol[0] > DBRI_MAX_GAIN || vol[1] > DBRI_MAX_GAIN)
2296 return -EINVAL;
2297 }
2298
2299 if (info->left_gain != vol[0]) {
2300 info->left_gain = vol[0];
2301 changed = 1;
2302 }
2303 if (info->right_gain != vol[1]) {
2304 info->right_gain = vol[1];
2305 changed = 1;
2306 }
2307 if (changed) {
2308 /* First mute outputs, and wait 1/8000 sec (125 us)
2309 * to make sure this takes. This avoids clicking noises.
2310 */
2311 cs4215_setdata(dbri, 1);
2312 udelay(125);
2313 cs4215_setdata(dbri, 0);
2314 }
2315 return changed;
2316 }
2317
2318 static int snd_cs4215_info_single(struct snd_kcontrol *kcontrol,
2319 struct snd_ctl_elem_info *uinfo)
2320 {
2321 int mask = (kcontrol->private_value >> 16) & 0xff;
2322
2323 uinfo->type = (mask == 1) ?
2324 SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
2325 uinfo->count = 1;
2326 uinfo->value.integer.min = 0;
2327 uinfo->value.integer.max = mask;
2328 return 0;
2329 }
2330
2331 static int snd_cs4215_get_single(struct snd_kcontrol *kcontrol,
2332 struct snd_ctl_elem_value *ucontrol)
2333 {
2334 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol);
2335 int elem = kcontrol->private_value & 0xff;
2336 int shift = (kcontrol->private_value >> 8) & 0xff;
2337 int mask = (kcontrol->private_value >> 16) & 0xff;
2338 int invert = (kcontrol->private_value >> 24) & 1;
2339
2340 if (snd_BUG_ON(!dbri))
2341 return -EINVAL;
2342
2343 if (elem < 4)
2344 ucontrol->value.integer.value[0] =
2345 (dbri->mm.data[elem] >> shift) & mask;
2346 else
2347 ucontrol->value.integer.value[0] =
2348 (dbri->mm.ctrl[elem - 4] >> shift) & mask;
2349
2350 if (invert == 1)
2351 ucontrol->value.integer.value[0] =
2352 mask - ucontrol->value.integer.value[0];
2353 return 0;
2354 }
2355
2356 static int snd_cs4215_put_single(struct snd_kcontrol *kcontrol,
2357 struct snd_ctl_elem_value *ucontrol)
2358 {
2359 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol);
2360 int elem = kcontrol->private_value & 0xff;
2361 int shift = (kcontrol->private_value >> 8) & 0xff;
2362 int mask = (kcontrol->private_value >> 16) & 0xff;
2363 int invert = (kcontrol->private_value >> 24) & 1;
2364 int changed = 0;
2365 unsigned short val;
2366
2367 if (snd_BUG_ON(!dbri))
2368 return -EINVAL;
2369
2370 val = (ucontrol->value.integer.value[0] & mask);
2371 if (invert == 1)
2372 val = mask - val;
2373 val <<= shift;
2374
2375 if (elem < 4) {
2376 dbri->mm.data[elem] = (dbri->mm.data[elem] &
2377 ~(mask << shift)) | val;
2378 changed = (val != dbri->mm.data[elem]);
2379 } else {
2380 dbri->mm.ctrl[elem - 4] = (dbri->mm.ctrl[elem - 4] &
2381 ~(mask << shift)) | val;
2382 changed = (val != dbri->mm.ctrl[elem - 4]);
2383 }
2384
2385 dprintk(D_GEN, "put_single: mask=0x%x, changed=%d, "
2386 "mixer-value=%ld, mm-value=0x%x\n",
2387 mask, changed, ucontrol->value.integer.value[0],
2388 dbri->mm.data[elem & 3]);
2389
2390 if (changed) {
2391 /* First mute outputs, and wait 1/8000 sec (125 us)
2392 * to make sure this takes. This avoids clicking noises.
2393 */
2394 cs4215_setdata(dbri, 1);
2395 udelay(125);
2396 cs4215_setdata(dbri, 0);
2397 }
2398 return changed;
2399 }
2400
2401 /* Entries 0-3 map to the 4 data timeslots, entries 4-7 map to the 4 control
2402 timeslots. Shift is the bit offset in the timeslot, mask defines the
2403 number of bits. invert is a boolean for use with attenuation.
2404 */
2405 #define CS4215_SINGLE(xname, entry, shift, mask, invert) \
2406 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
2407 .info = snd_cs4215_info_single, \
2408 .get = snd_cs4215_get_single, .put = snd_cs4215_put_single, \
2409 .private_value = (entry) | ((shift) << 8) | ((mask) << 16) | \
2410 ((invert) << 24) },
2411
2412 static struct snd_kcontrol_new dbri_controls[] __devinitdata = {
2413 {
2414 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2415 .name = "Playback Volume",
2416 .info = snd_cs4215_info_volume,
2417 .get = snd_cs4215_get_volume,
2418 .put = snd_cs4215_put_volume,
2419 .private_value = DBRI_PLAY,
2420 },
2421 CS4215_SINGLE("Headphone switch", 0, 7, 1, 0)
2422 CS4215_SINGLE("Line out switch", 0, 6, 1, 0)
2423 CS4215_SINGLE("Speaker switch", 1, 6, 1, 0)
2424 {
2425 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2426 .name = "Capture Volume",
2427 .info = snd_cs4215_info_volume,
2428 .get = snd_cs4215_get_volume,
2429 .put = snd_cs4215_put_volume,
2430 .private_value = DBRI_REC,
2431 },
2432 /* FIXME: mic/line switch */
2433 CS4215_SINGLE("Line in switch", 2, 4, 1, 0)
2434 CS4215_SINGLE("High Pass Filter switch", 5, 7, 1, 0)
2435 CS4215_SINGLE("Monitor Volume", 3, 4, 0xf, 1)
2436 CS4215_SINGLE("Mic boost", 4, 4, 1, 1)
2437 };
2438
2439 static int __devinit snd_dbri_mixer(struct snd_card *card)
2440 {
2441 int idx, err;
2442 struct snd_dbri *dbri;
2443
2444 if (snd_BUG_ON(!card || !card->private_data))
2445 return -EINVAL;
2446 dbri = card->private_data;
2447
2448 strcpy(card->mixername, card->shortname);
2449
2450 for (idx = 0; idx < ARRAY_SIZE(dbri_controls); idx++) {
2451 err = snd_ctl_add(card,
2452 snd_ctl_new1(&dbri_controls[idx], dbri));
2453 if (err < 0)
2454 return err;
2455 }
2456
2457 for (idx = DBRI_REC; idx < DBRI_NO_STREAMS; idx++) {
2458 dbri->stream_info[idx].left_gain = 0;
2459 dbri->stream_info[idx].right_gain = 0;
2460 }
2461
2462 return 0;
2463 }
2464
2465 /****************************************************************************
2466 /proc interface
2467 ****************************************************************************/
2468 static void dbri_regs_read(struct snd_info_entry *entry,
2469 struct snd_info_buffer *buffer)
2470 {
2471 struct snd_dbri *dbri = entry->private_data;
2472
2473 snd_iprintf(buffer, "REG0: 0x%x\n", sbus_readl(dbri->regs + REG0));
2474 snd_iprintf(buffer, "REG2: 0x%x\n", sbus_readl(dbri->regs + REG2));
2475 snd_iprintf(buffer, "REG8: 0x%x\n", sbus_readl(dbri->regs + REG8));
2476 snd_iprintf(buffer, "REG9: 0x%x\n", sbus_readl(dbri->regs + REG9));
2477 }
2478
2479 #ifdef DBRI_DEBUG
2480 static void dbri_debug_read(struct snd_info_entry *entry,
2481 struct snd_info_buffer *buffer)
2482 {
2483 struct snd_dbri *dbri = entry->private_data;
2484 int pipe;
2485 snd_iprintf(buffer, "debug=%d\n", dbri_debug);
2486
2487 for (pipe = 0; pipe < 32; pipe++) {
2488 if (pipe_active(dbri, pipe)) {
2489 struct dbri_pipe *pptr = &dbri->pipes[pipe];
2490 snd_iprintf(buffer,
2491 "Pipe %d: %s SDP=0x%x desc=%d, "
2492 "len=%d next %d\n",
2493 pipe,
2494 (pptr->sdp & D_SDP_TO_SER) ? "output" :
2495 "input",
2496 pptr->sdp, pptr->desc,
2497 pptr->length, pptr->nextpipe);
2498 }
2499 }
2500 }
2501 #endif
2502
2503 static void __devinit snd_dbri_proc(struct snd_card *card)
2504 {
2505 struct snd_dbri *dbri = card->private_data;
2506 struct snd_info_entry *entry;
2507
2508 if (!snd_card_proc_new(card, "regs", &entry))
2509 snd_info_set_text_ops(entry, dbri, dbri_regs_read);
2510
2511 #ifdef DBRI_DEBUG
2512 if (!snd_card_proc_new(card, "debug", &entry)) {
2513 snd_info_set_text_ops(entry, dbri, dbri_debug_read);
2514 entry->mode = S_IFREG | S_IRUGO; /* Readable only. */
2515 }
2516 #endif
2517 }
2518
2519 /*
2520 ****************************************************************************
2521 **************************** Initialization ********************************
2522 ****************************************************************************
2523 */
2524 static void snd_dbri_free(struct snd_dbri *dbri);
2525
2526 static int __devinit snd_dbri_create(struct snd_card *card,
2527 struct platform_device *op,
2528 int irq, int dev)
2529 {
2530 struct snd_dbri *dbri = card->private_data;
2531 int err;
2532
2533 spin_lock_init(&dbri->lock);
2534 dbri->op = op;
2535 dbri->irq = irq;
2536
2537 dbri->dma = dma_alloc_coherent(&op->dev,
2538 sizeof(struct dbri_dma),
2539 &dbri->dma_dvma, GFP_ATOMIC);
2540 if (!dbri->dma)
2541 return -ENOMEM;
2542 memset((void *)dbri->dma, 0, sizeof(struct dbri_dma));
2543
2544 dprintk(D_GEN, "DMA Cmd Block 0x%p (0x%08x)\n",
2545 dbri->dma, dbri->dma_dvma);
2546
2547 /* Map the registers into memory. */
2548 dbri->regs_size = resource_size(&op->resource[0]);
2549 dbri->regs = of_ioremap(&op->resource[0], 0,
2550 dbri->regs_size, "DBRI Registers");
2551 if (!dbri->regs) {
2552 printk(KERN_ERR "DBRI: could not allocate registers\n");
2553 dma_free_coherent(&op->dev, sizeof(struct dbri_dma),
2554 (void *)dbri->dma, dbri->dma_dvma);
2555 return -EIO;
2556 }
2557
2558 err = request_irq(dbri->irq, snd_dbri_interrupt, IRQF_SHARED,
2559 "DBRI audio", dbri);
2560 if (err) {
2561 printk(KERN_ERR "DBRI: Can't get irq %d\n", dbri->irq);
2562 of_iounmap(&op->resource[0], dbri->regs, dbri->regs_size);
2563 dma_free_coherent(&op->dev, sizeof(struct dbri_dma),
2564 (void *)dbri->dma, dbri->dma_dvma);
2565 return err;
2566 }
2567
2568 /* Do low level initialization of the DBRI and CS4215 chips */
2569 dbri_initialize(dbri);
2570 err = cs4215_init(dbri);
2571 if (err) {
2572 snd_dbri_free(dbri);
2573 return err;
2574 }
2575
2576 return 0;
2577 }
2578
2579 static void snd_dbri_free(struct snd_dbri *dbri)
2580 {
2581 dprintk(D_GEN, "snd_dbri_free\n");
2582 dbri_reset(dbri);
2583
2584 if (dbri->irq)
2585 free_irq(dbri->irq, dbri);
2586
2587 if (dbri->regs)
2588 of_iounmap(&dbri->op->resource[0], dbri->regs, dbri->regs_size);
2589
2590 if (dbri->dma)
2591 dma_free_coherent(&dbri->op->dev,
2592 sizeof(struct dbri_dma),
2593 (void *)dbri->dma, dbri->dma_dvma);
2594 }
2595
2596 static int __devinit dbri_probe(struct platform_device *op)
2597 {
2598 struct snd_dbri *dbri;
2599 struct resource *rp;
2600 struct snd_card *card;
2601 static int dev = 0;
2602 int irq;
2603 int err;
2604
2605 if (dev >= SNDRV_CARDS)
2606 return -ENODEV;
2607 if (!enable[dev]) {
2608 dev++;
2609 return -ENOENT;
2610 }
2611
2612 irq = op->archdata.irqs[0];
2613 if (irq <= 0) {
2614 printk(KERN_ERR "DBRI-%d: No IRQ.\n", dev);
2615 return -ENODEV;
2616 }
2617
2618 err = snd_card_create(index[dev], id[dev], THIS_MODULE,
2619 sizeof(struct snd_dbri), &card);
2620 if (err < 0)
2621 return err;
2622
2623 strcpy(card->driver, "DBRI");
2624 strcpy(card->shortname, "Sun DBRI");
2625 rp = &op->resource[0];
2626 sprintf(card->longname, "%s at 0x%02lx:0x%016Lx, irq %d",
2627 card->shortname,
2628 rp->flags & 0xffL, (unsigned long long)rp->start, irq);
2629
2630 err = snd_dbri_create(card, op, irq, dev);
2631 if (err < 0) {
2632 snd_card_free(card);
2633 return err;
2634 }
2635
2636 dbri = card->private_data;
2637 err = snd_dbri_pcm(card);
2638 if (err < 0)
2639 goto _err;
2640
2641 err = snd_dbri_mixer(card);
2642 if (err < 0)
2643 goto _err;
2644
2645 /* /proc file handling */
2646 snd_dbri_proc(card);
2647 dev_set_drvdata(&op->dev, card);
2648
2649 err = snd_card_register(card);
2650 if (err < 0)
2651 goto _err;
2652
2653 printk(KERN_INFO "audio%d at %p (irq %d) is DBRI(%c)+CS4215(%d)\n",
2654 dev, dbri->regs,
2655 dbri->irq, op->dev.of_node->name[9], dbri->mm.version);
2656 dev++;
2657
2658 return 0;
2659
2660 _err:
2661 snd_dbri_free(dbri);
2662 snd_card_free(card);
2663 return err;
2664 }
2665
2666 static int __devexit dbri_remove(struct platform_device *op)
2667 {
2668 struct snd_card *card = dev_get_drvdata(&op->dev);
2669
2670 snd_dbri_free(card->private_data);
2671 snd_card_free(card);
2672
2673 dev_set_drvdata(&op->dev, NULL);
2674
2675 return 0;
2676 }
2677
2678 static const struct of_device_id dbri_match[] = {
2679 {
2680 .name = "SUNW,DBRIe",
2681 },
2682 {
2683 .name = "SUNW,DBRIf",
2684 },
2685 {},
2686 };
2687
2688 MODULE_DEVICE_TABLE(of, dbri_match);
2689
2690 static struct platform_driver dbri_sbus_driver = {
2691 .driver = {
2692 .name = "dbri",
2693 .owner = THIS_MODULE,
2694 .of_match_table = dbri_match,
2695 },
2696 .probe = dbri_probe,
2697 .remove = __devexit_p(dbri_remove),
2698 };
2699
2700 module_platform_driver(dbri_sbus_driver);