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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound-2.6
[zen-stable.git] / drivers / tty / serial / 8250_pci.c
blobf41b4259ecddea3e6fc49c858c77a070ba400bcc
1 /*
2 * Probe module for 8250/16550-type PCI serial ports.
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright (C) 2001 Russell King, All Rights Reserved.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License.
11 */
12 #include <linux/module.h>
13 #include <linux/init.h>
14 #include <linux/pci.h>
15 #include <linux/string.h>
16 #include <linux/kernel.h>
17 #include <linux/slab.h>
18 #include <linux/delay.h>
19 #include <linux/tty.h>
20 #include <linux/serial_core.h>
21 #include <linux/8250_pci.h>
22 #include <linux/bitops.h>
23
24 #include <asm/byteorder.h>
25 #include <asm/io.h>
26
27 #include "8250.h"
28
29 #undef SERIAL_DEBUG_PCI
30
31 /*
32 * init function returns:
33 * > 0 - number of ports
34 * = 0 - use board->num_ports
35 * < 0 - error
36 */
37 struct pci_serial_quirk {
38 u32 vendor;
39 u32 device;
40 u32 subvendor;
41 u32 subdevice;
42 int (*init)(struct pci_dev *dev);
43 int (*setup)(struct serial_private *,
44 const struct pciserial_board *,
45 struct uart_port *, int);
46 void (*exit)(struct pci_dev *dev);
47 };
48
49 #define PCI_NUM_BAR_RESOURCES 6
50
51 struct serial_private {
52 struct pci_dev *dev;
53 unsigned int nr;
54 void __iomem *remapped_bar[PCI_NUM_BAR_RESOURCES];
55 struct pci_serial_quirk *quirk;
56 int line[0];
57 };
58
59 static void moan_device(const char *str, struct pci_dev *dev)
60 {
61 printk(KERN_WARNING
62 "%s: %s\n"
63 "Please send the output of lspci -vv, this\n"
64 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
65 "manufacturer and name of serial board or\n"
66 "modem board to rmk+serial@arm.linux.org.uk.\n",
67 pci_name(dev), str, dev->vendor, dev->device,
68 dev->subsystem_vendor, dev->subsystem_device);
69 }
70
71 static int
72 setup_port(struct serial_private *priv, struct uart_port *port,
73 int bar, int offset, int regshift)
74 {
75 struct pci_dev *dev = priv->dev;
76 unsigned long base, len;
77
78 if (bar >= PCI_NUM_BAR_RESOURCES)
79 return -EINVAL;
80
81 base = pci_resource_start(dev, bar);
82
83 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
84 len = pci_resource_len(dev, bar);
85
86 if (!priv->remapped_bar[bar])
87 priv->remapped_bar[bar] = ioremap_nocache(base, len);
88 if (!priv->remapped_bar[bar])
89 return -ENOMEM;
90
91 port->iotype = UPIO_MEM;
92 port->iobase = 0;
93 port->mapbase = base + offset;
94 port->membase = priv->remapped_bar[bar] + offset;
95 port->regshift = regshift;
96 } else {
97 port->iotype = UPIO_PORT;
98 port->iobase = base + offset;
99 port->mapbase = 0;
100 port->membase = NULL;
101 port->regshift = 0;
102 }
103 return 0;
104 }
105
106 /*
107 * ADDI-DATA GmbH communication cards <info@addi-data.com>
108 */
109 static int addidata_apci7800_setup(struct serial_private *priv,
110 const struct pciserial_board *board,
111 struct uart_port *port, int idx)
112 {
113 unsigned int bar = 0, offset = board->first_offset;
114 bar = FL_GET_BASE(board->flags);
115
116 if (idx < 2) {
117 offset += idx * board->uart_offset;
118 } else if ((idx >= 2) && (idx < 4)) {
119 bar += 1;
120 offset += ((idx - 2) * board->uart_offset);
121 } else if ((idx >= 4) && (idx < 6)) {
122 bar += 2;
123 offset += ((idx - 4) * board->uart_offset);
124 } else if (idx >= 6) {
125 bar += 3;
126 offset += ((idx - 6) * board->uart_offset);
127 }
128
129 return setup_port(priv, port, bar, offset, board->reg_shift);
130 }
131
132 /*
133 * AFAVLAB uses a different mixture of BARs and offsets
134 * Not that ugly ;) -- HW
135 */
136 static int
137 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
138 struct uart_port *port, int idx)
139 {
140 unsigned int bar, offset = board->first_offset;
141
142 bar = FL_GET_BASE(board->flags);
143 if (idx < 4)
144 bar += idx;
145 else {
146 bar = 4;
147 offset += (idx - 4) * board->uart_offset;
148 }
149
150 return setup_port(priv, port, bar, offset, board->reg_shift);
151 }
152
153 /*
154 * HP's Remote Management Console. The Diva chip came in several
155 * different versions. N-class, L2000 and A500 have two Diva chips, each
156 * with 3 UARTs (the third UART on the second chip is unused). Superdome
157 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
158 * one Diva chip, but it has been expanded to 5 UARTs.
159 */
160 static int pci_hp_diva_init(struct pci_dev *dev)
161 {
162 int rc = 0;
163
164 switch (dev->subsystem_device) {
165 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
166 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
167 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
168 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
169 rc = 3;
170 break;
171 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
172 rc = 2;
173 break;
174 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
175 rc = 4;
176 break;
177 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
178 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
179 rc = 1;
180 break;
181 }
182
183 return rc;
184 }
185
186 /*
187 * HP's Diva chip puts the 4th/5th serial port further out, and
188 * some serial ports are supposed to be hidden on certain models.
189 */
190 static int
191 pci_hp_diva_setup(struct serial_private *priv,
192 const struct pciserial_board *board,
193 struct uart_port *port, int idx)
194 {
195 unsigned int offset = board->first_offset;
196 unsigned int bar = FL_GET_BASE(board->flags);
197
198 switch (priv->dev->subsystem_device) {
199 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
200 if (idx == 3)
201 idx++;
202 break;
203 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
204 if (idx > 0)
205 idx++;
206 if (idx > 2)
207 idx++;
208 break;
209 }
210 if (idx > 2)
211 offset = 0x18;
212
213 offset += idx * board->uart_offset;
214
215 return setup_port(priv, port, bar, offset, board->reg_shift);
216 }
217
218 /*
219 * Added for EKF Intel i960 serial boards
220 */
221 static int pci_inteli960ni_init(struct pci_dev *dev)
222 {
223 unsigned long oldval;
224
225 if (!(dev->subsystem_device & 0x1000))
226 return -ENODEV;
227
228 /* is firmware started? */
229 pci_read_config_dword(dev, 0x44, (void *)&oldval);
230 if (oldval == 0x00001000L) { /* RESET value */
231 printk(KERN_DEBUG "Local i960 firmware missing");
232 return -ENODEV;
233 }
234 return 0;
235 }
236
237 /*
238 * Some PCI serial cards using the PLX 9050 PCI interface chip require
239 * that the card interrupt be explicitly enabled or disabled. This
240 * seems to be mainly needed on card using the PLX which also use I/O
241 * mapped memory.
242 */
243 static int pci_plx9050_init(struct pci_dev *dev)
244 {
245 u8 irq_config;
246 void __iomem *p;
247
248 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
249 moan_device("no memory in bar 0", dev);
250 return 0;
251 }
252
253 irq_config = 0x41;
254 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
255 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
256 irq_config = 0x43;
257
258 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
259 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
260 /*
261 * As the megawolf cards have the int pins active
262 * high, and have 2 UART chips, both ints must be
263 * enabled on the 9050. Also, the UARTS are set in
264 * 16450 mode by default, so we have to enable the
265 * 16C950 'enhanced' mode so that we can use the
266 * deep FIFOs
267 */
268 irq_config = 0x5b;
269 /*
270 * enable/disable interrupts
271 */
272 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
273 if (p == NULL)
274 return -ENOMEM;
275 writel(irq_config, p + 0x4c);
276
277 /*
278 * Read the register back to ensure that it took effect.
279 */
280 readl(p + 0x4c);
281 iounmap(p);
282
283 return 0;
284 }
285
286 static void __devexit pci_plx9050_exit(struct pci_dev *dev)
287 {
288 u8 __iomem *p;
289
290 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
291 return;
292
293 /*
294 * disable interrupts
295 */
296 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
297 if (p != NULL) {
298 writel(0, p + 0x4c);
299
300 /*
301 * Read the register back to ensure that it took effect.
302 */
303 readl(p + 0x4c);
304 iounmap(p);
305 }
306 }
307
308 #define NI8420_INT_ENABLE_REG 0x38
309 #define NI8420_INT_ENABLE_BIT 0x2000
310
311 static void __devexit pci_ni8420_exit(struct pci_dev *dev)
312 {
313 void __iomem *p;
314 unsigned long base, len;
315 unsigned int bar = 0;
316
317 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
318 moan_device("no memory in bar", dev);
319 return;
320 }
321
322 base = pci_resource_start(dev, bar);
323 len = pci_resource_len(dev, bar);
324 p = ioremap_nocache(base, len);
325 if (p == NULL)
326 return;
327
328 /* Disable the CPU Interrupt */
329 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
330 p + NI8420_INT_ENABLE_REG);
331 iounmap(p);
332 }
333
334
335 /* MITE registers */
336 #define MITE_IOWBSR1 0xc4
337 #define MITE_IOWCR1 0xf4
338 #define MITE_LCIMR1 0x08
339 #define MITE_LCIMR2 0x10
340
341 #define MITE_LCIMR2_CLR_CPU_IE (1 << 30)
342
343 static void __devexit pci_ni8430_exit(struct pci_dev *dev)
344 {
345 void __iomem *p;
346 unsigned long base, len;
347 unsigned int bar = 0;
348
349 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
350 moan_device("no memory in bar", dev);
351 return;
352 }
353
354 base = pci_resource_start(dev, bar);
355 len = pci_resource_len(dev, bar);
356 p = ioremap_nocache(base, len);
357 if (p == NULL)
358 return;
359
360 /* Disable the CPU Interrupt */
361 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
362 iounmap(p);
363 }
364
365 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
366 static int
367 sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
368 struct uart_port *port, int idx)
369 {
370 unsigned int bar, offset = board->first_offset;
371
372 bar = 0;
373
374 if (idx < 4) {
375 /* first four channels map to 0, 0x100, 0x200, 0x300 */
376 offset += idx * board->uart_offset;
377 } else if (idx < 8) {
378 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
379 offset += idx * board->uart_offset + 0xC00;
380 } else /* we have only 8 ports on PMC-OCTALPRO */
381 return 1;
382
383 return setup_port(priv, port, bar, offset, board->reg_shift);
384 }
385
386 /*
387 * This does initialization for PMC OCTALPRO cards:
388 * maps the device memory, resets the UARTs (needed, bc
389 * if the module is removed and inserted again, the card
390 * is in the sleep mode) and enables global interrupt.
391 */
392
393 /* global control register offset for SBS PMC-OctalPro */
394 #define OCT_REG_CR_OFF 0x500
395
396 static int sbs_init(struct pci_dev *dev)
397 {
398 u8 __iomem *p;
399
400 p = pci_ioremap_bar(dev, 0);
401
402 if (p == NULL)
403 return -ENOMEM;
404 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
405 writeb(0x10, p + OCT_REG_CR_OFF);
406 udelay(50);
407 writeb(0x0, p + OCT_REG_CR_OFF);
408
409 /* Set bit-2 (INTENABLE) of Control Register */
410 writeb(0x4, p + OCT_REG_CR_OFF);
411 iounmap(p);
412
413 return 0;
414 }
415
416 /*
417 * Disables the global interrupt of PMC-OctalPro
418 */
419
420 static void __devexit sbs_exit(struct pci_dev *dev)
421 {
422 u8 __iomem *p;
423
424 p = pci_ioremap_bar(dev, 0);
425 /* FIXME: What if resource_len < OCT_REG_CR_OFF */
426 if (p != NULL)
427 writeb(0, p + OCT_REG_CR_OFF);
428 iounmap(p);
429 }
430
431 /*
432 * SIIG serial cards have an PCI interface chip which also controls
433 * the UART clocking frequency. Each UART can be clocked independently
434 * (except cards equipped with 4 UARTs) and initial clocking settings
435 * are stored in the EEPROM chip. It can cause problems because this
436 * version of serial driver doesn't support differently clocked UART's
437 * on single PCI card. To prevent this, initialization functions set
438 * high frequency clocking for all UART's on given card. It is safe (I
439 * hope) because it doesn't touch EEPROM settings to prevent conflicts
440 * with other OSes (like M$ DOS).
441 *
442 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
443 *
444 * There is two family of SIIG serial cards with different PCI
445 * interface chip and different configuration methods:
446 * - 10x cards have control registers in IO and/or memory space;
447 * - 20x cards have control registers in standard PCI configuration space.
448 *
449 * Note: all 10x cards have PCI device ids 0x10..
450 * all 20x cards have PCI device ids 0x20..
451 *
452 * There are also Quartet Serial cards which use Oxford Semiconductor
453 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
454 *
455 * Note: some SIIG cards are probed by the parport_serial object.
456 */
457
458 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
459 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
460
461 static int pci_siig10x_init(struct pci_dev *dev)
462 {
463 u16 data;
464 void __iomem *p;
465
466 switch (dev->device & 0xfff8) {
467 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
468 data = 0xffdf;
469 break;
470 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
471 data = 0xf7ff;
472 break;
473 default: /* 1S1P, 4S */
474 data = 0xfffb;
475 break;
476 }
477
478 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
479 if (p == NULL)
480 return -ENOMEM;
481
482 writew(readw(p + 0x28) & data, p + 0x28);
483 readw(p + 0x28);
484 iounmap(p);
485 return 0;
486 }
487
488 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
489 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
490
491 static int pci_siig20x_init(struct pci_dev *dev)
492 {
493 u8 data;
494
495 /* Change clock frequency for the first UART. */
496 pci_read_config_byte(dev, 0x6f, &data);
497 pci_write_config_byte(dev, 0x6f, data & 0xef);
498
499 /* If this card has 2 UART, we have to do the same with second UART. */
500 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
501 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
502 pci_read_config_byte(dev, 0x73, &data);
503 pci_write_config_byte(dev, 0x73, data & 0xef);
504 }
505 return 0;
506 }
507
508 static int pci_siig_init(struct pci_dev *dev)
509 {
510 unsigned int type = dev->device & 0xff00;
511
512 if (type == 0x1000)
513 return pci_siig10x_init(dev);
514 else if (type == 0x2000)
515 return pci_siig20x_init(dev);
516
517 moan_device("Unknown SIIG card", dev);
518 return -ENODEV;
519 }
520
521 static int pci_siig_setup(struct serial_private *priv,
522 const struct pciserial_board *board,
523 struct uart_port *port, int idx)
524 {
525 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
526
527 if (idx > 3) {
528 bar = 4;
529 offset = (idx - 4) * 8;
530 }
531
532 return setup_port(priv, port, bar, offset, 0);
533 }
534
535 /*
536 * Timedia has an explosion of boards, and to avoid the PCI table from
537 * growing *huge*, we use this function to collapse some 70 entries
538 * in the PCI table into one, for sanity's and compactness's sake.
539 */
540 static const unsigned short timedia_single_port[] = {
541 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
542 };
543
544 static const unsigned short timedia_dual_port[] = {
545 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
546 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
547 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
548 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
549 0xD079, 0
550 };
551
552 static const unsigned short timedia_quad_port[] = {
553 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
554 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
555 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
556 0xB157, 0
557 };
558
559 static const unsigned short timedia_eight_port[] = {
560 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
561 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
562 };
563
564 static const struct timedia_struct {
565 int num;
566 const unsigned short *ids;
567 } timedia_data[] = {
568 { 1, timedia_single_port },
569 { 2, timedia_dual_port },
570 { 4, timedia_quad_port },
571 { 8, timedia_eight_port }
572 };
573
574 static int pci_timedia_init(struct pci_dev *dev)
575 {
576 const unsigned short *ids;
577 int i, j;
578
579 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
580 ids = timedia_data[i].ids;
581 for (j = 0; ids[j]; j++)
582 if (dev->subsystem_device == ids[j])
583 return timedia_data[i].num;
584 }
585 return 0;
586 }
587
588 /*
589 * Timedia/SUNIX uses a mixture of BARs and offsets
590 * Ugh, this is ugly as all hell --- TYT
591 */
592 static int
593 pci_timedia_setup(struct serial_private *priv,
594 const struct pciserial_board *board,
595 struct uart_port *port, int idx)
596 {
597 unsigned int bar = 0, offset = board->first_offset;
598
599 switch (idx) {
600 case 0:
601 bar = 0;
602 break;
603 case 1:
604 offset = board->uart_offset;
605 bar = 0;
606 break;
607 case 2:
608 bar = 1;
609 break;
610 case 3:
611 offset = board->uart_offset;
612 /* FALLTHROUGH */
613 case 4: /* BAR 2 */
614 case 5: /* BAR 3 */
615 case 6: /* BAR 4 */
616 case 7: /* BAR 5 */
617 bar = idx - 2;
618 }
619
620 return setup_port(priv, port, bar, offset, board->reg_shift);
621 }
622
623 /*
624 * Some Titan cards are also a little weird
625 */
626 static int
627 titan_400l_800l_setup(struct serial_private *priv,
628 const struct pciserial_board *board,
629 struct uart_port *port, int idx)
630 {
631 unsigned int bar, offset = board->first_offset;
632
633 switch (idx) {
634 case 0:
635 bar = 1;
636 break;
637 case 1:
638 bar = 2;
639 break;
640 default:
641 bar = 4;
642 offset = (idx - 2) * board->uart_offset;
643 }
644
645 return setup_port(priv, port, bar, offset, board->reg_shift);
646 }
647
648 static int pci_xircom_init(struct pci_dev *dev)
649 {
650 msleep(100);
651 return 0;
652 }
653
654 static int pci_ni8420_init(struct pci_dev *dev)
655 {
656 void __iomem *p;
657 unsigned long base, len;
658 unsigned int bar = 0;
659
660 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
661 moan_device("no memory in bar", dev);
662 return 0;
663 }
664
665 base = pci_resource_start(dev, bar);
666 len = pci_resource_len(dev, bar);
667 p = ioremap_nocache(base, len);
668 if (p == NULL)
669 return -ENOMEM;
670
671 /* Enable CPU Interrupt */
672 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
673 p + NI8420_INT_ENABLE_REG);
674
675 iounmap(p);
676 return 0;
677 }
678
679 #define MITE_IOWBSR1_WSIZE 0xa
680 #define MITE_IOWBSR1_WIN_OFFSET 0x800
681 #define MITE_IOWBSR1_WENAB (1 << 7)
682 #define MITE_LCIMR1_IO_IE_0 (1 << 24)
683 #define MITE_LCIMR2_SET_CPU_IE (1 << 31)
684 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
685
686 static int pci_ni8430_init(struct pci_dev *dev)
687 {
688 void __iomem *p;
689 unsigned long base, len;
690 u32 device_window;
691 unsigned int bar = 0;
692
693 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
694 moan_device("no memory in bar", dev);
695 return 0;
696 }
697
698 base = pci_resource_start(dev, bar);
699 len = pci_resource_len(dev, bar);
700 p = ioremap_nocache(base, len);
701 if (p == NULL)
702 return -ENOMEM;
703
704 /* Set device window address and size in BAR0 */
705 device_window = ((base + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
706 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
707 writel(device_window, p + MITE_IOWBSR1);
708
709 /* Set window access to go to RAMSEL IO address space */
710 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
711 p + MITE_IOWCR1);
712
713 /* Enable IO Bus Interrupt 0 */
714 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
715
716 /* Enable CPU Interrupt */
717 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
718
719 iounmap(p);
720 return 0;
721 }
722
723 /* UART Port Control Register */
724 #define NI8430_PORTCON 0x0f
725 #define NI8430_PORTCON_TXVR_ENABLE (1 << 3)
726
727 static int
728 pci_ni8430_setup(struct serial_private *priv,
729 const struct pciserial_board *board,
730 struct uart_port *port, int idx)
731 {
732 void __iomem *p;
733 unsigned long base, len;
734 unsigned int bar, offset = board->first_offset;
735
736 if (idx >= board->num_ports)
737 return 1;
738
739 bar = FL_GET_BASE(board->flags);
740 offset += idx * board->uart_offset;
741
742 base = pci_resource_start(priv->dev, bar);
743 len = pci_resource_len(priv->dev, bar);
744 p = ioremap_nocache(base, len);
745
746 /* enable the transciever */
747 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
748 p + offset + NI8430_PORTCON);
749
750 iounmap(p);
751
752 return setup_port(priv, port, bar, offset, board->reg_shift);
753 }
754
755
756 static int pci_netmos_init(struct pci_dev *dev)
757 {
758 /* subdevice 0x00PS means <P> parallel, <S> serial */
759 unsigned int num_serial = dev->subsystem_device & 0xf;
760
761 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
762 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
763 return 0;
764 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
765 dev->subsystem_device == 0x0299)
766 return 0;
767
768 if (num_serial == 0)
769 return -ENODEV;
770 return num_serial;
771 }
772
773 /*
774 * These chips are available with optionally one parallel port and up to
775 * two serial ports. Unfortunately they all have the same product id.
776 *
777 * Basic configuration is done over a region of 32 I/O ports. The base
778 * ioport is called INTA or INTC, depending on docs/other drivers.
779 *
780 * The region of the 32 I/O ports is configured in POSIO0R...
781 */
782
783 /* registers */
784 #define ITE_887x_MISCR 0x9c
785 #define ITE_887x_INTCBAR 0x78
786 #define ITE_887x_UARTBAR 0x7c
787 #define ITE_887x_PS0BAR 0x10
788 #define ITE_887x_POSIO0 0x60
789
790 /* I/O space size */
791 #define ITE_887x_IOSIZE 32
792 /* I/O space size (bits 26-24; 8 bytes = 011b) */
793 #define ITE_887x_POSIO_IOSIZE_8 (3 << 24)
794 /* I/O space size (bits 26-24; 32 bytes = 101b) */
795 #define ITE_887x_POSIO_IOSIZE_32 (5 << 24)
796 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
797 #define ITE_887x_POSIO_SPEED (3 << 29)
798 /* enable IO_Space bit */
799 #define ITE_887x_POSIO_ENABLE (1 << 31)
800
801 static int pci_ite887x_init(struct pci_dev *dev)
802 {
803 /* inta_addr are the configuration addresses of the ITE */
804 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
805 0x200, 0x280, 0 };
806 int ret, i, type;
807 struct resource *iobase = NULL;
808 u32 miscr, uartbar, ioport;
809
810 /* search for the base-ioport */
811 i = 0;
812 while (inta_addr[i] && iobase == NULL) {
813 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
814 "ite887x");
815 if (iobase != NULL) {
816 /* write POSIO0R - speed | size | ioport */
817 pci_write_config_dword(dev, ITE_887x_POSIO0,
818 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
819 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
820 /* write INTCBAR - ioport */
821 pci_write_config_dword(dev, ITE_887x_INTCBAR,
822 inta_addr[i]);
823 ret = inb(inta_addr[i]);
824 if (ret != 0xff) {
825 /* ioport connected */
826 break;
827 }
828 release_region(iobase->start, ITE_887x_IOSIZE);
829 iobase = NULL;
830 }
831 i++;
832 }
833
834 if (!inta_addr[i]) {
835 printk(KERN_ERR "ite887x: could not find iobase\n");
836 return -ENODEV;
837 }
838
839 /* start of undocumented type checking (see parport_pc.c) */
840 type = inb(iobase->start + 0x18) & 0x0f;
841
842 switch (type) {
843 case 0x2: /* ITE8871 (1P) */
844 case 0xa: /* ITE8875 (1P) */
845 ret = 0;
846 break;
847 case 0xe: /* ITE8872 (2S1P) */
848 ret = 2;
849 break;
850 case 0x6: /* ITE8873 (1S) */
851 ret = 1;
852 break;
853 case 0x8: /* ITE8874 (2S) */
854 ret = 2;
855 break;
856 default:
857 moan_device("Unknown ITE887x", dev);
858 ret = -ENODEV;
859 }
860
861 /* configure all serial ports */
862 for (i = 0; i < ret; i++) {
863 /* read the I/O port from the device */
864 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
865 &ioport);
866 ioport &= 0x0000FF00; /* the actual base address */
867 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
868 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
869 ITE_887x_POSIO_IOSIZE_8 | ioport);
870
871 /* write the ioport to the UARTBAR */
872 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
873 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */
874 uartbar |= (ioport << (16 * i)); /* set the ioport */
875 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
876
877 /* get current config */
878 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
879 /* disable interrupts (UARTx_Routing[3:0]) */
880 miscr &= ~(0xf << (12 - 4 * i));
881 /* activate the UART (UARTx_En) */
882 miscr |= 1 << (23 - i);
883 /* write new config with activated UART */
884 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
885 }
886
887 if (ret <= 0) {
888 /* the device has no UARTs if we get here */
889 release_region(iobase->start, ITE_887x_IOSIZE);
890 }
891
892 return ret;
893 }
894
895 static void __devexit pci_ite887x_exit(struct pci_dev *dev)
896 {
897 u32 ioport;
898 /* the ioport is bit 0-15 in POSIO0R */
899 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
900 ioport &= 0xffff;
901 release_region(ioport, ITE_887x_IOSIZE);
902 }
903
904 /*
905 * Oxford Semiconductor Inc.
906 * Check that device is part of the Tornado range of devices, then determine
907 * the number of ports available on the device.
908 */
909 static int pci_oxsemi_tornado_init(struct pci_dev *dev)
910 {
911 u8 __iomem *p;
912 unsigned long deviceID;
913 unsigned int number_uarts = 0;
914
915 /* OxSemi Tornado devices are all 0xCxxx */
916 if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
917 (dev->device & 0xF000) != 0xC000)
918 return 0;
919
920 p = pci_iomap(dev, 0, 5);
921 if (p == NULL)
922 return -ENOMEM;
923
924 deviceID = ioread32(p);
925 /* Tornado device */
926 if (deviceID == 0x07000200) {
927 number_uarts = ioread8(p + 4);
928 printk(KERN_DEBUG
929 "%d ports detected on Oxford PCI Express device\n",
930 number_uarts);
931 }
932 pci_iounmap(dev, p);
933 return number_uarts;
934 }
935
936 static int
937 pci_default_setup(struct serial_private *priv,
938 const struct pciserial_board *board,
939 struct uart_port *port, int idx)
940 {
941 unsigned int bar, offset = board->first_offset, maxnr;
942
943 bar = FL_GET_BASE(board->flags);
944 if (board->flags & FL_BASE_BARS)
945 bar += idx;
946 else
947 offset += idx * board->uart_offset;
948
949 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
950 (board->reg_shift + 3);
951
952 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
953 return 1;
954
955 return setup_port(priv, port, bar, offset, board->reg_shift);
956 }
957
958 static int
959 ce4100_serial_setup(struct serial_private *priv,
960 const struct pciserial_board *board,
961 struct uart_port *port, int idx)
962 {
963 int ret;
964
965 ret = setup_port(priv, port, 0, 0, board->reg_shift);
966 port->iotype = UPIO_MEM32;
967 port->type = PORT_XSCALE;
968 port->flags = (port->flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
969 port->regshift = 2;
970
971 return ret;
972 }
973
974 static int
975 pci_omegapci_setup(struct serial_private *priv,
976 const struct pciserial_board *board,
977 struct uart_port *port, int idx)
978 {
979 return setup_port(priv, port, 2, idx * 8, 0);
980 }
981
982 static int skip_tx_en_setup(struct serial_private *priv,
983 const struct pciserial_board *board,
984 struct uart_port *port, int idx)
985 {
986 port->flags |= UPF_NO_TXEN_TEST;
987 printk(KERN_DEBUG "serial8250: skipping TxEn test for device "
988 "[%04x:%04x] subsystem [%04x:%04x]\n",
989 priv->dev->vendor,
990 priv->dev->device,
991 priv->dev->subsystem_vendor,
992 priv->dev->subsystem_device);
993
994 return pci_default_setup(priv, board, port, idx);
995 }
996
997 static int pci_eg20t_init(struct pci_dev *dev)
998 {
999 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1000 return -ENODEV;
1001 #else
1002 return 0;
1003 #endif
1004 }
1005
1006 /* This should be in linux/pci_ids.h */
1007 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B
1008 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
1009 #define PCI_DEVICE_ID_OCTPRO 0x0001
1010 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
1011 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
1012 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308
1013 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408
1014 #define PCI_VENDOR_ID_ADVANTECH 0x13fe
1015 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
1016 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
1017 #define PCI_DEVICE_ID_TITAN_200I 0x8028
1018 #define PCI_DEVICE_ID_TITAN_400I 0x8048
1019 #define PCI_DEVICE_ID_TITAN_800I 0x8088
1020 #define PCI_DEVICE_ID_TITAN_800EH 0xA007
1021 #define PCI_DEVICE_ID_TITAN_800EHB 0xA008
1022 #define PCI_DEVICE_ID_TITAN_400EH 0xA009
1023 #define PCI_DEVICE_ID_TITAN_100E 0xA010
1024 #define PCI_DEVICE_ID_TITAN_200E 0xA012
1025 #define PCI_DEVICE_ID_TITAN_400E 0xA013
1026 #define PCI_DEVICE_ID_TITAN_800E 0xA014
1027 #define PCI_DEVICE_ID_TITAN_200EI 0xA016
1028 #define PCI_DEVICE_ID_TITAN_200EISI 0xA017
1029 #define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538
1030 #define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6
1031 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001
1032
1033 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */
1034 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
1035
1036 /*
1037 * Master list of serial port init/setup/exit quirks.
1038 * This does not describe the general nature of the port.
1039 * (ie, baud base, number and location of ports, etc)
1040 *
1041 * This list is ordered alphabetically by vendor then device.
1042 * Specific entries must come before more generic entries.
1043 */
1044 static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
1045 /*
1046 * ADDI-DATA GmbH communication cards <info@addi-data.com>
1047 */
1048 {
1049 .vendor = PCI_VENDOR_ID_ADDIDATA_OLD,
1050 .device = PCI_DEVICE_ID_ADDIDATA_APCI7800,
1051 .subvendor = PCI_ANY_ID,
1052 .subdevice = PCI_ANY_ID,
1053 .setup = addidata_apci7800_setup,
1054 },
1055 /*
1056 * AFAVLAB cards - these may be called via parport_serial
1057 * It is not clear whether this applies to all products.
1058 */
1059 {
1060 .vendor = PCI_VENDOR_ID_AFAVLAB,
1061 .device = PCI_ANY_ID,
1062 .subvendor = PCI_ANY_ID,
1063 .subdevice = PCI_ANY_ID,
1064 .setup = afavlab_setup,
1065 },
1066 /*
1067 * HP Diva
1068 */
1069 {
1070 .vendor = PCI_VENDOR_ID_HP,
1071 .device = PCI_DEVICE_ID_HP_DIVA,
1072 .subvendor = PCI_ANY_ID,
1073 .subdevice = PCI_ANY_ID,
1074 .init = pci_hp_diva_init,
1075 .setup = pci_hp_diva_setup,
1076 },
1077 /*
1078 * Intel
1079 */
1080 {
1081 .vendor = PCI_VENDOR_ID_INTEL,
1082 .device = PCI_DEVICE_ID_INTEL_80960_RP,
1083 .subvendor = 0xe4bf,
1084 .subdevice = PCI_ANY_ID,
1085 .init = pci_inteli960ni_init,
1086 .setup = pci_default_setup,
1087 },
1088 {
1089 .vendor = PCI_VENDOR_ID_INTEL,
1090 .device = PCI_DEVICE_ID_INTEL_8257X_SOL,
1091 .subvendor = PCI_ANY_ID,
1092 .subdevice = PCI_ANY_ID,
1093 .setup = skip_tx_en_setup,
1094 },
1095 {
1096 .vendor = PCI_VENDOR_ID_INTEL,
1097 .device = PCI_DEVICE_ID_INTEL_82573L_SOL,
1098 .subvendor = PCI_ANY_ID,
1099 .subdevice = PCI_ANY_ID,
1100 .setup = skip_tx_en_setup,
1101 },
1102 {
1103 .vendor = PCI_VENDOR_ID_INTEL,
1104 .device = PCI_DEVICE_ID_INTEL_82573E_SOL,
1105 .subvendor = PCI_ANY_ID,
1106 .subdevice = PCI_ANY_ID,
1107 .setup = skip_tx_en_setup,
1108 },
1109 {
1110 .vendor = PCI_VENDOR_ID_INTEL,
1111 .device = PCI_DEVICE_ID_INTEL_CE4100_UART,
1112 .subvendor = PCI_ANY_ID,
1113 .subdevice = PCI_ANY_ID,
1114 .setup = ce4100_serial_setup,
1115 },
1116 /*
1117 * ITE
1118 */
1119 {
1120 .vendor = PCI_VENDOR_ID_ITE,
1121 .device = PCI_DEVICE_ID_ITE_8872,
1122 .subvendor = PCI_ANY_ID,
1123 .subdevice = PCI_ANY_ID,
1124 .init = pci_ite887x_init,
1125 .setup = pci_default_setup,
1126 .exit = __devexit_p(pci_ite887x_exit),
1127 },
1128 /*
1129 * National Instruments
1130 */
1131 {
1132 .vendor = PCI_VENDOR_ID_NI,
1133 .device = PCI_DEVICE_ID_NI_PCI23216,
1134 .subvendor = PCI_ANY_ID,
1135 .subdevice = PCI_ANY_ID,
1136 .init = pci_ni8420_init,
1137 .setup = pci_default_setup,
1138 .exit = __devexit_p(pci_ni8420_exit),
1139 },
1140 {
1141 .vendor = PCI_VENDOR_ID_NI,
1142 .device = PCI_DEVICE_ID_NI_PCI2328,
1143 .subvendor = PCI_ANY_ID,
1144 .subdevice = PCI_ANY_ID,
1145 .init = pci_ni8420_init,
1146 .setup = pci_default_setup,
1147 .exit = __devexit_p(pci_ni8420_exit),
1148 },
1149 {
1150 .vendor = PCI_VENDOR_ID_NI,
1151 .device = PCI_DEVICE_ID_NI_PCI2324,
1152 .subvendor = PCI_ANY_ID,
1153 .subdevice = PCI_ANY_ID,
1154 .init = pci_ni8420_init,
1155 .setup = pci_default_setup,
1156 .exit = __devexit_p(pci_ni8420_exit),
1157 },
1158 {
1159 .vendor = PCI_VENDOR_ID_NI,
1160 .device = PCI_DEVICE_ID_NI_PCI2322,
1161 .subvendor = PCI_ANY_ID,
1162 .subdevice = PCI_ANY_ID,
1163 .init = pci_ni8420_init,
1164 .setup = pci_default_setup,
1165 .exit = __devexit_p(pci_ni8420_exit),
1166 },
1167 {
1168 .vendor = PCI_VENDOR_ID_NI,
1169 .device = PCI_DEVICE_ID_NI_PCI2324I,
1170 .subvendor = PCI_ANY_ID,
1171 .subdevice = PCI_ANY_ID,
1172 .init = pci_ni8420_init,
1173 .setup = pci_default_setup,
1174 .exit = __devexit_p(pci_ni8420_exit),
1175 },
1176 {
1177 .vendor = PCI_VENDOR_ID_NI,
1178 .device = PCI_DEVICE_ID_NI_PCI2322I,
1179 .subvendor = PCI_ANY_ID,
1180 .subdevice = PCI_ANY_ID,
1181 .init = pci_ni8420_init,
1182 .setup = pci_default_setup,
1183 .exit = __devexit_p(pci_ni8420_exit),
1184 },
1185 {
1186 .vendor = PCI_VENDOR_ID_NI,
1187 .device = PCI_DEVICE_ID_NI_PXI8420_23216,
1188 .subvendor = PCI_ANY_ID,
1189 .subdevice = PCI_ANY_ID,
1190 .init = pci_ni8420_init,
1191 .setup = pci_default_setup,
1192 .exit = __devexit_p(pci_ni8420_exit),
1193 },
1194 {
1195 .vendor = PCI_VENDOR_ID_NI,
1196 .device = PCI_DEVICE_ID_NI_PXI8420_2328,
1197 .subvendor = PCI_ANY_ID,
1198 .subdevice = PCI_ANY_ID,
1199 .init = pci_ni8420_init,
1200 .setup = pci_default_setup,
1201 .exit = __devexit_p(pci_ni8420_exit),
1202 },
1203 {
1204 .vendor = PCI_VENDOR_ID_NI,
1205 .device = PCI_DEVICE_ID_NI_PXI8420_2324,
1206 .subvendor = PCI_ANY_ID,
1207 .subdevice = PCI_ANY_ID,
1208 .init = pci_ni8420_init,
1209 .setup = pci_default_setup,
1210 .exit = __devexit_p(pci_ni8420_exit),
1211 },
1212 {
1213 .vendor = PCI_VENDOR_ID_NI,
1214 .device = PCI_DEVICE_ID_NI_PXI8420_2322,
1215 .subvendor = PCI_ANY_ID,
1216 .subdevice = PCI_ANY_ID,
1217 .init = pci_ni8420_init,
1218 .setup = pci_default_setup,
1219 .exit = __devexit_p(pci_ni8420_exit),
1220 },
1221 {
1222 .vendor = PCI_VENDOR_ID_NI,
1223 .device = PCI_DEVICE_ID_NI_PXI8422_2324,
1224 .subvendor = PCI_ANY_ID,
1225 .subdevice = PCI_ANY_ID,
1226 .init = pci_ni8420_init,
1227 .setup = pci_default_setup,
1228 .exit = __devexit_p(pci_ni8420_exit),
1229 },
1230 {
1231 .vendor = PCI_VENDOR_ID_NI,
1232 .device = PCI_DEVICE_ID_NI_PXI8422_2322,
1233 .subvendor = PCI_ANY_ID,
1234 .subdevice = PCI_ANY_ID,
1235 .init = pci_ni8420_init,
1236 .setup = pci_default_setup,
1237 .exit = __devexit_p(pci_ni8420_exit),
1238 },
1239 {
1240 .vendor = PCI_VENDOR_ID_NI,
1241 .device = PCI_ANY_ID,
1242 .subvendor = PCI_ANY_ID,
1243 .subdevice = PCI_ANY_ID,
1244 .init = pci_ni8430_init,
1245 .setup = pci_ni8430_setup,
1246 .exit = __devexit_p(pci_ni8430_exit),
1247 },
1248 /*
1249 * Panacom
1250 */
1251 {
1252 .vendor = PCI_VENDOR_ID_PANACOM,
1253 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
1254 .subvendor = PCI_ANY_ID,
1255 .subdevice = PCI_ANY_ID,
1256 .init = pci_plx9050_init,
1257 .setup = pci_default_setup,
1258 .exit = __devexit_p(pci_plx9050_exit),
1259 },
1260 {
1261 .vendor = PCI_VENDOR_ID_PANACOM,
1262 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
1263 .subvendor = PCI_ANY_ID,
1264 .subdevice = PCI_ANY_ID,
1265 .init = pci_plx9050_init,
1266 .setup = pci_default_setup,
1267 .exit = __devexit_p(pci_plx9050_exit),
1268 },
1269 /*
1270 * PLX
1271 */
1272 {
1273 .vendor = PCI_VENDOR_ID_PLX,
1274 .device = PCI_DEVICE_ID_PLX_9030,
1275 .subvendor = PCI_SUBVENDOR_ID_PERLE,
1276 .subdevice = PCI_ANY_ID,
1277 .setup = pci_default_setup,
1278 },
1279 {
1280 .vendor = PCI_VENDOR_ID_PLX,
1281 .device = PCI_DEVICE_ID_PLX_9050,
1282 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
1283 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
1284 .init = pci_plx9050_init,
1285 .setup = pci_default_setup,
1286 .exit = __devexit_p(pci_plx9050_exit),
1287 },
1288 {
1289 .vendor = PCI_VENDOR_ID_PLX,
1290 .device = PCI_DEVICE_ID_PLX_9050,
1291 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
1292 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
1293 .init = pci_plx9050_init,
1294 .setup = pci_default_setup,
1295 .exit = __devexit_p(pci_plx9050_exit),
1296 },
1297 {
1298 .vendor = PCI_VENDOR_ID_PLX,
1299 .device = PCI_DEVICE_ID_PLX_9050,
1300 .subvendor = PCI_VENDOR_ID_PLX,
1301 .subdevice = PCI_SUBDEVICE_ID_UNKNOWN_0x1584,
1302 .init = pci_plx9050_init,
1303 .setup = pci_default_setup,
1304 .exit = __devexit_p(pci_plx9050_exit),
1305 },
1306 {
1307 .vendor = PCI_VENDOR_ID_PLX,
1308 .device = PCI_DEVICE_ID_PLX_ROMULUS,
1309 .subvendor = PCI_VENDOR_ID_PLX,
1310 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
1311 .init = pci_plx9050_init,
1312 .setup = pci_default_setup,
1313 .exit = __devexit_p(pci_plx9050_exit),
1314 },
1315 /*
1316 * SBS Technologies, Inc., PMC-OCTALPRO 232
1317 */
1318 {
1319 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1320 .device = PCI_DEVICE_ID_OCTPRO,
1321 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1322 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
1323 .init = sbs_init,
1324 .setup = sbs_setup,
1325 .exit = __devexit_p(sbs_exit),
1326 },
1327 /*
1328 * SBS Technologies, Inc., PMC-OCTALPRO 422
1329 */
1330 {
1331 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1332 .device = PCI_DEVICE_ID_OCTPRO,
1333 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1334 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
1335 .init = sbs_init,
1336 .setup = sbs_setup,
1337 .exit = __devexit_p(sbs_exit),
1338 },
1339 /*
1340 * SBS Technologies, Inc., P-Octal 232
1341 */
1342 {
1343 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1344 .device = PCI_DEVICE_ID_OCTPRO,
1345 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1346 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
1347 .init = sbs_init,
1348 .setup = sbs_setup,
1349 .exit = __devexit_p(sbs_exit),
1350 },
1351 /*
1352 * SBS Technologies, Inc., P-Octal 422
1353 */
1354 {
1355 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1356 .device = PCI_DEVICE_ID_OCTPRO,
1357 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1358 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
1359 .init = sbs_init,
1360 .setup = sbs_setup,
1361 .exit = __devexit_p(sbs_exit),
1362 },
1363 /*
1364 * SIIG cards - these may be called via parport_serial
1365 */
1366 {
1367 .vendor = PCI_VENDOR_ID_SIIG,
1368 .device = PCI_ANY_ID,
1369 .subvendor = PCI_ANY_ID,
1370 .subdevice = PCI_ANY_ID,
1371 .init = pci_siig_init,
1372 .setup = pci_siig_setup,
1373 },
1374 /*
1375 * Titan cards
1376 */
1377 {
1378 .vendor = PCI_VENDOR_ID_TITAN,
1379 .device = PCI_DEVICE_ID_TITAN_400L,
1380 .subvendor = PCI_ANY_ID,
1381 .subdevice = PCI_ANY_ID,
1382 .setup = titan_400l_800l_setup,
1383 },
1384 {
1385 .vendor = PCI_VENDOR_ID_TITAN,
1386 .device = PCI_DEVICE_ID_TITAN_800L,
1387 .subvendor = PCI_ANY_ID,
1388 .subdevice = PCI_ANY_ID,
1389 .setup = titan_400l_800l_setup,
1390 },
1391 /*
1392 * Timedia cards
1393 */
1394 {
1395 .vendor = PCI_VENDOR_ID_TIMEDIA,
1396 .device = PCI_DEVICE_ID_TIMEDIA_1889,
1397 .subvendor = PCI_VENDOR_ID_TIMEDIA,
1398 .subdevice = PCI_ANY_ID,
1399 .init = pci_timedia_init,
1400 .setup = pci_timedia_setup,
1401 },
1402 {
1403 .vendor = PCI_VENDOR_ID_TIMEDIA,
1404 .device = PCI_ANY_ID,
1405 .subvendor = PCI_ANY_ID,
1406 .subdevice = PCI_ANY_ID,
1407 .setup = pci_timedia_setup,
1408 },
1409 /*
1410 * Xircom cards
1411 */
1412 {
1413 .vendor = PCI_VENDOR_ID_XIRCOM,
1414 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
1415 .subvendor = PCI_ANY_ID,
1416 .subdevice = PCI_ANY_ID,
1417 .init = pci_xircom_init,
1418 .setup = pci_default_setup,
1419 },
1420 /*
1421 * Netmos cards - these may be called via parport_serial
1422 */
1423 {
1424 .vendor = PCI_VENDOR_ID_NETMOS,
1425 .device = PCI_ANY_ID,
1426 .subvendor = PCI_ANY_ID,
1427 .subdevice = PCI_ANY_ID,
1428 .init = pci_netmos_init,
1429 .setup = pci_default_setup,
1430 },
1431 /*
1432 * For Oxford Semiconductor Tornado based devices
1433 */
1434 {
1435 .vendor = PCI_VENDOR_ID_OXSEMI,
1436 .device = PCI_ANY_ID,
1437 .subvendor = PCI_ANY_ID,
1438 .subdevice = PCI_ANY_ID,
1439 .init = pci_oxsemi_tornado_init,
1440 .setup = pci_default_setup,
1441 },
1442 {
1443 .vendor = PCI_VENDOR_ID_MAINPINE,
1444 .device = PCI_ANY_ID,
1445 .subvendor = PCI_ANY_ID,
1446 .subdevice = PCI_ANY_ID,
1447 .init = pci_oxsemi_tornado_init,
1448 .setup = pci_default_setup,
1449 },
1450 {
1451 .vendor = PCI_VENDOR_ID_DIGI,
1452 .device = PCIE_DEVICE_ID_NEO_2_OX_IBM,
1453 .subvendor = PCI_SUBVENDOR_ID_IBM,
1454 .subdevice = PCI_ANY_ID,
1455 .init = pci_oxsemi_tornado_init,
1456 .setup = pci_default_setup,
1457 },
1458 {
1459 .vendor = PCI_VENDOR_ID_INTEL,
1460 .device = 0x8811,
1461 .init = pci_eg20t_init,
1462 },
1463 {
1464 .vendor = PCI_VENDOR_ID_INTEL,
1465 .device = 0x8812,
1466 .init = pci_eg20t_init,
1467 },
1468 {
1469 .vendor = PCI_VENDOR_ID_INTEL,
1470 .device = 0x8813,
1471 .init = pci_eg20t_init,
1472 },
1473 {
1474 .vendor = PCI_VENDOR_ID_INTEL,
1475 .device = 0x8814,
1476 .init = pci_eg20t_init,
1477 },
1478 {
1479 .vendor = 0x10DB,
1480 .device = 0x8027,
1481 .init = pci_eg20t_init,
1482 },
1483 {
1484 .vendor = 0x10DB,
1485 .device = 0x8028,
1486 .init = pci_eg20t_init,
1487 },
1488 {
1489 .vendor = 0x10DB,
1490 .device = 0x8029,
1491 .init = pci_eg20t_init,
1492 },
1493 {
1494 .vendor = 0x10DB,
1495 .device = 0x800C,
1496 .init = pci_eg20t_init,
1497 },
1498 {
1499 .vendor = 0x10DB,
1500 .device = 0x800D,
1501 .init = pci_eg20t_init,
1502 },
1503 {
1504 .vendor = 0x10DB,
1505 .device = 0x800D,
1506 .init = pci_eg20t_init,
1507 },
1508 /*
1509 * Cronyx Omega PCI (PLX-chip based)
1510 */
1511 {
1512 .vendor = PCI_VENDOR_ID_PLX,
1513 .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
1514 .subvendor = PCI_ANY_ID,
1515 .subdevice = PCI_ANY_ID,
1516 .setup = pci_omegapci_setup,
1517 },
1518 /*
1519 * Default "match everything" terminator entry
1520 */
1521 {
1522 .vendor = PCI_ANY_ID,
1523 .device = PCI_ANY_ID,
1524 .subvendor = PCI_ANY_ID,
1525 .subdevice = PCI_ANY_ID,
1526 .setup = pci_default_setup,
1527 }
1528 };
1529
1530 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
1531 {
1532 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
1533 }
1534
1535 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
1536 {
1537 struct pci_serial_quirk *quirk;
1538
1539 for (quirk = pci_serial_quirks; ; quirk++)
1540 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
1541 quirk_id_matches(quirk->device, dev->device) &&
1542 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
1543 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
1544 break;
1545 return quirk;
1546 }
1547
1548 static inline int get_pci_irq(struct pci_dev *dev,
1549 const struct pciserial_board *board)
1550 {
1551 if (board->flags & FL_NOIRQ)
1552 return 0;
1553 else
1554 return dev->irq;
1555 }
1556
1557 /*
1558 * This is the configuration table for all of the PCI serial boards
1559 * which we support. It is directly indexed by the pci_board_num_t enum
1560 * value, which is encoded in the pci_device_id PCI probe table's
1561 * driver_data member.
1562 *
1563 * The makeup of these names are:
1564 * pbn_bn{_bt}_n_baud{_offsetinhex}
1565 *
1566 * bn = PCI BAR number
1567 * bt = Index using PCI BARs
1568 * n = number of serial ports
1569 * baud = baud rate
1570 * offsetinhex = offset for each sequential port (in hex)
1571 *
1572 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
1573 *
1574 * Please note: in theory if n = 1, _bt infix should make no difference.
1575 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
1576 */
1577 enum pci_board_num_t {
1578 pbn_default = 0,
1579
1580 pbn_b0_1_115200,
1581 pbn_b0_2_115200,
1582 pbn_b0_4_115200,
1583 pbn_b0_5_115200,
1584 pbn_b0_8_115200,
1585
1586 pbn_b0_1_921600,
1587 pbn_b0_2_921600,
1588 pbn_b0_4_921600,
1589
1590 pbn_b0_2_1130000,
1591
1592 pbn_b0_4_1152000,
1593
1594 pbn_b0_2_1843200,
1595 pbn_b0_4_1843200,
1596
1597 pbn_b0_2_1843200_200,
1598 pbn_b0_4_1843200_200,
1599 pbn_b0_8_1843200_200,
1600
1601 pbn_b0_1_4000000,
1602
1603 pbn_b0_bt_1_115200,
1604 pbn_b0_bt_2_115200,
1605 pbn_b0_bt_4_115200,
1606 pbn_b0_bt_8_115200,
1607
1608 pbn_b0_bt_1_460800,
1609 pbn_b0_bt_2_460800,
1610 pbn_b0_bt_4_460800,
1611
1612 pbn_b0_bt_1_921600,
1613 pbn_b0_bt_2_921600,
1614 pbn_b0_bt_4_921600,
1615 pbn_b0_bt_8_921600,
1616
1617 pbn_b1_1_115200,
1618 pbn_b1_2_115200,
1619 pbn_b1_4_115200,
1620 pbn_b1_8_115200,
1621 pbn_b1_16_115200,
1622
1623 pbn_b1_1_921600,
1624 pbn_b1_2_921600,
1625 pbn_b1_4_921600,
1626 pbn_b1_8_921600,
1627
1628 pbn_b1_2_1250000,
1629
1630 pbn_b1_bt_1_115200,
1631 pbn_b1_bt_2_115200,
1632 pbn_b1_bt_4_115200,
1633
1634 pbn_b1_bt_2_921600,
1635
1636 pbn_b1_1_1382400,
1637 pbn_b1_2_1382400,
1638 pbn_b1_4_1382400,
1639 pbn_b1_8_1382400,
1640
1641 pbn_b2_1_115200,
1642 pbn_b2_2_115200,
1643 pbn_b2_4_115200,
1644 pbn_b2_8_115200,
1645
1646 pbn_b2_1_460800,
1647 pbn_b2_4_460800,
1648 pbn_b2_8_460800,
1649 pbn_b2_16_460800,
1650
1651 pbn_b2_1_921600,
1652 pbn_b2_4_921600,
1653 pbn_b2_8_921600,
1654
1655 pbn_b2_8_1152000,
1656
1657 pbn_b2_bt_1_115200,
1658 pbn_b2_bt_2_115200,
1659 pbn_b2_bt_4_115200,
1660
1661 pbn_b2_bt_2_921600,
1662 pbn_b2_bt_4_921600,
1663
1664 pbn_b3_2_115200,
1665 pbn_b3_4_115200,
1666 pbn_b3_8_115200,
1667
1668 pbn_b4_bt_2_921600,
1669 pbn_b4_bt_4_921600,
1670 pbn_b4_bt_8_921600,
1671
1672 /*
1673 * Board-specific versions.
1674 */
1675 pbn_panacom,
1676 pbn_panacom2,
1677 pbn_panacom4,
1678 pbn_exsys_4055,
1679 pbn_plx_romulus,
1680 pbn_oxsemi,
1681 pbn_oxsemi_1_4000000,
1682 pbn_oxsemi_2_4000000,
1683 pbn_oxsemi_4_4000000,
1684 pbn_oxsemi_8_4000000,
1685 pbn_intel_i960,
1686 pbn_sgi_ioc3,
1687 pbn_computone_4,
1688 pbn_computone_6,
1689 pbn_computone_8,
1690 pbn_sbsxrsio,
1691 pbn_exar_XR17C152,
1692 pbn_exar_XR17C154,
1693 pbn_exar_XR17C158,
1694 pbn_exar_ibm_saturn,
1695 pbn_pasemi_1682M,
1696 pbn_ni8430_2,
1697 pbn_ni8430_4,
1698 pbn_ni8430_8,
1699 pbn_ni8430_16,
1700 pbn_ADDIDATA_PCIe_1_3906250,
1701 pbn_ADDIDATA_PCIe_2_3906250,
1702 pbn_ADDIDATA_PCIe_4_3906250,
1703 pbn_ADDIDATA_PCIe_8_3906250,
1704 pbn_ce4100_1_115200,
1705 pbn_omegapci,
1706 };
1707
1708 /*
1709 * uart_offset - the space between channels
1710 * reg_shift - describes how the UART registers are mapped
1711 * to PCI memory by the card.
1712 * For example IER register on SBS, Inc. PMC-OctPro is located at
1713 * offset 0x10 from the UART base, while UART_IER is defined as 1
1714 * in include/linux/serial_reg.h,
1715 * see first lines of serial_in() and serial_out() in 8250.c
1716 */
1717
1718 static struct pciserial_board pci_boards[] __devinitdata = {
1719 [pbn_default] = {
1720 .flags = FL_BASE0,
1721 .num_ports = 1,
1722 .base_baud = 115200,
1723 .uart_offset = 8,
1724 },
1725 [pbn_b0_1_115200] = {
1726 .flags = FL_BASE0,
1727 .num_ports = 1,
1728 .base_baud = 115200,
1729 .uart_offset = 8,
1730 },
1731 [pbn_b0_2_115200] = {
1732 .flags = FL_BASE0,
1733 .num_ports = 2,
1734 .base_baud = 115200,
1735 .uart_offset = 8,
1736 },
1737 [pbn_b0_4_115200] = {
1738 .flags = FL_BASE0,
1739 .num_ports = 4,
1740 .base_baud = 115200,
1741 .uart_offset = 8,
1742 },
1743 [pbn_b0_5_115200] = {
1744 .flags = FL_BASE0,
1745 .num_ports = 5,
1746 .base_baud = 115200,
1747 .uart_offset = 8,
1748 },
1749 [pbn_b0_8_115200] = {
1750 .flags = FL_BASE0,
1751 .num_ports = 8,
1752 .base_baud = 115200,
1753 .uart_offset = 8,
1754 },
1755 [pbn_b0_1_921600] = {
1756 .flags = FL_BASE0,
1757 .num_ports = 1,
1758 .base_baud = 921600,
1759 .uart_offset = 8,
1760 },
1761 [pbn_b0_2_921600] = {
1762 .flags = FL_BASE0,
1763 .num_ports = 2,
1764 .base_baud = 921600,
1765 .uart_offset = 8,
1766 },
1767 [pbn_b0_4_921600] = {
1768 .flags = FL_BASE0,
1769 .num_ports = 4,
1770 .base_baud = 921600,
1771 .uart_offset = 8,
1772 },
1773
1774 [pbn_b0_2_1130000] = {
1775 .flags = FL_BASE0,
1776 .num_ports = 2,
1777 .base_baud = 1130000,
1778 .uart_offset = 8,
1779 },
1780
1781 [pbn_b0_4_1152000] = {
1782 .flags = FL_BASE0,
1783 .num_ports = 4,
1784 .base_baud = 1152000,
1785 .uart_offset = 8,
1786 },
1787
1788 [pbn_b0_2_1843200] = {
1789 .flags = FL_BASE0,
1790 .num_ports = 2,
1791 .base_baud = 1843200,
1792 .uart_offset = 8,
1793 },
1794 [pbn_b0_4_1843200] = {
1795 .flags = FL_BASE0,
1796 .num_ports = 4,
1797 .base_baud = 1843200,
1798 .uart_offset = 8,
1799 },
1800
1801 [pbn_b0_2_1843200_200] = {
1802 .flags = FL_BASE0,
1803 .num_ports = 2,
1804 .base_baud = 1843200,
1805 .uart_offset = 0x200,
1806 },
1807 [pbn_b0_4_1843200_200] = {
1808 .flags = FL_BASE0,
1809 .num_ports = 4,
1810 .base_baud = 1843200,
1811 .uart_offset = 0x200,
1812 },
1813 [pbn_b0_8_1843200_200] = {
1814 .flags = FL_BASE0,
1815 .num_ports = 8,
1816 .base_baud = 1843200,
1817 .uart_offset = 0x200,
1818 },
1819 [pbn_b0_1_4000000] = {
1820 .flags = FL_BASE0,
1821 .num_ports = 1,
1822 .base_baud = 4000000,
1823 .uart_offset = 8,
1824 },
1825
1826 [pbn_b0_bt_1_115200] = {
1827 .flags = FL_BASE0|FL_BASE_BARS,
1828 .num_ports = 1,
1829 .base_baud = 115200,
1830 .uart_offset = 8,
1831 },
1832 [pbn_b0_bt_2_115200] = {
1833 .flags = FL_BASE0|FL_BASE_BARS,
1834 .num_ports = 2,
1835 .base_baud = 115200,
1836 .uart_offset = 8,
1837 },
1838 [pbn_b0_bt_4_115200] = {
1839 .flags = FL_BASE0|FL_BASE_BARS,
1840 .num_ports = 4,
1841 .base_baud = 115200,
1842 .uart_offset = 8,
1843 },
1844 [pbn_b0_bt_8_115200] = {
1845 .flags = FL_BASE0|FL_BASE_BARS,
1846 .num_ports = 8,
1847 .base_baud = 115200,
1848 .uart_offset = 8,
1849 },
1850
1851 [pbn_b0_bt_1_460800] = {
1852 .flags = FL_BASE0|FL_BASE_BARS,
1853 .num_ports = 1,
1854 .base_baud = 460800,
1855 .uart_offset = 8,
1856 },
1857 [pbn_b0_bt_2_460800] = {
1858 .flags = FL_BASE0|FL_BASE_BARS,
1859 .num_ports = 2,
1860 .base_baud = 460800,
1861 .uart_offset = 8,
1862 },
1863 [pbn_b0_bt_4_460800] = {
1864 .flags = FL_BASE0|FL_BASE_BARS,
1865 .num_ports = 4,
1866 .base_baud = 460800,
1867 .uart_offset = 8,
1868 },
1869
1870 [pbn_b0_bt_1_921600] = {
1871 .flags = FL_BASE0|FL_BASE_BARS,
1872 .num_ports = 1,
1873 .base_baud = 921600,
1874 .uart_offset = 8,
1875 },
1876 [pbn_b0_bt_2_921600] = {
1877 .flags = FL_BASE0|FL_BASE_BARS,
1878 .num_ports = 2,
1879 .base_baud = 921600,
1880 .uart_offset = 8,
1881 },
1882 [pbn_b0_bt_4_921600] = {
1883 .flags = FL_BASE0|FL_BASE_BARS,
1884 .num_ports = 4,
1885 .base_baud = 921600,
1886 .uart_offset = 8,
1887 },
1888 [pbn_b0_bt_8_921600] = {
1889 .flags = FL_BASE0|FL_BASE_BARS,
1890 .num_ports = 8,
1891 .base_baud = 921600,
1892 .uart_offset = 8,
1893 },
1894
1895 [pbn_b1_1_115200] = {
1896 .flags = FL_BASE1,
1897 .num_ports = 1,
1898 .base_baud = 115200,
1899 .uart_offset = 8,
1900 },
1901 [pbn_b1_2_115200] = {
1902 .flags = FL_BASE1,
1903 .num_ports = 2,
1904 .base_baud = 115200,
1905 .uart_offset = 8,
1906 },
1907 [pbn_b1_4_115200] = {
1908 .flags = FL_BASE1,
1909 .num_ports = 4,
1910 .base_baud = 115200,
1911 .uart_offset = 8,
1912 },
1913 [pbn_b1_8_115200] = {
1914 .flags = FL_BASE1,
1915 .num_ports = 8,
1916 .base_baud = 115200,
1917 .uart_offset = 8,
1918 },
1919 [pbn_b1_16_115200] = {
1920 .flags = FL_BASE1,
1921 .num_ports = 16,
1922 .base_baud = 115200,
1923 .uart_offset = 8,
1924 },
1925
1926 [pbn_b1_1_921600] = {
1927 .flags = FL_BASE1,
1928 .num_ports = 1,
1929 .base_baud = 921600,
1930 .uart_offset = 8,
1931 },
1932 [pbn_b1_2_921600] = {
1933 .flags = FL_BASE1,
1934 .num_ports = 2,
1935 .base_baud = 921600,
1936 .uart_offset = 8,
1937 },
1938 [pbn_b1_4_921600] = {
1939 .flags = FL_BASE1,
1940 .num_ports = 4,
1941 .base_baud = 921600,
1942 .uart_offset = 8,
1943 },
1944 [pbn_b1_8_921600] = {
1945 .flags = FL_BASE1,
1946 .num_ports = 8,
1947 .base_baud = 921600,
1948 .uart_offset = 8,
1949 },
1950 [pbn_b1_2_1250000] = {
1951 .flags = FL_BASE1,
1952 .num_ports = 2,
1953 .base_baud = 1250000,
1954 .uart_offset = 8,
1955 },
1956
1957 [pbn_b1_bt_1_115200] = {
1958 .flags = FL_BASE1|FL_BASE_BARS,
1959 .num_ports = 1,
1960 .base_baud = 115200,
1961 .uart_offset = 8,
1962 },
1963 [pbn_b1_bt_2_115200] = {
1964 .flags = FL_BASE1|FL_BASE_BARS,
1965 .num_ports = 2,
1966 .base_baud = 115200,
1967 .uart_offset = 8,
1968 },
1969 [pbn_b1_bt_4_115200] = {
1970 .flags = FL_BASE1|FL_BASE_BARS,
1971 .num_ports = 4,
1972 .base_baud = 115200,
1973 .uart_offset = 8,
1974 },
1975
1976 [pbn_b1_bt_2_921600] = {
1977 .flags = FL_BASE1|FL_BASE_BARS,
1978 .num_ports = 2,
1979 .base_baud = 921600,
1980 .uart_offset = 8,
1981 },
1982
1983 [pbn_b1_1_1382400] = {
1984 .flags = FL_BASE1,
1985 .num_ports = 1,
1986 .base_baud = 1382400,
1987 .uart_offset = 8,
1988 },
1989 [pbn_b1_2_1382400] = {
1990 .flags = FL_BASE1,
1991 .num_ports = 2,
1992 .base_baud = 1382400,
1993 .uart_offset = 8,
1994 },
1995 [pbn_b1_4_1382400] = {
1996 .flags = FL_BASE1,
1997 .num_ports = 4,
1998 .base_baud = 1382400,
1999 .uart_offset = 8,
2000 },
2001 [pbn_b1_8_1382400] = {
2002 .flags = FL_BASE1,
2003 .num_ports = 8,
2004 .base_baud = 1382400,
2005 .uart_offset = 8,
2006 },
2007
2008 [pbn_b2_1_115200] = {
2009 .flags = FL_BASE2,
2010 .num_ports = 1,
2011 .base_baud = 115200,
2012 .uart_offset = 8,
2013 },
2014 [pbn_b2_2_115200] = {
2015 .flags = FL_BASE2,
2016 .num_ports = 2,
2017 .base_baud = 115200,
2018 .uart_offset = 8,
2019 },
2020 [pbn_b2_4_115200] = {
2021 .flags = FL_BASE2,
2022 .num_ports = 4,
2023 .base_baud = 115200,
2024 .uart_offset = 8,
2025 },
2026 [pbn_b2_8_115200] = {
2027 .flags = FL_BASE2,
2028 .num_ports = 8,
2029 .base_baud = 115200,
2030 .uart_offset = 8,
2031 },
2032
2033 [pbn_b2_1_460800] = {
2034 .flags = FL_BASE2,
2035 .num_ports = 1,
2036 .base_baud = 460800,
2037 .uart_offset = 8,
2038 },
2039 [pbn_b2_4_460800] = {
2040 .flags = FL_BASE2,
2041 .num_ports = 4,
2042 .base_baud = 460800,
2043 .uart_offset = 8,
2044 },
2045 [pbn_b2_8_460800] = {
2046 .flags = FL_BASE2,
2047 .num_ports = 8,
2048 .base_baud = 460800,
2049 .uart_offset = 8,
2050 },
2051 [pbn_b2_16_460800] = {
2052 .flags = FL_BASE2,
2053 .num_ports = 16,
2054 .base_baud = 460800,
2055 .uart_offset = 8,
2056 },
2057
2058 [pbn_b2_1_921600] = {
2059 .flags = FL_BASE2,
2060 .num_ports = 1,
2061 .base_baud = 921600,
2062 .uart_offset = 8,
2063 },
2064 [pbn_b2_4_921600] = {
2065 .flags = FL_BASE2,
2066 .num_ports = 4,
2067 .base_baud = 921600,
2068 .uart_offset = 8,
2069 },
2070 [pbn_b2_8_921600] = {
2071 .flags = FL_BASE2,
2072 .num_ports = 8,
2073 .base_baud = 921600,
2074 .uart_offset = 8,
2075 },
2076
2077 [pbn_b2_8_1152000] = {
2078 .flags = FL_BASE2,
2079 .num_ports = 8,
2080 .base_baud = 1152000,
2081 .uart_offset = 8,
2082 },
2083
2084 [pbn_b2_bt_1_115200] = {
2085 .flags = FL_BASE2|FL_BASE_BARS,
2086 .num_ports = 1,
2087 .base_baud = 115200,
2088 .uart_offset = 8,
2089 },
2090 [pbn_b2_bt_2_115200] = {
2091 .flags = FL_BASE2|FL_BASE_BARS,
2092 .num_ports = 2,
2093 .base_baud = 115200,
2094 .uart_offset = 8,
2095 },
2096 [pbn_b2_bt_4_115200] = {
2097 .flags = FL_BASE2|FL_BASE_BARS,
2098 .num_ports = 4,
2099 .base_baud = 115200,
2100 .uart_offset = 8,
2101 },
2102
2103 [pbn_b2_bt_2_921600] = {
2104 .flags = FL_BASE2|FL_BASE_BARS,
2105 .num_ports = 2,
2106 .base_baud = 921600,
2107 .uart_offset = 8,
2108 },
2109 [pbn_b2_bt_4_921600] = {
2110 .flags = FL_BASE2|FL_BASE_BARS,
2111 .num_ports = 4,
2112 .base_baud = 921600,
2113 .uart_offset = 8,
2114 },
2115
2116 [pbn_b3_2_115200] = {
2117 .flags = FL_BASE3,
2118 .num_ports = 2,
2119 .base_baud = 115200,
2120 .uart_offset = 8,
2121 },
2122 [pbn_b3_4_115200] = {
2123 .flags = FL_BASE3,
2124 .num_ports = 4,
2125 .base_baud = 115200,
2126 .uart_offset = 8,
2127 },
2128 [pbn_b3_8_115200] = {
2129 .flags = FL_BASE3,
2130 .num_ports = 8,
2131 .base_baud = 115200,
2132 .uart_offset = 8,
2133 },
2134
2135 [pbn_b4_bt_2_921600] = {
2136 .flags = FL_BASE4,
2137 .num_ports = 2,
2138 .base_baud = 921600,
2139 .uart_offset = 8,
2140 },
2141 [pbn_b4_bt_4_921600] = {
2142 .flags = FL_BASE4,
2143 .num_ports = 4,
2144 .base_baud = 921600,
2145 .uart_offset = 8,
2146 },
2147 [pbn_b4_bt_8_921600] = {
2148 .flags = FL_BASE4,
2149 .num_ports = 8,
2150 .base_baud = 921600,
2151 .uart_offset = 8,
2152 },
2153
2154 /*
2155 * Entries following this are board-specific.
2156 */
2157
2158 /*
2159 * Panacom - IOMEM
2160 */
2161 [pbn_panacom] = {
2162 .flags = FL_BASE2,
2163 .num_ports = 2,
2164 .base_baud = 921600,
2165 .uart_offset = 0x400,
2166 .reg_shift = 7,
2167 },
2168 [pbn_panacom2] = {
2169 .flags = FL_BASE2|FL_BASE_BARS,
2170 .num_ports = 2,
2171 .base_baud = 921600,
2172 .uart_offset = 0x400,
2173 .reg_shift = 7,
2174 },
2175 [pbn_panacom4] = {
2176 .flags = FL_BASE2|FL_BASE_BARS,
2177 .num_ports = 4,
2178 .base_baud = 921600,
2179 .uart_offset = 0x400,
2180 .reg_shift = 7,
2181 },
2182
2183 [pbn_exsys_4055] = {
2184 .flags = FL_BASE2,
2185 .num_ports = 4,
2186 .base_baud = 115200,
2187 .uart_offset = 8,
2188 },
2189
2190 /* I think this entry is broken - the first_offset looks wrong --rmk */
2191 [pbn_plx_romulus] = {
2192 .flags = FL_BASE2,
2193 .num_ports = 4,
2194 .base_baud = 921600,
2195 .uart_offset = 8 << 2,
2196 .reg_shift = 2,
2197 .first_offset = 0x03,
2198 },
2199
2200 /*
2201 * This board uses the size of PCI Base region 0 to
2202 * signal now many ports are available
2203 */
2204 [pbn_oxsemi] = {
2205 .flags = FL_BASE0|FL_REGION_SZ_CAP,
2206 .num_ports = 32,
2207 .base_baud = 115200,
2208 .uart_offset = 8,
2209 },
2210 [pbn_oxsemi_1_4000000] = {
2211 .flags = FL_BASE0,
2212 .num_ports = 1,
2213 .base_baud = 4000000,
2214 .uart_offset = 0x200,
2215 .first_offset = 0x1000,
2216 },
2217 [pbn_oxsemi_2_4000000] = {
2218 .flags = FL_BASE0,
2219 .num_ports = 2,
2220 .base_baud = 4000000,
2221 .uart_offset = 0x200,
2222 .first_offset = 0x1000,
2223 },
2224 [pbn_oxsemi_4_4000000] = {
2225 .flags = FL_BASE0,
2226 .num_ports = 4,
2227 .base_baud = 4000000,
2228 .uart_offset = 0x200,
2229 .first_offset = 0x1000,
2230 },
2231 [pbn_oxsemi_8_4000000] = {
2232 .flags = FL_BASE0,
2233 .num_ports = 8,
2234 .base_baud = 4000000,
2235 .uart_offset = 0x200,
2236 .first_offset = 0x1000,
2237 },
2238
2239
2240 /*
2241 * EKF addition for i960 Boards form EKF with serial port.
2242 * Max 256 ports.
2243 */
2244 [pbn_intel_i960] = {
2245 .flags = FL_BASE0,
2246 .num_ports = 32,
2247 .base_baud = 921600,
2248 .uart_offset = 8 << 2,
2249 .reg_shift = 2,
2250 .first_offset = 0x10000,
2251 },
2252 [pbn_sgi_ioc3] = {
2253 .flags = FL_BASE0|FL_NOIRQ,
2254 .num_ports = 1,
2255 .base_baud = 458333,
2256 .uart_offset = 8,
2257 .reg_shift = 0,
2258 .first_offset = 0x20178,
2259 },
2260
2261 /*
2262 * Computone - uses IOMEM.
2263 */
2264 [pbn_computone_4] = {
2265 .flags = FL_BASE0,
2266 .num_ports = 4,
2267 .base_baud = 921600,
2268 .uart_offset = 0x40,
2269 .reg_shift = 2,
2270 .first_offset = 0x200,
2271 },
2272 [pbn_computone_6] = {
2273 .flags = FL_BASE0,
2274 .num_ports = 6,
2275 .base_baud = 921600,
2276 .uart_offset = 0x40,
2277 .reg_shift = 2,
2278 .first_offset = 0x200,
2279 },
2280 [pbn_computone_8] = {
2281 .flags = FL_BASE0,
2282 .num_ports = 8,
2283 .base_baud = 921600,
2284 .uart_offset = 0x40,
2285 .reg_shift = 2,
2286 .first_offset = 0x200,
2287 },
2288 [pbn_sbsxrsio] = {
2289 .flags = FL_BASE0,
2290 .num_ports = 8,
2291 .base_baud = 460800,
2292 .uart_offset = 256,
2293 .reg_shift = 4,
2294 },
2295 /*
2296 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
2297 * Only basic 16550A support.
2298 * XR17C15[24] are not tested, but they should work.
2299 */
2300 [pbn_exar_XR17C152] = {
2301 .flags = FL_BASE0,
2302 .num_ports = 2,
2303 .base_baud = 921600,
2304 .uart_offset = 0x200,
2305 },
2306 [pbn_exar_XR17C154] = {
2307 .flags = FL_BASE0,
2308 .num_ports = 4,
2309 .base_baud = 921600,
2310 .uart_offset = 0x200,
2311 },
2312 [pbn_exar_XR17C158] = {
2313 .flags = FL_BASE0,
2314 .num_ports = 8,
2315 .base_baud = 921600,
2316 .uart_offset = 0x200,
2317 },
2318 [pbn_exar_ibm_saturn] = {
2319 .flags = FL_BASE0,
2320 .num_ports = 1,
2321 .base_baud = 921600,
2322 .uart_offset = 0x200,
2323 },
2324
2325 /*
2326 * PA Semi PWRficient PA6T-1682M on-chip UART
2327 */
2328 [pbn_pasemi_1682M] = {
2329 .flags = FL_BASE0,
2330 .num_ports = 1,
2331 .base_baud = 8333333,
2332 },
2333 /*
2334 * National Instruments 843x
2335 */
2336 [pbn_ni8430_16] = {
2337 .flags = FL_BASE0,
2338 .num_ports = 16,
2339 .base_baud = 3686400,
2340 .uart_offset = 0x10,
2341 .first_offset = 0x800,
2342 },
2343 [pbn_ni8430_8] = {
2344 .flags = FL_BASE0,
2345 .num_ports = 8,
2346 .base_baud = 3686400,
2347 .uart_offset = 0x10,
2348 .first_offset = 0x800,
2349 },
2350 [pbn_ni8430_4] = {
2351 .flags = FL_BASE0,
2352 .num_ports = 4,
2353 .base_baud = 3686400,
2354 .uart_offset = 0x10,
2355 .first_offset = 0x800,
2356 },
2357 [pbn_ni8430_2] = {
2358 .flags = FL_BASE0,
2359 .num_ports = 2,
2360 .base_baud = 3686400,
2361 .uart_offset = 0x10,
2362 .first_offset = 0x800,
2363 },
2364 /*
2365 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
2366 */
2367 [pbn_ADDIDATA_PCIe_1_3906250] = {
2368 .flags = FL_BASE0,
2369 .num_ports = 1,
2370 .base_baud = 3906250,
2371 .uart_offset = 0x200,
2372 .first_offset = 0x1000,
2373 },
2374 [pbn_ADDIDATA_PCIe_2_3906250] = {
2375 .flags = FL_BASE0,
2376 .num_ports = 2,
2377 .base_baud = 3906250,
2378 .uart_offset = 0x200,
2379 .first_offset = 0x1000,
2380 },
2381 [pbn_ADDIDATA_PCIe_4_3906250] = {
2382 .flags = FL_BASE0,
2383 .num_ports = 4,
2384 .base_baud = 3906250,
2385 .uart_offset = 0x200,
2386 .first_offset = 0x1000,
2387 },
2388 [pbn_ADDIDATA_PCIe_8_3906250] = {
2389 .flags = FL_BASE0,
2390 .num_ports = 8,
2391 .base_baud = 3906250,
2392 .uart_offset = 0x200,
2393 .first_offset = 0x1000,
2394 },
2395 [pbn_ce4100_1_115200] = {
2396 .flags = FL_BASE0,
2397 .num_ports = 1,
2398 .base_baud = 921600,
2399 .reg_shift = 2,
2400 },
2401 [pbn_omegapci] = {
2402 .flags = FL_BASE0,
2403 .num_ports = 8,
2404 .base_baud = 115200,
2405 .uart_offset = 0x200,
2406 },
2407 };
2408
2409 static const struct pci_device_id softmodem_blacklist[] = {
2410 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
2411 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
2412 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
2413 };
2414
2415 /*
2416 * Given a complete unknown PCI device, try to use some heuristics to
2417 * guess what the configuration might be, based on the pitiful PCI
2418 * serial specs. Returns 0 on success, 1 on failure.
2419 */
2420 static int __devinit
2421 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
2422 {
2423 const struct pci_device_id *blacklist;
2424 int num_iomem, num_port, first_port = -1, i;
2425
2426 /*
2427 * If it is not a communications device or the programming
2428 * interface is greater than 6, give up.
2429 *
2430 * (Should we try to make guesses for multiport serial devices
2431 * later?)
2432 */
2433 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
2434 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
2435 (dev->class & 0xff) > 6)
2436 return -ENODEV;
2437
2438 /*
2439 * Do not access blacklisted devices that are known not to
2440 * feature serial ports.
2441 */
2442 for (blacklist = softmodem_blacklist;
2443 blacklist < softmodem_blacklist + ARRAY_SIZE(softmodem_blacklist);
2444 blacklist++) {
2445 if (dev->vendor == blacklist->vendor &&
2446 dev->device == blacklist->device)
2447 return -ENODEV;
2448 }
2449
2450 num_iomem = num_port = 0;
2451 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2452 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
2453 num_port++;
2454 if (first_port == -1)
2455 first_port = i;
2456 }
2457 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
2458 num_iomem++;
2459 }
2460
2461 /*
2462 * If there is 1 or 0 iomem regions, and exactly one port,
2463 * use it. We guess the number of ports based on the IO
2464 * region size.
2465 */
2466 if (num_iomem <= 1 && num_port == 1) {
2467 board->flags = first_port;
2468 board->num_ports = pci_resource_len(dev, first_port) / 8;
2469 return 0;
2470 }
2471
2472 /*
2473 * Now guess if we've got a board which indexes by BARs.
2474 * Each IO BAR should be 8 bytes, and they should follow
2475 * consecutively.
2476 */
2477 first_port = -1;
2478 num_port = 0;
2479 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2480 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
2481 pci_resource_len(dev, i) == 8 &&
2482 (first_port == -1 || (first_port + num_port) == i)) {
2483 num_port++;
2484 if (first_port == -1)
2485 first_port = i;
2486 }
2487 }
2488
2489 if (num_port > 1) {
2490 board->flags = first_port | FL_BASE_BARS;
2491 board->num_ports = num_port;
2492 return 0;
2493 }
2494
2495 return -ENODEV;
2496 }
2497
2498 static inline int
2499 serial_pci_matches(const struct pciserial_board *board,
2500 const struct pciserial_board *guessed)
2501 {
2502 return
2503 board->num_ports == guessed->num_ports &&
2504 board->base_baud == guessed->base_baud &&
2505 board->uart_offset == guessed->uart_offset &&
2506 board->reg_shift == guessed->reg_shift &&
2507 board->first_offset == guessed->first_offset;
2508 }
2509
2510 struct serial_private *
2511 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
2512 {
2513 struct uart_port serial_port;
2514 struct serial_private *priv;
2515 struct pci_serial_quirk *quirk;
2516 int rc, nr_ports, i;
2517
2518 nr_ports = board->num_ports;
2519
2520 /*
2521 * Find an init and setup quirks.
2522 */
2523 quirk = find_quirk(dev);
2524
2525 /*
2526 * Run the new-style initialization function.
2527 * The initialization function returns:
2528 * <0 - error
2529 * 0 - use board->num_ports
2530 * >0 - number of ports
2531 */
2532 if (quirk->init) {
2533 rc = quirk->init(dev);
2534 if (rc < 0) {
2535 priv = ERR_PTR(rc);
2536 goto err_out;
2537 }
2538 if (rc)
2539 nr_ports = rc;
2540 }
2541
2542 priv = kzalloc(sizeof(struct serial_private) +
2543 sizeof(unsigned int) * nr_ports,
2544 GFP_KERNEL);
2545 if (!priv) {
2546 priv = ERR_PTR(-ENOMEM);
2547 goto err_deinit;
2548 }
2549
2550 priv->dev = dev;
2551 priv->quirk = quirk;
2552
2553 memset(&serial_port, 0, sizeof(struct uart_port));
2554 serial_port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
2555 serial_port.uartclk = board->base_baud * 16;
2556 serial_port.irq = get_pci_irq(dev, board);
2557 serial_port.dev = &dev->dev;
2558
2559 for (i = 0; i < nr_ports; i++) {
2560 if (quirk->setup(priv, board, &serial_port, i))
2561 break;
2562
2563 #ifdef SERIAL_DEBUG_PCI
2564 printk(KERN_DEBUG "Setup PCI port: port %lx, irq %d, type %d\n",
2565 serial_port.iobase, serial_port.irq, serial_port.iotype);
2566 #endif
2567
2568 priv->line[i] = serial8250_register_port(&serial_port);
2569 if (priv->line[i] < 0) {
2570 printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]);
2571 break;
2572 }
2573 }
2574 priv->nr = i;
2575 return priv;
2576
2577 err_deinit:
2578 if (quirk->exit)
2579 quirk->exit(dev);
2580 err_out:
2581 return priv;
2582 }
2583 EXPORT_SYMBOL_GPL(pciserial_init_ports);
2584
2585 void pciserial_remove_ports(struct serial_private *priv)
2586 {
2587 struct pci_serial_quirk *quirk;
2588 int i;
2589
2590 for (i = 0; i < priv->nr; i++)
2591 serial8250_unregister_port(priv->line[i]);
2592
2593 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2594 if (priv->remapped_bar[i])
2595 iounmap(priv->remapped_bar[i]);
2596 priv->remapped_bar[i] = NULL;
2597 }
2598
2599 /*
2600 * Find the exit quirks.
2601 */
2602 quirk = find_quirk(priv->dev);
2603 if (quirk->exit)
2604 quirk->exit(priv->dev);
2605
2606 kfree(priv);
2607 }
2608 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
2609
2610 void pciserial_suspend_ports(struct serial_private *priv)
2611 {
2612 int i;
2613
2614 for (i = 0; i < priv->nr; i++)
2615 if (priv->line[i] >= 0)
2616 serial8250_suspend_port(priv->line[i]);
2617 }
2618 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
2619
2620 void pciserial_resume_ports(struct serial_private *priv)
2621 {
2622 int i;
2623
2624 /*
2625 * Ensure that the board is correctly configured.
2626 */
2627 if (priv->quirk->init)
2628 priv->quirk->init(priv->dev);
2629
2630 for (i = 0; i < priv->nr; i++)
2631 if (priv->line[i] >= 0)
2632 serial8250_resume_port(priv->line[i]);
2633 }
2634 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
2635
2636 /*
2637 * Probe one serial board. Unfortunately, there is no rhyme nor reason
2638 * to the arrangement of serial ports on a PCI card.
2639 */
2640 static int __devinit
2641 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
2642 {
2643 struct serial_private *priv;
2644 const struct pciserial_board *board;
2645 struct pciserial_board tmp;
2646 int rc;
2647
2648 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
2649 printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n",
2650 ent->driver_data);
2651 return -EINVAL;
2652 }
2653
2654 board = &pci_boards[ent->driver_data];
2655
2656 rc = pci_enable_device(dev);
2657 if (rc)
2658 return rc;
2659
2660 if (ent->driver_data == pbn_default) {
2661 /*
2662 * Use a copy of the pci_board entry for this;
2663 * avoid changing entries in the table.
2664 */
2665 memcpy(&tmp, board, sizeof(struct pciserial_board));
2666 board = &tmp;
2667
2668 /*
2669 * We matched one of our class entries. Try to
2670 * determine the parameters of this board.
2671 */
2672 rc = serial_pci_guess_board(dev, &tmp);
2673 if (rc)
2674 goto disable;
2675 } else {
2676 /*
2677 * We matched an explicit entry. If we are able to
2678 * detect this boards settings with our heuristic,
2679 * then we no longer need this entry.
2680 */
2681 memcpy(&tmp, &pci_boards[pbn_default],
2682 sizeof(struct pciserial_board));
2683 rc = serial_pci_guess_board(dev, &tmp);
2684 if (rc == 0 && serial_pci_matches(board, &tmp))
2685 moan_device("Redundant entry in serial pci_table.",
2686 dev);
2687 }
2688
2689 priv = pciserial_init_ports(dev, board);
2690 if (!IS_ERR(priv)) {
2691 pci_set_drvdata(dev, priv);
2692 return 0;
2693 }
2694
2695 rc = PTR_ERR(priv);
2696
2697 disable:
2698 pci_disable_device(dev);
2699 return rc;
2700 }
2701
2702 static void __devexit pciserial_remove_one(struct pci_dev *dev)
2703 {
2704 struct serial_private *priv = pci_get_drvdata(dev);
2705
2706 pci_set_drvdata(dev, NULL);
2707
2708 pciserial_remove_ports(priv);
2709
2710 pci_disable_device(dev);
2711 }
2712
2713 #ifdef CONFIG_PM
2714 static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
2715 {
2716 struct serial_private *priv = pci_get_drvdata(dev);
2717
2718 if (priv)
2719 pciserial_suspend_ports(priv);
2720
2721 pci_save_state(dev);
2722 pci_set_power_state(dev, pci_choose_state(dev, state));
2723 return 0;
2724 }
2725
2726 static int pciserial_resume_one(struct pci_dev *dev)
2727 {
2728 int err;
2729 struct serial_private *priv = pci_get_drvdata(dev);
2730
2731 pci_set_power_state(dev, PCI_D0);
2732 pci_restore_state(dev);
2733
2734 if (priv) {
2735 /*
2736 * The device may have been disabled. Re-enable it.
2737 */
2738 err = pci_enable_device(dev);
2739 /* FIXME: We cannot simply error out here */
2740 if (err)
2741 printk(KERN_ERR "pciserial: Unable to re-enable ports, trying to continue.\n");
2742 pciserial_resume_ports(priv);
2743 }
2744 return 0;
2745 }
2746 #endif
2747
2748 static struct pci_device_id serial_pci_tbl[] = {
2749 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
2750 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
2751 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
2752 pbn_b2_8_921600 },
2753 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2754 PCI_SUBVENDOR_ID_CONNECT_TECH,
2755 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
2756 pbn_b1_8_1382400 },
2757 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2758 PCI_SUBVENDOR_ID_CONNECT_TECH,
2759 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
2760 pbn_b1_4_1382400 },
2761 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2762 PCI_SUBVENDOR_ID_CONNECT_TECH,
2763 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
2764 pbn_b1_2_1382400 },
2765 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2766 PCI_SUBVENDOR_ID_CONNECT_TECH,
2767 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
2768 pbn_b1_8_1382400 },
2769 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2770 PCI_SUBVENDOR_ID_CONNECT_TECH,
2771 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
2772 pbn_b1_4_1382400 },
2773 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2774 PCI_SUBVENDOR_ID_CONNECT_TECH,
2775 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
2776 pbn_b1_2_1382400 },
2777 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2778 PCI_SUBVENDOR_ID_CONNECT_TECH,
2779 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
2780 pbn_b1_8_921600 },
2781 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2782 PCI_SUBVENDOR_ID_CONNECT_TECH,
2783 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
2784 pbn_b1_8_921600 },
2785 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2786 PCI_SUBVENDOR_ID_CONNECT_TECH,
2787 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
2788 pbn_b1_4_921600 },
2789 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2790 PCI_SUBVENDOR_ID_CONNECT_TECH,
2791 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
2792 pbn_b1_4_921600 },
2793 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2794 PCI_SUBVENDOR_ID_CONNECT_TECH,
2795 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
2796 pbn_b1_2_921600 },
2797 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2798 PCI_SUBVENDOR_ID_CONNECT_TECH,
2799 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
2800 pbn_b1_8_921600 },
2801 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2802 PCI_SUBVENDOR_ID_CONNECT_TECH,
2803 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
2804 pbn_b1_8_921600 },
2805 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2806 PCI_SUBVENDOR_ID_CONNECT_TECH,
2807 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
2808 pbn_b1_4_921600 },
2809 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2810 PCI_SUBVENDOR_ID_CONNECT_TECH,
2811 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
2812 pbn_b1_2_1250000 },
2813 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2814 PCI_SUBVENDOR_ID_CONNECT_TECH,
2815 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
2816 pbn_b0_2_1843200 },
2817 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2818 PCI_SUBVENDOR_ID_CONNECT_TECH,
2819 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
2820 pbn_b0_4_1843200 },
2821 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2822 PCI_VENDOR_ID_AFAVLAB,
2823 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
2824 pbn_b0_4_1152000 },
2825 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2826 PCI_SUBVENDOR_ID_CONNECT_TECH,
2827 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
2828 pbn_b0_2_1843200_200 },
2829 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2830 PCI_SUBVENDOR_ID_CONNECT_TECH,
2831 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
2832 pbn_b0_4_1843200_200 },
2833 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2834 PCI_SUBVENDOR_ID_CONNECT_TECH,
2835 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
2836 pbn_b0_8_1843200_200 },
2837 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2838 PCI_SUBVENDOR_ID_CONNECT_TECH,
2839 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
2840 pbn_b0_2_1843200_200 },
2841 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2842 PCI_SUBVENDOR_ID_CONNECT_TECH,
2843 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
2844 pbn_b0_4_1843200_200 },
2845 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2846 PCI_SUBVENDOR_ID_CONNECT_TECH,
2847 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
2848 pbn_b0_8_1843200_200 },
2849 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2850 PCI_SUBVENDOR_ID_CONNECT_TECH,
2851 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
2852 pbn_b0_2_1843200_200 },
2853 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2854 PCI_SUBVENDOR_ID_CONNECT_TECH,
2855 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
2856 pbn_b0_4_1843200_200 },
2857 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2858 PCI_SUBVENDOR_ID_CONNECT_TECH,
2859 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
2860 pbn_b0_8_1843200_200 },
2861 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2862 PCI_SUBVENDOR_ID_CONNECT_TECH,
2863 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
2864 pbn_b0_2_1843200_200 },
2865 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2866 PCI_SUBVENDOR_ID_CONNECT_TECH,
2867 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
2868 pbn_b0_4_1843200_200 },
2869 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2870 PCI_SUBVENDOR_ID_CONNECT_TECH,
2871 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
2872 pbn_b0_8_1843200_200 },
2873 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2874 PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT,
2875 0, 0, pbn_exar_ibm_saturn },
2876
2877 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
2878 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2879 pbn_b2_bt_1_115200 },
2880 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
2881 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2882 pbn_b2_bt_2_115200 },
2883 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
2884 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2885 pbn_b2_bt_4_115200 },
2886 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
2887 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2888 pbn_b2_bt_2_115200 },
2889 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
2890 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2891 pbn_b2_bt_4_115200 },
2892 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
2893 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2894 pbn_b2_8_115200 },
2895 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
2896 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2897 pbn_b2_8_460800 },
2898 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
2899 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2900 pbn_b2_8_115200 },
2901
2902 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
2903 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2904 pbn_b2_bt_2_115200 },
2905 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
2906 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2907 pbn_b2_bt_2_921600 },
2908 /*
2909 * VScom SPCOM800, from sl@s.pl
2910 */
2911 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
2912 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2913 pbn_b2_8_921600 },
2914 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
2915 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2916 pbn_b2_4_921600 },
2917 /* Unknown card - subdevice 0x1584 */
2918 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2919 PCI_VENDOR_ID_PLX,
2920 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
2921 pbn_b0_4_115200 },
2922 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2923 PCI_SUBVENDOR_ID_KEYSPAN,
2924 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
2925 pbn_panacom },
2926 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
2927 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2928 pbn_panacom4 },
2929 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
2930 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2931 pbn_panacom2 },
2932 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
2933 PCI_VENDOR_ID_ESDGMBH,
2934 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
2935 pbn_b2_4_115200 },
2936 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2937 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2938 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
2939 pbn_b2_4_460800 },
2940 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2941 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2942 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
2943 pbn_b2_8_460800 },
2944 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2945 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2946 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
2947 pbn_b2_16_460800 },
2948 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2949 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2950 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
2951 pbn_b2_16_460800 },
2952 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2953 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
2954 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
2955 pbn_b2_4_460800 },
2956 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2957 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
2958 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
2959 pbn_b2_8_460800 },
2960 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2961 PCI_SUBVENDOR_ID_EXSYS,
2962 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
2963 pbn_exsys_4055 },
2964 /*
2965 * Megawolf Romulus PCI Serial Card, from Mike Hudson
2966 * (Exoray@isys.ca)
2967 */
2968 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
2969 0x10b5, 0x106a, 0, 0,
2970 pbn_plx_romulus },
2971 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
2972 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2973 pbn_b1_4_115200 },
2974 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
2975 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2976 pbn_b1_2_115200 },
2977 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
2978 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2979 pbn_b1_8_115200 },
2980 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
2981 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2982 pbn_b1_8_115200 },
2983 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
2984 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
2985 0, 0,
2986 pbn_b0_4_921600 },
2987 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2988 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
2989 0, 0,
2990 pbn_b0_4_1152000 },
2991 { PCI_VENDOR_ID_OXSEMI, 0x9505,
2992 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2993 pbn_b0_bt_2_921600 },
2994
2995 /*
2996 * The below card is a little controversial since it is the
2997 * subject of a PCI vendor/device ID clash. (See
2998 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
2999 * For now just used the hex ID 0x950a.
3000 */
3001 { PCI_VENDOR_ID_OXSEMI, 0x950a,
3002 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_SERIAL, 0, 0,
3003 pbn_b0_2_115200 },
3004 { PCI_VENDOR_ID_OXSEMI, 0x950a,
3005 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3006 pbn_b0_2_1130000 },
3007 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
3008 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
3009 pbn_b0_1_921600 },
3010 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3011 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3012 pbn_b0_4_115200 },
3013 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
3014 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3015 pbn_b0_bt_2_921600 },
3016 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
3017 PCI_ANY_ID , PCI_ANY_ID, 0, 0,
3018 pbn_b2_8_1152000 },
3019
3020 /*
3021 * Oxford Semiconductor Inc. Tornado PCI express device range.
3022 */
3023 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */
3024 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3025 pbn_b0_1_4000000 },
3026 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */
3027 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3028 pbn_b0_1_4000000 },
3029 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */
3030 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3031 pbn_oxsemi_1_4000000 },
3032 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */
3033 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3034 pbn_oxsemi_1_4000000 },
3035 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */
3036 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3037 pbn_b0_1_4000000 },
3038 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */
3039 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3040 pbn_b0_1_4000000 },
3041 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */
3042 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3043 pbn_oxsemi_1_4000000 },
3044 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */
3045 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3046 pbn_oxsemi_1_4000000 },
3047 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */
3048 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3049 pbn_b0_1_4000000 },
3050 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */
3051 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3052 pbn_b0_1_4000000 },
3053 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */
3054 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3055 pbn_b0_1_4000000 },
3056 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */
3057 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3058 pbn_b0_1_4000000 },
3059 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */
3060 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3061 pbn_oxsemi_2_4000000 },
3062 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */
3063 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3064 pbn_oxsemi_2_4000000 },
3065 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */
3066 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3067 pbn_oxsemi_4_4000000 },
3068 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */
3069 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3070 pbn_oxsemi_4_4000000 },
3071 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */
3072 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3073 pbn_oxsemi_8_4000000 },
3074 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */
3075 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3076 pbn_oxsemi_8_4000000 },
3077 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */
3078 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3079 pbn_oxsemi_1_4000000 },
3080 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */
3081 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3082 pbn_oxsemi_1_4000000 },
3083 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */
3084 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3085 pbn_oxsemi_1_4000000 },
3086 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */
3087 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3088 pbn_oxsemi_1_4000000 },
3089 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */
3090 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3091 pbn_oxsemi_1_4000000 },
3092 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */
3093 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3094 pbn_oxsemi_1_4000000 },
3095 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */
3096 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3097 pbn_oxsemi_1_4000000 },
3098 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */
3099 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3100 pbn_oxsemi_1_4000000 },
3101 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */
3102 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3103 pbn_oxsemi_1_4000000 },
3104 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */
3105 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3106 pbn_oxsemi_1_4000000 },
3107 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */
3108 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3109 pbn_oxsemi_1_4000000 },
3110 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */
3111 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3112 pbn_oxsemi_1_4000000 },
3113 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */
3114 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3115 pbn_oxsemi_1_4000000 },
3116 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */
3117 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3118 pbn_oxsemi_1_4000000 },
3119 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */
3120 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3121 pbn_oxsemi_1_4000000 },
3122 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */
3123 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3124 pbn_oxsemi_1_4000000 },
3125 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */
3126 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3127 pbn_oxsemi_1_4000000 },
3128 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */
3129 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3130 pbn_oxsemi_1_4000000 },
3131 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */
3132 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3133 pbn_oxsemi_1_4000000 },
3134 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */
3135 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3136 pbn_oxsemi_1_4000000 },
3137 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */
3138 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3139 pbn_oxsemi_1_4000000 },
3140 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */
3141 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3142 pbn_oxsemi_1_4000000 },
3143 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */
3144 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3145 pbn_oxsemi_1_4000000 },
3146 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */
3147 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3148 pbn_oxsemi_1_4000000 },
3149 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */
3150 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3151 pbn_oxsemi_1_4000000 },
3152 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */
3153 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3154 pbn_oxsemi_1_4000000 },
3155 /*
3156 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
3157 */
3158 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
3159 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
3160 pbn_oxsemi_1_4000000 },
3161 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
3162 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
3163 pbn_oxsemi_2_4000000 },
3164 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
3165 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
3166 pbn_oxsemi_4_4000000 },
3167 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
3168 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
3169 pbn_oxsemi_8_4000000 },
3170
3171 /*
3172 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
3173 */
3174 { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
3175 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
3176 pbn_oxsemi_2_4000000 },
3177
3178 /*
3179 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
3180 * from skokodyn@yahoo.com
3181 */
3182 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3183 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
3184 pbn_sbsxrsio },
3185 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3186 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
3187 pbn_sbsxrsio },
3188 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3189 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
3190 pbn_sbsxrsio },
3191 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3192 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
3193 pbn_sbsxrsio },
3194
3195 /*
3196 * Digitan DS560-558, from jimd@esoft.com
3197 */
3198 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
3199 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3200 pbn_b1_1_115200 },
3201
3202 /*
3203 * Titan Electronic cards
3204 * The 400L and 800L have a custom setup quirk.
3205 */
3206 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
3207 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3208 pbn_b0_1_921600 },
3209 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
3210 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3211 pbn_b0_2_921600 },
3212 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
3213 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3214 pbn_b0_4_921600 },
3215 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
3216 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3217 pbn_b0_4_921600 },
3218 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
3219 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3220 pbn_b1_1_921600 },
3221 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
3222 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3223 pbn_b1_bt_2_921600 },
3224 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
3225 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3226 pbn_b0_bt_4_921600 },
3227 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
3228 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3229 pbn_b0_bt_8_921600 },
3230 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
3231 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3232 pbn_b4_bt_2_921600 },
3233 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
3234 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3235 pbn_b4_bt_4_921600 },
3236 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
3237 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3238 pbn_b4_bt_8_921600 },
3239 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
3240 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3241 pbn_b0_4_921600 },
3242 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
3243 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3244 pbn_b0_4_921600 },
3245 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
3246 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3247 pbn_b0_4_921600 },
3248 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
3249 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3250 pbn_oxsemi_1_4000000 },
3251 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
3252 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3253 pbn_oxsemi_2_4000000 },
3254 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
3255 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3256 pbn_oxsemi_4_4000000 },
3257 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
3258 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3259 pbn_oxsemi_8_4000000 },
3260 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
3261 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3262 pbn_oxsemi_2_4000000 },
3263 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
3264 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3265 pbn_oxsemi_2_4000000 },
3266
3267 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
3268 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3269 pbn_b2_1_460800 },
3270 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
3271 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3272 pbn_b2_1_460800 },
3273 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
3274 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3275 pbn_b2_1_460800 },
3276 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
3277 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3278 pbn_b2_bt_2_921600 },
3279 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
3280 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3281 pbn_b2_bt_2_921600 },
3282 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
3283 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3284 pbn_b2_bt_2_921600 },
3285 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
3286 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3287 pbn_b2_bt_4_921600 },
3288 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
3289 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3290 pbn_b2_bt_4_921600 },
3291 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
3292 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3293 pbn_b2_bt_4_921600 },
3294 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
3295 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3296 pbn_b0_1_921600 },
3297 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
3298 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3299 pbn_b0_1_921600 },
3300 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
3301 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3302 pbn_b0_1_921600 },
3303 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
3304 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3305 pbn_b0_bt_2_921600 },
3306 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
3307 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3308 pbn_b0_bt_2_921600 },
3309 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
3310 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3311 pbn_b0_bt_2_921600 },
3312 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
3313 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3314 pbn_b0_bt_4_921600 },
3315 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
3316 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3317 pbn_b0_bt_4_921600 },
3318 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
3319 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3320 pbn_b0_bt_4_921600 },
3321 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
3322 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3323 pbn_b0_bt_8_921600 },
3324 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
3325 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3326 pbn_b0_bt_8_921600 },
3327 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
3328 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3329 pbn_b0_bt_8_921600 },
3330
3331 /*
3332 * Computone devices submitted by Doug McNash dmcnash@computone.com
3333 */
3334 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3335 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
3336 0, 0, pbn_computone_4 },
3337 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3338 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
3339 0, 0, pbn_computone_8 },
3340 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3341 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
3342 0, 0, pbn_computone_6 },
3343
3344 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
3345 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3346 pbn_oxsemi },
3347 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
3348 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
3349 pbn_b0_bt_1_921600 },
3350
3351 /*
3352 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
3353 */
3354 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
3355 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3356 pbn_b0_bt_8_115200 },
3357 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
3358 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3359 pbn_b0_bt_8_115200 },
3360
3361 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
3362 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3363 pbn_b0_bt_2_115200 },
3364 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
3365 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3366 pbn_b0_bt_2_115200 },
3367 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
3368 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3369 pbn_b0_bt_2_115200 },
3370 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
3371 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3372 pbn_b0_bt_2_115200 },
3373 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
3374 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3375 pbn_b0_bt_2_115200 },
3376 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
3377 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3378 pbn_b0_bt_4_460800 },
3379 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
3380 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3381 pbn_b0_bt_4_460800 },
3382 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
3383 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3384 pbn_b0_bt_2_460800 },
3385 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
3386 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3387 pbn_b0_bt_2_460800 },
3388 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
3389 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3390 pbn_b0_bt_2_460800 },
3391 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
3392 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3393 pbn_b0_bt_1_115200 },
3394 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
3395 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3396 pbn_b0_bt_1_460800 },
3397
3398 /*
3399 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
3400 * Cards are identified by their subsystem vendor IDs, which
3401 * (in hex) match the model number.
3402 *
3403 * Note that JC140x are RS422/485 cards which require ox950
3404 * ACR = 0x10, and as such are not currently fully supported.
3405 */
3406 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3407 0x1204, 0x0004, 0, 0,
3408 pbn_b0_4_921600 },
3409 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3410 0x1208, 0x0004, 0, 0,
3411 pbn_b0_4_921600 },
3412 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3413 0x1402, 0x0002, 0, 0,
3414 pbn_b0_2_921600 }, */
3415 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3416 0x1404, 0x0004, 0, 0,
3417 pbn_b0_4_921600 }, */
3418 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
3419 0x1208, 0x0004, 0, 0,
3420 pbn_b0_4_921600 },
3421
3422 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
3423 0x1204, 0x0004, 0, 0,
3424 pbn_b0_4_921600 },
3425 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
3426 0x1208, 0x0004, 0, 0,
3427 pbn_b0_4_921600 },
3428 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
3429 0x1208, 0x0004, 0, 0,
3430 pbn_b0_4_921600 },
3431 /*
3432 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
3433 */
3434 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
3435 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3436 pbn_b1_1_1382400 },
3437
3438 /*
3439 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
3440 */
3441 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
3442 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3443 pbn_b1_1_1382400 },
3444
3445 /*
3446 * RAStel 2 port modem, gerg@moreton.com.au
3447 */
3448 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
3449 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3450 pbn_b2_bt_2_115200 },
3451
3452 /*
3453 * EKF addition for i960 Boards form EKF with serial port
3454 */
3455 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
3456 0xE4BF, PCI_ANY_ID, 0, 0,
3457 pbn_intel_i960 },
3458
3459 /*
3460 * Xircom Cardbus/Ethernet combos
3461 */
3462 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
3463 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3464 pbn_b0_1_115200 },
3465 /*
3466 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
3467 */
3468 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
3469 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3470 pbn_b0_1_115200 },
3471
3472 /*
3473 * Untested PCI modems, sent in from various folks...
3474 */
3475
3476 /*
3477 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
3478 */
3479 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
3480 0x1048, 0x1500, 0, 0,
3481 pbn_b1_1_115200 },
3482
3483 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
3484 0xFF00, 0, 0, 0,
3485 pbn_sgi_ioc3 },
3486
3487 /*
3488 * HP Diva card
3489 */
3490 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
3491 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
3492 pbn_b1_1_115200 },
3493 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
3494 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3495 pbn_b0_5_115200 },
3496 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
3497 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3498 pbn_b2_1_115200 },
3499
3500 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
3501 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3502 pbn_b3_2_115200 },
3503 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
3504 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3505 pbn_b3_4_115200 },
3506 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
3507 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3508 pbn_b3_8_115200 },
3509
3510 /*
3511 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
3512 */
3513 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3514 PCI_ANY_ID, PCI_ANY_ID,
3515 0,
3516 0, pbn_exar_XR17C152 },
3517 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3518 PCI_ANY_ID, PCI_ANY_ID,
3519 0,
3520 0, pbn_exar_XR17C154 },
3521 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3522 PCI_ANY_ID, PCI_ANY_ID,
3523 0,
3524 0, pbn_exar_XR17C158 },
3525
3526 /*
3527 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
3528 */
3529 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
3530 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3531 pbn_b0_1_115200 },
3532 /*
3533 * ITE
3534 */
3535 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
3536 PCI_ANY_ID, PCI_ANY_ID,
3537 0, 0,
3538 pbn_b1_bt_1_115200 },
3539
3540 /*
3541 * IntaShield IS-200
3542 */
3543 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
3544 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */
3545 pbn_b2_2_115200 },
3546 /*
3547 * IntaShield IS-400
3548 */
3549 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
3550 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */
3551 pbn_b2_4_115200 },
3552 /*
3553 * Perle PCI-RAS cards
3554 */
3555 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3556 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
3557 0, 0, pbn_b2_4_921600 },
3558 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3559 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
3560 0, 0, pbn_b2_8_921600 },
3561
3562 /*
3563 * Mainpine series cards: Fairly standard layout but fools
3564 * parts of the autodetect in some cases and uses otherwise
3565 * unmatched communications subclasses in the PCI Express case
3566 */
3567
3568 { /* RockForceDUO */
3569 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3570 PCI_VENDOR_ID_MAINPINE, 0x0200,
3571 0, 0, pbn_b0_2_115200 },
3572 { /* RockForceQUATRO */
3573 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3574 PCI_VENDOR_ID_MAINPINE, 0x0300,
3575 0, 0, pbn_b0_4_115200 },
3576 { /* RockForceDUO+ */
3577 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3578 PCI_VENDOR_ID_MAINPINE, 0x0400,
3579 0, 0, pbn_b0_2_115200 },
3580 { /* RockForceQUATRO+ */
3581 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3582 PCI_VENDOR_ID_MAINPINE, 0x0500,
3583 0, 0, pbn_b0_4_115200 },
3584 { /* RockForce+ */
3585 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3586 PCI_VENDOR_ID_MAINPINE, 0x0600,
3587 0, 0, pbn_b0_2_115200 },
3588 { /* RockForce+ */
3589 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3590 PCI_VENDOR_ID_MAINPINE, 0x0700,
3591 0, 0, pbn_b0_4_115200 },
3592 { /* RockForceOCTO+ */
3593 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3594 PCI_VENDOR_ID_MAINPINE, 0x0800,
3595 0, 0, pbn_b0_8_115200 },
3596 { /* RockForceDUO+ */
3597 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3598 PCI_VENDOR_ID_MAINPINE, 0x0C00,
3599 0, 0, pbn_b0_2_115200 },
3600 { /* RockForceQUARTRO+ */
3601 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3602 PCI_VENDOR_ID_MAINPINE, 0x0D00,
3603 0, 0, pbn_b0_4_115200 },
3604 { /* RockForceOCTO+ */
3605 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3606 PCI_VENDOR_ID_MAINPINE, 0x1D00,
3607 0, 0, pbn_b0_8_115200 },
3608 { /* RockForceD1 */
3609 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3610 PCI_VENDOR_ID_MAINPINE, 0x2000,
3611 0, 0, pbn_b0_1_115200 },
3612 { /* RockForceF1 */
3613 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3614 PCI_VENDOR_ID_MAINPINE, 0x2100,
3615 0, 0, pbn_b0_1_115200 },
3616 { /* RockForceD2 */
3617 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3618 PCI_VENDOR_ID_MAINPINE, 0x2200,
3619 0, 0, pbn_b0_2_115200 },
3620 { /* RockForceF2 */
3621 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3622 PCI_VENDOR_ID_MAINPINE, 0x2300,
3623 0, 0, pbn_b0_2_115200 },
3624 { /* RockForceD4 */
3625 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3626 PCI_VENDOR_ID_MAINPINE, 0x2400,
3627 0, 0, pbn_b0_4_115200 },
3628 { /* RockForceF4 */
3629 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3630 PCI_VENDOR_ID_MAINPINE, 0x2500,
3631 0, 0, pbn_b0_4_115200 },
3632 { /* RockForceD8 */
3633 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3634 PCI_VENDOR_ID_MAINPINE, 0x2600,
3635 0, 0, pbn_b0_8_115200 },
3636 { /* RockForceF8 */
3637 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3638 PCI_VENDOR_ID_MAINPINE, 0x2700,
3639 0, 0, pbn_b0_8_115200 },
3640 { /* IQ Express D1 */
3641 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3642 PCI_VENDOR_ID_MAINPINE, 0x3000,
3643 0, 0, pbn_b0_1_115200 },
3644 { /* IQ Express F1 */
3645 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3646 PCI_VENDOR_ID_MAINPINE, 0x3100,
3647 0, 0, pbn_b0_1_115200 },
3648 { /* IQ Express D2 */
3649 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3650 PCI_VENDOR_ID_MAINPINE, 0x3200,
3651 0, 0, pbn_b0_2_115200 },
3652 { /* IQ Express F2 */
3653 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3654 PCI_VENDOR_ID_MAINPINE, 0x3300,
3655 0, 0, pbn_b0_2_115200 },
3656 { /* IQ Express D4 */
3657 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3658 PCI_VENDOR_ID_MAINPINE, 0x3400,
3659 0, 0, pbn_b0_4_115200 },
3660 { /* IQ Express F4 */
3661 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3662 PCI_VENDOR_ID_MAINPINE, 0x3500,
3663 0, 0, pbn_b0_4_115200 },
3664 { /* IQ Express D8 */
3665 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3666 PCI_VENDOR_ID_MAINPINE, 0x3C00,
3667 0, 0, pbn_b0_8_115200 },
3668 { /* IQ Express F8 */
3669 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3670 PCI_VENDOR_ID_MAINPINE, 0x3D00,
3671 0, 0, pbn_b0_8_115200 },
3672
3673
3674 /*
3675 * PA Semi PA6T-1682M on-chip UART
3676 */
3677 { PCI_VENDOR_ID_PASEMI, 0xa004,
3678 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3679 pbn_pasemi_1682M },
3680
3681 /*
3682 * National Instruments
3683 */
3684 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
3685 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3686 pbn_b1_16_115200 },
3687 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
3688 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3689 pbn_b1_8_115200 },
3690 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
3691 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3692 pbn_b1_bt_4_115200 },
3693 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
3694 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3695 pbn_b1_bt_2_115200 },
3696 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
3697 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3698 pbn_b1_bt_4_115200 },
3699 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
3700 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3701 pbn_b1_bt_2_115200 },
3702 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
3703 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3704 pbn_b1_16_115200 },
3705 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
3706 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3707 pbn_b1_8_115200 },
3708 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
3709 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3710 pbn_b1_bt_4_115200 },
3711 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
3712 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3713 pbn_b1_bt_2_115200 },
3714 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
3715 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3716 pbn_b1_bt_4_115200 },
3717 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
3718 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3719 pbn_b1_bt_2_115200 },
3720 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
3721 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3722 pbn_ni8430_2 },
3723 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
3724 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3725 pbn_ni8430_2 },
3726 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
3727 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3728 pbn_ni8430_4 },
3729 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
3730 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3731 pbn_ni8430_4 },
3732 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
3733 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3734 pbn_ni8430_8 },
3735 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
3736 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3737 pbn_ni8430_8 },
3738 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
3739 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3740 pbn_ni8430_16 },
3741 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
3742 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3743 pbn_ni8430_16 },
3744 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
3745 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3746 pbn_ni8430_2 },
3747 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
3748 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3749 pbn_ni8430_2 },
3750 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
3751 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3752 pbn_ni8430_4 },
3753 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
3754 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3755 pbn_ni8430_4 },
3756
3757 /*
3758 * ADDI-DATA GmbH communication cards <info@addi-data.com>
3759 */
3760 { PCI_VENDOR_ID_ADDIDATA,
3761 PCI_DEVICE_ID_ADDIDATA_APCI7500,
3762 PCI_ANY_ID,
3763 PCI_ANY_ID,
3764 0,
3765 0,
3766 pbn_b0_4_115200 },
3767
3768 { PCI_VENDOR_ID_ADDIDATA,
3769 PCI_DEVICE_ID_ADDIDATA_APCI7420,
3770 PCI_ANY_ID,
3771 PCI_ANY_ID,
3772 0,
3773 0,
3774 pbn_b0_2_115200 },
3775
3776 { PCI_VENDOR_ID_ADDIDATA,
3777 PCI_DEVICE_ID_ADDIDATA_APCI7300,
3778 PCI_ANY_ID,
3779 PCI_ANY_ID,
3780 0,
3781 0,
3782 pbn_b0_1_115200 },
3783
3784 { PCI_VENDOR_ID_ADDIDATA_OLD,
3785 PCI_DEVICE_ID_ADDIDATA_APCI7800,
3786 PCI_ANY_ID,
3787 PCI_ANY_ID,
3788 0,
3789 0,
3790 pbn_b1_8_115200 },
3791
3792 { PCI_VENDOR_ID_ADDIDATA,
3793 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
3794 PCI_ANY_ID,
3795 PCI_ANY_ID,
3796 0,
3797 0,
3798 pbn_b0_4_115200 },
3799
3800 { PCI_VENDOR_ID_ADDIDATA,
3801 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
3802 PCI_ANY_ID,
3803 PCI_ANY_ID,
3804 0,
3805 0,
3806 pbn_b0_2_115200 },
3807
3808 { PCI_VENDOR_ID_ADDIDATA,
3809 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
3810 PCI_ANY_ID,
3811 PCI_ANY_ID,
3812 0,
3813 0,
3814 pbn_b0_1_115200 },
3815
3816 { PCI_VENDOR_ID_ADDIDATA,
3817 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
3818 PCI_ANY_ID,
3819 PCI_ANY_ID,
3820 0,
3821 0,
3822 pbn_b0_4_115200 },
3823
3824 { PCI_VENDOR_ID_ADDIDATA,
3825 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
3826 PCI_ANY_ID,
3827 PCI_ANY_ID,
3828 0,
3829 0,
3830 pbn_b0_2_115200 },
3831
3832 { PCI_VENDOR_ID_ADDIDATA,
3833 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
3834 PCI_ANY_ID,
3835 PCI_ANY_ID,
3836 0,
3837 0,
3838 pbn_b0_1_115200 },
3839
3840 { PCI_VENDOR_ID_ADDIDATA,
3841 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
3842 PCI_ANY_ID,
3843 PCI_ANY_ID,
3844 0,
3845 0,
3846 pbn_b0_8_115200 },
3847
3848 { PCI_VENDOR_ID_ADDIDATA,
3849 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
3850 PCI_ANY_ID,
3851 PCI_ANY_ID,
3852 0,
3853 0,
3854 pbn_ADDIDATA_PCIe_4_3906250 },
3855
3856 { PCI_VENDOR_ID_ADDIDATA,
3857 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
3858 PCI_ANY_ID,
3859 PCI_ANY_ID,
3860 0,
3861 0,
3862 pbn_ADDIDATA_PCIe_2_3906250 },
3863
3864 { PCI_VENDOR_ID_ADDIDATA,
3865 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
3866 PCI_ANY_ID,
3867 PCI_ANY_ID,
3868 0,
3869 0,
3870 pbn_ADDIDATA_PCIe_1_3906250 },
3871
3872 { PCI_VENDOR_ID_ADDIDATA,
3873 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
3874 PCI_ANY_ID,
3875 PCI_ANY_ID,
3876 0,
3877 0,
3878 pbn_ADDIDATA_PCIe_8_3906250 },
3879
3880 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
3881 PCI_VENDOR_ID_IBM, 0x0299,
3882 0, 0, pbn_b0_bt_2_115200 },
3883
3884 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
3885 0xA000, 0x1000,
3886 0, 0, pbn_b0_1_115200 },
3887
3888 /*
3889 * Best Connectivity PCI Multi I/O cards
3890 */
3891
3892 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
3893 0xA000, 0x1000,
3894 0, 0, pbn_b0_1_115200 },
3895
3896 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
3897 0xA000, 0x3004,
3898 0, 0, pbn_b0_bt_4_115200 },
3899 /* Intel CE4100 */
3900 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
3901 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3902 pbn_ce4100_1_115200 },
3903
3904 /*
3905 * Cronyx Omega PCI
3906 */
3907 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
3908 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3909 pbn_omegapci },
3910
3911 /*
3912 * These entries match devices with class COMMUNICATION_SERIAL,
3913 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
3914 */
3915 { PCI_ANY_ID, PCI_ANY_ID,
3916 PCI_ANY_ID, PCI_ANY_ID,
3917 PCI_CLASS_COMMUNICATION_SERIAL << 8,
3918 0xffff00, pbn_default },
3919 { PCI_ANY_ID, PCI_ANY_ID,
3920 PCI_ANY_ID, PCI_ANY_ID,
3921 PCI_CLASS_COMMUNICATION_MODEM << 8,
3922 0xffff00, pbn_default },
3923 { PCI_ANY_ID, PCI_ANY_ID,
3924 PCI_ANY_ID, PCI_ANY_ID,
3925 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
3926 0xffff00, pbn_default },
3927 { 0, }
3928 };
3929
3930 static struct pci_driver serial_pci_driver = {
3931 .name = "serial",
3932 .probe = pciserial_init_one,
3933 .remove = __devexit_p(pciserial_remove_one),
3934 #ifdef CONFIG_PM
3935 .suspend = pciserial_suspend_one,
3936 .resume = pciserial_resume_one,
3937 #endif
3938 .id_table = serial_pci_tbl,
3939 };
3940
3941 static int __init serial8250_pci_init(void)
3942 {
3943 return pci_register_driver(&serial_pci_driver);
3944 }
3945
3946 static void __exit serial8250_pci_exit(void)
3947 {
3948 pci_unregister_driver(&serial_pci_driver);
3949 }
3950
3951 module_init(serial8250_pci_init);
3952 module_exit(serial8250_pci_exit);
3953
3954 MODULE_LICENSE("GPL");
3955 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
3956 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);