drivers/tty/serial/s3c2440.c

   1 /*
   2  * Driver for Samsung S3C2440 and S3C2442 SoC onboard UARTs.
   3  *
   4  * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
   5  *      http://armlinux.simtec.co.uk/
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10 */
  11
  12 #include <linux/module.h>
  13 #include <linux/ioport.h>
  14 #include <linux/io.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/init.h>
  17 #include <linux/serial_core.h>
  18 #include <linux/serial.h>
  19
  20 #include <asm/irq.h>
  21 #include <mach/hardware.h>
  22
  23 #include <plat/regs-serial.h>
  24 #include <mach/regs-gpio.h>
  25
  26 #include "samsung.h"
  27
  28
  29 static int s3c2440_serial_setsource(struct uart_port *port,
  30                                      struct s3c24xx_uart_clksrc *clk)
  31 {
  32         unsigned long ucon = rd_regl(port, S3C2410_UCON);
  33
  34         /* todo - proper fclk<>nonfclk switch. */
  35
  36         ucon &= ~S3C2440_UCON_CLKMASK;
  37
  38         if (strcmp(clk->name, "uclk") == 0)
  39                 ucon |= S3C2440_UCON_UCLK;
  40         else if (strcmp(clk->name, "pclk") == 0)
  41                 ucon |= S3C2440_UCON_PCLK;
  42         else if (strcmp(clk->name, "fclk") == 0)
  43                 ucon |= S3C2440_UCON_FCLK;
  44         else {
  45                 printk(KERN_ERR "unknown clock source %s\n", clk->name);
  46                 return -EINVAL;
  47         }
  48
  49         wr_regl(port, S3C2410_UCON, ucon);
  50         return 0;
  51 }
  52
  53
  54 static int s3c2440_serial_getsource(struct uart_port *port,
  55                                     struct s3c24xx_uart_clksrc *clk)
  56 {
  57         unsigned long ucon = rd_regl(port, S3C2410_UCON);
  58         unsigned long ucon0, ucon1, ucon2;
  59
  60         switch (ucon & S3C2440_UCON_CLKMASK) {
  61         case S3C2440_UCON_UCLK:
  62                 clk->divisor = 1;
  63                 clk->name = "uclk";
  64                 break;
  65
  66         case S3C2440_UCON_PCLK:
  67         case S3C2440_UCON_PCLK2:
  68                 clk->divisor = 1;
  69                 clk->name = "pclk";
  70                 break;
  71
  72         case S3C2440_UCON_FCLK:
  73                 /* the fun of calculating the uart divisors on
  74                  * the s3c2440 */
  75
  76                 ucon0 = __raw_readl(S3C24XX_VA_UART0 + S3C2410_UCON);
  77                 ucon1 = __raw_readl(S3C24XX_VA_UART1 + S3C2410_UCON);
  78                 ucon2 = __raw_readl(S3C24XX_VA_UART2 + S3C2410_UCON);
  79
  80                 printk("ucons: %08lx, %08lx, %08lx\n", ucon0, ucon1, ucon2);
  81
  82                 ucon0 &= S3C2440_UCON0_DIVMASK;
  83                 ucon1 &= S3C2440_UCON1_DIVMASK;
  84                 ucon2 &= S3C2440_UCON2_DIVMASK;
  85
  86                 if (ucon0 != 0) {
  87                         clk->divisor = ucon0 >> S3C2440_UCON_DIVSHIFT;
  88                         clk->divisor += 6;
  89                 } else if (ucon1 != 0) {
  90                         clk->divisor = ucon1 >> S3C2440_UCON_DIVSHIFT;
  91                         clk->divisor += 21;
  92                 } else if (ucon2 != 0) {
  93                         clk->divisor = ucon2 >> S3C2440_UCON_DIVSHIFT;
  94                         clk->divisor += 36;
  95                 } else {
  96                         /* manual calims 44, seems to be 9 */
  97                         clk->divisor = 9;
  98                 }
  99
 100                 clk->name = "fclk";
 101                 break;
 102         }
 103
 104         return 0;
 105 }
 106
 107 static int s3c2440_serial_resetport(struct uart_port *port,
 108                                     struct s3c2410_uartcfg *cfg)
 109 {
 110         unsigned long ucon = rd_regl(port, S3C2410_UCON);
 111
 112         dbg("s3c2440_serial_resetport: port=%p (%08lx), cfg=%p\n",
 113             port, port->mapbase, cfg);
 114
 115         /* ensure we don't change the clock settings... */
 116
 117         ucon &= (S3C2440_UCON0_DIVMASK | (3<<10));
 118
 119         wr_regl(port, S3C2410_UCON,  ucon | cfg->ucon);
 120         wr_regl(port, S3C2410_ULCON, cfg->ulcon);
 121
 122         /* reset both fifos */
 123
 124         wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
 125         wr_regl(port, S3C2410_UFCON, cfg->ufcon);
 126
 127         return 0;
 128 }
 129
 130 static struct s3c24xx_uart_info s3c2440_uart_inf = {
 131         .name           = "Samsung S3C2440 UART",
 132         .type           = PORT_S3C2440,
 133         .fifosize       = 64,
 134         .rx_fifomask    = S3C2440_UFSTAT_RXMASK,
 135         .rx_fifoshift   = S3C2440_UFSTAT_RXSHIFT,
 136         .rx_fifofull    = S3C2440_UFSTAT_RXFULL,
 137         .tx_fifofull    = S3C2440_UFSTAT_TXFULL,
 138         .tx_fifomask    = S3C2440_UFSTAT_TXMASK,
 139         .tx_fifoshift   = S3C2440_UFSTAT_TXSHIFT,
 140         .get_clksrc     = s3c2440_serial_getsource,
 141         .set_clksrc     = s3c2440_serial_setsource,
 142         .reset_port     = s3c2440_serial_resetport,
 143 };
 144
 145 /* device management */
 146
 147 static int s3c2440_serial_probe(struct platform_device *dev)
 148 {
 149         dbg("s3c2440_serial_probe: dev=%p\n", dev);
 150         return s3c24xx_serial_probe(dev, &s3c2440_uart_inf);
 151 }
 152
 153 static struct platform_driver s3c2440_serial_driver = {
 154         .probe          = s3c2440_serial_probe,
 155         .remove         = __devexit_p(s3c24xx_serial_remove),
 156         .driver         = {
 157                 .name   = "s3c2440-uart",
 158                 .owner  = THIS_MODULE,
 159         },
 160 };
 161
 162 s3c24xx_console_init(&s3c2440_serial_driver, &s3c2440_uart_inf);
 163
 164 static int __init s3c2440_serial_init(void)
 165 {
 166         return s3c24xx_serial_init(&s3c2440_serial_driver, &s3c2440_uart_inf);
 167 }
 168
 169 static void __exit s3c2440_serial_exit(void)
 170 {
 171         platform_driver_unregister(&s3c2440_serial_driver);
 172 }
 173
 174 module_init(s3c2440_serial_init);
 175 module_exit(s3c2440_serial_exit);
 176
 177 MODULE_DESCRIPTION("Samsung S3C2440,S3C2442 SoC Serial port driver");
 178 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
 179 MODULE_LICENSE("GPL v2");
 180 MODULE_ALIAS("platform:s3c2440-uart");