drivers/tty/serial/sh-sci.h

   1 #include <linux/serial_core.h>
   2 #include <linux/io.h>
   3 #include <linux/gpio.h>
   4
   5 #if defined(CONFIG_H83007) || defined(CONFIG_H83068)
   6 #include <asm/regs306x.h>
   7 #endif
   8 #if defined(CONFIG_H8S2678)
   9 #include <asm/regs267x.h>
  10 #endif
  11
  12 #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
  13     defined(CONFIG_CPU_SUBTYPE_SH7707) || \
  14     defined(CONFIG_CPU_SUBTYPE_SH7708) || \
  15     defined(CONFIG_CPU_SUBTYPE_SH7709)
  16 # define SCPCR  0xA4000116 /* 16 bit SCI and SCIF */
  17 # define SCPDR  0xA4000136 /* 8  bit SCI and SCIF */
  18 #elif defined(CONFIG_CPU_SUBTYPE_SH7705)
  19 # define SCIF0          0xA4400000
  20 # define SCIF2          0xA4410000
  21 # define SCPCR 0xA4000116
  22 # define SCPDR 0xA4000136
  23 #elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \
  24       defined(CONFIG_CPU_SUBTYPE_SH7721) || \
  25       defined(CONFIG_ARCH_SH73A0) || \
  26       defined(CONFIG_ARCH_SH7367) || \
  27       defined(CONFIG_ARCH_SH7377) || \
  28       defined(CONFIG_ARCH_SH7372)
  29 # define PORT_PTCR         0xA405011EUL
  30 # define PORT_PVCR         0xA4050122UL
  31 # define SCIF_ORER         0x0200   /* overrun error bit */
  32 #elif defined(CONFIG_SH_RTS7751R2D)
  33 # define SCSPTR1 0xFFE0001C /* 8 bit SCIF */
  34 # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
  35 # define SCIF_ORER 0x0001   /* overrun error bit */
  36 #elif defined(CONFIG_CPU_SUBTYPE_SH7750)  || \
  37       defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
  38       defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
  39       defined(CONFIG_CPU_SUBTYPE_SH7091)  || \
  40       defined(CONFIG_CPU_SUBTYPE_SH7751)  || \
  41       defined(CONFIG_CPU_SUBTYPE_SH7751R)
  42 # define SCSPTR1 0xffe0001c /* 8  bit SCI */
  43 # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
  44 # define SCIF_ORER 0x0001   /* overrun error bit */
  45 #elif defined(CONFIG_CPU_SUBTYPE_SH7760)
  46 # define SCSPTR0 0xfe600024 /* 16 bit SCIF */
  47 # define SCSPTR1 0xfe610024 /* 16 bit SCIF */
  48 # define SCSPTR2 0xfe620024 /* 16 bit SCIF */
  49 # define SCIF_ORER 0x0001  /* overrun error bit */
  50 #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
  51 # define SCSPTR0 0xA4400000       /* 16 bit SCIF */
  52 # define SCIF_ORER 0x0001   /* overrun error bit */
  53 # define PACR 0xa4050100
  54 # define PBCR 0xa4050102
  55 #elif defined(CONFIG_CPU_SUBTYPE_SH7343)
  56 # define SCSPTR0 0xffe00010     /* 16 bit SCIF */
  57 #elif defined(CONFIG_CPU_SUBTYPE_SH7722)
  58 # define PADR                   0xA4050120
  59 # define PSDR                   0xA405013e
  60 # define PWDR                   0xA4050166
  61 # define PSCR                   0xA405011E
  62 # define SCIF_ORER              0x0001  /* overrun error bit */
  63 #elif defined(CONFIG_CPU_SUBTYPE_SH7366)
  64 # define SCPDR0                 0xA405013E      /* 16 bit SCIF0 PSDR */
  65 # define SCSPTR0                SCPDR0
  66 # define SCIF_ORER              0x0001  /* overrun error bit */
  67 #elif defined(CONFIG_CPU_SUBTYPE_SH7723)
  68 # define SCSPTR0                0xa4050160
  69 # define SCIF_ORER              0x0001  /* overrun error bit */
  70 #elif defined(CONFIG_CPU_SUBTYPE_SH7724)
  71 # define SCIF_ORER              0x0001  /* overrun error bit */
  72 #elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
  73 # define SCSPTR2 0xffe80020 /* 16 bit SCIF */
  74 # define SCIF_ORER 0x0001   /* overrun error bit */
  75 #elif defined(CONFIG_H83007) || defined(CONFIG_H83068)
  76 # define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
  77 #elif defined(CONFIG_H8S2678)
  78 # define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
  79 #elif defined(CONFIG_CPU_SUBTYPE_SH7757)
  80 # define SCSPTR0 0xfe4b0020
  81 # define SCIF_ORER 0x0001
  82 #elif defined(CONFIG_CPU_SUBTYPE_SH7763)
  83 # define SCSPTR0 0xffe00024 /* 16 bit SCIF */
  84 # define SCIF_ORER 0x0001  /* overrun error bit */
  85 #elif defined(CONFIG_CPU_SUBTYPE_SH7770)
  86 # define SCSPTR0 0xff923020 /* 16 bit SCIF */
  87 # define SCIF_ORER 0x0001  /* overrun error bit */
  88 #elif defined(CONFIG_CPU_SUBTYPE_SH7780)
  89 # define SCSPTR0        0xffe00024      /* 16 bit SCIF */
  90 # define SCIF_ORER      0x0001          /* Overrun error bit */
  91 #elif defined(CONFIG_CPU_SUBTYPE_SH7785) || \
  92       defined(CONFIG_CPU_SUBTYPE_SH7786)
  93 # define SCSPTR0        0xffea0024      /* 16 bit SCIF */
  94 # define SCIF_ORER      0x0001          /* Overrun error bit */
  95 #elif defined(CONFIG_CPU_SUBTYPE_SH7201) || \
  96       defined(CONFIG_CPU_SUBTYPE_SH7203) || \
  97       defined(CONFIG_CPU_SUBTYPE_SH7206) || \
  98       defined(CONFIG_CPU_SUBTYPE_SH7263)
  99 # define SCSPTR0 0xfffe8020 /* 16 bit SCIF */
 100 #elif defined(CONFIG_CPU_SUBTYPE_SH7619)
 101 # define SCSPTR0 0xf8400020 /* 16 bit SCIF */
 102 # define SCIF_ORER 0x0001  /* overrun error bit */
 103 #elif defined(CONFIG_CPU_SUBTYPE_SHX3)
 104 # define SCSPTR0 0xffc30020             /* 16 bit SCIF */
 105 # define SCIF_ORER 0x0001               /* Overrun error bit */
 106 #else
 107 # error CPU subtype not defined
 108 #endif
 109
 110 /* SCxSR SCI */
 111 #define SCI_TDRE  0x80 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 112 #define SCI_RDRF  0x40 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 113 #define SCI_ORER  0x20 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 114 #define SCI_FER   0x10 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 115 #define SCI_PER   0x08 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 116 #define SCI_TEND  0x04 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 117 /*      SCI_MPB   0x02  * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 118 /*      SCI_MPBT  0x01  * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 119
 120 #define SCI_ERRORS ( SCI_PER | SCI_FER | SCI_ORER)
 121
 122 /* SCxSR SCIF */
 123 #define SCIF_ER    0x0080 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
 124 #define SCIF_TEND  0x0040 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
 125 #define SCIF_TDFE  0x0020 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
 126 #define SCIF_BRK   0x0010 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
 127 #define SCIF_FER   0x0008 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
 128 #define SCIF_PER   0x0004 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
 129 #define SCIF_RDF   0x0002 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
 130 #define SCIF_DR    0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
 131
 132 #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
 133     defined(CONFIG_CPU_SUBTYPE_SH7720) || \
 134     defined(CONFIG_CPU_SUBTYPE_SH7721) || \
 135     defined(CONFIG_ARCH_SH73A0) || \
 136     defined(CONFIG_ARCH_SH7367) || \
 137     defined(CONFIG_ARCH_SH7377) || \
 138     defined(CONFIG_ARCH_SH7372)
 139 # define SCIF_ORER    0x0200
 140 # define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER)
 141 # define SCIF_RFDC_MASK 0x007f
 142 # define SCIF_TXROOM_MAX 64
 143 #elif defined(CONFIG_CPU_SUBTYPE_SH7763)
 144 # define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK )
 145 # define SCIF_RFDC_MASK 0x007f
 146 # define SCIF_TXROOM_MAX 64
 147 /* SH7763 SCIF2 support */
 148 # define SCIF2_RFDC_MASK 0x001f
 149 # define SCIF2_TXROOM_MAX 16
 150 #else
 151 # define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
 152 # define SCIF_RFDC_MASK 0x001f
 153 # define SCIF_TXROOM_MAX 16
 154 #endif
 155
 156 #ifndef SCIF_ORER
 157 #define SCIF_ORER       0x0000
 158 #endif
 159
 160 #define SCxSR_TEND(port)        (((port)->type == PORT_SCI) ? SCI_TEND   : SCIF_TEND)
 161 #define SCxSR_ERRORS(port)      (((port)->type == PORT_SCI) ? SCI_ERRORS : SCIF_ERRORS)
 162 #define SCxSR_RDxF(port)        (((port)->type == PORT_SCI) ? SCI_RDRF   : SCIF_RDF)
 163 #define SCxSR_TDxE(port)        (((port)->type == PORT_SCI) ? SCI_TDRE   : SCIF_TDFE)
 164 #define SCxSR_FER(port)         (((port)->type == PORT_SCI) ? SCI_FER    : SCIF_FER)
 165 #define SCxSR_PER(port)         (((port)->type == PORT_SCI) ? SCI_PER    : SCIF_PER)
 166 #define SCxSR_BRK(port)         (((port)->type == PORT_SCI) ? 0x00       : SCIF_BRK)
 167 #define SCxSR_ORER(port)        (((port)->type == PORT_SCI) ? SCI_ORER   : SCIF_ORER)
 168
 169 #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
 170     defined(CONFIG_CPU_SUBTYPE_SH7720) || \
 171     defined(CONFIG_CPU_SUBTYPE_SH7721) || \
 172     defined(CONFIG_ARCH_SH73A0) || \
 173     defined(CONFIG_ARCH_SH7367) || \
 174     defined(CONFIG_ARCH_SH7377) || \
 175     defined(CONFIG_ARCH_SH7372)
 176 # define SCxSR_RDxF_CLEAR(port)  (sci_in(port, SCxSR) & 0xfffc)
 177 # define SCxSR_ERROR_CLEAR(port) (sci_in(port, SCxSR) & 0xfd73)
 178 # define SCxSR_TDxE_CLEAR(port)  (sci_in(port, SCxSR) & 0xffdf)
 179 # define SCxSR_BREAK_CLEAR(port) (sci_in(port, SCxSR) & 0xffe3)
 180 #else
 181 # define SCxSR_RDxF_CLEAR(port)  (((port)->type == PORT_SCI) ? 0xbc : 0x00fc)
 182 # define SCxSR_ERROR_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x0073)
 183 # define SCxSR_TDxE_CLEAR(port)  (((port)->type == PORT_SCI) ? 0x78 : 0x00df)
 184 # define SCxSR_BREAK_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x00e3)
 185 #endif
 186
 187 /* SCFCR */
 188 #define SCFCR_RFRST 0x0002
 189 #define SCFCR_TFRST 0x0004
 190 #define SCFCR_MCE   0x0008
 191
 192 #define SCI_MAJOR               204
 193 #define SCI_MINOR_START         8
 194
 195 #define SCI_IN(size, offset)                                    \
 196   if ((size) == 8) {                                            \
 197     return ioread8(port->membase + (offset));                   \
 198   } else {                                                      \
 199     return ioread16(port->membase + (offset));                  \
 200   }
 201 #define SCI_OUT(size, offset, value)                            \
 202   if ((size) == 8) {                                            \
 203     iowrite8(value, port->membase + (offset));                  \
 204   } else if ((size) == 16) {                                    \
 205     iowrite16(value, port->membase + (offset));                 \
 206   }
 207
 208 #define CPU_SCIx_FNS(name, sci_offset, sci_size, scif_offset, scif_size)\
 209   static inline unsigned int sci_##name##_in(struct uart_port *port)    \
 210   {                                                                     \
 211     if (port->type == PORT_SCIF || port->type == PORT_SCIFB) {          \
 212       SCI_IN(scif_size, scif_offset)                                    \
 213     } else {    /* PORT_SCI or PORT_SCIFA */                            \
 214       SCI_IN(sci_size, sci_offset);                                     \
 215     }                                                                   \
 216   }                                                                     \
 217   static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
 218   {                                                                     \
 219     if (port->type == PORT_SCIF || port->type == PORT_SCIFB) {          \
 220       SCI_OUT(scif_size, scif_offset, value)                            \
 221     } else {    /* PORT_SCI or PORT_SCIFA */                            \
 222       SCI_OUT(sci_size, sci_offset, value);                             \
 223     }                                                                   \
 224   }
 225
 226 #ifdef CONFIG_H8300
 227 /* h8300 don't have SCIF */
 228 #define CPU_SCIF_FNS(name)                                              \
 229   static inline unsigned int sci_##name##_in(struct uart_port *port)    \
 230   {                                                                     \
 231     return 0;                                                           \
 232   }                                                                     \
 233   static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
 234   {                                                                     \
 235   }
 236 #else
 237 #define CPU_SCIF_FNS(name, scif_offset, scif_size)                      \
 238   static inline unsigned int sci_##name##_in(struct uart_port *port)    \
 239   {                                                                     \
 240     SCI_IN(scif_size, scif_offset);                                     \
 241   }                                                                     \
 242   static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
 243   {                                                                     \
 244     SCI_OUT(scif_size, scif_offset, value);                             \
 245   }
 246 #endif
 247
 248 #define CPU_SCI_FNS(name, sci_offset, sci_size)                         \
 249   static inline unsigned int sci_##name##_in(struct uart_port* port)    \
 250   {                                                                     \
 251     SCI_IN(sci_size, sci_offset);                                       \
 252   }                                                                     \
 253   static inline void sci_##name##_out(struct uart_port* port, unsigned int value) \
 254   {                                                                     \
 255     SCI_OUT(sci_size, sci_offset, value);                               \
 256   }
 257
 258 #if defined(CONFIG_CPU_SH3) || \
 259     defined(CONFIG_ARCH_SH73A0) || \
 260     defined(CONFIG_ARCH_SH7367) || \
 261     defined(CONFIG_ARCH_SH7377) || \
 262     defined(CONFIG_ARCH_SH7372)
 263 #if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
 264 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
 265                                 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
 266                                  h8_sci_offset, h8_sci_size) \
 267   CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size)
 268 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
 269           CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
 270 #elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
 271       defined(CONFIG_CPU_SUBTYPE_SH7720) || \
 272       defined(CONFIG_CPU_SUBTYPE_SH7721) || \
 273       defined(CONFIG_ARCH_SH7367)
 274 #define SCIF_FNS(name, scif_offset, scif_size) \
 275   CPU_SCIF_FNS(name, scif_offset, scif_size)
 276 #elif defined(CONFIG_ARCH_SH7377) || \
 277       defined(CONFIG_ARCH_SH7372) || \
 278       defined(CONFIG_ARCH_SH73A0)
 279 #define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scifb_offset, sh4_scifb_size) \
 280   CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scifb_offset, sh4_scifb_size)
 281 #define SCIF_FNS(name, scif_offset, scif_size) \
 282   CPU_SCIF_FNS(name, scif_offset, scif_size)
 283 #else
 284 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
 285                  sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
 286                  h8_sci_offset, h8_sci_size) \
 287   CPU_SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh3_scif_offset, sh3_scif_size)
 288 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
 289   CPU_SCIF_FNS(name, sh3_scif_offset, sh3_scif_size)
 290 #endif
 291 #elif defined(__H8300H__) || defined(__H8300S__)
 292 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
 293                  sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
 294                  h8_sci_offset, h8_sci_size) \
 295   CPU_SCI_FNS(name, h8_sci_offset, h8_sci_size)
 296 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
 297   CPU_SCIF_FNS(name)
 298 #elif defined(CONFIG_CPU_SUBTYPE_SH7723) ||\
 299       defined(CONFIG_CPU_SUBTYPE_SH7724)
 300         #define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scif_offset, sh4_scif_size) \
 301                 CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scif_offset, sh4_scif_size)
 302         #define SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) \
 303                 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
 304 #else
 305 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
 306                  sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
 307                  h8_sci_offset, h8_sci_size) \
 308   CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size)
 309 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
 310   CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
 311 #endif
 312
 313 #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
 314     defined(CONFIG_CPU_SUBTYPE_SH7720) || \
 315     defined(CONFIG_CPU_SUBTYPE_SH7721) || \
 316     defined(CONFIG_ARCH_SH7367)
 317
 318 SCIF_FNS(SCSMR,  0x00, 16)
 319 SCIF_FNS(SCBRR,  0x04,  8)
 320 SCIF_FNS(SCSCR,  0x08, 16)
 321 SCIF_FNS(SCxSR,  0x14, 16)
 322 SCIF_FNS(SCFCR,  0x18, 16)
 323 SCIF_FNS(SCFDR,  0x1c, 16)
 324 SCIF_FNS(SCxTDR, 0x20,  8)
 325 SCIF_FNS(SCxRDR, 0x24,  8)
 326 SCIF_FNS(SCLSR,  0x00,  0)
 327 #elif defined(CONFIG_ARCH_SH7377) || \
 328       defined(CONFIG_ARCH_SH7372) || \
 329       defined(CONFIG_ARCH_SH73A0)
 330 SCIF_FNS(SCSMR,  0x00, 16)
 331 SCIF_FNS(SCBRR,  0x04,  8)
 332 SCIF_FNS(SCSCR,  0x08, 16)
 333 SCIF_FNS(SCTDSR, 0x0c, 16)
 334 SCIF_FNS(SCFER,  0x10, 16)
 335 SCIF_FNS(SCxSR,  0x14, 16)
 336 SCIF_FNS(SCFCR,  0x18, 16)
 337 SCIF_FNS(SCFDR,  0x1c, 16)
 338 SCIF_FNS(SCTFDR, 0x38, 16)
 339 SCIF_FNS(SCRFDR, 0x3c, 16)
 340 SCIx_FNS(SCxTDR, 0x20,  8, 0x40,  8)
 341 SCIx_FNS(SCxRDR, 0x24,  8, 0x60,  8)
 342 SCIF_FNS(SCLSR,  0x00,  0)
 343 #elif defined(CONFIG_CPU_SUBTYPE_SH7723) ||\
 344       defined(CONFIG_CPU_SUBTYPE_SH7724)
 345 SCIx_FNS(SCSMR,  0x00, 16, 0x00, 16)
 346 SCIx_FNS(SCBRR,  0x04,  8, 0x04,  8)
 347 SCIx_FNS(SCSCR,  0x08, 16, 0x08, 16)
 348 SCIx_FNS(SCxTDR, 0x20,  8, 0x0c,  8)
 349 SCIx_FNS(SCxSR,  0x14, 16, 0x10, 16)
 350 SCIx_FNS(SCxRDR, 0x24,  8, 0x14,  8)
 351 SCIx_FNS(SCSPTR, 0,     0,    0,  0)
 352 SCIF_FNS(SCFCR,  0x18, 16)
 353 SCIF_FNS(SCFDR,  0x1c, 16)
 354 SCIF_FNS(SCLSR,  0x24, 16)
 355 #else
 356 /*      reg      SCI/SH3   SCI/SH4  SCIF/SH3   SCIF/SH4  SCI/H8*/
 357 /*      name     off  sz   off  sz   off  sz   off  sz   off  sz*/
 358 SCIx_FNS(SCSMR,  0x00,  8, 0x00,  8, 0x00,  8, 0x00, 16, 0x00,  8)
 359 SCIx_FNS(SCBRR,  0x02,  8, 0x04,  8, 0x02,  8, 0x04,  8, 0x01,  8)
 360 SCIx_FNS(SCSCR,  0x04,  8, 0x08,  8, 0x04,  8, 0x08, 16, 0x02,  8)
 361 SCIx_FNS(SCxTDR, 0x06,  8, 0x0c,  8, 0x06,  8, 0x0C,  8, 0x03,  8)
 362 SCIx_FNS(SCxSR,  0x08,  8, 0x10,  8, 0x08, 16, 0x10, 16, 0x04,  8)
 363 SCIx_FNS(SCxRDR, 0x0a,  8, 0x14,  8, 0x0A,  8, 0x14,  8, 0x05,  8)
 364 SCIF_FNS(SCFCR,                      0x0c,  8, 0x18, 16)
 365 #if defined(CONFIG_CPU_SUBTYPE_SH7760) || \
 366     defined(CONFIG_CPU_SUBTYPE_SH7780) || \
 367     defined(CONFIG_CPU_SUBTYPE_SH7785) || \
 368     defined(CONFIG_CPU_SUBTYPE_SH7786)
 369 SCIF_FNS(SCFDR,                      0x0e, 16, 0x1C, 16)
 370 SCIF_FNS(SCTFDR,                     0x0e, 16, 0x1C, 16)
 371 SCIF_FNS(SCRFDR,                     0x0e, 16, 0x20, 16)
 372 SCIF_FNS(SCSPTR,                        0,  0, 0x24, 16)
 373 SCIF_FNS(SCLSR,                         0,  0, 0x28, 16)
 374 #elif defined(CONFIG_CPU_SUBTYPE_SH7763)
 375 SCIF_FNS(SCFDR,                         0,  0, 0x1C, 16)
 376 SCIF_FNS(SCTFDR,                     0x0e, 16, 0x1C, 16)
 377 SCIF_FNS(SCRFDR,                     0x0e, 16, 0x20, 16)
 378 SCIF_FNS(SCSPTR,                        0,  0, 0x24, 16)
 379 SCIF_FNS(SCLSR,                         0,  0, 0x28, 16)
 380 #else
 381 SCIF_FNS(SCFDR,                      0x0e, 16, 0x1C, 16)
 382 #if defined(CONFIG_CPU_SUBTYPE_SH7722)
 383 SCIF_FNS(SCSPTR,                        0,  0, 0, 0)
 384 #else
 385 SCIF_FNS(SCSPTR,                        0,  0, 0x20, 16)
 386 #endif
 387 SCIF_FNS(SCLSR,                         0,  0, 0x24, 16)
 388 #endif
 389 #endif
 390 #define sci_in(port, reg) sci_##reg##_in(port)
 391 #define sci_out(port, reg, value) sci_##reg##_out(port, value)
 392
 393 /* H8/300 series SCI pins assignment */
 394 #if defined(__H8300H__) || defined(__H8300S__)
 395 static const struct __attribute__((packed)) {
 396         int port;             /* GPIO port no */
 397         unsigned short rx,tx; /* GPIO bit no */
 398 } h8300_sci_pins[] = {
 399 #if defined(CONFIG_H83007) || defined(CONFIG_H83068)
 400         {    /* SCI0 */
 401                 .port = H8300_GPIO_P9,
 402                 .rx   = H8300_GPIO_B2,
 403                 .tx   = H8300_GPIO_B0,
 404         },
 405         {    /* SCI1 */
 406                 .port = H8300_GPIO_P9,
 407                 .rx   = H8300_GPIO_B3,
 408                 .tx   = H8300_GPIO_B1,
 409         },
 410         {    /* SCI2 */
 411                 .port = H8300_GPIO_PB,
 412                 .rx   = H8300_GPIO_B7,
 413                 .tx   = H8300_GPIO_B6,
 414         }
 415 #elif defined(CONFIG_H8S2678)
 416         {    /* SCI0 */
 417                 .port = H8300_GPIO_P3,
 418                 .rx   = H8300_GPIO_B2,
 419                 .tx   = H8300_GPIO_B0,
 420         },
 421         {    /* SCI1 */
 422                 .port = H8300_GPIO_P3,
 423                 .rx   = H8300_GPIO_B3,
 424                 .tx   = H8300_GPIO_B1,
 425         },
 426         {    /* SCI2 */
 427                 .port = H8300_GPIO_P5,
 428                 .rx   = H8300_GPIO_B1,
 429                 .tx   = H8300_GPIO_B0,
 430         }
 431 #endif
 432 };
 433 #endif
 434
 435 #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
 436     defined(CONFIG_CPU_SUBTYPE_SH7707) || \
 437     defined(CONFIG_CPU_SUBTYPE_SH7708) || \
 438     defined(CONFIG_CPU_SUBTYPE_SH7709)
 439 static inline int sci_rxd_in(struct uart_port *port)
 440 {
 441         if (port->mapbase == 0xfffffe80)
 442                 return __raw_readb(SCPDR)&0x01 ? 1 : 0; /* SCI */
 443         return 1;
 444 }
 445 #elif defined(CONFIG_CPU_SUBTYPE_SH7750)  || \
 446       defined(CONFIG_CPU_SUBTYPE_SH7751)  || \
 447       defined(CONFIG_CPU_SUBTYPE_SH7751R) || \
 448       defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
 449       defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
 450       defined(CONFIG_CPU_SUBTYPE_SH7091)
 451 static inline int sci_rxd_in(struct uart_port *port)
 452 {
 453         if (port->mapbase == 0xffe00000)
 454                 return __raw_readb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */
 455         return 1;
 456 }
 457 #elif defined(__H8300H__) || defined(__H8300S__)
 458 static inline int sci_rxd_in(struct uart_port *port)
 459 {
 460         int ch = (port->mapbase - SMR0) >> 3;
 461         return (H8300_SCI_DR(ch) & h8300_sci_pins[ch].rx) ? 1 : 0;
 462 }
 463 #else /* default case for non-SCI processors */
 464 static inline int sci_rxd_in(struct uart_port *port)
 465 {
 466         return 1;
 467 }
 468 #endif