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ASoC: sh: fsi: remove pm_runtime from fsi_dai_set_fmt.
[zen-stable.git] / sound / soc / sh / fsi.c
bloba1081c755239e5670f41941a580195c9d007309f
1 /*
2 * Fifo-attached Serial Interface (FSI) support for SH7724
3 *
4 * Copyright (C) 2009 Renesas Solutions Corp.
5 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
6 *
7 * Based on ssi.c
8 * Copyright (c) 2007 Manuel Lauss <mano@roarinelk.homelinux.net>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15 #include <linux/delay.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/io.h>
18 #include <linux/slab.h>
19 #include <sound/soc.h>
20 #include <sound/sh_fsi.h>
21
22 /* PortA/PortB register */
23 #define REG_DO_FMT 0x0000
24 #define REG_DOFF_CTL 0x0004
25 #define REG_DOFF_ST 0x0008
26 #define REG_DI_FMT 0x000C
27 #define REG_DIFF_CTL 0x0010
28 #define REG_DIFF_ST 0x0014
29 #define REG_CKG1 0x0018
30 #define REG_CKG2 0x001C
31 #define REG_DIDT 0x0020
32 #define REG_DODT 0x0024
33 #define REG_MUTE_ST 0x0028
34 #define REG_OUT_SEL 0x0030
35
36 /* master register */
37 #define MST_CLK_RST 0x0210
38 #define MST_SOFT_RST 0x0214
39 #define MST_FIFO_SZ 0x0218
40
41 /* core register (depend on FSI version) */
42 #define A_MST_CTLR 0x0180
43 #define B_MST_CTLR 0x01A0
44 #define CPU_INT_ST 0x01F4
45 #define CPU_IEMSK 0x01F8
46 #define CPU_IMSK 0x01FC
47 #define INT_ST 0x0200
48 #define IEMSK 0x0204
49 #define IMSK 0x0208
50
51 /* DO_FMT */
52 /* DI_FMT */
53 #define CR_BWS_24 (0x0 << 20) /* FSI2 */
54 #define CR_BWS_16 (0x1 << 20) /* FSI2 */
55 #define CR_BWS_20 (0x2 << 20) /* FSI2 */
56
57 #define CR_DTMD_PCM (0x0 << 8) /* FSI2 */
58 #define CR_DTMD_SPDIF_PCM (0x1 << 8) /* FSI2 */
59 #define CR_DTMD_SPDIF_STREAM (0x2 << 8) /* FSI2 */
60
61 #define CR_MONO (0x0 << 4)
62 #define CR_MONO_D (0x1 << 4)
63 #define CR_PCM (0x2 << 4)
64 #define CR_I2S (0x3 << 4)
65 #define CR_TDM (0x4 << 4)
66 #define CR_TDM_D (0x5 << 4)
67
68 /* DOFF_CTL */
69 /* DIFF_CTL */
70 #define IRQ_HALF 0x00100000
71 #define FIFO_CLR 0x00000001
72
73 /* DOFF_ST */
74 #define ERR_OVER 0x00000010
75 #define ERR_UNDER 0x00000001
76 #define ST_ERR (ERR_OVER | ERR_UNDER)
77
78 /* CKG1 */
79 #define ACKMD_MASK 0x00007000
80 #define BPFMD_MASK 0x00000700
81 #define DIMD (1 << 4)
82 #define DOMD (1 << 0)
83
84 /* A/B MST_CTLR */
85 #define BP (1 << 4) /* Fix the signal of Biphase output */
86 #define SE (1 << 0) /* Fix the master clock */
87
88 /* CLK_RST */
89 #define CRB (1 << 4)
90 #define CRA (1 << 0)
91
92 /* IO SHIFT / MACRO */
93 #define BI_SHIFT 12
94 #define BO_SHIFT 8
95 #define AI_SHIFT 4
96 #define AO_SHIFT 0
97 #define AB_IO(param, shift) (param << shift)
98
99 /* SOFT_RST */
100 #define PBSR (1 << 12) /* Port B Software Reset */
101 #define PASR (1 << 8) /* Port A Software Reset */
102 #define IR (1 << 4) /* Interrupt Reset */
103 #define FSISR (1 << 0) /* Software Reset */
104
105 /* OUT_SEL (FSI2) */
106 #define DMMD (1 << 4) /* SPDIF output timing 0: Biphase only */
107 /* 1: Biphase and serial */
108
109 /* FIFO_SZ */
110 #define FIFO_SZ_MASK 0x7
111
112 #define FSI_RATES SNDRV_PCM_RATE_8000_96000
113
114 #define FSI_FMTS (SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S16_LE)
115
116 typedef int (*set_rate_func)(struct device *dev, int is_porta, int rate, int enable);
117
118 /*
119 * FSI driver use below type name for variable
120 *
121 * xxx_num : number of data
122 * xxx_pos : position of data
123 * xxx_capa : capacity of data
124 */
125
126 /*
127 * period/frame/sample image
128 *
129 * ex) PCM (2ch)
130 *
131 * period pos period pos
132 * [n] [n + 1]
133 * |<-------------------- period--------------------->|
134 * ==|============================================ ... =|==
135 * | |
136 * ||<----- frame ----->|<------ frame ----->| ... |
137 * |+--------------------+--------------------+- ... |
138 * ||[ sample ][ sample ]|[ sample ][ sample ]| ... |
139 * |+--------------------+--------------------+- ... |
140 * ==|============================================ ... =|==
141 */
142
143 /*
144 * FSI FIFO image
145 *
146 * | |
147 * | |
148 * | [ sample ] |
149 * | [ sample ] |
150 * | [ sample ] |
151 * | [ sample ] |
152 * --> go to codecs
153 */
154
155 /*
156 * struct
157 */
158
159 struct fsi_stream {
160 struct snd_pcm_substream *substream;
161
162 int fifo_sample_capa; /* sample capacity of FSI FIFO */
163 int buff_sample_capa; /* sample capacity of ALSA buffer */
164 int buff_sample_pos; /* sample position of ALSA buffer */
165 int period_samples; /* sample number / 1 period */
166 int period_pos; /* current period position */
167
168 int uerr_num;
169 int oerr_num;
170 };
171
172 struct fsi_priv {
173 void __iomem *base;
174 struct fsi_master *master;
175
176 struct fsi_stream playback;
177 struct fsi_stream capture;
178
179 u32 do_fmt;
180 u32 di_fmt;
181
182 int chan_num:16;
183 int clk_master:1;
184 int spdif:1;
185
186 long rate;
187
188 /* for suspend/resume */
189 u32 saved_do_fmt;
190 u32 saved_di_fmt;
191 u32 saved_ckg1;
192 u32 saved_ckg2;
193 u32 saved_out_sel;
194 };
195
196 struct fsi_core {
197 int ver;
198
199 u32 int_st;
200 u32 iemsk;
201 u32 imsk;
202 u32 a_mclk;
203 u32 b_mclk;
204 };
205
206 struct fsi_master {
207 void __iomem *base;
208 int irq;
209 struct fsi_priv fsia;
210 struct fsi_priv fsib;
211 struct fsi_core *core;
212 struct sh_fsi_platform_info *info;
213 spinlock_t lock;
214
215 /* for suspend/resume */
216 u32 saved_a_mclk;
217 u32 saved_b_mclk;
218 u32 saved_iemsk;
219 u32 saved_imsk;
220 u32 saved_clk_rst;
221 u32 saved_soft_rst;
222 };
223
224 /*
225 * basic read write function
226 */
227
228 static void __fsi_reg_write(u32 reg, u32 data)
229 {
230 /* valid data area is 24bit */
231 data &= 0x00ffffff;
232
233 __raw_writel(data, reg);
234 }
235
236 static u32 __fsi_reg_read(u32 reg)
237 {
238 return __raw_readl(reg);
239 }
240
241 static void __fsi_reg_mask_set(u32 reg, u32 mask, u32 data)
242 {
243 u32 val = __fsi_reg_read(reg);
244
245 val &= ~mask;
246 val |= data & mask;
247
248 __fsi_reg_write(reg, val);
249 }
250
251 #define fsi_reg_write(p, r, d)\
252 __fsi_reg_write((u32)(p->base + REG_##r), d)
253
254 #define fsi_reg_read(p, r)\
255 __fsi_reg_read((u32)(p->base + REG_##r))
256
257 #define fsi_reg_mask_set(p, r, m, d)\
258 __fsi_reg_mask_set((u32)(p->base + REG_##r), m, d)
259
260 #define fsi_master_read(p, r) _fsi_master_read(p, MST_##r)
261 #define fsi_core_read(p, r) _fsi_master_read(p, p->core->r)
262 static u32 _fsi_master_read(struct fsi_master *master, u32 reg)
263 {
264 u32 ret;
265 unsigned long flags;
266
267 spin_lock_irqsave(&master->lock, flags);
268 ret = __fsi_reg_read((u32)(master->base + reg));
269 spin_unlock_irqrestore(&master->lock, flags);
270
271 return ret;
272 }
273
274 #define fsi_master_mask_set(p, r, m, d) _fsi_master_mask_set(p, MST_##r, m, d)
275 #define fsi_core_mask_set(p, r, m, d) _fsi_master_mask_set(p, p->core->r, m, d)
276 static void _fsi_master_mask_set(struct fsi_master *master,
277 u32 reg, u32 mask, u32 data)
278 {
279 unsigned long flags;
280
281 spin_lock_irqsave(&master->lock, flags);
282 __fsi_reg_mask_set((u32)(master->base + reg), mask, data);
283 spin_unlock_irqrestore(&master->lock, flags);
284 }
285
286 /*
287 * basic function
288 */
289
290 static struct fsi_master *fsi_get_master(struct fsi_priv *fsi)
291 {
292 return fsi->master;
293 }
294
295 static int fsi_is_clk_master(struct fsi_priv *fsi)
296 {
297 return fsi->clk_master;
298 }
299
300 static int fsi_is_port_a(struct fsi_priv *fsi)
301 {
302 return fsi->master->base == fsi->base;
303 }
304
305 static int fsi_is_spdif(struct fsi_priv *fsi)
306 {
307 return fsi->spdif;
308 }
309
310 static struct snd_soc_dai *fsi_get_dai(struct snd_pcm_substream *substream)
311 {
312 struct snd_soc_pcm_runtime *rtd = substream->private_data;
313
314 return rtd->cpu_dai;
315 }
316
317 static struct fsi_priv *fsi_get_priv_frm_dai(struct snd_soc_dai *dai)
318 {
319 struct fsi_master *master = snd_soc_dai_get_drvdata(dai);
320
321 if (dai->id == 0)
322 return &master->fsia;
323 else
324 return &master->fsib;
325 }
326
327 static struct fsi_priv *fsi_get_priv(struct snd_pcm_substream *substream)
328 {
329 return fsi_get_priv_frm_dai(fsi_get_dai(substream));
330 }
331
332 static set_rate_func fsi_get_info_set_rate(struct fsi_master *master)
333 {
334 if (!master->info)
335 return NULL;
336
337 return master->info->set_rate;
338 }
339
340 static u32 fsi_get_info_flags(struct fsi_priv *fsi)
341 {
342 int is_porta = fsi_is_port_a(fsi);
343 struct fsi_master *master = fsi_get_master(fsi);
344
345 if (!master->info)
346 return 0;
347
348 return is_porta ? master->info->porta_flags :
349 master->info->portb_flags;
350 }
351
352 static inline int fsi_stream_is_play(int stream)
353 {
354 return stream == SNDRV_PCM_STREAM_PLAYBACK;
355 }
356
357 static inline int fsi_is_play(struct snd_pcm_substream *substream)
358 {
359 return fsi_stream_is_play(substream->stream);
360 }
361
362 static inline struct fsi_stream *fsi_get_stream(struct fsi_priv *fsi,
363 int is_play)
364 {
365 return is_play ? &fsi->playback : &fsi->capture;
366 }
367
368 static u32 fsi_get_port_shift(struct fsi_priv *fsi, int is_play)
369 {
370 int is_porta = fsi_is_port_a(fsi);
371 u32 shift;
372
373 if (is_porta)
374 shift = is_play ? AO_SHIFT : AI_SHIFT;
375 else
376 shift = is_play ? BO_SHIFT : BI_SHIFT;
377
378 return shift;
379 }
380
381 static int fsi_frame2sample(struct fsi_priv *fsi, int frames)
382 {
383 return frames * fsi->chan_num;
384 }
385
386 static int fsi_sample2frame(struct fsi_priv *fsi, int samples)
387 {
388 return samples / fsi->chan_num;
389 }
390
391 static void fsi_stream_push(struct fsi_priv *fsi,
392 int is_play,
393 struct snd_pcm_substream *substream)
394 {
395 struct fsi_stream *io = fsi_get_stream(fsi, is_play);
396 struct snd_pcm_runtime *runtime = substream->runtime;
397
398 io->substream = substream;
399 io->buff_sample_capa = fsi_frame2sample(fsi, runtime->buffer_size);
400 io->buff_sample_pos = 0;
401 io->period_samples = fsi_frame2sample(fsi, runtime->period_size);
402 io->period_pos = 0;
403 io->oerr_num = -1; /* ignore 1st err */
404 io->uerr_num = -1; /* ignore 1st err */
405 }
406
407 static void fsi_stream_pop(struct fsi_priv *fsi, int is_play)
408 {
409 struct fsi_stream *io = fsi_get_stream(fsi, is_play);
410 struct snd_soc_dai *dai = fsi_get_dai(io->substream);
411
412
413 if (io->oerr_num > 0)
414 dev_err(dai->dev, "over_run = %d\n", io->oerr_num);
415
416 if (io->uerr_num > 0)
417 dev_err(dai->dev, "under_run = %d\n", io->uerr_num);
418
419 io->substream = NULL;
420 io->buff_sample_capa = 0;
421 io->buff_sample_pos = 0;
422 io->period_samples = 0;
423 io->period_pos = 0;
424 io->oerr_num = 0;
425 io->uerr_num = 0;
426 }
427
428 static int fsi_get_current_fifo_samples(struct fsi_priv *fsi, int is_play)
429 {
430 u32 status;
431 int frames;
432
433 status = is_play ?
434 fsi_reg_read(fsi, DOFF_ST) :
435 fsi_reg_read(fsi, DIFF_ST);
436
437 frames = 0x1ff & (status >> 8);
438
439 return fsi_frame2sample(fsi, frames);
440 }
441
442 static void fsi_count_fifo_err(struct fsi_priv *fsi)
443 {
444 u32 ostatus = fsi_reg_read(fsi, DOFF_ST);
445 u32 istatus = fsi_reg_read(fsi, DIFF_ST);
446
447 if (ostatus & ERR_OVER)
448 fsi->playback.oerr_num++;
449
450 if (ostatus & ERR_UNDER)
451 fsi->playback.uerr_num++;
452
453 if (istatus & ERR_OVER)
454 fsi->capture.oerr_num++;
455
456 if (istatus & ERR_UNDER)
457 fsi->capture.uerr_num++;
458
459 fsi_reg_write(fsi, DOFF_ST, 0);
460 fsi_reg_write(fsi, DIFF_ST, 0);
461 }
462
463 /*
464 * dma function
465 */
466
467 static u8 *fsi_dma_get_area(struct fsi_priv *fsi, int stream)
468 {
469 int is_play = fsi_stream_is_play(stream);
470 struct fsi_stream *io = fsi_get_stream(fsi, is_play);
471 struct snd_pcm_runtime *runtime = io->substream->runtime;
472
473 return runtime->dma_area +
474 samples_to_bytes(runtime, io->buff_sample_pos);
475 }
476
477 static void fsi_dma_soft_push16(struct fsi_priv *fsi, int num)
478 {
479 u16 *start;
480 int i;
481
482 start = (u16 *)fsi_dma_get_area(fsi, SNDRV_PCM_STREAM_PLAYBACK);
483
484 for (i = 0; i < num; i++)
485 fsi_reg_write(fsi, DODT, ((u32)*(start + i) << 8));
486 }
487
488 static void fsi_dma_soft_pop16(struct fsi_priv *fsi, int num)
489 {
490 u16 *start;
491 int i;
492
493 start = (u16 *)fsi_dma_get_area(fsi, SNDRV_PCM_STREAM_CAPTURE);
494
495
496 for (i = 0; i < num; i++)
497 *(start + i) = (u16)(fsi_reg_read(fsi, DIDT) >> 8);
498 }
499
500 static void fsi_dma_soft_push32(struct fsi_priv *fsi, int num)
501 {
502 u32 *start;
503 int i;
504
505 start = (u32 *)fsi_dma_get_area(fsi, SNDRV_PCM_STREAM_PLAYBACK);
506
507
508 for (i = 0; i < num; i++)
509 fsi_reg_write(fsi, DODT, *(start + i));
510 }
511
512 static void fsi_dma_soft_pop32(struct fsi_priv *fsi, int num)
513 {
514 u32 *start;
515 int i;
516
517 start = (u32 *)fsi_dma_get_area(fsi, SNDRV_PCM_STREAM_CAPTURE);
518
519 for (i = 0; i < num; i++)
520 *(start + i) = fsi_reg_read(fsi, DIDT);
521 }
522
523 /*
524 * irq function
525 */
526
527 static void fsi_irq_enable(struct fsi_priv *fsi, int is_play)
528 {
529 u32 data = AB_IO(1, fsi_get_port_shift(fsi, is_play));
530 struct fsi_master *master = fsi_get_master(fsi);
531
532 fsi_core_mask_set(master, imsk, data, data);
533 fsi_core_mask_set(master, iemsk, data, data);
534 }
535
536 static void fsi_irq_disable(struct fsi_priv *fsi, int is_play)
537 {
538 u32 data = AB_IO(1, fsi_get_port_shift(fsi, is_play));
539 struct fsi_master *master = fsi_get_master(fsi);
540
541 fsi_core_mask_set(master, imsk, data, 0);
542 fsi_core_mask_set(master, iemsk, data, 0);
543 }
544
545 static u32 fsi_irq_get_status(struct fsi_master *master)
546 {
547 return fsi_core_read(master, int_st);
548 }
549
550 static void fsi_irq_clear_status(struct fsi_priv *fsi)
551 {
552 u32 data = 0;
553 struct fsi_master *master = fsi_get_master(fsi);
554
555 data |= AB_IO(1, fsi_get_port_shift(fsi, 0));
556 data |= AB_IO(1, fsi_get_port_shift(fsi, 1));
557
558 /* clear interrupt factor */
559 fsi_core_mask_set(master, int_st, data, 0);
560 }
561
562 /*
563 * SPDIF master clock function
564 *
565 * These functions are used later FSI2
566 */
567 static void fsi_spdif_clk_ctrl(struct fsi_priv *fsi, int enable)
568 {
569 struct fsi_master *master = fsi_get_master(fsi);
570 u32 mask, val;
571
572 if (master->core->ver < 2) {
573 pr_err("fsi: register access err (%s)\n", __func__);
574 return;
575 }
576
577 mask = BP | SE;
578 val = enable ? mask : 0;
579
580 fsi_is_port_a(fsi) ?
581 fsi_core_mask_set(master, a_mclk, mask, val) :
582 fsi_core_mask_set(master, b_mclk, mask, val);
583 }
584
585 /*
586 * clock function
587 */
588 static int fsi_set_master_clk(struct device *dev, struct fsi_priv *fsi,
589 long rate, int enable)
590 {
591 struct fsi_master *master = fsi_get_master(fsi);
592 set_rate_func set_rate = fsi_get_info_set_rate(master);
593 int fsi_ver = master->core->ver;
594 int ret;
595
596 ret = set_rate(dev, fsi_is_port_a(fsi), rate, enable);
597 if (ret < 0) /* error */
598 return ret;
599
600 if (!enable)
601 return 0;
602
603 if (ret > 0) {
604 u32 data = 0;
605
606 switch (ret & SH_FSI_ACKMD_MASK) {
607 default:
608 /* FALL THROUGH */
609 case SH_FSI_ACKMD_512:
610 data |= (0x0 << 12);
611 break;
612 case SH_FSI_ACKMD_256:
613 data |= (0x1 << 12);
614 break;
615 case SH_FSI_ACKMD_128:
616 data |= (0x2 << 12);
617 break;
618 case SH_FSI_ACKMD_64:
619 data |= (0x3 << 12);
620 break;
621 case SH_FSI_ACKMD_32:
622 if (fsi_ver < 2)
623 dev_err(dev, "unsupported ACKMD\n");
624 else
625 data |= (0x4 << 12);
626 break;
627 }
628
629 switch (ret & SH_FSI_BPFMD_MASK) {
630 default:
631 /* FALL THROUGH */
632 case SH_FSI_BPFMD_32:
633 data |= (0x0 << 8);
634 break;
635 case SH_FSI_BPFMD_64:
636 data |= (0x1 << 8);
637 break;
638 case SH_FSI_BPFMD_128:
639 data |= (0x2 << 8);
640 break;
641 case SH_FSI_BPFMD_256:
642 data |= (0x3 << 8);
643 break;
644 case SH_FSI_BPFMD_512:
645 data |= (0x4 << 8);
646 break;
647 case SH_FSI_BPFMD_16:
648 if (fsi_ver < 2)
649 dev_err(dev, "unsupported ACKMD\n");
650 else
651 data |= (0x7 << 8);
652 break;
653 }
654
655 fsi_reg_mask_set(fsi, CKG1, (ACKMD_MASK | BPFMD_MASK) , data);
656 udelay(10);
657 ret = 0;
658 }
659
660 return ret;
661
662 }
663
664 #define fsi_module_init(m, d) __fsi_module_clk_ctrl(m, d, 1)
665 #define fsi_module_kill(m, d) __fsi_module_clk_ctrl(m, d, 0)
666 static void __fsi_module_clk_ctrl(struct fsi_master *master,
667 struct device *dev,
668 int enable)
669 {
670 pm_runtime_get_sync(dev);
671
672 if (enable) {
673 /* enable only SR */
674 fsi_master_mask_set(master, SOFT_RST, FSISR, FSISR);
675 fsi_master_mask_set(master, SOFT_RST, PASR | PBSR, 0);
676 } else {
677 /* clear all registers */
678 fsi_master_mask_set(master, SOFT_RST, FSISR, 0);
679 }
680
681 pm_runtime_put_sync(dev);
682 }
683
684 #define fsi_port_start(f, i) __fsi_port_clk_ctrl(f, i, 1)
685 #define fsi_port_stop(f, i) __fsi_port_clk_ctrl(f, i, 0)
686 static void __fsi_port_clk_ctrl(struct fsi_priv *fsi, int is_play, int enable)
687 {
688 struct fsi_master *master = fsi_get_master(fsi);
689 u32 soft = fsi_is_port_a(fsi) ? PASR : PBSR;
690 u32 clk = fsi_is_port_a(fsi) ? CRA : CRB;
691 int is_master = fsi_is_clk_master(fsi);
692
693 if (enable)
694 fsi_irq_enable(fsi, is_play);
695 else
696 fsi_irq_disable(fsi, is_play);
697
698 fsi_master_mask_set(master, SOFT_RST, soft, (enable) ? soft : 0);
699 if (is_master)
700 fsi_master_mask_set(master, CLK_RST, clk, (enable) ? clk : 0);
701 }
702
703 /*
704 * ctrl function
705 */
706 static void fsi_fifo_init(struct fsi_priv *fsi,
707 int is_play,
708 struct snd_soc_dai *dai)
709 {
710 struct fsi_master *master = fsi_get_master(fsi);
711 struct fsi_stream *io = fsi_get_stream(fsi, is_play);
712 u32 shift, i;
713 int frame_capa;
714
715 /* get on-chip RAM capacity */
716 shift = fsi_master_read(master, FIFO_SZ);
717 shift >>= fsi_get_port_shift(fsi, is_play);
718 shift &= FIFO_SZ_MASK;
719 frame_capa = 256 << shift;
720 dev_dbg(dai->dev, "fifo = %d words\n", frame_capa);
721
722 /*
723 * The maximum number of sample data varies depending
724 * on the number of channels selected for the format.
725 *
726 * FIFOs are used in 4-channel units in 3-channel mode
727 * and in 8-channel units in 5- to 7-channel mode
728 * meaning that more FIFOs than the required size of DPRAM
729 * are used.
730 *
731 * ex) if 256 words of DP-RAM is connected
732 * 1 channel: 256 (256 x 1 = 256)
733 * 2 channels: 128 (128 x 2 = 256)
734 * 3 channels: 64 ( 64 x 3 = 192)
735 * 4 channels: 64 ( 64 x 4 = 256)
736 * 5 channels: 32 ( 32 x 5 = 160)
737 * 6 channels: 32 ( 32 x 6 = 192)
738 * 7 channels: 32 ( 32 x 7 = 224)
739 * 8 channels: 32 ( 32 x 8 = 256)
740 */
741 for (i = 1; i < fsi->chan_num; i <<= 1)
742 frame_capa >>= 1;
743 dev_dbg(dai->dev, "%d channel %d store\n",
744 fsi->chan_num, frame_capa);
745
746 io->fifo_sample_capa = fsi_frame2sample(fsi, frame_capa);
747
748 /*
749 * set interrupt generation factor
750 * clear FIFO
751 */
752 if (is_play) {
753 fsi_reg_write(fsi, DOFF_CTL, IRQ_HALF);
754 fsi_reg_mask_set(fsi, DOFF_CTL, FIFO_CLR, FIFO_CLR);
755 } else {
756 fsi_reg_write(fsi, DIFF_CTL, IRQ_HALF);
757 fsi_reg_mask_set(fsi, DIFF_CTL, FIFO_CLR, FIFO_CLR);
758 }
759 }
760
761 static int fsi_fifo_data_ctrl(struct fsi_priv *fsi, int stream)
762 {
763 struct snd_pcm_runtime *runtime;
764 struct snd_pcm_substream *substream = NULL;
765 int is_play = fsi_stream_is_play(stream);
766 struct fsi_stream *io = fsi_get_stream(fsi, is_play);
767 int sample_residues;
768 int sample_width;
769 int samples;
770 int samples_max;
771 int over_period;
772 void (*fn)(struct fsi_priv *fsi, int size);
773
774 if (!fsi ||
775 !io->substream ||
776 !io->substream->runtime)
777 return -EINVAL;
778
779 over_period = 0;
780 substream = io->substream;
781 runtime = substream->runtime;
782
783 /* FSI FIFO has limit.
784 * So, this driver can not send periods data at a time
785 */
786 if (io->buff_sample_pos >=
787 io->period_samples * (io->period_pos + 1)) {
788
789 over_period = 1;
790 io->period_pos = (io->period_pos + 1) % runtime->periods;
791
792 if (0 == io->period_pos)
793 io->buff_sample_pos = 0;
794 }
795
796 /* get 1 sample data width */
797 sample_width = samples_to_bytes(runtime, 1);
798
799 /* get number of residue samples */
800 sample_residues = io->buff_sample_capa - io->buff_sample_pos;
801
802 if (is_play) {
803 /*
804 * for play-back
805 *
806 * samples_max : number of FSI fifo free samples space
807 * samples : number of ALSA residue samples
808 */
809 samples_max = io->fifo_sample_capa;
810 samples_max -= fsi_get_current_fifo_samples(fsi, is_play);
811
812 samples = sample_residues;
813
814 switch (sample_width) {
815 case 2:
816 fn = fsi_dma_soft_push16;
817 break;
818 case 4:
819 fn = fsi_dma_soft_push32;
820 break;
821 default:
822 return -EINVAL;
823 }
824 } else {
825 /*
826 * for capture
827 *
828 * samples_max : number of ALSA free samples space
829 * samples : number of samples in FSI fifo
830 */
831 samples_max = sample_residues;
832 samples = fsi_get_current_fifo_samples(fsi, is_play);
833
834 switch (sample_width) {
835 case 2:
836 fn = fsi_dma_soft_pop16;
837 break;
838 case 4:
839 fn = fsi_dma_soft_pop32;
840 break;
841 default:
842 return -EINVAL;
843 }
844 }
845
846 samples = min(samples, samples_max);
847
848 fn(fsi, samples);
849
850 /* update buff_sample_pos */
851 io->buff_sample_pos += samples;
852
853 if (over_period)
854 snd_pcm_period_elapsed(substream);
855
856 return 0;
857 }
858
859 static int fsi_data_pop(struct fsi_priv *fsi)
860 {
861 return fsi_fifo_data_ctrl(fsi, SNDRV_PCM_STREAM_CAPTURE);
862 }
863
864 static int fsi_data_push(struct fsi_priv *fsi)
865 {
866 return fsi_fifo_data_ctrl(fsi, SNDRV_PCM_STREAM_PLAYBACK);
867 }
868
869 static irqreturn_t fsi_interrupt(int irq, void *data)
870 {
871 struct fsi_master *master = data;
872 u32 int_st = fsi_irq_get_status(master);
873
874 /* clear irq status */
875 fsi_master_mask_set(master, SOFT_RST, IR, 0);
876 fsi_master_mask_set(master, SOFT_RST, IR, IR);
877
878 if (int_st & AB_IO(1, AO_SHIFT))
879 fsi_data_push(&master->fsia);
880 if (int_st & AB_IO(1, BO_SHIFT))
881 fsi_data_push(&master->fsib);
882 if (int_st & AB_IO(1, AI_SHIFT))
883 fsi_data_pop(&master->fsia);
884 if (int_st & AB_IO(1, BI_SHIFT))
885 fsi_data_pop(&master->fsib);
886
887 fsi_count_fifo_err(&master->fsia);
888 fsi_count_fifo_err(&master->fsib);
889
890 fsi_irq_clear_status(&master->fsia);
891 fsi_irq_clear_status(&master->fsib);
892
893 return IRQ_HANDLED;
894 }
895
896 /*
897 * dai ops
898 */
899
900 static int fsi_dai_startup(struct snd_pcm_substream *substream,
901 struct snd_soc_dai *dai)
902 {
903 struct fsi_priv *fsi = fsi_get_priv(substream);
904 u32 flags = fsi_get_info_flags(fsi);
905 u32 data = 0;
906 int is_play = fsi_is_play(substream);
907
908 pm_runtime_get_sync(dai->dev);
909
910 /* clock setting */
911 if (fsi_is_clk_master(fsi))
912 data = DIMD | DOMD;
913
914 fsi_reg_mask_set(fsi, CKG1, (DIMD | DOMD), data);
915
916 /* clock inversion (CKG2) */
917 data = 0;
918 if (SH_FSI_LRM_INV & flags)
919 data |= 1 << 12;
920 if (SH_FSI_BRM_INV & flags)
921 data |= 1 << 8;
922 if (SH_FSI_LRS_INV & flags)
923 data |= 1 << 4;
924 if (SH_FSI_BRS_INV & flags)
925 data |= 1 << 0;
926
927 fsi_reg_write(fsi, CKG2, data);
928
929 /* set format */
930 fsi_reg_write(fsi, DO_FMT, fsi->do_fmt);
931 fsi_reg_write(fsi, DI_FMT, fsi->di_fmt);
932
933 /* spdif ? */
934 if (fsi_is_spdif(fsi)) {
935 fsi_spdif_clk_ctrl(fsi, 1);
936 fsi_reg_mask_set(fsi, OUT_SEL, DMMD, DMMD);
937 }
938
939 /* irq clear */
940 fsi_irq_disable(fsi, is_play);
941 fsi_irq_clear_status(fsi);
942
943 /* fifo init */
944 fsi_fifo_init(fsi, is_play, dai);
945
946 return 0;
947 }
948
949 static void fsi_dai_shutdown(struct snd_pcm_substream *substream,
950 struct snd_soc_dai *dai)
951 {
952 struct fsi_priv *fsi = fsi_get_priv(substream);
953
954 if (fsi_is_clk_master(fsi))
955 fsi_set_master_clk(dai->dev, fsi, fsi->rate, 0);
956
957 fsi->rate = 0;
958
959 pm_runtime_put_sync(dai->dev);
960 }
961
962 static int fsi_dai_trigger(struct snd_pcm_substream *substream, int cmd,
963 struct snd_soc_dai *dai)
964 {
965 struct fsi_priv *fsi = fsi_get_priv(substream);
966 int is_play = fsi_is_play(substream);
967 int ret = 0;
968
969 switch (cmd) {
970 case SNDRV_PCM_TRIGGER_START:
971 fsi_stream_push(fsi, is_play, substream);
972 ret = is_play ? fsi_data_push(fsi) : fsi_data_pop(fsi);
973 fsi_port_start(fsi, is_play);
974 break;
975 case SNDRV_PCM_TRIGGER_STOP:
976 fsi_port_stop(fsi, is_play);
977 fsi_stream_pop(fsi, is_play);
978 break;
979 }
980
981 return ret;
982 }
983
984 static int fsi_set_fmt_dai(struct fsi_priv *fsi, unsigned int fmt)
985 {
986 u32 data = 0;
987
988 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
989 case SND_SOC_DAIFMT_I2S:
990 data = CR_I2S;
991 fsi->chan_num = 2;
992 break;
993 case SND_SOC_DAIFMT_LEFT_J:
994 data = CR_PCM;
995 fsi->chan_num = 2;
996 break;
997 default:
998 return -EINVAL;
999 }
1000
1001 fsi->do_fmt = data;
1002 fsi->di_fmt = data;
1003
1004 return 0;
1005 }
1006
1007 static int fsi_set_fmt_spdif(struct fsi_priv *fsi)
1008 {
1009 struct fsi_master *master = fsi_get_master(fsi);
1010 u32 data = 0;
1011
1012 if (master->core->ver < 2)
1013 return -EINVAL;
1014
1015 data = CR_BWS_16 | CR_DTMD_SPDIF_PCM | CR_PCM;
1016 fsi->chan_num = 2;
1017 fsi->spdif = 1;
1018
1019 fsi->do_fmt = data;
1020 fsi->di_fmt = data;
1021
1022 return 0;
1023 }
1024
1025 static int fsi_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1026 {
1027 struct fsi_priv *fsi = fsi_get_priv_frm_dai(dai);
1028 struct fsi_master *master = fsi_get_master(fsi);
1029 set_rate_func set_rate = fsi_get_info_set_rate(master);
1030 u32 flags = fsi_get_info_flags(fsi);
1031 int ret;
1032
1033 /* set master/slave audio interface */
1034 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1035 case SND_SOC_DAIFMT_CBM_CFM:
1036 fsi->clk_master = 1;
1037 break;
1038 case SND_SOC_DAIFMT_CBS_CFS:
1039 break;
1040 default:
1041 return -EINVAL;
1042 }
1043
1044 if (fsi_is_clk_master(fsi) && !set_rate) {
1045 dev_err(dai->dev, "platform doesn't have set_rate\n");
1046 return -EINVAL;
1047 }
1048
1049 /* set format */
1050 switch (flags & SH_FSI_FMT_MASK) {
1051 case SH_FSI_FMT_DAI:
1052 ret = fsi_set_fmt_dai(fsi, fmt & SND_SOC_DAIFMT_FORMAT_MASK);
1053 break;
1054 case SH_FSI_FMT_SPDIF:
1055 ret = fsi_set_fmt_spdif(fsi);
1056 break;
1057 default:
1058 ret = -EINVAL;
1059 }
1060
1061 return ret;
1062 }
1063
1064 static int fsi_dai_hw_params(struct snd_pcm_substream *substream,
1065 struct snd_pcm_hw_params *params,
1066 struct snd_soc_dai *dai)
1067 {
1068 struct fsi_priv *fsi = fsi_get_priv(substream);
1069 long rate = params_rate(params);
1070 int ret;
1071
1072 if (!fsi_is_clk_master(fsi))
1073 return 0;
1074
1075 ret = fsi_set_master_clk(dai->dev, fsi, rate, 1);
1076 if (ret < 0)
1077 return ret;
1078
1079 fsi->rate = rate;
1080
1081 return ret;
1082 }
1083
1084 static struct snd_soc_dai_ops fsi_dai_ops = {
1085 .startup = fsi_dai_startup,
1086 .shutdown = fsi_dai_shutdown,
1087 .trigger = fsi_dai_trigger,
1088 .set_fmt = fsi_dai_set_fmt,
1089 .hw_params = fsi_dai_hw_params,
1090 };
1091
1092 /*
1093 * pcm ops
1094 */
1095
1096 static struct snd_pcm_hardware fsi_pcm_hardware = {
1097 .info = SNDRV_PCM_INFO_INTERLEAVED |
1098 SNDRV_PCM_INFO_MMAP |
1099 SNDRV_PCM_INFO_MMAP_VALID |
1100 SNDRV_PCM_INFO_PAUSE,
1101 .formats = FSI_FMTS,
1102 .rates = FSI_RATES,
1103 .rate_min = 8000,
1104 .rate_max = 192000,
1105 .channels_min = 1,
1106 .channels_max = 2,
1107 .buffer_bytes_max = 64 * 1024,
1108 .period_bytes_min = 32,
1109 .period_bytes_max = 8192,
1110 .periods_min = 1,
1111 .periods_max = 32,
1112 .fifo_size = 256,
1113 };
1114
1115 static int fsi_pcm_open(struct snd_pcm_substream *substream)
1116 {
1117 struct snd_pcm_runtime *runtime = substream->runtime;
1118 int ret = 0;
1119
1120 snd_soc_set_runtime_hwparams(substream, &fsi_pcm_hardware);
1121
1122 ret = snd_pcm_hw_constraint_integer(runtime,
1123 SNDRV_PCM_HW_PARAM_PERIODS);
1124
1125 return ret;
1126 }
1127
1128 static int fsi_hw_params(struct snd_pcm_substream *substream,
1129 struct snd_pcm_hw_params *hw_params)
1130 {
1131 return snd_pcm_lib_malloc_pages(substream,
1132 params_buffer_bytes(hw_params));
1133 }
1134
1135 static int fsi_hw_free(struct snd_pcm_substream *substream)
1136 {
1137 return snd_pcm_lib_free_pages(substream);
1138 }
1139
1140 static snd_pcm_uframes_t fsi_pointer(struct snd_pcm_substream *substream)
1141 {
1142 struct fsi_priv *fsi = fsi_get_priv(substream);
1143 struct fsi_stream *io = fsi_get_stream(fsi, fsi_is_play(substream));
1144 int samples_pos = io->buff_sample_pos - 1;
1145
1146 if (samples_pos < 0)
1147 samples_pos = 0;
1148
1149 return fsi_sample2frame(fsi, samples_pos);
1150 }
1151
1152 static struct snd_pcm_ops fsi_pcm_ops = {
1153 .open = fsi_pcm_open,
1154 .ioctl = snd_pcm_lib_ioctl,
1155 .hw_params = fsi_hw_params,
1156 .hw_free = fsi_hw_free,
1157 .pointer = fsi_pointer,
1158 };
1159
1160 /*
1161 * snd_soc_platform
1162 */
1163
1164 #define PREALLOC_BUFFER (32 * 1024)
1165 #define PREALLOC_BUFFER_MAX (32 * 1024)
1166
1167 static void fsi_pcm_free(struct snd_pcm *pcm)
1168 {
1169 snd_pcm_lib_preallocate_free_for_all(pcm);
1170 }
1171
1172 static int fsi_pcm_new(struct snd_card *card,
1173 struct snd_soc_dai *dai,
1174 struct snd_pcm *pcm)
1175 {
1176 /*
1177 * dont use SNDRV_DMA_TYPE_DEV, since it will oops the SH kernel
1178 * in MMAP mode (i.e. aplay -M)
1179 */
1180 return snd_pcm_lib_preallocate_pages_for_all(
1181 pcm,
1182 SNDRV_DMA_TYPE_CONTINUOUS,
1183 snd_dma_continuous_data(GFP_KERNEL),
1184 PREALLOC_BUFFER, PREALLOC_BUFFER_MAX);
1185 }
1186
1187 /*
1188 * alsa struct
1189 */
1190
1191 static struct snd_soc_dai_driver fsi_soc_dai[] = {
1192 {
1193 .name = "fsia-dai",
1194 .playback = {
1195 .rates = FSI_RATES,
1196 .formats = FSI_FMTS,
1197 .channels_min = 1,
1198 .channels_max = 8,
1199 },
1200 .capture = {
1201 .rates = FSI_RATES,
1202 .formats = FSI_FMTS,
1203 .channels_min = 1,
1204 .channels_max = 8,
1205 },
1206 .ops = &fsi_dai_ops,
1207 },
1208 {
1209 .name = "fsib-dai",
1210 .playback = {
1211 .rates = FSI_RATES,
1212 .formats = FSI_FMTS,
1213 .channels_min = 1,
1214 .channels_max = 8,
1215 },
1216 .capture = {
1217 .rates = FSI_RATES,
1218 .formats = FSI_FMTS,
1219 .channels_min = 1,
1220 .channels_max = 8,
1221 },
1222 .ops = &fsi_dai_ops,
1223 },
1224 };
1225
1226 static struct snd_soc_platform_driver fsi_soc_platform = {
1227 .ops = &fsi_pcm_ops,
1228 .pcm_new = fsi_pcm_new,
1229 .pcm_free = fsi_pcm_free,
1230 };
1231
1232 /*
1233 * platform function
1234 */
1235
1236 static int fsi_probe(struct platform_device *pdev)
1237 {
1238 struct fsi_master *master;
1239 const struct platform_device_id *id_entry;
1240 struct resource *res;
1241 unsigned int irq;
1242 int ret;
1243
1244 id_entry = pdev->id_entry;
1245 if (!id_entry) {
1246 dev_err(&pdev->dev, "unknown fsi device\n");
1247 return -ENODEV;
1248 }
1249
1250 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1251 irq = platform_get_irq(pdev, 0);
1252 if (!res || (int)irq <= 0) {
1253 dev_err(&pdev->dev, "Not enough FSI platform resources.\n");
1254 ret = -ENODEV;
1255 goto exit;
1256 }
1257
1258 master = kzalloc(sizeof(*master), GFP_KERNEL);
1259 if (!master) {
1260 dev_err(&pdev->dev, "Could not allocate master\n");
1261 ret = -ENOMEM;
1262 goto exit;
1263 }
1264
1265 master->base = ioremap_nocache(res->start, resource_size(res));
1266 if (!master->base) {
1267 ret = -ENXIO;
1268 dev_err(&pdev->dev, "Unable to ioremap FSI registers.\n");
1269 goto exit_kfree;
1270 }
1271
1272 /* master setting */
1273 master->irq = irq;
1274 master->info = pdev->dev.platform_data;
1275 master->core = (struct fsi_core *)id_entry->driver_data;
1276 spin_lock_init(&master->lock);
1277
1278 /* FSI A setting */
1279 master->fsia.base = master->base;
1280 master->fsia.master = master;
1281
1282 /* FSI B setting */
1283 master->fsib.base = master->base + 0x40;
1284 master->fsib.master = master;
1285
1286 pm_runtime_enable(&pdev->dev);
1287 dev_set_drvdata(&pdev->dev, master);
1288
1289 fsi_module_init(master, &pdev->dev);
1290
1291 ret = request_irq(irq, &fsi_interrupt, IRQF_DISABLED,
1292 id_entry->name, master);
1293 if (ret) {
1294 dev_err(&pdev->dev, "irq request err\n");
1295 goto exit_iounmap;
1296 }
1297
1298 ret = snd_soc_register_platform(&pdev->dev, &fsi_soc_platform);
1299 if (ret < 0) {
1300 dev_err(&pdev->dev, "cannot snd soc register\n");
1301 goto exit_free_irq;
1302 }
1303
1304 ret = snd_soc_register_dais(&pdev->dev, fsi_soc_dai,
1305 ARRAY_SIZE(fsi_soc_dai));
1306 if (ret < 0) {
1307 dev_err(&pdev->dev, "cannot snd dai register\n");
1308 goto exit_snd_soc;
1309 }
1310
1311 return ret;
1312
1313 exit_snd_soc:
1314 snd_soc_unregister_platform(&pdev->dev);
1315 exit_free_irq:
1316 free_irq(irq, master);
1317 exit_iounmap:
1318 iounmap(master->base);
1319 pm_runtime_disable(&pdev->dev);
1320 exit_kfree:
1321 kfree(master);
1322 master = NULL;
1323 exit:
1324 return ret;
1325 }
1326
1327 static int fsi_remove(struct platform_device *pdev)
1328 {
1329 struct fsi_master *master;
1330
1331 master = dev_get_drvdata(&pdev->dev);
1332
1333 fsi_module_kill(master, &pdev->dev);
1334
1335 free_irq(master->irq, master);
1336 pm_runtime_disable(&pdev->dev);
1337
1338 snd_soc_unregister_dais(&pdev->dev, ARRAY_SIZE(fsi_soc_dai));
1339 snd_soc_unregister_platform(&pdev->dev);
1340
1341 iounmap(master->base);
1342 kfree(master);
1343
1344 return 0;
1345 }
1346
1347 static void __fsi_suspend(struct fsi_priv *fsi,
1348 struct device *dev)
1349 {
1350 fsi->saved_do_fmt = fsi_reg_read(fsi, DO_FMT);
1351 fsi->saved_di_fmt = fsi_reg_read(fsi, DI_FMT);
1352 fsi->saved_ckg1 = fsi_reg_read(fsi, CKG1);
1353 fsi->saved_ckg2 = fsi_reg_read(fsi, CKG2);
1354 fsi->saved_out_sel = fsi_reg_read(fsi, OUT_SEL);
1355
1356 if (fsi_is_clk_master(fsi))
1357 fsi_set_master_clk(dev, fsi, fsi->rate, 0);
1358 }
1359
1360 static void __fsi_resume(struct fsi_priv *fsi,
1361 struct device *dev)
1362 {
1363 fsi_reg_write(fsi, DO_FMT, fsi->saved_do_fmt);
1364 fsi_reg_write(fsi, DI_FMT, fsi->saved_di_fmt);
1365 fsi_reg_write(fsi, CKG1, fsi->saved_ckg1);
1366 fsi_reg_write(fsi, CKG2, fsi->saved_ckg2);
1367 fsi_reg_write(fsi, OUT_SEL, fsi->saved_out_sel);
1368
1369 if (fsi_is_clk_master(fsi))
1370 fsi_set_master_clk(dev, fsi, fsi->rate, 1);
1371 }
1372
1373 static int fsi_suspend(struct device *dev)
1374 {
1375 struct fsi_master *master = dev_get_drvdata(dev);
1376
1377 pm_runtime_get_sync(dev);
1378
1379 __fsi_suspend(&master->fsia, dev);
1380 __fsi_suspend(&master->fsib, dev);
1381
1382 master->saved_a_mclk = fsi_core_read(master, a_mclk);
1383 master->saved_b_mclk = fsi_core_read(master, b_mclk);
1384 master->saved_iemsk = fsi_core_read(master, iemsk);
1385 master->saved_imsk = fsi_core_read(master, imsk);
1386 master->saved_clk_rst = fsi_master_read(master, CLK_RST);
1387 master->saved_soft_rst = fsi_master_read(master, SOFT_RST);
1388
1389 fsi_module_kill(master, dev);
1390
1391 pm_runtime_put_sync(dev);
1392
1393 return 0;
1394 }
1395
1396 static int fsi_resume(struct device *dev)
1397 {
1398 struct fsi_master *master = dev_get_drvdata(dev);
1399
1400 pm_runtime_get_sync(dev);
1401
1402 fsi_module_init(master, dev);
1403
1404 fsi_master_mask_set(master, SOFT_RST, 0xffff, master->saved_soft_rst);
1405 fsi_master_mask_set(master, CLK_RST, 0xffff, master->saved_clk_rst);
1406 fsi_core_mask_set(master, a_mclk, 0xffff, master->saved_a_mclk);
1407 fsi_core_mask_set(master, b_mclk, 0xffff, master->saved_b_mclk);
1408 fsi_core_mask_set(master, iemsk, 0xffff, master->saved_iemsk);
1409 fsi_core_mask_set(master, imsk, 0xffff, master->saved_imsk);
1410
1411 __fsi_resume(&master->fsia, dev);
1412 __fsi_resume(&master->fsib, dev);
1413
1414 pm_runtime_put_sync(dev);
1415
1416 return 0;
1417 }
1418
1419 static int fsi_runtime_nop(struct device *dev)
1420 {
1421 /* Runtime PM callback shared between ->runtime_suspend()
1422 * and ->runtime_resume(). Simply returns success.
1423 *
1424 * This driver re-initializes all registers after
1425 * pm_runtime_get_sync() anyway so there is no need
1426 * to save and restore registers here.
1427 */
1428 return 0;
1429 }
1430
1431 static struct dev_pm_ops fsi_pm_ops = {
1432 .suspend = fsi_suspend,
1433 .resume = fsi_resume,
1434 .runtime_suspend = fsi_runtime_nop,
1435 .runtime_resume = fsi_runtime_nop,
1436 };
1437
1438 static struct fsi_core fsi1_core = {
1439 .ver = 1,
1440
1441 /* Interrupt */
1442 .int_st = INT_ST,
1443 .iemsk = IEMSK,
1444 .imsk = IMSK,
1445 };
1446
1447 static struct fsi_core fsi2_core = {
1448 .ver = 2,
1449
1450 /* Interrupt */
1451 .int_st = CPU_INT_ST,
1452 .iemsk = CPU_IEMSK,
1453 .imsk = CPU_IMSK,
1454 .a_mclk = A_MST_CTLR,
1455 .b_mclk = B_MST_CTLR,
1456 };
1457
1458 static struct platform_device_id fsi_id_table[] = {
1459 { "sh_fsi", (kernel_ulong_t)&fsi1_core },
1460 { "sh_fsi2", (kernel_ulong_t)&fsi2_core },
1461 {},
1462 };
1463 MODULE_DEVICE_TABLE(platform, fsi_id_table);
1464
1465 static struct platform_driver fsi_driver = {
1466 .driver = {
1467 .name = "fsi-pcm-audio",
1468 .pm = &fsi_pm_ops,
1469 },
1470 .probe = fsi_probe,
1471 .remove = fsi_remove,
1472 .id_table = fsi_id_table,
1473 };
1474
1475 static int __init fsi_mobile_init(void)
1476 {
1477 return platform_driver_register(&fsi_driver);
1478 }
1479
1480 static void __exit fsi_mobile_exit(void)
1481 {
1482 platform_driver_unregister(&fsi_driver);
1483 }
1484
1485 module_init(fsi_mobile_init);
1486 module_exit(fsi_mobile_exit);
1487
1488 MODULE_LICENSE("GPL");
1489 MODULE_DESCRIPTION("SuperH onchip FSI audio driver");
1490 MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>");
1491 MODULE_ALIAS("platform:fsi-pcm-audio");