arch/arm/mach-at91/include/mach/at91sam9261_matrix.h

   1 /*
   2  * arch/arm/mach-at91/include/mach/at91sam9261_matrix.h
   3  *
   4  *  Copyright (C) 2007 Atmel Corporation.
   5  *
   6  * Memory Controllers (MATRIX, EBI) - System peripherals registers.
   7  * Based on AT91SAM9261 datasheet revision D.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  */
  14
  15 #ifndef AT91SAM9261_MATRIX_H
  16 #define AT91SAM9261_MATRIX_H
  17
  18 #define AT91_MATRIX_MCFG        (AT91_MATRIX + 0x00)    /* Master Configuration Register */
  19 #define         AT91_MATRIX_RCB0        (1 << 0)                /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
  20 #define         AT91_MATRIX_RCB1        (1 << 1)                /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
  21
  22 #define AT91_MATRIX_SCFG0       (AT91_MATRIX + 0x04)    /* Slave Configuration Register 0 */
  23 #define AT91_MATRIX_SCFG1       (AT91_MATRIX + 0x08)    /* Slave Configuration Register 1 */
  24 #define AT91_MATRIX_SCFG2       (AT91_MATRIX + 0x0C)    /* Slave Configuration Register 2 */
  25 #define AT91_MATRIX_SCFG3       (AT91_MATRIX + 0x10)    /* Slave Configuration Register 3 */
  26 #define AT91_MATRIX_SCFG4       (AT91_MATRIX + 0x14)    /* Slave Configuration Register 4 */
  27 #define         AT91_MATRIX_SLOT_CYCLE          (0xff << 0)     /* Maximum Number of Allowed Cycles for a Burst */
  28 #define         AT91_MATRIX_DEFMSTR_TYPE        (3    << 16)    /* Default Master Type */
  29 #define                 AT91_MATRIX_DEFMSTR_TYPE_NONE   (0 << 16)
  30 #define                 AT91_MATRIX_DEFMSTR_TYPE_LAST   (1 << 16)
  31 #define                 AT91_MATRIX_DEFMSTR_TYPE_FIXED  (2 << 16)
  32 #define         AT91_MATRIX_FIXED_DEFMSTR       (7    << 18)    /* Fixed Index of Default Master */
  33
  34 #define AT91_MATRIX_TCR         (AT91_MATRIX + 0x24)    /* TCM Configuration Register */
  35 #define         AT91_MATRIX_ITCM_SIZE           (0xf << 0)      /* Size of ITCM enabled memory block */
  36 #define                 AT91_MATRIX_ITCM_0              (0 << 0)
  37 #define                 AT91_MATRIX_ITCM_16             (5 << 0)
  38 #define                 AT91_MATRIX_ITCM_32             (6 << 0)
  39 #define                 AT91_MATRIX_ITCM_64             (7 << 0)
  40 #define         AT91_MATRIX_DTCM_SIZE           (0xf << 4)      /* Size of DTCM enabled memory block */
  41 #define                 AT91_MATRIX_DTCM_0              (0 << 4)
  42 #define                 AT91_MATRIX_DTCM_16             (5 << 4)
  43 #define                 AT91_MATRIX_DTCM_32             (6 << 4)
  44 #define                 AT91_MATRIX_DTCM_64             (7 << 4)
  45
  46 #define AT91_MATRIX_EBICSA      (AT91_MATRIX + 0x30)    /* EBI Chip Select Assignment Register */
  47 #define         AT91_MATRIX_CS1A                (1 << 1)        /* Chip Select 1 Assignment */
  48 #define                 AT91_MATRIX_CS1A_SMC            (0 << 1)
  49 #define                 AT91_MATRIX_CS1A_SDRAMC         (1 << 1)
  50 #define         AT91_MATRIX_CS3A                (1 << 3)        /* Chip Select 3 Assignment */
  51 #define                 AT91_MATRIX_CS3A_SMC            (0 << 3)
  52 #define                 AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
  53 #define         AT91_MATRIX_CS4A                (1 << 4)        /* Chip Select 4 Assignment */
  54 #define                 AT91_MATRIX_CS4A_SMC            (0 << 4)
  55 #define                 AT91_MATRIX_CS4A_SMC_CF1        (1 << 4)
  56 #define         AT91_MATRIX_CS5A                (1 << 5)        /* Chip Select 5 Assignment */
  57 #define                 AT91_MATRIX_CS5A_SMC            (0 << 5)
  58 #define                 AT91_MATRIX_CS5A_SMC_CF2        (1 << 5)
  59 #define         AT91_MATRIX_DBPUC               (1 << 8)        /* Data Bus Pull-up Configuration */
  60
  61 #define AT91_MATRIX_USBPUCR     (AT91_MATRIX + 0x34)    /* USB Pad Pull-Up Control Register */
  62 #define         AT91_MATRIX_USBPUCR_PUON        (1 << 30)       /* USB Device PAD Pull-up Enable */
  63
  64 #endif