arch/arm/mach-at91/include/mach/at_hdmac.h

   1 /*
   2  * Header file for the Atmel AHB DMA Controller driver
   3  *
   4  * Copyright (C) 2008 Atmel Corporation
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  */
  11 #ifndef AT_HDMAC_H
  12 #define AT_HDMAC_H
  13
  14 #include <linux/dmaengine.h>
  15
  16 /**
  17  * struct at_dma_platform_data - Controller configuration parameters
  18  * @nr_channels: Number of channels supported by hardware (max 8)
  19  * @cap_mask: dma_capability flags supported by the platform
  20  */
  21 struct at_dma_platform_data {
  22         unsigned int    nr_channels;
  23         dma_cap_mask_t  cap_mask;
  24 };
  25
  26 /**
  27  * enum at_dma_slave_width - DMA slave register access width.
  28  * @AT_DMA_SLAVE_WIDTH_8BIT: Do 8-bit slave register accesses
  29  * @AT_DMA_SLAVE_WIDTH_16BIT: Do 16-bit slave register accesses
  30  * @AT_DMA_SLAVE_WIDTH_32BIT: Do 32-bit slave register accesses
  31  */
  32 enum at_dma_slave_width {
  33         AT_DMA_SLAVE_WIDTH_8BIT = 0,
  34         AT_DMA_SLAVE_WIDTH_16BIT,
  35         AT_DMA_SLAVE_WIDTH_32BIT,
  36 };
  37
  38 /**
  39  * struct at_dma_slave - Controller-specific information about a slave
  40  * @dma_dev: required DMA master device
  41  * @tx_reg: physical address of data register used for
  42  *      memory-to-peripheral transfers
  43  * @rx_reg: physical address of data register used for
  44  *      peripheral-to-memory transfers
  45  * @reg_width: peripheral register width
  46  * @cfg: Platform-specific initializer for the CFG register
  47  * @ctrla: Platform-specific initializer for the CTRLA register
  48  */
  49 struct at_dma_slave {
  50         struct device           *dma_dev;
  51         dma_addr_t              tx_reg;
  52         dma_addr_t              rx_reg;
  53         enum at_dma_slave_width reg_width;
  54         u32                     cfg;
  55         u32                     ctrla;
  56 };
  57
  58
  59 /* Platform-configurable bits in CFG */
  60 #define ATC_SRC_PER(h)          (0xFU & (h))    /* Channel src rq associated with periph handshaking ifc h */
  61 #define ATC_DST_PER(h)          ((0xFU & (h)) <<  4)    /* Channel dst rq associated with periph handshaking ifc h */
  62 #define ATC_SRC_REP             (0x1 <<  8)     /* Source Replay Mod */
  63 #define ATC_SRC_H2SEL           (0x1 <<  9)     /* Source Handshaking Mod */
  64 #define         ATC_SRC_H2SEL_SW        (0x0 <<  9)
  65 #define         ATC_SRC_H2SEL_HW        (0x1 <<  9)
  66 #define ATC_DST_REP             (0x1 << 12)     /* Destination Replay Mod */
  67 #define ATC_DST_H2SEL           (0x1 << 13)     /* Destination Handshaking Mod */
  68 #define         ATC_DST_H2SEL_SW        (0x0 << 13)
  69 #define         ATC_DST_H2SEL_HW        (0x1 << 13)
  70 #define ATC_SOD                 (0x1 << 16)     /* Stop On Done */
  71 #define ATC_LOCK_IF             (0x1 << 20)     /* Interface Lock */
  72 #define ATC_LOCK_B              (0x1 << 21)     /* AHB Bus Lock */
  73 #define ATC_LOCK_IF_L           (0x1 << 22)     /* Master Interface Arbiter Lock */
  74 #define         ATC_LOCK_IF_L_CHUNK     (0x0 << 22)
  75 #define         ATC_LOCK_IF_L_BUFFER    (0x1 << 22)
  76 #define ATC_AHB_PROT_MASK       (0x7 << 24)     /* AHB Protection */
  77 #define ATC_FIFOCFG_MASK        (0x3 << 28)     /* FIFO Request Configuration */
  78 #define         ATC_FIFOCFG_LARGESTBURST        (0x0 << 28)
  79 #define         ATC_FIFOCFG_HALFFIFO            (0x1 << 28)
  80 #define         ATC_FIFOCFG_ENOUGHSPACE         (0x2 << 28)
  81
  82 /* Platform-configurable bits in CTRLA */
  83 #define ATC_SCSIZE_MASK         (0x7 << 16)     /* Source Chunk Transfer Size */
  84 #define         ATC_SCSIZE_1            (0x0 << 16)
  85 #define         ATC_SCSIZE_4            (0x1 << 16)
  86 #define         ATC_SCSIZE_8            (0x2 << 16)
  87 #define         ATC_SCSIZE_16           (0x3 << 16)
  88 #define         ATC_SCSIZE_32           (0x4 << 16)
  89 #define         ATC_SCSIZE_64           (0x5 << 16)
  90 #define         ATC_SCSIZE_128          (0x6 << 16)
  91 #define         ATC_SCSIZE_256          (0x7 << 16)
  92 #define ATC_DCSIZE_MASK         (0x7 << 20)     /* Destination Chunk Transfer Size */
  93 #define         ATC_DCSIZE_1            (0x0 << 20)
  94 #define         ATC_DCSIZE_4            (0x1 << 20)
  95 #define         ATC_DCSIZE_8            (0x2 << 20)
  96 #define         ATC_DCSIZE_16           (0x3 << 20)
  97 #define         ATC_DCSIZE_32           (0x4 << 20)
  98 #define         ATC_DCSIZE_64           (0x5 << 20)
  99 #define         ATC_DCSIZE_128          (0x6 << 20)
 100 #define         ATC_DCSIZE_256          (0x7 << 20)
 101
 102 #endif /* AT_HDMAC_H */