arch/arm/plat-omap/include/plat/dmtimer.h

   1 /*
   2  * arch/arm/plat-omap/include/mach/dmtimer.h
   3  *
   4  * OMAP Dual-Mode Timers
   5  *
   6  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
   7  * Tarun Kanti DebBarma <tarun.kanti@ti.com>
   8  * Thara Gopinath <thara@ti.com>
   9  *
  10  * Platform device conversion and hwmod support.
  11  *
  12  * Copyright (C) 2005 Nokia Corporation
  13  * Author: Lauri Leukkunen <lauri.leukkunen@nokia.com>
  14  * PWM and clock framwork support by Timo Teras.
  15  *
  16  * This program is free software; you can redistribute it and/or modify it
  17  * under the terms of the GNU General Public License as published by the
  18  * Free Software Foundation; either version 2 of the License, or (at your
  19  * option) any later version.
  20  *
  21  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  22  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  23  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  24  * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  25  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  26  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  27  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  28  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  29  *
  30  * You should have received a copy of the  GNU General Public License along
  31  * with this program; if not, write  to the Free Software Foundation, Inc.,
  32  * 675 Mass Ave, Cambridge, MA 02139, USA.
  33  */
  34
  35 #include <linux/clk.h>
  36 #include <linux/delay.h>
  37 #include <linux/io.h>
  38
  39 #ifndef __ASM_ARCH_DMTIMER_H
  40 #define __ASM_ARCH_DMTIMER_H
  41
  42 /* clock sources */
  43 #define OMAP_TIMER_SRC_SYS_CLK                  0x00
  44 #define OMAP_TIMER_SRC_32_KHZ                   0x01
  45 #define OMAP_TIMER_SRC_EXT_CLK                  0x02
  46
  47 /* timer interrupt enable bits */
  48 #define OMAP_TIMER_INT_CAPTURE                  (1 << 2)
  49 #define OMAP_TIMER_INT_OVERFLOW                 (1 << 1)
  50 #define OMAP_TIMER_INT_MATCH                    (1 << 0)
  51
  52 /* trigger types */
  53 #define OMAP_TIMER_TRIGGER_NONE                 0x00
  54 #define OMAP_TIMER_TRIGGER_OVERFLOW             0x01
  55 #define OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE 0x02
  56
  57 /*
  58  * IP revision identifier so that Highlander IP
  59  * in OMAP4 can be distinguished.
  60  */
  61 #define OMAP_TIMER_IP_VERSION_1                        0x1
  62 struct omap_dm_timer;
  63 struct clk;
  64
  65 struct omap_dm_timer *omap_dm_timer_request(void);
  66 struct omap_dm_timer *omap_dm_timer_request_specific(int timer_id);
  67 void omap_dm_timer_free(struct omap_dm_timer *timer);
  68 void omap_dm_timer_enable(struct omap_dm_timer *timer);
  69 void omap_dm_timer_disable(struct omap_dm_timer *timer);
  70
  71 int omap_dm_timer_get_irq(struct omap_dm_timer *timer);
  72
  73 u32 omap_dm_timer_modify_idlect_mask(u32 inputmask);
  74 struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer);
  75
  76 void omap_dm_timer_trigger(struct omap_dm_timer *timer);
  77 void omap_dm_timer_start(struct omap_dm_timer *timer);
  78 void omap_dm_timer_stop(struct omap_dm_timer *timer);
  79
  80 int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source);
  81 void omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload, unsigned int value);
  82 void omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload, unsigned int value);
  83 void omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable, unsigned int match);
  84 void omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on, int toggle, int trigger);
  85 void omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler);
  86
  87 void omap_dm_timer_set_int_enable(struct omap_dm_timer *timer, unsigned int value);
  88
  89 unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer);
  90 void omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value);
  91 unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer);
  92 void omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value);
  93
  94 int omap_dm_timers_active(void);
  95
  96 /*
  97  * Do not use the defines below, they are not needed. They should be only
  98  * used by dmtimer.c and sys_timer related code.
  99  */
 100
 101 /* register offsets */
 102 #define _OMAP_TIMER_ID_OFFSET           0x00
 103 #define _OMAP_TIMER_OCP_CFG_OFFSET      0x10
 104 #define _OMAP_TIMER_SYS_STAT_OFFSET     0x14
 105 #define _OMAP_TIMER_STAT_OFFSET         0x18
 106 #define _OMAP_TIMER_INT_EN_OFFSET       0x1c
 107 #define _OMAP_TIMER_WAKEUP_EN_OFFSET    0x20
 108 #define _OMAP_TIMER_CTRL_OFFSET         0x24
 109 #define         OMAP_TIMER_CTRL_GPOCFG          (1 << 14)
 110 #define         OMAP_TIMER_CTRL_CAPTMODE        (1 << 13)
 111 #define         OMAP_TIMER_CTRL_PT              (1 << 12)
 112 #define         OMAP_TIMER_CTRL_TCM_LOWTOHIGH   (0x1 << 8)
 113 #define         OMAP_TIMER_CTRL_TCM_HIGHTOLOW   (0x2 << 8)
 114 #define         OMAP_TIMER_CTRL_TCM_BOTHEDGES   (0x3 << 8)
 115 #define         OMAP_TIMER_CTRL_SCPWM           (1 << 7)
 116 #define         OMAP_TIMER_CTRL_CE              (1 << 6) /* compare enable */
 117 #define         OMAP_TIMER_CTRL_PRE             (1 << 5) /* prescaler enable */
 118 #define         OMAP_TIMER_CTRL_PTV_SHIFT       2 /* prescaler value shift */
 119 #define         OMAP_TIMER_CTRL_POSTED          (1 << 2)
 120 #define         OMAP_TIMER_CTRL_AR              (1 << 1) /* auto-reload enable */
 121 #define         OMAP_TIMER_CTRL_ST              (1 << 0) /* start timer */
 122 #define _OMAP_TIMER_COUNTER_OFFSET      0x28
 123 #define _OMAP_TIMER_LOAD_OFFSET         0x2c
 124 #define _OMAP_TIMER_TRIGGER_OFFSET      0x30
 125 #define _OMAP_TIMER_WRITE_PEND_OFFSET   0x34
 126 #define         WP_NONE                 0       /* no write pending bit */
 127 #define         WP_TCLR                 (1 << 0)
 128 #define         WP_TCRR                 (1 << 1)
 129 #define         WP_TLDR                 (1 << 2)
 130 #define         WP_TTGR                 (1 << 3)
 131 #define         WP_TMAR                 (1 << 4)
 132 #define         WP_TPIR                 (1 << 5)
 133 #define         WP_TNIR                 (1 << 6)
 134 #define         WP_TCVR                 (1 << 7)
 135 #define         WP_TOCR                 (1 << 8)
 136 #define         WP_TOWR                 (1 << 9)
 137 #define _OMAP_TIMER_MATCH_OFFSET        0x38
 138 #define _OMAP_TIMER_CAPTURE_OFFSET      0x3c
 139 #define _OMAP_TIMER_IF_CTRL_OFFSET      0x40
 140 #define _OMAP_TIMER_CAPTURE2_OFFSET             0x44    /* TCAR2, 34xx only */
 141 #define _OMAP_TIMER_TICK_POS_OFFSET             0x48    /* TPIR, 34xx only */
 142 #define _OMAP_TIMER_TICK_NEG_OFFSET             0x4c    /* TNIR, 34xx only */
 143 #define _OMAP_TIMER_TICK_COUNT_OFFSET           0x50    /* TCVR, 34xx only */
 144 #define _OMAP_TIMER_TICK_INT_MASK_SET_OFFSET    0x54    /* TOCR, 34xx only */
 145 #define _OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET  0x58    /* TOWR, 34xx only */
 146
 147 /* register offsets with the write pending bit encoded */
 148 #define WPSHIFT                                 16
 149
 150 #define OMAP_TIMER_ID_REG                       (_OMAP_TIMER_ID_OFFSET \
 151                                                         | (WP_NONE << WPSHIFT))
 152
 153 #define OMAP_TIMER_OCP_CFG_REG                  (_OMAP_TIMER_OCP_CFG_OFFSET \
 154                                                         | (WP_NONE << WPSHIFT))
 155
 156 #define OMAP_TIMER_SYS_STAT_REG                 (_OMAP_TIMER_SYS_STAT_OFFSET \
 157                                                         | (WP_NONE << WPSHIFT))
 158
 159 #define OMAP_TIMER_STAT_REG                     (_OMAP_TIMER_STAT_OFFSET \
 160                                                         | (WP_NONE << WPSHIFT))
 161
 162 #define OMAP_TIMER_INT_EN_REG                   (_OMAP_TIMER_INT_EN_OFFSET \
 163                                                         | (WP_NONE << WPSHIFT))
 164
 165 #define OMAP_TIMER_WAKEUP_EN_REG                (_OMAP_TIMER_WAKEUP_EN_OFFSET \
 166                                                         | (WP_NONE << WPSHIFT))
 167
 168 #define OMAP_TIMER_CTRL_REG                     (_OMAP_TIMER_CTRL_OFFSET \
 169                                                         | (WP_TCLR << WPSHIFT))
 170
 171 #define OMAP_TIMER_COUNTER_REG                  (_OMAP_TIMER_COUNTER_OFFSET \
 172                                                         | (WP_TCRR << WPSHIFT))
 173
 174 #define OMAP_TIMER_LOAD_REG                     (_OMAP_TIMER_LOAD_OFFSET \
 175                                                         | (WP_TLDR << WPSHIFT))
 176
 177 #define OMAP_TIMER_TRIGGER_REG                  (_OMAP_TIMER_TRIGGER_OFFSET \
 178                                                         | (WP_TTGR << WPSHIFT))
 179
 180 #define OMAP_TIMER_WRITE_PEND_REG               (_OMAP_TIMER_WRITE_PEND_OFFSET \
 181                                                         | (WP_NONE << WPSHIFT))
 182
 183 #define OMAP_TIMER_MATCH_REG                    (_OMAP_TIMER_MATCH_OFFSET \
 184                                                         | (WP_TMAR << WPSHIFT))
 185
 186 #define OMAP_TIMER_CAPTURE_REG                  (_OMAP_TIMER_CAPTURE_OFFSET \
 187                                                         | (WP_NONE << WPSHIFT))
 188
 189 #define OMAP_TIMER_IF_CTRL_REG                  (_OMAP_TIMER_IF_CTRL_OFFSET \
 190                                                         | (WP_NONE << WPSHIFT))
 191
 192 #define OMAP_TIMER_CAPTURE2_REG                 (_OMAP_TIMER_CAPTURE2_OFFSET \
 193                                                         | (WP_NONE << WPSHIFT))
 194
 195 #define OMAP_TIMER_TICK_POS_REG                 (_OMAP_TIMER_TICK_POS_OFFSET \
 196                                                         | (WP_TPIR << WPSHIFT))
 197
 198 #define OMAP_TIMER_TICK_NEG_REG                 (_OMAP_TIMER_TICK_NEG_OFFSET \
 199                                                         | (WP_TNIR << WPSHIFT))
 200
 201 #define OMAP_TIMER_TICK_COUNT_REG               (_OMAP_TIMER_TICK_COUNT_OFFSET \
 202                                                         | (WP_TCVR << WPSHIFT))
 203
 204 #define OMAP_TIMER_TICK_INT_MASK_SET_REG                                \
 205                 (_OMAP_TIMER_TICK_INT_MASK_SET_OFFSET | (WP_TOCR << WPSHIFT))
 206
 207 #define OMAP_TIMER_TICK_INT_MASK_COUNT_REG                              \
 208                 (_OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET | (WP_TOWR << WPSHIFT))
 209
 210 struct omap_dm_timer {
 211         unsigned long phys_base;
 212         int irq;
 213 #ifdef CONFIG_ARCH_OMAP2PLUS
 214         struct clk *iclk, *fclk;
 215 #endif
 216         void __iomem *io_base;
 217         unsigned long rate;
 218         unsigned reserved:1;
 219         unsigned enabled:1;
 220         unsigned posted:1;
 221 };
 222
 223 extern u32 sys_timer_reserved;
 224 void omap_dm_timer_prepare(struct omap_dm_timer *timer);
 225
 226 static inline u32 __omap_dm_timer_read(void __iomem *base, u32 reg,
 227                                                 int posted)
 228 {
 229         if (posted)
 230                 while (__raw_readl(base + (OMAP_TIMER_WRITE_PEND_REG & 0xff))
 231                                 & (reg >> WPSHIFT))
 232                         cpu_relax();
 233
 234         return __raw_readl(base + (reg & 0xff));
 235 }
 236
 237 static inline void __omap_dm_timer_write(void __iomem *base, u32 reg, u32 val,
 238                                                 int posted)
 239 {
 240         if (posted)
 241                 while (__raw_readl(base + (OMAP_TIMER_WRITE_PEND_REG & 0xff))
 242                                 & (reg >> WPSHIFT))
 243                         cpu_relax();
 244
 245         __raw_writel(val, base + (reg & 0xff));
 246 }
 247
 248 /* Assumes the source clock has been set by caller */
 249 static inline void __omap_dm_timer_reset(void __iomem *base, int autoidle,
 250                                                 int wakeup)
 251 {
 252         u32 l;
 253
 254         l = __omap_dm_timer_read(base, OMAP_TIMER_OCP_CFG_REG, 0);
 255         l |= 0x02 << 3;  /* Set to smart-idle mode */
 256         l |= 0x2 << 8;   /* Set clock activity to perserve f-clock on idle */
 257
 258         if (autoidle)
 259                 l |= 0x1 << 0;
 260
 261         if (wakeup)
 262                 l |= 1 << 2;
 263
 264         __omap_dm_timer_write(base, OMAP_TIMER_OCP_CFG_REG, l, 0);
 265
 266         /* Match hardware reset default of posted mode */
 267         __omap_dm_timer_write(base, OMAP_TIMER_IF_CTRL_REG,
 268                                         OMAP_TIMER_CTRL_POSTED, 0);
 269 }
 270
 271 static inline int __omap_dm_timer_set_source(struct clk *timer_fck,
 272                                                 struct clk *parent)
 273 {
 274         int ret;
 275
 276         clk_disable(timer_fck);
 277         ret = clk_set_parent(timer_fck, parent);
 278         clk_enable(timer_fck);
 279
 280         /*
 281          * When the functional clock disappears, too quick writes seem
 282          * to cause an abort. XXX Is this still necessary?
 283          */
 284         __delay(300000);
 285
 286         return ret;
 287 }
 288
 289 static inline void __omap_dm_timer_stop(void __iomem *base, int posted,
 290                                                 unsigned long rate)
 291 {
 292         u32 l;
 293
 294         l = __omap_dm_timer_read(base, OMAP_TIMER_CTRL_REG, posted);
 295         if (l & OMAP_TIMER_CTRL_ST) {
 296                 l &= ~0x1;
 297                 __omap_dm_timer_write(base, OMAP_TIMER_CTRL_REG, l, posted);
 298 #ifdef CONFIG_ARCH_OMAP2PLUS
 299                 /* Readback to make sure write has completed */
 300                 __omap_dm_timer_read(base, OMAP_TIMER_CTRL_REG, posted);
 301                 /*
 302                  * Wait for functional clock period x 3.5 to make sure that
 303                  * timer is stopped
 304                  */
 305                 udelay(3500000 / rate + 1);
 306 #endif
 307         }
 308
 309         /* Ack possibly pending interrupt */
 310         __omap_dm_timer_write(base, OMAP_TIMER_STAT_REG,
 311                                         OMAP_TIMER_INT_OVERFLOW, 0);
 312 }
 313
 314 static inline void __omap_dm_timer_load_start(void __iomem *base, u32 ctrl,
 315                                                 unsigned int load, int posted)
 316 {
 317         __omap_dm_timer_write(base, OMAP_TIMER_COUNTER_REG, load, posted);
 318         __omap_dm_timer_write(base, OMAP_TIMER_CTRL_REG, ctrl, posted);
 319 }
 320
 321 static inline void __omap_dm_timer_int_enable(void __iomem *base,
 322                                                 unsigned int value)
 323 {
 324         __omap_dm_timer_write(base, OMAP_TIMER_INT_EN_REG, value, 0);
 325         __omap_dm_timer_write(base, OMAP_TIMER_WAKEUP_EN_REG, value, 0);
 326 }
 327
 328 static inline unsigned int __omap_dm_timer_read_counter(void __iomem *base,
 329                                                         int posted)
 330 {
 331         return __omap_dm_timer_read(base, OMAP_TIMER_COUNTER_REG, posted);
 332 }
 333
 334 static inline void __omap_dm_timer_write_status(void __iomem *base,
 335                                                 unsigned int value)
 336 {
 337         __omap_dm_timer_write(base, OMAP_TIMER_STAT_REG, value, 0);
 338 }
 339
 340 #endif /* __ASM_ARCH_DMTIMER_H */