arch/powerpc/platforms/cell/axon_msi.c

   1 /*
   2  * Copyright 2007, Michael Ellerman, IBM Corporation.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * as published by the Free Software Foundation; either version
   7  * 2 of the License, or (at your option) any later version.
   8  */
   9
  10
  11 #include <linux/interrupt.h>
  12 #include <linux/irq.h>
  13 #include <linux/kernel.h>
  14 #include <linux/pci.h>
  15 #include <linux/msi.h>
  16 #include <linux/of_platform.h>
  17 #include <linux/debugfs.h>
  18 #include <linux/slab.h>
  19
  20 #include <asm/dcr.h>
  21 #include <asm/machdep.h>
  22 #include <asm/prom.h>
  23
  24
  25 /*
  26  * MSIC registers, specified as offsets from dcr_base
  27  */
  28 #define MSIC_CTRL_REG   0x0
  29
  30 /* Base Address registers specify FIFO location in BE memory */
  31 #define MSIC_BASE_ADDR_HI_REG   0x3
  32 #define MSIC_BASE_ADDR_LO_REG   0x4
  33
  34 /* Hold the read/write offsets into the FIFO */
  35 #define MSIC_READ_OFFSET_REG    0x5
  36 #define MSIC_WRITE_OFFSET_REG   0x6
  37
  38
  39 /* MSIC control register flags */
  40 #define MSIC_CTRL_ENABLE                0x0001
  41 #define MSIC_CTRL_FIFO_FULL_ENABLE      0x0002
  42 #define MSIC_CTRL_IRQ_ENABLE            0x0008
  43 #define MSIC_CTRL_FULL_STOP_ENABLE      0x0010
  44
  45 /*
  46  * The MSIC can be configured to use a FIFO of 32KB, 64KB, 128KB or 256KB.
  47  * Currently we're using a 64KB FIFO size.
  48  */
  49 #define MSIC_FIFO_SIZE_SHIFT    16
  50 #define MSIC_FIFO_SIZE_BYTES    (1 << MSIC_FIFO_SIZE_SHIFT)
  51
  52 /*
  53  * To configure the FIFO size as (1 << n) bytes, we write (n - 15) into bits
  54  * 8-9 of the MSIC control reg.
  55  */
  56 #define MSIC_CTRL_FIFO_SIZE     (((MSIC_FIFO_SIZE_SHIFT - 15) << 8) & 0x300)
  57
  58 /*
  59  * We need to mask the read/write offsets to make sure they stay within
  60  * the bounds of the FIFO. Also they should always be 16-byte aligned.
  61  */
  62 #define MSIC_FIFO_SIZE_MASK     ((MSIC_FIFO_SIZE_BYTES - 1) & ~0xFu)
  63
  64 /* Each entry in the FIFO is 16 bytes, the first 4 bytes hold the irq # */
  65 #define MSIC_FIFO_ENTRY_SIZE    0x10
  66
  67
  68 struct axon_msic {
  69         struct irq_host *irq_host;
  70         __le32 *fifo_virt;
  71         dma_addr_t fifo_phys;
  72         dcr_host_t dcr_host;
  73         u32 read_offset;
  74 #ifdef DEBUG
  75         u32 __iomem *trigger;
  76 #endif
  77 };
  78
  79 #ifdef DEBUG
  80 void axon_msi_debug_setup(struct device_node *dn, struct axon_msic *msic);
  81 #else
  82 static inline void axon_msi_debug_setup(struct device_node *dn,
  83                                         struct axon_msic *msic) { }
  84 #endif
  85
  86
  87 static void msic_dcr_write(struct axon_msic *msic, unsigned int dcr_n, u32 val)
  88 {
  89         pr_devel("axon_msi: dcr_write(0x%x, 0x%x)\n", val, dcr_n);
  90
  91         dcr_write(msic->dcr_host, dcr_n, val);
  92 }
  93
  94 static void axon_msi_cascade(unsigned int irq, struct irq_desc *desc)
  95 {
  96         struct irq_chip *chip = irq_desc_get_chip(desc);
  97         struct axon_msic *msic = irq_get_handler_data(irq);
  98         u32 write_offset, msi;
  99         int idx;
 100         int retry = 0;
 101
 102         write_offset = dcr_read(msic->dcr_host, MSIC_WRITE_OFFSET_REG);
 103         pr_devel("axon_msi: original write_offset 0x%x\n", write_offset);
 104
 105         /* write_offset doesn't wrap properly, so we have to mask it */
 106         write_offset &= MSIC_FIFO_SIZE_MASK;
 107
 108         while (msic->read_offset != write_offset && retry < 100) {
 109                 idx  = msic->read_offset / sizeof(__le32);
 110                 msi  = le32_to_cpu(msic->fifo_virt[idx]);
 111                 msi &= 0xFFFF;
 112
 113                 pr_devel("axon_msi: woff %x roff %x msi %x\n",
 114                           write_offset, msic->read_offset, msi);
 115
 116                 if (msi < NR_IRQS && irq_get_chip_data(msi) == msic) {
 117                         generic_handle_irq(msi);
 118                         msic->fifo_virt[idx] = cpu_to_le32(0xffffffff);
 119                 } else {
 120                         /*
 121                          * Reading the MSIC_WRITE_OFFSET_REG does not
 122                          * reliably flush the outstanding DMA to the
 123                          * FIFO buffer. Here we were reading stale
 124                          * data, so we need to retry.
 125                          */
 126                         udelay(1);
 127                         retry++;
 128                         pr_devel("axon_msi: invalid irq 0x%x!\n", msi);
 129                         continue;
 130                 }
 131
 132                 if (retry) {
 133                         pr_devel("axon_msi: late irq 0x%x, retry %d\n",
 134                                  msi, retry);
 135                         retry = 0;
 136                 }
 137
 138                 msic->read_offset += MSIC_FIFO_ENTRY_SIZE;
 139                 msic->read_offset &= MSIC_FIFO_SIZE_MASK;
 140         }
 141
 142         if (retry) {
 143                 printk(KERN_WARNING "axon_msi: irq timed out\n");
 144
 145                 msic->read_offset += MSIC_FIFO_ENTRY_SIZE;
 146                 msic->read_offset &= MSIC_FIFO_SIZE_MASK;
 147         }
 148
 149         chip->irq_eoi(&desc->irq_data);
 150 }
 151
 152 static struct axon_msic *find_msi_translator(struct pci_dev *dev)
 153 {
 154         struct irq_host *irq_host;
 155         struct device_node *dn, *tmp;
 156         const phandle *ph;
 157         struct axon_msic *msic = NULL;
 158
 159         dn = of_node_get(pci_device_to_OF_node(dev));
 160         if (!dn) {
 161                 dev_dbg(&dev->dev, "axon_msi: no pci_dn found\n");
 162                 return NULL;
 163         }
 164
 165         for (; dn; dn = of_get_next_parent(dn)) {
 166                 ph = of_get_property(dn, "msi-translator", NULL);
 167                 if (ph)
 168                         break;
 169         }
 170
 171         if (!ph) {
 172                 dev_dbg(&dev->dev,
 173                         "axon_msi: no msi-translator property found\n");
 174                 goto out_error;
 175         }
 176
 177         tmp = dn;
 178         dn = of_find_node_by_phandle(*ph);
 179         of_node_put(tmp);
 180         if (!dn) {
 181                 dev_dbg(&dev->dev,
 182                         "axon_msi: msi-translator doesn't point to a node\n");
 183                 goto out_error;
 184         }
 185
 186         irq_host = irq_find_host(dn);
 187         if (!irq_host) {
 188                 dev_dbg(&dev->dev, "axon_msi: no irq_host found for node %s\n",
 189                         dn->full_name);
 190                 goto out_error;
 191         }
 192
 193         msic = irq_host->host_data;
 194
 195 out_error:
 196         of_node_put(dn);
 197
 198         return msic;
 199 }
 200
 201 static int axon_msi_check_device(struct pci_dev *dev, int nvec, int type)
 202 {
 203         if (!find_msi_translator(dev))
 204                 return -ENODEV;
 205
 206         return 0;
 207 }
 208
 209 static int setup_msi_msg_address(struct pci_dev *dev, struct msi_msg *msg)
 210 {
 211         struct device_node *dn;
 212         struct msi_desc *entry;
 213         int len;
 214         const u32 *prop;
 215
 216         dn = of_node_get(pci_device_to_OF_node(dev));
 217         if (!dn) {
 218                 dev_dbg(&dev->dev, "axon_msi: no pci_dn found\n");
 219                 return -ENODEV;
 220         }
 221
 222         entry = list_first_entry(&dev->msi_list, struct msi_desc, list);
 223
 224         for (; dn; dn = of_get_next_parent(dn)) {
 225                 if (entry->msi_attrib.is_64) {
 226                         prop = of_get_property(dn, "msi-address-64", &len);
 227                         if (prop)
 228                                 break;
 229                 }
 230
 231                 prop = of_get_property(dn, "msi-address-32", &len);
 232                 if (prop)
 233                         break;
 234         }
 235
 236         if (!prop) {
 237                 dev_dbg(&dev->dev,
 238                         "axon_msi: no msi-address-(32|64) properties found\n");
 239                 return -ENOENT;
 240         }
 241
 242         switch (len) {
 243         case 8:
 244                 msg->address_hi = prop[0];
 245                 msg->address_lo = prop[1];
 246                 break;
 247         case 4:
 248                 msg->address_hi = 0;
 249                 msg->address_lo = prop[0];
 250                 break;
 251         default:
 252                 dev_dbg(&dev->dev,
 253                         "axon_msi: malformed msi-address-(32|64) property\n");
 254                 of_node_put(dn);
 255                 return -EINVAL;
 256         }
 257
 258         of_node_put(dn);
 259
 260         return 0;
 261 }
 262
 263 static int axon_msi_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
 264 {
 265         unsigned int virq, rc;
 266         struct msi_desc *entry;
 267         struct msi_msg msg;
 268         struct axon_msic *msic;
 269
 270         msic = find_msi_translator(dev);
 271         if (!msic)
 272                 return -ENODEV;
 273
 274         rc = setup_msi_msg_address(dev, &msg);
 275         if (rc)
 276                 return rc;
 277
 278         /* We rely on being able to stash a virq in a u16 */
 279         BUILD_BUG_ON(NR_IRQS > 65536);
 280
 281         list_for_each_entry(entry, &dev->msi_list, list) {
 282                 virq = irq_create_direct_mapping(msic->irq_host);
 283                 if (virq == NO_IRQ) {
 284                         dev_warn(&dev->dev,
 285                                  "axon_msi: virq allocation failed!\n");
 286                         return -1;
 287                 }
 288                 dev_dbg(&dev->dev, "axon_msi: allocated virq 0x%x\n", virq);
 289
 290                 irq_set_msi_desc(virq, entry);
 291                 msg.data = virq;
 292                 write_msi_msg(virq, &msg);
 293         }
 294
 295         return 0;
 296 }
 297
 298 static void axon_msi_teardown_msi_irqs(struct pci_dev *dev)
 299 {
 300         struct msi_desc *entry;
 301
 302         dev_dbg(&dev->dev, "axon_msi: tearing down msi irqs\n");
 303
 304         list_for_each_entry(entry, &dev->msi_list, list) {
 305                 if (entry->irq == NO_IRQ)
 306                         continue;
 307
 308                 irq_set_msi_desc(entry->irq, NULL);
 309                 irq_dispose_mapping(entry->irq);
 310         }
 311 }
 312
 313 static struct irq_chip msic_irq_chip = {
 314         .irq_mask       = mask_msi_irq,
 315         .irq_unmask     = unmask_msi_irq,
 316         .irq_shutdown   = mask_msi_irq,
 317         .name           = "AXON-MSI",
 318 };
 319
 320 static int msic_host_map(struct irq_host *h, unsigned int virq,
 321                          irq_hw_number_t hw)
 322 {
 323         irq_set_chip_data(virq, h->host_data);
 324         irq_set_chip_and_handler(virq, &msic_irq_chip, handle_simple_irq);
 325
 326         return 0;
 327 }
 328
 329 static struct irq_host_ops msic_host_ops = {
 330         .map    = msic_host_map,
 331 };
 332
 333 static void axon_msi_shutdown(struct platform_device *device)
 334 {
 335         struct axon_msic *msic = dev_get_drvdata(&device->dev);
 336         u32 tmp;
 337
 338         pr_devel("axon_msi: disabling %s\n",
 339                   msic->irq_host->of_node->full_name);
 340         tmp  = dcr_read(msic->dcr_host, MSIC_CTRL_REG);
 341         tmp &= ~MSIC_CTRL_ENABLE & ~MSIC_CTRL_IRQ_ENABLE;
 342         msic_dcr_write(msic, MSIC_CTRL_REG, tmp);
 343 }
 344
 345 static int axon_msi_probe(struct platform_device *device)
 346 {
 347         struct device_node *dn = device->dev.of_node;
 348         struct axon_msic *msic;
 349         unsigned int virq;
 350         int dcr_base, dcr_len;
 351
 352         pr_devel("axon_msi: setting up dn %s\n", dn->full_name);
 353
 354         msic = kzalloc(sizeof(struct axon_msic), GFP_KERNEL);
 355         if (!msic) {
 356                 printk(KERN_ERR "axon_msi: couldn't allocate msic for %s\n",
 357                        dn->full_name);
 358                 goto out;
 359         }
 360
 361         dcr_base = dcr_resource_start(dn, 0);
 362         dcr_len = dcr_resource_len(dn, 0);
 363
 364         if (dcr_base == 0 || dcr_len == 0) {
 365                 printk(KERN_ERR
 366                        "axon_msi: couldn't parse dcr properties on %s\n",
 367                         dn->full_name);
 368                 goto out_free_msic;
 369         }
 370
 371         msic->dcr_host = dcr_map(dn, dcr_base, dcr_len);
 372         if (!DCR_MAP_OK(msic->dcr_host)) {
 373                 printk(KERN_ERR "axon_msi: dcr_map failed for %s\n",
 374                        dn->full_name);
 375                 goto out_free_msic;
 376         }
 377
 378         msic->fifo_virt = dma_alloc_coherent(&device->dev, MSIC_FIFO_SIZE_BYTES,
 379                                              &msic->fifo_phys, GFP_KERNEL);
 380         if (!msic->fifo_virt) {
 381                 printk(KERN_ERR "axon_msi: couldn't allocate fifo for %s\n",
 382                        dn->full_name);
 383                 goto out_free_msic;
 384         }
 385
 386         virq = irq_of_parse_and_map(dn, 0);
 387         if (virq == NO_IRQ) {
 388                 printk(KERN_ERR "axon_msi: irq parse and map failed for %s\n",
 389                        dn->full_name);
 390                 goto out_free_fifo;
 391         }
 392         memset(msic->fifo_virt, 0xff, MSIC_FIFO_SIZE_BYTES);
 393
 394         msic->irq_host = irq_alloc_host(dn, IRQ_HOST_MAP_NOMAP,
 395                                         NR_IRQS, &msic_host_ops, 0);
 396         if (!msic->irq_host) {
 397                 printk(KERN_ERR "axon_msi: couldn't allocate irq_host for %s\n",
 398                        dn->full_name);
 399                 goto out_free_fifo;
 400         }
 401
 402         msic->irq_host->host_data = msic;
 403
 404         irq_set_handler_data(virq, msic);
 405         irq_set_chained_handler(virq, axon_msi_cascade);
 406         pr_devel("axon_msi: irq 0x%x setup for axon_msi\n", virq);
 407
 408         /* Enable the MSIC hardware */
 409         msic_dcr_write(msic, MSIC_BASE_ADDR_HI_REG, msic->fifo_phys >> 32);
 410         msic_dcr_write(msic, MSIC_BASE_ADDR_LO_REG,
 411                                   msic->fifo_phys & 0xFFFFFFFF);
 412         msic_dcr_write(msic, MSIC_CTRL_REG,
 413                         MSIC_CTRL_IRQ_ENABLE | MSIC_CTRL_ENABLE |
 414                         MSIC_CTRL_FIFO_SIZE);
 415
 416         msic->read_offset = dcr_read(msic->dcr_host, MSIC_WRITE_OFFSET_REG)
 417                                 & MSIC_FIFO_SIZE_MASK;
 418
 419         dev_set_drvdata(&device->dev, msic);
 420
 421         ppc_md.setup_msi_irqs = axon_msi_setup_msi_irqs;
 422         ppc_md.teardown_msi_irqs = axon_msi_teardown_msi_irqs;
 423         ppc_md.msi_check_device = axon_msi_check_device;
 424
 425         axon_msi_debug_setup(dn, msic);
 426
 427         printk(KERN_DEBUG "axon_msi: setup MSIC on %s\n", dn->full_name);
 428
 429         return 0;
 430
 431 out_free_fifo:
 432         dma_free_coherent(&device->dev, MSIC_FIFO_SIZE_BYTES, msic->fifo_virt,
 433                           msic->fifo_phys);
 434 out_free_msic:
 435         kfree(msic);
 436 out:
 437
 438         return -1;
 439 }
 440
 441 static const struct of_device_id axon_msi_device_id[] = {
 442         {
 443                 .compatible     = "ibm,axon-msic"
 444         },
 445         {}
 446 };
 447
 448 static struct platform_driver axon_msi_driver = {
 449         .probe          = axon_msi_probe,
 450         .shutdown       = axon_msi_shutdown,
 451         .driver = {
 452                 .name = "axon-msi",
 453                 .owner = THIS_MODULE,
 454                 .of_match_table = axon_msi_device_id,
 455         },
 456 };
 457
 458 static int __init axon_msi_init(void)
 459 {
 460         return platform_driver_register(&axon_msi_driver);
 461 }
 462 subsys_initcall(axon_msi_init);
 463
 464
 465 #ifdef DEBUG
 466 static int msic_set(void *data, u64 val)
 467 {
 468         struct axon_msic *msic = data;
 469         out_le32(msic->trigger, val);
 470         return 0;
 471 }
 472
 473 static int msic_get(void *data, u64 *val)
 474 {
 475         *val = 0;
 476         return 0;
 477 }
 478
 479 DEFINE_SIMPLE_ATTRIBUTE(fops_msic, msic_get, msic_set, "%llu\n");
 480
 481 void axon_msi_debug_setup(struct device_node *dn, struct axon_msic *msic)
 482 {
 483         char name[8];
 484         u64 addr;
 485
 486         addr = of_translate_address(dn, of_get_property(dn, "reg", NULL));
 487         if (addr == OF_BAD_ADDR) {
 488                 pr_devel("axon_msi: couldn't translate reg property\n");
 489                 return;
 490         }
 491
 492         msic->trigger = ioremap(addr, 0x4);
 493         if (!msic->trigger) {
 494                 pr_devel("axon_msi: ioremap failed\n");
 495                 return;
 496         }
 497
 498         snprintf(name, sizeof(name), "msic_%d", of_node_to_nid(dn));
 499
 500         if (!debugfs_create_file(name, 0600, powerpc_debugfs_root,
 501                                  msic, &fops_msic)) {
 502                 pr_devel("axon_msi: debugfs_create_file failed!\n");
 503                 return;
 504         }
 505 }
 506 #endif /* DEBUG */