2 * Copyright (C) 2001 Allan Trautman, IBM Corporation
3 * Copyright (C) 2005,2007 Stephen Rothwell, IBM Corp
5 * iSeries specific routines for PCI.
7 * Based on code from pci.c and iSeries_pci.c 32bit
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
26 #include <linux/jiffies.h>
27 #include <linux/kernel.h>
28 #include <linux/list.h>
29 #include <linux/string.h>
30 #include <linux/slab.h>
31 #include <linux/init.h>
32 #include <linux/module.h>
33 #include <linux/pci.h>
35 #include <linux/ratelimit.h>
37 #include <asm/types.h>
41 #include <asm/machdep.h>
42 #include <asm/pci-bridge.h>
43 #include <asm/iommu.h>
44 #include <asm/abs_addr.h>
45 #include <asm/firmware.h>
47 #include <asm/iseries/hv_types.h>
48 #include <asm/iseries/hv_call_xm.h>
49 #include <asm/iseries/mf.h>
50 #include <asm/iseries/iommu.h>
52 #include <asm/ppc-pci.h>
58 #define PCI_RETRY_MAX 3
59 static int limit_pci_retries
= 1; /* Set Retry Error on. */
63 * Each Entry size is 4 MB * 1024 Entries = 4GB I/O address space.
65 #define IOMM_TABLE_MAX_ENTRIES 1024
66 #define IOMM_TABLE_ENTRY_SIZE 0x0000000000400000UL
67 #define BASE_IO_MEMORY 0xE000000000000000UL
68 #define END_IO_MEMORY 0xEFFFFFFFFFFFFFFFUL
70 static unsigned long max_io_memory
= BASE_IO_MEMORY
;
71 static long current_iomm_table_entry
;
76 static struct device_node
*iomm_table
[IOMM_TABLE_MAX_ENTRIES
];
77 static u64 ds_addr_table
[IOMM_TABLE_MAX_ENTRIES
];
79 static DEFINE_SPINLOCK(iomm_table_lock
);
82 * Generate a Direct Select Address for the Hypervisor
84 static inline u64
iseries_ds_addr(struct device_node
*node
)
86 struct pci_dn
*pdn
= PCI_DN(node
);
87 const u32
*sbp
= of_get_property(node
, "linux,subbus", NULL
);
89 return ((u64
)pdn
->busno
<< 48) + ((u64
)(sbp
? *sbp
: 0) << 40)
94 * Size of Bus VPD data
96 #define BUS_VPDSIZE 1024
101 #define VPD_END_OF_AREA 0x79
102 #define VPD_ID_STRING 0x82
103 #define VPD_VENDOR_AREA 0x84
108 #define VPD_FRU_FRAME_ID 0x4649 /* "FI" */
109 #define VPD_SLOT_MAP_FORMAT 0x4D46 /* "MF" */
110 #define VPD_SLOT_MAP 0x534D /* "SM" */
113 * Structures of the areas
115 struct mfg_vpd_area
{
121 #define MFG_ENTRY_SIZE 3
127 char card_location
[3];
131 #define SLOT_ENTRY_SIZE 16
134 * Parse the Slot Area
136 static void __init
iseries_parse_slot_area(struct slot_map
*map
, int len
,
137 HvAgentId agent
, u8
*phb
, char card
[4])
140 * Parse Slot label until we find the one requested
143 if (map
->agent
== agent
) {
145 * If Phb wasn't found, grab the entry first one found.
149 /* Found it, extract the data. */
150 if (map
->phb
== *phb
) {
151 memcpy(card
, &map
->card_location
, 3);
156 /* Point to the next Slot */
157 map
= (struct slot_map
*)((char *)map
+ SLOT_ENTRY_SIZE
);
158 len
-= SLOT_ENTRY_SIZE
;
165 static void __init
iseries_parse_mfg_area(struct mfg_vpd_area
*area
, int len
,
166 HvAgentId agent
, u8
*phb
, u8
*frame
, char card
[4])
168 u16 slot_map_fmt
= 0;
172 int mfg_tag_len
= area
->length
;
173 /* Frame ID (FI 4649020310 ) */
174 if (area
->tag
== VPD_FRU_FRAME_ID
)
175 *frame
= area
->data1
;
176 /* Slot Map Format (MF 4D46020004 ) */
177 else if (area
->tag
== VPD_SLOT_MAP_FORMAT
)
178 slot_map_fmt
= (area
->data1
* 256)
180 /* Slot Map (SM 534D90 */
181 else if (area
->tag
== VPD_SLOT_MAP
) {
182 struct slot_map
*slot_map
;
184 if (slot_map_fmt
== 0x1004)
185 slot_map
= (struct slot_map
*)((char *)area
186 + MFG_ENTRY_SIZE
+ 1);
188 slot_map
= (struct slot_map
*)((char *)area
190 iseries_parse_slot_area(slot_map
, mfg_tag_len
,
194 * Point to the next Mfg Area
195 * Use defined size, sizeof give wrong answer
197 area
= (struct mfg_vpd_area
*)((char *)area
+ mfg_tag_len
199 len
-= (mfg_tag_len
+ MFG_ENTRY_SIZE
);
204 * Look for "BUS".. Data is not Null terminated.
205 * PHBID of 0xFF indicates PHB was not found in VPD Data.
207 static u8 __init
iseries_parse_phbid(u8
*area
, int len
)
210 if ((*area
== 'B') && (*(area
+ 1) == 'U')
211 && (*(area
+ 2) == 'S')) {
224 * Parse out the VPD Areas
226 static void __init
iseries_parse_vpd(u8
*data
, int data_len
,
227 HvAgentId agent
, u8
*frame
, char card
[4])
231 while (data_len
> 0) {
235 if (tag
== VPD_END_OF_AREA
)
237 len
= *(data
+ 1) + (*(data
+ 2) * 256);
240 if (tag
== VPD_ID_STRING
)
241 phb
= iseries_parse_phbid(data
, len
);
242 else if (tag
== VPD_VENDOR_AREA
)
243 iseries_parse_mfg_area((struct mfg_vpd_area
*)data
, len
,
244 agent
, &phb
, frame
, card
);
245 /* Point to next Area. */
251 static int __init
iseries_get_location_code(u16 bus
, HvAgentId agent
,
252 u8
*frame
, char card
[4])
256 u8
*bus_vpd
= kmalloc(BUS_VPDSIZE
, GFP_KERNEL
);
258 if (bus_vpd
== NULL
) {
259 printk("PCI: Bus VPD Buffer allocation failure.\n");
262 bus_vpd_len
= HvCallPci_getBusVpd(bus
, iseries_hv_addr(bus_vpd
),
264 if (bus_vpd_len
== 0) {
265 printk("PCI: Bus VPD Buffer zero length.\n");
268 /* printk("PCI: bus_vpd: %p, %d\n",bus_vpd, bus_vpd_len); */
269 /* Make sure this is what I think it is */
270 if (*bus_vpd
!= VPD_ID_STRING
) {
271 printk("PCI: Bus VPD Buffer missing starting tag.\n");
274 iseries_parse_vpd(bus_vpd
, bus_vpd_len
, agent
, frame
, card
);
282 * Prints the device information.
283 * - Pass in pci_dev* pointer to the device.
284 * - Pass in the device count
287 * PCI: Bus 0, Device 26, Vendor 0x12AE Frame 1, Card C10 Ethernet
290 static void __init
iseries_device_information(struct pci_dev
*pdev
,
291 u16 bus
, HvSubBusNumber subbus
)
297 agent
= ISERIES_PCI_AGENTID(ISERIES_GET_DEVICE_FROM_SUBBUS(subbus
),
298 ISERIES_GET_FUNCTION_FROM_SUBBUS(subbus
));
300 if (iseries_get_location_code(bus
, agent
, &frame
, card
)) {
301 printk(KERN_INFO
"PCI: %s, Vendor %04X Frame%3d, "
302 "Card %4s 0x%04X\n", pci_name(pdev
), pdev
->vendor
,
303 frame
, card
, (int)(pdev
->class >> 8));
308 * iomm_table_allocate_entry
310 * Adds pci_dev entry in address translation table
312 * - Allocates the number of entries required in table base on BAR
314 * - Allocates starting at BASE_IO_MEMORY and increases.
315 * - The size is round up to be a multiple of entry size.
316 * - CurrentIndex is incremented to keep track of the last entry.
317 * - Builds the resource entry for allocated BARs.
319 static void __init
iomm_table_allocate_entry(struct pci_dev
*dev
, int bar_num
)
321 struct resource
*bar_res
= &dev
->resource
[bar_num
];
322 long bar_size
= pci_resource_len(dev
, bar_num
);
323 struct device_node
*dn
= pci_device_to_OF_node(dev
);
326 * No space to allocate, quick exit, skip Allocation.
331 * Set Resource values.
333 spin_lock(&iomm_table_lock
);
334 bar_res
->start
= BASE_IO_MEMORY
+
335 IOMM_TABLE_ENTRY_SIZE
* current_iomm_table_entry
;
336 bar_res
->end
= bar_res
->start
+ bar_size
- 1;
338 * Allocate the number of table entries needed for BAR.
340 while (bar_size
> 0 ) {
341 iomm_table
[current_iomm_table_entry
] = dn
;
342 ds_addr_table
[current_iomm_table_entry
] =
343 iseries_ds_addr(dn
) | (bar_num
<< 24);
344 bar_size
-= IOMM_TABLE_ENTRY_SIZE
;
345 ++current_iomm_table_entry
;
347 max_io_memory
= BASE_IO_MEMORY
+
348 IOMM_TABLE_ENTRY_SIZE
* current_iomm_table_entry
;
349 spin_unlock(&iomm_table_lock
);
353 * allocate_device_bars
355 * - Allocates ALL pci_dev BAR's and updates the resources with the
356 * BAR value. BARS with zero length will have the resources
357 * The HvCallPci_getBarParms is used to get the size of the BAR
358 * space. It calls iomm_table_allocate_entry to allocate
360 * - Loops through The Bar resources(0 - 5) including the ROM
363 static void __init
allocate_device_bars(struct pci_dev
*dev
)
367 for (bar_num
= 0; bar_num
<= PCI_ROM_RESOURCE
; ++bar_num
)
368 iomm_table_allocate_entry(dev
, bar_num
);
372 * Log error information to system console.
373 * Filter out the device not there errors.
374 * PCI: EADs Connect Failed 0x18.58.10 Rc: 0x00xx
375 * PCI: Read Vendor Failed 0x18.58.10 Rc: 0x00xx
376 * PCI: Connect Bus Unit Failed 0x18.58.10 Rc: 0x00xx
378 static void pci_log_error(char *error
, int bus
, int subbus
,
379 int agent
, int hv_res
)
381 if (hv_res
== 0x0302)
383 printk(KERN_ERR
"PCI: %s Failed: 0x%02X.%02X.%02X Rc: 0x%04X",
384 error
, bus
, subbus
, agent
, hv_res
);
388 * Look down the chain to find the matching Device Device
390 static struct device_node
*find_device_node(int bus
, int devfn
)
392 struct device_node
*node
;
394 for (node
= NULL
; (node
= of_find_all_nodes(node
)); ) {
395 struct pci_dn
*pdn
= PCI_DN(node
);
397 if (pdn
&& (bus
== pdn
->busno
) && (devfn
== pdn
->devfn
))
404 * iSeries_pcibios_fixup_resources
406 * Fixes up all resources for devices
408 void __init
iSeries_pcibios_fixup_resources(struct pci_dev
*pdev
)
412 unsigned char bus
= pdev
->bus
->number
;
413 struct device_node
*node
;
416 node
= pci_device_to_OF_node(pdev
);
417 pr_debug("PCI: iSeries %s, pdev %p, node %p\n",
418 pci_name(pdev
), pdev
, node
);
420 printk("PCI: %s disabled, device tree entry not found !\n",
422 for (i
= 0; i
<= PCI_ROM_RESOURCE
; i
++)
423 pdev
->resource
[i
].flags
= 0;
426 sub_bus
= of_get_property(node
, "linux,subbus", NULL
);
427 agent
= of_get_property(node
, "linux,agent-id", NULL
);
428 if (agent
&& sub_bus
) {
429 u8 irq
= iSeries_allocate_IRQ(bus
, 0, *sub_bus
);
432 err
= HvCallXm_connectBusUnit(bus
, *sub_bus
, *agent
, irq
);
434 pci_log_error("Connect Bus Unit",
435 bus
, *sub_bus
, *agent
, err
);
437 err
= HvCallPci_configStore8(bus
, *sub_bus
,
438 *agent
, PCI_INTERRUPT_LINE
, irq
);
440 pci_log_error("PciCfgStore Irq Failed!",
441 bus
, *sub_bus
, *agent
, err
);
447 allocate_device_bars(pdev
);
449 iseries_device_information(pdev
, bus
, *sub_bus
);
451 printk(KERN_ERR
"PCI: Device node %s has missing or invalid "
452 "linux,subbus property\n", node
->full_name
);
456 * iSeries_pci_final_fixup(void)
458 void __init
iSeries_pci_final_fixup(void)
460 /* Fix up at the device node and pci_dev relationship */
461 mf_display_src(0xC9000100);
462 iSeries_activate_IRQs();
463 mf_display_src(0xC9000200);
467 * Config space read and write functions.
468 * For now at least, we look for the device node for the bus and devfn
469 * that we are asked to access. It may be possible to translate the devfn
470 * to a subbus and deviceid more directly.
472 static u64 hv_cfg_read_func
[4] = {
473 HvCallPciConfigLoad8
, HvCallPciConfigLoad16
,
474 HvCallPciConfigLoad32
, HvCallPciConfigLoad32
477 static u64 hv_cfg_write_func
[4] = {
478 HvCallPciConfigStore8
, HvCallPciConfigStore16
,
479 HvCallPciConfigStore32
, HvCallPciConfigStore32
483 * Read PCI config space
485 static int iSeries_pci_read_config(struct pci_bus
*bus
, unsigned int devfn
,
486 int offset
, int size
, u32
*val
)
488 struct device_node
*node
= find_device_node(bus
->number
, devfn
);
490 struct HvCallPci_LoadReturn ret
;
493 return PCIBIOS_DEVICE_NOT_FOUND
;
496 return PCIBIOS_BAD_REGISTER_NUMBER
;
499 fn
= hv_cfg_read_func
[(size
- 1) & 3];
500 HvCall3Ret16(fn
, &ret
, iseries_ds_addr(node
), offset
, 0);
504 return PCIBIOS_DEVICE_NOT_FOUND
; /* or something */
512 * Write PCI config space
515 static int iSeries_pci_write_config(struct pci_bus
*bus
, unsigned int devfn
,
516 int offset
, int size
, u32 val
)
518 struct device_node
*node
= find_device_node(bus
->number
, devfn
);
523 return PCIBIOS_DEVICE_NOT_FOUND
;
525 return PCIBIOS_BAD_REGISTER_NUMBER
;
527 fn
= hv_cfg_write_func
[(size
- 1) & 3];
528 ret
= HvCall4(fn
, iseries_ds_addr(node
), offset
, val
, 0);
531 return PCIBIOS_DEVICE_NOT_FOUND
;
536 static struct pci_ops iSeries_pci_ops
= {
537 .read
= iSeries_pci_read_config
,
538 .write
= iSeries_pci_write_config
543 * -> On Failure, print and log information.
544 * Increment Retry Count, if exceeds max, panic partition.
546 * PCI: Device 23.90 ReadL I/O Error( 0): 0x1234
547 * PCI: Device 23.90 ReadL Retry( 1)
548 * PCI: Device 23.90 ReadL Retry Successful(1)
550 static int check_return_code(char *type
, struct device_node
*dn
,
554 struct pci_dn
*pdn
= PCI_DN(dn
);
557 printk("PCI: %s: Device 0x%04X:%02X I/O Error(%2d): 0x%04X\n",
558 type
, pdn
->busno
, pdn
->devfn
,
561 * Bump the retry and check for retry count exceeded.
562 * If, Exceeded, panic the system.
564 if (((*retry
) > PCI_RETRY_MAX
) &&
565 (limit_pci_retries
> 0)) {
566 mf_display_src(0xB6000103);
568 panic("PCI: Hardware I/O Error, SRC B6000103, "
569 "Automatic Reboot Disabled.\n");
571 return -1; /* Retry Try */
577 * Translate the I/O Address into a device node, bar, and bar offset.
578 * Note: Make sure the passed variable end up on the stack to avoid
579 * the exposure of being device global.
581 static inline struct device_node
*xlate_iomm_address(
582 const volatile void __iomem
*addr
,
583 u64
*dsaptr
, u64
*bar_offset
, const char *func
)
585 unsigned long orig_addr
;
586 unsigned long base_addr
;
588 struct device_node
*dn
;
590 orig_addr
= (unsigned long __force
)addr
;
591 if ((orig_addr
< BASE_IO_MEMORY
) || (orig_addr
>= max_io_memory
)) {
592 static DEFINE_RATELIMIT_STATE(ratelimit
, 60 * HZ
, 10);
594 if (__ratelimit(&ratelimit
))
596 "iSeries_%s: invalid access at IO address %p\n",
600 base_addr
= orig_addr
- BASE_IO_MEMORY
;
601 ind
= base_addr
/ IOMM_TABLE_ENTRY_SIZE
;
602 dn
= iomm_table
[ind
];
605 *dsaptr
= ds_addr_table
[ind
];
606 *bar_offset
= base_addr
% IOMM_TABLE_ENTRY_SIZE
;
608 panic("PCI: Invalid PCI IO address detected!\n");
613 * Read MM I/O Instructions for the iSeries
614 * On MM I/O error, all ones are returned and iSeries_pci_IoError is cal
615 * else, data is returned in Big Endian format.
617 static u8
iseries_readb(const volatile void __iomem
*addr
)
622 struct HvCallPci_LoadReturn ret
;
623 struct device_node
*dn
=
624 xlate_iomm_address(addr
, &dsa
, &bar_offset
, "read_byte");
629 HvCall3Ret16(HvCallPciBarLoad8
, &ret
, dsa
, bar_offset
, 0);
630 } while (check_return_code("RDB", dn
, &retry
, ret
.rc
) != 0);
635 static u16
iseries_readw_be(const volatile void __iomem
*addr
)
640 struct HvCallPci_LoadReturn ret
;
641 struct device_node
*dn
=
642 xlate_iomm_address(addr
, &dsa
, &bar_offset
, "read_word");
647 HvCall3Ret16(HvCallPciBarLoad16
, &ret
, dsa
,
649 } while (check_return_code("RDW", dn
, &retry
, ret
.rc
) != 0);
654 static u32
iseries_readl_be(const volatile void __iomem
*addr
)
659 struct HvCallPci_LoadReturn ret
;
660 struct device_node
*dn
=
661 xlate_iomm_address(addr
, &dsa
, &bar_offset
, "read_long");
666 HvCall3Ret16(HvCallPciBarLoad32
, &ret
, dsa
,
668 } while (check_return_code("RDL", dn
, &retry
, ret
.rc
) != 0);
674 * Write MM I/O Instructions for the iSeries
677 static void iseries_writeb(u8 data
, volatile void __iomem
*addr
)
683 struct device_node
*dn
=
684 xlate_iomm_address(addr
, &dsa
, &bar_offset
, "write_byte");
689 rc
= HvCall4(HvCallPciBarStore8
, dsa
, bar_offset
, data
, 0);
690 } while (check_return_code("WWB", dn
, &retry
, rc
) != 0);
693 static void iseries_writew_be(u16 data
, volatile void __iomem
*addr
)
699 struct device_node
*dn
=
700 xlate_iomm_address(addr
, &dsa
, &bar_offset
, "write_word");
705 rc
= HvCall4(HvCallPciBarStore16
, dsa
, bar_offset
, data
, 0);
706 } while (check_return_code("WWW", dn
, &retry
, rc
) != 0);
709 static void iseries_writel_be(u32 data
, volatile void __iomem
*addr
)
715 struct device_node
*dn
=
716 xlate_iomm_address(addr
, &dsa
, &bar_offset
, "write_long");
721 rc
= HvCall4(HvCallPciBarStore32
, dsa
, bar_offset
, data
, 0);
722 } while (check_return_code("WWL", dn
, &retry
, rc
) != 0);
725 static u16
iseries_readw(const volatile void __iomem
*addr
)
727 return le16_to_cpu(iseries_readw_be(addr
));
730 static u32
iseries_readl(const volatile void __iomem
*addr
)
732 return le32_to_cpu(iseries_readl_be(addr
));
735 static void iseries_writew(u16 data
, volatile void __iomem
*addr
)
737 iseries_writew_be(cpu_to_le16(data
), addr
);
740 static void iseries_writel(u32 data
, volatile void __iomem
*addr
)
742 iseries_writel(cpu_to_le32(data
), addr
);
745 static void iseries_readsb(const volatile void __iomem
*addr
, void *buf
,
750 *(dst
++) = iseries_readb(addr
);
753 static void iseries_readsw(const volatile void __iomem
*addr
, void *buf
,
758 *(dst
++) = iseries_readw_be(addr
);
761 static void iseries_readsl(const volatile void __iomem
*addr
, void *buf
,
766 *(dst
++) = iseries_readl_be(addr
);
769 static void iseries_writesb(volatile void __iomem
*addr
, const void *buf
,
774 iseries_writeb(*(src
++), addr
);
777 static void iseries_writesw(volatile void __iomem
*addr
, const void *buf
,
780 const u16
*src
= buf
;
782 iseries_writew_be(*(src
++), addr
);
785 static void iseries_writesl(volatile void __iomem
*addr
, const void *buf
,
788 const u32
*src
= buf
;
790 iseries_writel_be(*(src
++), addr
);
793 static void iseries_memset_io(volatile void __iomem
*addr
, int c
,
796 volatile char __iomem
*d
= addr
;
799 iseries_writeb(c
, d
++);
802 static void iseries_memcpy_fromio(void *dest
, const volatile void __iomem
*src
,
806 const volatile char __iomem
*s
= src
;
809 *d
++ = iseries_readb(s
++);
812 static void iseries_memcpy_toio(volatile void __iomem
*dest
, const void *src
,
816 volatile char __iomem
*d
= dest
;
819 iseries_writeb(*s
++, d
++);
822 /* We only set MMIO ops. The default PIO ops will be default
823 * to the MMIO ops + pci_io_base which is 0 on iSeries as
824 * expected so both should work.
826 * Note that we don't implement the readq/writeq versions as
827 * I don't know of an HV call for doing so. Thus, the default
828 * operation will be used instead, which will fault a the value
829 * return by iSeries for MMIO addresses always hits a non mapped
830 * area. This is as good as the BUG() we used to have there.
832 static struct ppc_pci_io __initdata iseries_pci_io
= {
833 .readb
= iseries_readb
,
834 .readw
= iseries_readw
,
835 .readl
= iseries_readl
,
836 .readw_be
= iseries_readw_be
,
837 .readl_be
= iseries_readl_be
,
838 .writeb
= iseries_writeb
,
839 .writew
= iseries_writew
,
840 .writel
= iseries_writel
,
841 .writew_be
= iseries_writew_be
,
842 .writel_be
= iseries_writel_be
,
843 .readsb
= iseries_readsb
,
844 .readsw
= iseries_readsw
,
845 .readsl
= iseries_readsl
,
846 .writesb
= iseries_writesb
,
847 .writesw
= iseries_writesw
,
848 .writesl
= iseries_writesl
,
849 .memset_io
= iseries_memset_io
,
850 .memcpy_fromio
= iseries_memcpy_fromio
,
851 .memcpy_toio
= iseries_memcpy_toio
,
855 * iSeries_pcibios_init
858 * This function checks for all possible system PCI host bridges that connect
859 * PCI buses. The system hypervisor is queried as to the guest partition
860 * ownership status. A pci_controller is built for any bus which is partially
861 * owned or fully owned by this guest partition.
863 void __init
iSeries_pcibios_init(void)
865 struct pci_controller
*phb
;
866 struct device_node
*root
= of_find_node_by_path("/");
867 struct device_node
*node
= NULL
;
869 /* Install IO hooks */
870 ppc_pci_io
= iseries_pci_io
;
874 /* iSeries has no IO space in the common sense, it needs to set
880 printk(KERN_CRIT
"iSeries_pcibios_init: can't find root "
884 while ((node
= of_get_next_child(root
, node
)) != NULL
) {
888 if ((node
->type
== NULL
) || (strcmp(node
->type
, "pci") != 0))
891 busp
= of_get_property(node
, "bus-range", NULL
);
895 printk("bus %d appears to exist\n", bus
);
896 phb
= pcibios_alloc_controller(node
);
899 /* All legacy iSeries PHBs are in domain zero */
900 phb
->global_number
= 0;
902 phb
->first_busno
= bus
;
903 phb
->last_busno
= bus
;
904 phb
->ops
= &iSeries_pci_ops
;
905 phb
->io_base_virt
= (void __iomem
*)_IO_BASE
;
906 phb
->io_resource
.flags
= IORESOURCE_IO
;
907 phb
->io_resource
.start
= BASE_IO_MEMORY
;
908 phb
->io_resource
.end
= END_IO_MEMORY
;
909 phb
->io_resource
.name
= "iSeries PCI IO";
910 phb
->mem_resources
[0].flags
= IORESOURCE_MEM
;
911 phb
->mem_resources
[0].start
= BASE_IO_MEMORY
;
912 phb
->mem_resources
[0].end
= END_IO_MEMORY
;
913 phb
->mem_resources
[0].name
= "Series PCI MEM";