drivers/staging/et131x/et1310_eeprom.c

   1 /*
   2  * Agere Systems Inc.
   3  * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
   4  *
   5  * Copyright © 2005 Agere Systems Inc.
   6  * All rights reserved.
   7  *   http://www.agere.com
   8  *
   9  * Copyright (c) 2011 Mark Einon <mark.einon@gmail.com>
  10  *
  11  *------------------------------------------------------------------------------
  12  *
  13  * et1310_eeprom.c - Code used to access the device's EEPROM
  14  *
  15  *------------------------------------------------------------------------------
  16  *
  17  * SOFTWARE LICENSE
  18  *
  19  * This software is provided subject to the following terms and conditions,
  20  * which you should read carefully before using the software.  Using this
  21  * software indicates your acceptance of these terms and conditions.  If you do
  22  * not agree with these terms and conditions, do not use the software.
  23  *
  24  * Copyright © 2005 Agere Systems Inc.
  25  * All rights reserved.
  26  *
  27  * Redistribution and use in source or binary forms, with or without
  28  * modifications, are permitted provided that the following conditions are met:
  29  *
  30  * . Redistributions of source code must retain the above copyright notice, this
  31  *    list of conditions and the following Disclaimer as comments in the code as
  32  *    well as in the documentation and/or other materials provided with the
  33  *    distribution.
  34  *
  35  * . Redistributions in binary form must reproduce the above copyright notice,
  36  *    this list of conditions and the following Disclaimer in the documentation
  37  *    and/or other materials provided with the distribution.
  38  *
  39  * . Neither the name of Agere Systems Inc. nor the names of the contributors
  40  *    may be used to endorse or promote products derived from this software
  41  *    without specific prior written permission.
  42  *
  43  * Disclaimer
  44  *
  45  * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
  46  * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
  47  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  ANY
  48  * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
  49  * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
  50  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  51  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  52  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  53  * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
  54  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
  55  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
  56  * DAMAGE.
  57  *
  58  */
  59
  60 #include "et131x_defs.h"
  61
  62 #include <linux/pci.h>
  63 #include <linux/init.h>
  64 #include <linux/module.h>
  65 #include <linux/types.h>
  66 #include <linux/kernel.h>
  67
  68 #include <linux/sched.h>
  69 #include <linux/ptrace.h>
  70 #include <linux/ctype.h>
  71 #include <linux/string.h>
  72 #include <linux/timer.h>
  73 #include <linux/interrupt.h>
  74 #include <linux/in.h>
  75 #include <linux/delay.h>
  76 #include <linux/bitops.h>
  77 #include <linux/io.h>
  78 #include <asm/system.h>
  79
  80 #include <linux/netdevice.h>
  81 #include <linux/etherdevice.h>
  82 #include <linux/skbuff.h>
  83 #include <linux/if_arp.h>
  84 #include <linux/ioport.h>
  85
  86 #include "et1310_phy.h"
  87 #include "et131x_adapter.h"
  88 #include "et131x.h"
  89
  90 /*
  91  * EEPROM Defines
  92  */
  93
  94 /* LBCIF Register Groups (addressed via 32-bit offsets) */
  95 #define LBCIF_DWORD0_GROUP       0xAC
  96 #define LBCIF_DWORD1_GROUP       0xB0
  97
  98 /* LBCIF Registers (addressed via 8-bit offsets) */
  99 #define LBCIF_ADDRESS_REGISTER   0xAC
 100 #define LBCIF_DATA_REGISTER      0xB0
 101 #define LBCIF_CONTROL_REGISTER   0xB1
 102 #define LBCIF_STATUS_REGISTER    0xB2
 103
 104 /* LBCIF Control Register Bits */
 105 #define LBCIF_CONTROL_SEQUENTIAL_READ   0x01
 106 #define LBCIF_CONTROL_PAGE_WRITE        0x02
 107 #define LBCIF_CONTROL_EEPROM_RELOAD     0x08
 108 #define LBCIF_CONTROL_TWO_BYTE_ADDR     0x20
 109 #define LBCIF_CONTROL_I2C_WRITE         0x40
 110 #define LBCIF_CONTROL_LBCIF_ENABLE      0x80
 111
 112 /* LBCIF Status Register Bits */
 113 #define LBCIF_STATUS_PHY_QUEUE_AVAIL    0x01
 114 #define LBCIF_STATUS_I2C_IDLE           0x02
 115 #define LBCIF_STATUS_ACK_ERROR          0x04
 116 #define LBCIF_STATUS_GENERAL_ERROR      0x08
 117 #define LBCIF_STATUS_CHECKSUM_ERROR     0x40
 118 #define LBCIF_STATUS_EEPROM_PRESENT     0x80
 119
 120 /* Miscellaneous Constraints */
 121 #define MAX_NUM_REGISTER_POLLS          1000
 122 #define MAX_NUM_WRITE_RETRIES           2
 123
 124 static int eeprom_wait_ready(struct pci_dev *pdev, u32 *status)
 125 {
 126         u32 reg;
 127         int i;
 128
 129         /*
 130          * 1. Check LBCIF Status Register for bits 6 & 3:2 all equal to 0 and
 131          *    bits 7,1:0 both equal to 1, at least once after reset.
 132          *    Subsequent operations need only to check that bits 1:0 are equal
 133          *    to 1 prior to starting a single byte read/write
 134          */
 135
 136         for (i = 0; i < MAX_NUM_REGISTER_POLLS; i++) {
 137                 /* Read registers grouped in DWORD1 */
 138                 if (pci_read_config_dword(pdev, LBCIF_DWORD1_GROUP, &reg))
 139                         return -EIO;
 140
 141                 /* I2C idle and Phy Queue Avail both true */
 142                 if ((reg & 0x3000) == 0x3000) {
 143                         if (status)
 144                                 *status = reg;
 145                         return reg & 0xFF;
 146                 }
 147         }
 148         return -ETIMEDOUT;
 149 }
 150
 151
 152 /**
 153  * eeprom_write - Write a byte to the ET1310's EEPROM
 154  * @adapter: pointer to our private adapter structure
 155  * @addr: the address to write
 156  * @data: the value to write
 157  *
 158  * Returns 1 for a successful write.
 159  */
 160 static int eeprom_write(struct et131x_adapter *adapter, u32 addr, u8 data)
 161 {
 162         struct pci_dev *pdev = adapter->pdev;
 163         int index = 0;
 164         int retries;
 165         int err = 0;
 166         int i2c_wack = 0;
 167         int writeok = 0;
 168         u32 status;
 169         u32 val = 0;
 170
 171         /*
 172          * For an EEPROM, an I2C single byte write is defined as a START
 173          * condition followed by the device address, EEPROM address, one byte
 174          * of data and a STOP condition.  The STOP condition will trigger the
 175          * EEPROM's internally timed write cycle to the nonvolatile memory.
 176          * All inputs are disabled during this write cycle and the EEPROM will
 177          * not respond to any access until the internal write is complete.
 178          */
 179
 180         err = eeprom_wait_ready(pdev, NULL);
 181         if (err)
 182                 return err;
 183
 184          /*
 185          * 2. Write to the LBCIF Control Register:  bit 7=1, bit 6=1, bit 3=0,
 186          *    and bits 1:0 both =0.  Bit 5 should be set according to the
 187          *    type of EEPROM being accessed (1=two byte addressing, 0=one
 188          *    byte addressing).
 189          */
 190         if (pci_write_config_byte(pdev, LBCIF_CONTROL_REGISTER,
 191                         LBCIF_CONTROL_LBCIF_ENABLE | LBCIF_CONTROL_I2C_WRITE))
 192                 return -EIO;
 193
 194         i2c_wack = 1;
 195
 196         /* Prepare EEPROM address for Step 3 */
 197
 198         for (retries = 0; retries < MAX_NUM_WRITE_RETRIES; retries++) {
 199                 /* Write the address to the LBCIF Address Register */
 200                 if (pci_write_config_dword(pdev, LBCIF_ADDRESS_REGISTER, addr))
 201                         break;
 202                 /*
 203                  * Write the data to the LBCIF Data Register (the I2C write
 204                  * will begin).
 205                  */
 206                 if (pci_write_config_byte(pdev, LBCIF_DATA_REGISTER, data))
 207                         break;
 208                 /*
 209                  * Monitor bit 1:0 of the LBCIF Status Register.  When bits
 210                  * 1:0 are both equal to 1, the I2C write has completed and the
 211                  * internal write cycle of the EEPROM is about to start.
 212                  * (bits 1:0 = 01 is a legal state while waiting from both
 213                  * equal to 1, but bits 1:0 = 10 is invalid and implies that
 214                  * something is broken).
 215                  */
 216                 err = eeprom_wait_ready(pdev, &status);
 217                 if (err < 0)
 218                         return 0;
 219
 220                 /*
 221                  * Check bit 3 of the LBCIF Status Register.  If  equal to 1,
 222                  * an error has occurred.Don't break here if we are revision
 223                  * 1, this is so we do a blind write for load bug.
 224                  */
 225                 if ((status & LBCIF_STATUS_GENERAL_ERROR)
 226                         && adapter->pdev->revision == 0)
 227                         break;
 228
 229                 /*
 230                  * Check bit 2 of the LBCIF Status Register.  If equal to 1 an
 231                  * ACK error has occurred on the address phase of the write.
 232                  * This could be due to an actual hardware failure or the
 233                  * EEPROM may still be in its internal write cycle from a
 234                  * previous write. This write operation was ignored and must be
 235                   *repeated later.
 236                  */
 237                 if (status & LBCIF_STATUS_ACK_ERROR) {
 238                         /*
 239                          * This could be due to an actual hardware failure
 240                          * or the EEPROM may still be in its internal write
 241                          * cycle from a previous write. This write operation
 242                          * was ignored and must be repeated later.
 243                          */
 244                         udelay(10);
 245                         continue;
 246                 }
 247
 248                 writeok = 1;
 249                 break;
 250         }
 251
 252         /*
 253          * Set bit 6 of the LBCIF Control Register = 0.
 254          */
 255         udelay(10);
 256
 257         while (i2c_wack) {
 258                 if (pci_write_config_byte(pdev, LBCIF_CONTROL_REGISTER,
 259                         LBCIF_CONTROL_LBCIF_ENABLE))
 260                         writeok = 0;
 261
 262                 /* Do read until internal ACK_ERROR goes away meaning write
 263                  * completed
 264                  */
 265                 do {
 266                         pci_write_config_dword(pdev,
 267                                                LBCIF_ADDRESS_REGISTER,
 268                                                addr);
 269                         do {
 270                                 pci_read_config_dword(pdev,
 271                                         LBCIF_DATA_REGISTER, &val);
 272                         } while ((val & 0x00010000) == 0);
 273                 } while (val & 0x00040000);
 274
 275                 if ((val & 0xFF00) != 0xC000 || index == 10000)
 276                         break;
 277                 index++;
 278         }
 279         return writeok ? 0 : -EIO;
 280 }
 281
 282 /**
 283  * eeprom_read - Read a byte from the ET1310's EEPROM
 284  * @adapter: pointer to our private adapter structure
 285  * @addr: the address from which to read
 286  * @pdata: a pointer to a byte in which to store the value of the read
 287  * @eeprom_id: the ID of the EEPROM
 288  * @addrmode: how the EEPROM is to be accessed
 289  *
 290  * Returns 1 for a successful read
 291  */
 292 static int eeprom_read(struct et131x_adapter *adapter, u32 addr, u8 *pdata)
 293 {
 294         struct pci_dev *pdev = adapter->pdev;
 295         int err;
 296         u32 status;
 297
 298         /*
 299          * A single byte read is similar to the single byte write, with the
 300          * exception of the data flow:
 301          */
 302
 303         err = eeprom_wait_ready(pdev, NULL);
 304         if (err)
 305                 return err;
 306         /*
 307          * Write to the LBCIF Control Register:  bit 7=1, bit 6=0, bit 3=0,
 308          * and bits 1:0 both =0.  Bit 5 should be set according to the type
 309          * of EEPROM being accessed (1=two byte addressing, 0=one byte
 310          * addressing).
 311          */
 312         if (pci_write_config_byte(pdev, LBCIF_CONTROL_REGISTER,
 313                                   LBCIF_CONTROL_LBCIF_ENABLE))
 314                 return -EIO;
 315         /*
 316          * Write the address to the LBCIF Address Register (I2C read will
 317          * begin).
 318          */
 319         if (pci_write_config_dword(pdev, LBCIF_ADDRESS_REGISTER, addr))
 320                 return -EIO;
 321         /*
 322          * Monitor bit 0 of the LBCIF Status Register.  When = 1, I2C read
 323          * is complete. (if bit 1 =1 and bit 0 stays = 0, a hardware failure
 324          * has occurred).
 325          */
 326         err = eeprom_wait_ready(pdev, &status);
 327         if (err < 0)
 328                 return err;
 329         /*
 330          * Regardless of error status, read data byte from LBCIF Data
 331          * Register.
 332          */
 333         *pdata = err;
 334         /*
 335          * Check bit 2 of the LBCIF Status Register.  If = 1,
 336          * then an error has occurred.
 337          */
 338         return (status & LBCIF_STATUS_ACK_ERROR) ? -EIO : 0;
 339 }
 340
 341 int et131x_init_eeprom(struct et131x_adapter *adapter)
 342 {
 343         struct pci_dev *pdev = adapter->pdev;
 344         u8 eestatus;
 345
 346         /* We first need to check the EEPROM Status code located at offset
 347          * 0xB2 of config space
 348          */
 349         pci_read_config_byte(pdev, ET1310_PCI_EEPROM_STATUS,
 350                                       &eestatus);
 351
 352         /* THIS IS A WORKAROUND:
 353          * I need to call this function twice to get my card in a
 354          * LG M1 Express Dual running. I tried also a msleep before this
 355          * function, because I thougth there could be some time condidions
 356          * but it didn't work. Call the whole function twice also work.
 357          */
 358         if (pci_read_config_byte(pdev, ET1310_PCI_EEPROM_STATUS, &eestatus)) {
 359                 dev_err(&pdev->dev,
 360                        "Could not read PCI config space for EEPROM Status\n");
 361                 return -EIO;
 362         }
 363
 364         /* Determine if the error(s) we care about are present. If they are
 365          * present we need to fail.
 366          */
 367         if (eestatus & 0x4C) {
 368                 int write_failed = 0;
 369                 if (pdev->revision == 0x01) {
 370                         int     i;
 371                         static const u8 eedata[4] = { 0xFE, 0x13, 0x10, 0xFF };
 372
 373                         /* Re-write the first 4 bytes if we have an eeprom
 374                          * present and the revision id is 1, this fixes the
 375                          * corruption seen with 1310 B Silicon
 376                          */
 377                         for (i = 0; i < 3; i++)
 378                                 if (eeprom_write(adapter, i, eedata[i]) < 0)
 379                                         write_failed = 1;
 380                 }
 381                 if (pdev->revision  != 0x01 || write_failed) {
 382                         dev_err(&pdev->dev,
 383                             "Fatal EEPROM Status Error - 0x%04x\n", eestatus);
 384
 385                         /* This error could mean that there was an error
 386                          * reading the eeprom or that the eeprom doesn't exist.
 387                          * We will treat each case the same and not try to
 388                          * gather additional information that normally would
 389                          * come from the eeprom, like MAC Address
 390                          */
 391                         adapter->has_eeprom = 0;
 392                         return -EIO;
 393                 }
 394         }
 395         adapter->has_eeprom = 1;
 396
 397         /* Read the EEPROM for information regarding LED behavior. Refer to
 398          * ET1310_phy.c, et131x_xcvr_init(), for its use.
 399          */
 400         eeprom_read(adapter, 0x70, &adapter->eeprom_data[0]);
 401         eeprom_read(adapter, 0x71, &adapter->eeprom_data[1]);
 402
 403         if (adapter->eeprom_data[0] != 0xcd)
 404                 /* Disable all optional features */
 405                 adapter->eeprom_data[1] = 0x00;
 406
 407         return 0;
 408 }