3 * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
5 * Copyright © 2005 Agere Systems Inc.
9 * Copyright (c) 2011 Mark Einon <mark.einon@gmail.com>
11 *------------------------------------------------------------------------------
13 * et131x_isr.c - File which contains the ISR, ISR handler, and related routines
14 * for processing interrupts from the device.
16 *------------------------------------------------------------------------------
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21 * which you should read carefully before using the software. Using this
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25 * Copyright © 2005 Agere Systems Inc.
26 * All rights reserved.
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61 #include "et131x_defs.h"
63 #include <linux/init.h>
64 #include <linux/module.h>
65 #include <linux/types.h>
66 #include <linux/kernel.h>
68 #include <linux/sched.h>
69 #include <linux/ptrace.h>
70 #include <linux/ctype.h>
71 #include <linux/string.h>
72 #include <linux/timer.h>
73 #include <linux/interrupt.h>
75 #include <linux/delay.h>
77 #include <linux/bitops.h>
78 #include <linux/pci.h>
79 #include <asm/system.h>
81 #include <linux/netdevice.h>
82 #include <linux/etherdevice.h>
83 #include <linux/skbuff.h>
84 #include <linux/if_arp.h>
85 #include <linux/ioport.h>
87 #include "et1310_phy.h"
88 #include "et131x_adapter.h"
92 * For interrupts, normal running is:
93 * rxdma_xfr_done, phy_interrupt, mac_stat_interrupt,
94 * watchdog_interrupt & txdma_xfer_done
96 * In both cases, when flow control is enabled for either Tx or bi-direction,
97 * we additional enable rx_fbr0_low and rx_fbr1_low, so we know when the
98 * buffer rings are running low.
100 #define INT_MASK_DISABLE 0xffffffff
102 /* NOTE: Masking out MAC_STAT Interrupt for now...
103 * #define INT_MASK_ENABLE 0xfff6bf17
104 * #define INT_MASK_ENABLE_NO_FLOW 0xfff6bfd7
106 #define INT_MASK_ENABLE 0xfffebf17
107 #define INT_MASK_ENABLE_NO_FLOW 0xfffebfd7
111 * et131x_enable_interrupts - enable interrupt
112 * @adapter: et131x device
114 * Enable the appropriate interrupts on the ET131x according to our
118 void et131x_enable_interrupts(struct et131x_adapter
*adapter
)
122 /* Enable all global interrupts */
123 if (adapter
->flowcontrol
== FLOW_TXONLY
||
124 adapter
->flowcontrol
== FLOW_BOTH
)
125 mask
= INT_MASK_ENABLE
;
127 mask
= INT_MASK_ENABLE_NO_FLOW
;
129 writel(mask
, &adapter
->regs
->global
.int_mask
);
133 * et131x_disable_interrupts - interrupt disable
134 * @adapter: et131x device
136 * Block all interrupts from the et131x device at the device itself
139 void et131x_disable_interrupts(struct et131x_adapter
*adapter
)
141 /* Disable all global interrupts */
142 writel(INT_MASK_DISABLE
, &adapter
->regs
->global
.int_mask
);
147 * et131x_isr - The Interrupt Service Routine for the driver.
148 * @irq: the IRQ on which the interrupt was received.
149 * @dev_id: device-specific info (here a pointer to a net_device struct)
151 * Returns a value indicating if the interrupt was handled.
154 irqreturn_t
et131x_isr(int irq
, void *dev_id
)
157 struct net_device
*netdev
= (struct net_device
*)dev_id
;
158 struct et131x_adapter
*adapter
= NULL
;
161 if (!netif_device_present(netdev
)) {
166 adapter
= netdev_priv(netdev
);
168 /* If the adapter is in low power state, then it should not
169 * recognize any interrupt
172 /* Disable Device Interrupts */
173 et131x_disable_interrupts(adapter
);
175 /* Get a copy of the value in the interrupt status register
176 * so we can process the interrupting section
178 status
= readl(&adapter
->regs
->global
.int_status
);
180 if (adapter
->flowcontrol
== FLOW_TXONLY
||
181 adapter
->flowcontrol
== FLOW_BOTH
) {
182 status
&= ~INT_MASK_ENABLE
;
184 status
&= ~INT_MASK_ENABLE_NO_FLOW
;
187 /* Make sure this is our interrupt */
190 et131x_enable_interrupts(adapter
);
194 /* This is our interrupt, so process accordingly */
196 if (status
& ET_INTR_WATCHDOG
) {
197 struct tcb
*tcb
= adapter
->tx_ring
.send_head
;
200 if (++tcb
->stale
> 1)
201 status
|= ET_INTR_TXDMA_ISR
;
203 if (adapter
->rx_ring
.unfinished_receives
)
204 status
|= ET_INTR_RXDMA_XFR_DONE
;
205 else if (tcb
== NULL
)
206 writel(0, &adapter
->regs
->global
.watchdog_timer
);
208 status
&= ~ET_INTR_WATCHDOG
;
212 /* This interrupt has in some way been "handled" by
213 * the ISR. Either it was a spurious Rx interrupt, or
214 * it was a Tx interrupt that has been filtered by
217 et131x_enable_interrupts(adapter
);
221 /* We need to save the interrupt status value for use in our
222 * DPC. We will clear the software copy of that in that
225 adapter
->stats
.interrupt_status
= status
;
227 /* Schedule the ISR handler as a bottom-half task in the
228 * kernel's tq_immediate queue, and mark the queue for
231 schedule_work(&adapter
->task
);
233 return IRQ_RETVAL(handled
);
237 * et131x_isr_handler - The ISR handler
238 * @p_adapter, a pointer to the device's private adapter structure
240 * scheduled to run in a deferred context by the ISR. This is where the ISR's
241 * work actually gets done.
243 void et131x_isr_handler(struct work_struct
*work
)
245 struct et131x_adapter
*adapter
=
246 container_of(work
, struct et131x_adapter
, task
);
247 u32 status
= adapter
->stats
.interrupt_status
;
248 struct address_map __iomem
*iomem
= adapter
->regs
;
251 * These first two are by far the most common. Once handled, we clear
252 * their two bits in the status word. If the word is now zero, we
255 /* Handle all the completed Transmit interrupts */
256 if (status
& ET_INTR_TXDMA_ISR
)
257 et131x_handle_send_interrupt(adapter
);
259 /* Handle all the completed Receives interrupts */
260 if (status
& ET_INTR_RXDMA_XFR_DONE
)
261 et131x_handle_recv_interrupt(adapter
);
263 status
&= 0xffffffd7;
266 /* Handle the TXDMA Error interrupt */
267 if (status
& ET_INTR_TXDMA_ERR
) {
270 /* Following read also clears the register (COR) */
271 txdma_err
= readl(&iomem
->txdma
.tx_dma_error
);
273 dev_warn(&adapter
->pdev
->dev
,
274 "TXDMA_ERR interrupt, error = %d\n",
278 /* Handle Free Buffer Ring 0 and 1 Low interrupt */
280 (ET_INTR_RXDMA_FB_R0_LOW
| ET_INTR_RXDMA_FB_R1_LOW
)) {
282 * This indicates the number of unused buffers in
283 * RXDMA free buffer ring 0 is <= the limit you
284 * programmed. Free buffer resources need to be
285 * returned. Free buffers are consumed as packets
286 * are passed from the network to the host. The host
287 * becomes aware of the packets from the contents of
288 * the packet status ring. This ring is queried when
289 * the packet done interrupt occurs. Packets are then
290 * passed to the OS. When the OS is done with the
291 * packets the resources can be returned to the
292 * ET1310 for re-use. This interrupt is one method of
293 * returning resources.
296 /* If the user has flow control on, then we will
297 * send a pause packet, otherwise just exit
299 if (adapter
->flowcontrol
== FLOW_TXONLY
||
300 adapter
->flowcontrol
== FLOW_BOTH
) {
303 /* Tell the device to send a pause packet via
304 * the back pressure register (bp req and
307 pm_csr
= readl(&iomem
->global
.pm_csr
);
308 if (!et1310_in_phy_coma(adapter
))
309 writel(3, &iomem
->txmac
.bp_ctrl
);
313 /* Handle Packet Status Ring Low Interrupt */
314 if (status
& ET_INTR_RXDMA_STAT_LOW
) {
317 * Same idea as with the two Free Buffer Rings.
318 * Packets going from the network to the host each
319 * consume a free buffer resource and a packet status
320 * resource. These resoures are passed to the OS.
321 * When the OS is done with the resources, they need
322 * to be returned to the ET1310. This is one method
323 * of returning the resources.
327 /* Handle RXDMA Error Interrupt */
328 if (status
& ET_INTR_RXDMA_ERR
) {
330 * The rxdma_error interrupt is sent when a time-out
331 * on a request issued by the JAGCore has occurred or
332 * a completion is returned with an un-successful
333 * status. In both cases the request is considered
334 * complete. The JAGCore will automatically re-try the
335 * request in question. Normally information on events
336 * like these are sent to the host using the "Advanced
337 * Error Reporting" capability. This interrupt is
338 * another way of getting similar information. The
339 * only thing required is to clear the interrupt by
340 * reading the ISR in the global resources. The
341 * JAGCore will do a re-try on the request. Normally
342 * you should never see this interrupt. If you start
343 * to see this interrupt occurring frequently then
344 * something bad has occurred. A reset might be the
349 dev_warn(&adapter
->pdev
->dev
,
350 "RxDMA_ERR interrupt, error %x\n",
351 readl(&iomem
->txmac
.tx_test
));
354 /* Handle the Wake on LAN Event */
355 if (status
& ET_INTR_WOL
) {
357 * This is a secondary interrupt for wake on LAN.
358 * The driver should never see this, if it does,
359 * something serious is wrong. We will TRAP the
360 * message when we are in DBG mode, otherwise we
363 dev_err(&adapter
->pdev
->dev
, "WAKE_ON_LAN interrupt\n");
366 /* Let's move on to the TxMac */
367 if (status
& ET_INTR_TXMAC
) {
368 u32 err
= readl(&iomem
->txmac
.err
);
371 * When any of the errors occur and TXMAC generates
372 * an interrupt to report these errors, it usually
373 * means that TXMAC has detected an error in the data
374 * stream retrieved from the on-chip Tx Q. All of
375 * these errors are catastrophic and TXMAC won't be
376 * able to recover data when these errors occur. In
377 * a nutshell, the whole Tx path will have to be reset
378 * and re-configured afterwards.
380 dev_warn(&adapter
->pdev
->dev
,
381 "TXMAC interrupt, error 0x%08x\n",
384 /* If we are debugging, we want to see this error,
385 * otherwise we just want the device to be reset and
390 /* Handle RXMAC Interrupt */
391 if (status
& ET_INTR_RXMAC
) {
393 * These interrupts are catastrophic to the device,
394 * what we need to do is disable the interrupts and
395 * set the flag to cause us to reset so we can solve
398 /* MP_SET_FLAG( adapter,
399 fMP_ADAPTER_HARDWARE_ERROR); */
401 dev_warn(&adapter
->pdev
->dev
,
402 "RXMAC interrupt, error 0x%08x. Requesting reset\n",
403 readl(&iomem
->rxmac
.err_reg
));
405 dev_warn(&adapter
->pdev
->dev
,
406 "Enable 0x%08x, Diag 0x%08x\n",
407 readl(&iomem
->rxmac
.ctrl
),
408 readl(&iomem
->rxmac
.rxq_diag
));
411 * If we are debugging, we want to see this error,
412 * otherwise we just want the device to be reset and
417 /* Handle MAC_STAT Interrupt */
418 if (status
& ET_INTR_MAC_STAT
) {
420 * This means at least one of the un-masked counters
421 * in the MAC_STAT block has rolled over. Use this
422 * to maintain the top, software managed bits of the
425 et1310_handle_macstat_interrupt(adapter
);
428 /* Handle SLV Timeout Interrupt */
429 if (status
& ET_INTR_SLV_TIMEOUT
) {
431 * This means a timeout has occurred on a read or
432 * write request to one of the JAGCore registers. The
433 * Global Resources block has terminated the request
434 * and on a read request, returned a "fake" value.
435 * The most likely reasons are: Bad Address or the
436 * addressed module is in a power-down state and
441 et131x_enable_interrupts(adapter
);