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ASoC: tlv312aic23: unbreak resume
[zen-stable.git] / drivers / gpu / drm / i915 / i915_dma.c
blobddfe3d902b2a3a5d908b0c7664a4348f94ce3988
1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
2 */
3 /*
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 */
28
29 #include "drmP.h"
30 #include "drm.h"
31 #include "drm_crtc_helper.h"
32 #include "drm_fb_helper.h"
33 #include "intel_drv.h"
34 #include "i915_drm.h"
35 #include "i915_drv.h"
36 #include "i915_trace.h"
37 #include "../../../platform/x86/intel_ips.h"
38 #include <linux/pci.h>
39 #include <linux/vgaarb.h>
40 #include <linux/acpi.h>
41 #include <linux/pnp.h>
42 #include <linux/vga_switcheroo.h>
43 #include <linux/slab.h>
44 #include <linux/module.h>
45 #include <acpi/video.h>
46
47 static void i915_write_hws_pga(struct drm_device *dev)
48 {
49 drm_i915_private_t *dev_priv = dev->dev_private;
50 u32 addr;
51
52 addr = dev_priv->status_page_dmah->busaddr;
53 if (INTEL_INFO(dev)->gen >= 4)
54 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
55 I915_WRITE(HWS_PGA, addr);
56 }
57
58 /**
59 * Sets up the hardware status page for devices that need a physical address
60 * in the register.
61 */
62 static int i915_init_phys_hws(struct drm_device *dev)
63 {
64 drm_i915_private_t *dev_priv = dev->dev_private;
65
66 /* Program Hardware Status Page */
67 dev_priv->status_page_dmah =
68 drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE);
69
70 if (!dev_priv->status_page_dmah) {
71 DRM_ERROR("Can not allocate hardware status page\n");
72 return -ENOMEM;
73 }
74
75 memset_io((void __force __iomem *)dev_priv->status_page_dmah->vaddr,
76 0, PAGE_SIZE);
77
78 i915_write_hws_pga(dev);
79
80 DRM_DEBUG_DRIVER("Enabled hardware status page\n");
81 return 0;
82 }
83
84 /**
85 * Frees the hardware status page, whether it's a physical address or a virtual
86 * address set up by the X Server.
87 */
88 static void i915_free_hws(struct drm_device *dev)
89 {
90 drm_i915_private_t *dev_priv = dev->dev_private;
91 struct intel_ring_buffer *ring = LP_RING(dev_priv);
92
93 if (dev_priv->status_page_dmah) {
94 drm_pci_free(dev, dev_priv->status_page_dmah);
95 dev_priv->status_page_dmah = NULL;
96 }
97
98 if (ring->status_page.gfx_addr) {
99 ring->status_page.gfx_addr = 0;
100 drm_core_ioremapfree(&dev_priv->hws_map, dev);
101 }
102
103 /* Need to rewrite hardware status page */
104 I915_WRITE(HWS_PGA, 0x1ffff000);
105 }
106
107 void i915_kernel_lost_context(struct drm_device * dev)
108 {
109 drm_i915_private_t *dev_priv = dev->dev_private;
110 struct drm_i915_master_private *master_priv;
111 struct intel_ring_buffer *ring = LP_RING(dev_priv);
112
113 /*
114 * We should never lose context on the ring with modesetting
115 * as we don't expose it to userspace
116 */
117 if (drm_core_check_feature(dev, DRIVER_MODESET))
118 return;
119
120 ring->head = I915_READ_HEAD(ring) & HEAD_ADDR;
121 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
122 ring->space = ring->head - (ring->tail + 8);
123 if (ring->space < 0)
124 ring->space += ring->size;
125
126 if (!dev->primary->master)
127 return;
128
129 master_priv = dev->primary->master->driver_priv;
130 if (ring->head == ring->tail && master_priv->sarea_priv)
131 master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
132 }
133
134 static int i915_dma_cleanup(struct drm_device * dev)
135 {
136 drm_i915_private_t *dev_priv = dev->dev_private;
137 int i;
138
139 /* Make sure interrupts are disabled here because the uninstall ioctl
140 * may not have been called from userspace and after dev_private
141 * is freed, it's too late.
142 */
143 if (dev->irq_enabled)
144 drm_irq_uninstall(dev);
145
146 mutex_lock(&dev->struct_mutex);
147 for (i = 0; i < I915_NUM_RINGS; i++)
148 intel_cleanup_ring_buffer(&dev_priv->ring[i]);
149 mutex_unlock(&dev->struct_mutex);
150
151 /* Clear the HWS virtual address at teardown */
152 if (I915_NEED_GFX_HWS(dev))
153 i915_free_hws(dev);
154
155 return 0;
156 }
157
158 static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
159 {
160 drm_i915_private_t *dev_priv = dev->dev_private;
161 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
162 int ret;
163
164 master_priv->sarea = drm_getsarea(dev);
165 if (master_priv->sarea) {
166 master_priv->sarea_priv = (drm_i915_sarea_t *)
167 ((u8 *)master_priv->sarea->handle + init->sarea_priv_offset);
168 } else {
169 DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n");
170 }
171
172 if (init->ring_size != 0) {
173 if (LP_RING(dev_priv)->obj != NULL) {
174 i915_dma_cleanup(dev);
175 DRM_ERROR("Client tried to initialize ringbuffer in "
176 "GEM mode\n");
177 return -EINVAL;
178 }
179
180 ret = intel_render_ring_init_dri(dev,
181 init->ring_start,
182 init->ring_size);
183 if (ret) {
184 i915_dma_cleanup(dev);
185 return ret;
186 }
187 }
188
189 dev_priv->cpp = init->cpp;
190 dev_priv->back_offset = init->back_offset;
191 dev_priv->front_offset = init->front_offset;
192 dev_priv->current_page = 0;
193 if (master_priv->sarea_priv)
194 master_priv->sarea_priv->pf_current_page = 0;
195
196 /* Allow hardware batchbuffers unless told otherwise.
197 */
198 dev_priv->allow_batchbuffer = 1;
199
200 return 0;
201 }
202
203 static int i915_dma_resume(struct drm_device * dev)
204 {
205 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
206 struct intel_ring_buffer *ring = LP_RING(dev_priv);
207
208 DRM_DEBUG_DRIVER("%s\n", __func__);
209
210 if (ring->map.handle == NULL) {
211 DRM_ERROR("can not ioremap virtual address for"
212 " ring buffer\n");
213 return -ENOMEM;
214 }
215
216 /* Program Hardware Status Page */
217 if (!ring->status_page.page_addr) {
218 DRM_ERROR("Can not find hardware status page\n");
219 return -EINVAL;
220 }
221 DRM_DEBUG_DRIVER("hw status page @ %p\n",
222 ring->status_page.page_addr);
223 if (ring->status_page.gfx_addr != 0)
224 intel_ring_setup_status_page(ring);
225 else
226 i915_write_hws_pga(dev);
227
228 DRM_DEBUG_DRIVER("Enabled hardware status page\n");
229
230 return 0;
231 }
232
233 static int i915_dma_init(struct drm_device *dev, void *data,
234 struct drm_file *file_priv)
235 {
236 drm_i915_init_t *init = data;
237 int retcode = 0;
238
239 switch (init->func) {
240 case I915_INIT_DMA:
241 retcode = i915_initialize(dev, init);
242 break;
243 case I915_CLEANUP_DMA:
244 retcode = i915_dma_cleanup(dev);
245 break;
246 case I915_RESUME_DMA:
247 retcode = i915_dma_resume(dev);
248 break;
249 default:
250 retcode = -EINVAL;
251 break;
252 }
253
254 return retcode;
255 }
256
257 /* Implement basically the same security restrictions as hardware does
258 * for MI_BATCH_NON_SECURE. These can be made stricter at any time.
259 *
260 * Most of the calculations below involve calculating the size of a
261 * particular instruction. It's important to get the size right as
262 * that tells us where the next instruction to check is. Any illegal
263 * instruction detected will be given a size of zero, which is a
264 * signal to abort the rest of the buffer.
265 */
266 static int validate_cmd(int cmd)
267 {
268 switch (((cmd >> 29) & 0x7)) {
269 case 0x0:
270 switch ((cmd >> 23) & 0x3f) {
271 case 0x0:
272 return 1; /* MI_NOOP */
273 case 0x4:
274 return 1; /* MI_FLUSH */
275 default:
276 return 0; /* disallow everything else */
277 }
278 break;
279 case 0x1:
280 return 0; /* reserved */
281 case 0x2:
282 return (cmd & 0xff) + 2; /* 2d commands */
283 case 0x3:
284 if (((cmd >> 24) & 0x1f) <= 0x18)
285 return 1;
286
287 switch ((cmd >> 24) & 0x1f) {
288 case 0x1c:
289 return 1;
290 case 0x1d:
291 switch ((cmd >> 16) & 0xff) {
292 case 0x3:
293 return (cmd & 0x1f) + 2;
294 case 0x4:
295 return (cmd & 0xf) + 2;
296 default:
297 return (cmd & 0xffff) + 2;
298 }
299 case 0x1e:
300 if (cmd & (1 << 23))
301 return (cmd & 0xffff) + 1;
302 else
303 return 1;
304 case 0x1f:
305 if ((cmd & (1 << 23)) == 0) /* inline vertices */
306 return (cmd & 0x1ffff) + 2;
307 else if (cmd & (1 << 17)) /* indirect random */
308 if ((cmd & 0xffff) == 0)
309 return 0; /* unknown length, too hard */
310 else
311 return (((cmd & 0xffff) + 1) / 2) + 1;
312 else
313 return 2; /* indirect sequential */
314 default:
315 return 0;
316 }
317 default:
318 return 0;
319 }
320
321 return 0;
322 }
323
324 static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords)
325 {
326 drm_i915_private_t *dev_priv = dev->dev_private;
327 int i, ret;
328
329 if ((dwords+1) * sizeof(int) >= LP_RING(dev_priv)->size - 8)
330 return -EINVAL;
331
332 for (i = 0; i < dwords;) {
333 int sz = validate_cmd(buffer[i]);
334 if (sz == 0 || i + sz > dwords)
335 return -EINVAL;
336 i += sz;
337 }
338
339 ret = BEGIN_LP_RING((dwords+1)&~1);
340 if (ret)
341 return ret;
342
343 for (i = 0; i < dwords; i++)
344 OUT_RING(buffer[i]);
345 if (dwords & 1)
346 OUT_RING(0);
347
348 ADVANCE_LP_RING();
349
350 return 0;
351 }
352
353 int
354 i915_emit_box(struct drm_device *dev,
355 struct drm_clip_rect *box,
356 int DR1, int DR4)
357 {
358 struct drm_i915_private *dev_priv = dev->dev_private;
359 int ret;
360
361 if (box->y2 <= box->y1 || box->x2 <= box->x1 ||
362 box->y2 <= 0 || box->x2 <= 0) {
363 DRM_ERROR("Bad box %d,%d..%d,%d\n",
364 box->x1, box->y1, box->x2, box->y2);
365 return -EINVAL;
366 }
367
368 if (INTEL_INFO(dev)->gen >= 4) {
369 ret = BEGIN_LP_RING(4);
370 if (ret)
371 return ret;
372
373 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
374 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
375 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
376 OUT_RING(DR4);
377 } else {
378 ret = BEGIN_LP_RING(6);
379 if (ret)
380 return ret;
381
382 OUT_RING(GFX_OP_DRAWRECT_INFO);
383 OUT_RING(DR1);
384 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
385 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
386 OUT_RING(DR4);
387 OUT_RING(0);
388 }
389 ADVANCE_LP_RING();
390
391 return 0;
392 }
393
394 /* XXX: Emitting the counter should really be moved to part of the IRQ
395 * emit. For now, do it in both places:
396 */
397
398 static void i915_emit_breadcrumb(struct drm_device *dev)
399 {
400 drm_i915_private_t *dev_priv = dev->dev_private;
401 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
402
403 dev_priv->counter++;
404 if (dev_priv->counter > 0x7FFFFFFFUL)
405 dev_priv->counter = 0;
406 if (master_priv->sarea_priv)
407 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
408
409 if (BEGIN_LP_RING(4) == 0) {
410 OUT_RING(MI_STORE_DWORD_INDEX);
411 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
412 OUT_RING(dev_priv->counter);
413 OUT_RING(0);
414 ADVANCE_LP_RING();
415 }
416 }
417
418 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
419 drm_i915_cmdbuffer_t *cmd,
420 struct drm_clip_rect *cliprects,
421 void *cmdbuf)
422 {
423 int nbox = cmd->num_cliprects;
424 int i = 0, count, ret;
425
426 if (cmd->sz & 0x3) {
427 DRM_ERROR("alignment");
428 return -EINVAL;
429 }
430
431 i915_kernel_lost_context(dev);
432
433 count = nbox ? nbox : 1;
434
435 for (i = 0; i < count; i++) {
436 if (i < nbox) {
437 ret = i915_emit_box(dev, &cliprects[i],
438 cmd->DR1, cmd->DR4);
439 if (ret)
440 return ret;
441 }
442
443 ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);
444 if (ret)
445 return ret;
446 }
447
448 i915_emit_breadcrumb(dev);
449 return 0;
450 }
451
452 static int i915_dispatch_batchbuffer(struct drm_device * dev,
453 drm_i915_batchbuffer_t * batch,
454 struct drm_clip_rect *cliprects)
455 {
456 struct drm_i915_private *dev_priv = dev->dev_private;
457 int nbox = batch->num_cliprects;
458 int i, count, ret;
459
460 if ((batch->start | batch->used) & 0x7) {
461 DRM_ERROR("alignment");
462 return -EINVAL;
463 }
464
465 i915_kernel_lost_context(dev);
466
467 count = nbox ? nbox : 1;
468 for (i = 0; i < count; i++) {
469 if (i < nbox) {
470 ret = i915_emit_box(dev, &cliprects[i],
471 batch->DR1, batch->DR4);
472 if (ret)
473 return ret;
474 }
475
476 if (!IS_I830(dev) && !IS_845G(dev)) {
477 ret = BEGIN_LP_RING(2);
478 if (ret)
479 return ret;
480
481 if (INTEL_INFO(dev)->gen >= 4) {
482 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
483 OUT_RING(batch->start);
484 } else {
485 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
486 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
487 }
488 } else {
489 ret = BEGIN_LP_RING(4);
490 if (ret)
491 return ret;
492
493 OUT_RING(MI_BATCH_BUFFER);
494 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
495 OUT_RING(batch->start + batch->used - 4);
496 OUT_RING(0);
497 }
498 ADVANCE_LP_RING();
499 }
500
501
502 if (IS_G4X(dev) || IS_GEN5(dev)) {
503 if (BEGIN_LP_RING(2) == 0) {
504 OUT_RING(MI_FLUSH | MI_NO_WRITE_FLUSH | MI_INVALIDATE_ISP);
505 OUT_RING(MI_NOOP);
506 ADVANCE_LP_RING();
507 }
508 }
509
510 i915_emit_breadcrumb(dev);
511 return 0;
512 }
513
514 static int i915_dispatch_flip(struct drm_device * dev)
515 {
516 drm_i915_private_t *dev_priv = dev->dev_private;
517 struct drm_i915_master_private *master_priv =
518 dev->primary->master->driver_priv;
519 int ret;
520
521 if (!master_priv->sarea_priv)
522 return -EINVAL;
523
524 DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n",
525 __func__,
526 dev_priv->current_page,
527 master_priv->sarea_priv->pf_current_page);
528
529 i915_kernel_lost_context(dev);
530
531 ret = BEGIN_LP_RING(10);
532 if (ret)
533 return ret;
534
535 OUT_RING(MI_FLUSH | MI_READ_FLUSH);
536 OUT_RING(0);
537
538 OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
539 OUT_RING(0);
540 if (dev_priv->current_page == 0) {
541 OUT_RING(dev_priv->back_offset);
542 dev_priv->current_page = 1;
543 } else {
544 OUT_RING(dev_priv->front_offset);
545 dev_priv->current_page = 0;
546 }
547 OUT_RING(0);
548
549 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
550 OUT_RING(0);
551
552 ADVANCE_LP_RING();
553
554 master_priv->sarea_priv->last_enqueue = dev_priv->counter++;
555
556 if (BEGIN_LP_RING(4) == 0) {
557 OUT_RING(MI_STORE_DWORD_INDEX);
558 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
559 OUT_RING(dev_priv->counter);
560 OUT_RING(0);
561 ADVANCE_LP_RING();
562 }
563
564 master_priv->sarea_priv->pf_current_page = dev_priv->current_page;
565 return 0;
566 }
567
568 static int i915_quiescent(struct drm_device *dev)
569 {
570 struct intel_ring_buffer *ring = LP_RING(dev->dev_private);
571
572 i915_kernel_lost_context(dev);
573 return intel_wait_ring_idle(ring);
574 }
575
576 static int i915_flush_ioctl(struct drm_device *dev, void *data,
577 struct drm_file *file_priv)
578 {
579 int ret;
580
581 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
582
583 mutex_lock(&dev->struct_mutex);
584 ret = i915_quiescent(dev);
585 mutex_unlock(&dev->struct_mutex);
586
587 return ret;
588 }
589
590 static int i915_batchbuffer(struct drm_device *dev, void *data,
591 struct drm_file *file_priv)
592 {
593 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
594 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
595 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
596 master_priv->sarea_priv;
597 drm_i915_batchbuffer_t *batch = data;
598 int ret;
599 struct drm_clip_rect *cliprects = NULL;
600
601 if (!dev_priv->allow_batchbuffer) {
602 DRM_ERROR("Batchbuffer ioctl disabled\n");
603 return -EINVAL;
604 }
605
606 DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n",
607 batch->start, batch->used, batch->num_cliprects);
608
609 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
610
611 if (batch->num_cliprects < 0)
612 return -EINVAL;
613
614 if (batch->num_cliprects) {
615 cliprects = kcalloc(batch->num_cliprects,
616 sizeof(struct drm_clip_rect),
617 GFP_KERNEL);
618 if (cliprects == NULL)
619 return -ENOMEM;
620
621 ret = copy_from_user(cliprects, batch->cliprects,
622 batch->num_cliprects *
623 sizeof(struct drm_clip_rect));
624 if (ret != 0) {
625 ret = -EFAULT;
626 goto fail_free;
627 }
628 }
629
630 mutex_lock(&dev->struct_mutex);
631 ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
632 mutex_unlock(&dev->struct_mutex);
633
634 if (sarea_priv)
635 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
636
637 fail_free:
638 kfree(cliprects);
639
640 return ret;
641 }
642
643 static int i915_cmdbuffer(struct drm_device *dev, void *data,
644 struct drm_file *file_priv)
645 {
646 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
647 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
648 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
649 master_priv->sarea_priv;
650 drm_i915_cmdbuffer_t *cmdbuf = data;
651 struct drm_clip_rect *cliprects = NULL;
652 void *batch_data;
653 int ret;
654
655 DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
656 cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
657
658 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
659
660 if (cmdbuf->num_cliprects < 0)
661 return -EINVAL;
662
663 batch_data = kmalloc(cmdbuf->sz, GFP_KERNEL);
664 if (batch_data == NULL)
665 return -ENOMEM;
666
667 ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz);
668 if (ret != 0) {
669 ret = -EFAULT;
670 goto fail_batch_free;
671 }
672
673 if (cmdbuf->num_cliprects) {
674 cliprects = kcalloc(cmdbuf->num_cliprects,
675 sizeof(struct drm_clip_rect), GFP_KERNEL);
676 if (cliprects == NULL) {
677 ret = -ENOMEM;
678 goto fail_batch_free;
679 }
680
681 ret = copy_from_user(cliprects, cmdbuf->cliprects,
682 cmdbuf->num_cliprects *
683 sizeof(struct drm_clip_rect));
684 if (ret != 0) {
685 ret = -EFAULT;
686 goto fail_clip_free;
687 }
688 }
689
690 mutex_lock(&dev->struct_mutex);
691 ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
692 mutex_unlock(&dev->struct_mutex);
693 if (ret) {
694 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
695 goto fail_clip_free;
696 }
697
698 if (sarea_priv)
699 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
700
701 fail_clip_free:
702 kfree(cliprects);
703 fail_batch_free:
704 kfree(batch_data);
705
706 return ret;
707 }
708
709 static int i915_flip_bufs(struct drm_device *dev, void *data,
710 struct drm_file *file_priv)
711 {
712 int ret;
713
714 DRM_DEBUG_DRIVER("%s\n", __func__);
715
716 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
717
718 mutex_lock(&dev->struct_mutex);
719 ret = i915_dispatch_flip(dev);
720 mutex_unlock(&dev->struct_mutex);
721
722 return ret;
723 }
724
725 static int i915_getparam(struct drm_device *dev, void *data,
726 struct drm_file *file_priv)
727 {
728 drm_i915_private_t *dev_priv = dev->dev_private;
729 drm_i915_getparam_t *param = data;
730 int value;
731
732 if (!dev_priv) {
733 DRM_ERROR("called with no initialization\n");
734 return -EINVAL;
735 }
736
737 switch (param->param) {
738 case I915_PARAM_IRQ_ACTIVE:
739 value = dev->pdev->irq ? 1 : 0;
740 break;
741 case I915_PARAM_ALLOW_BATCHBUFFER:
742 value = dev_priv->allow_batchbuffer ? 1 : 0;
743 break;
744 case I915_PARAM_LAST_DISPATCH:
745 value = READ_BREADCRUMB(dev_priv);
746 break;
747 case I915_PARAM_CHIPSET_ID:
748 value = dev->pci_device;
749 break;
750 case I915_PARAM_HAS_GEM:
751 value = dev_priv->has_gem;
752 break;
753 case I915_PARAM_NUM_FENCES_AVAIL:
754 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
755 break;
756 case I915_PARAM_HAS_OVERLAY:
757 value = dev_priv->overlay ? 1 : 0;
758 break;
759 case I915_PARAM_HAS_PAGEFLIPPING:
760 value = 1;
761 break;
762 case I915_PARAM_HAS_EXECBUF2:
763 /* depends on GEM */
764 value = dev_priv->has_gem;
765 break;
766 case I915_PARAM_HAS_BSD:
767 value = HAS_BSD(dev);
768 break;
769 case I915_PARAM_HAS_BLT:
770 value = HAS_BLT(dev);
771 break;
772 case I915_PARAM_HAS_RELAXED_FENCING:
773 value = 1;
774 break;
775 case I915_PARAM_HAS_COHERENT_RINGS:
776 value = 1;
777 break;
778 case I915_PARAM_HAS_EXEC_CONSTANTS:
779 value = INTEL_INFO(dev)->gen >= 4;
780 break;
781 case I915_PARAM_HAS_RELAXED_DELTA:
782 value = 1;
783 break;
784 case I915_PARAM_HAS_GEN7_SOL_RESET:
785 value = 1;
786 break;
787 default:
788 DRM_DEBUG_DRIVER("Unknown parameter %d\n",
789 param->param);
790 return -EINVAL;
791 }
792
793 if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
794 DRM_ERROR("DRM_COPY_TO_USER failed\n");
795 return -EFAULT;
796 }
797
798 return 0;
799 }
800
801 static int i915_setparam(struct drm_device *dev, void *data,
802 struct drm_file *file_priv)
803 {
804 drm_i915_private_t *dev_priv = dev->dev_private;
805 drm_i915_setparam_t *param = data;
806
807 if (!dev_priv) {
808 DRM_ERROR("called with no initialization\n");
809 return -EINVAL;
810 }
811
812 switch (param->param) {
813 case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
814 break;
815 case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
816 dev_priv->tex_lru_log_granularity = param->value;
817 break;
818 case I915_SETPARAM_ALLOW_BATCHBUFFER:
819 dev_priv->allow_batchbuffer = param->value;
820 break;
821 case I915_SETPARAM_NUM_USED_FENCES:
822 if (param->value > dev_priv->num_fence_regs ||
823 param->value < 0)
824 return -EINVAL;
825 /* Userspace can use first N regs */
826 dev_priv->fence_reg_start = param->value;
827 break;
828 default:
829 DRM_DEBUG_DRIVER("unknown parameter %d\n",
830 param->param);
831 return -EINVAL;
832 }
833
834 return 0;
835 }
836
837 static int i915_set_status_page(struct drm_device *dev, void *data,
838 struct drm_file *file_priv)
839 {
840 drm_i915_private_t *dev_priv = dev->dev_private;
841 drm_i915_hws_addr_t *hws = data;
842 struct intel_ring_buffer *ring = LP_RING(dev_priv);
843
844 if (!I915_NEED_GFX_HWS(dev))
845 return -EINVAL;
846
847 if (!dev_priv) {
848 DRM_ERROR("called with no initialization\n");
849 return -EINVAL;
850 }
851
852 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
853 WARN(1, "tried to set status page when mode setting active\n");
854 return 0;
855 }
856
857 DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr);
858
859 ring->status_page.gfx_addr = hws->addr & (0x1ffff<<12);
860
861 dev_priv->hws_map.offset = dev->agp->base + hws->addr;
862 dev_priv->hws_map.size = 4*1024;
863 dev_priv->hws_map.type = 0;
864 dev_priv->hws_map.flags = 0;
865 dev_priv->hws_map.mtrr = 0;
866
867 drm_core_ioremap_wc(&dev_priv->hws_map, dev);
868 if (dev_priv->hws_map.handle == NULL) {
869 i915_dma_cleanup(dev);
870 ring->status_page.gfx_addr = 0;
871 DRM_ERROR("can not ioremap virtual address for"
872 " G33 hw status page\n");
873 return -ENOMEM;
874 }
875 ring->status_page.page_addr =
876 (void __force __iomem *)dev_priv->hws_map.handle;
877 memset_io(ring->status_page.page_addr, 0, PAGE_SIZE);
878 I915_WRITE(HWS_PGA, ring->status_page.gfx_addr);
879
880 DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n",
881 ring->status_page.gfx_addr);
882 DRM_DEBUG_DRIVER("load hws at %p\n",
883 ring->status_page.page_addr);
884 return 0;
885 }
886
887 static int i915_get_bridge_dev(struct drm_device *dev)
888 {
889 struct drm_i915_private *dev_priv = dev->dev_private;
890
891 dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
892 if (!dev_priv->bridge_dev) {
893 DRM_ERROR("bridge device not found\n");
894 return -1;
895 }
896 return 0;
897 }
898
899 #define MCHBAR_I915 0x44
900 #define MCHBAR_I965 0x48
901 #define MCHBAR_SIZE (4*4096)
902
903 #define DEVEN_REG 0x54
904 #define DEVEN_MCHBAR_EN (1 << 28)
905
906 /* Allocate space for the MCH regs if needed, return nonzero on error */
907 static int
908 intel_alloc_mchbar_resource(struct drm_device *dev)
909 {
910 drm_i915_private_t *dev_priv = dev->dev_private;
911 int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
912 u32 temp_lo, temp_hi = 0;
913 u64 mchbar_addr;
914 int ret;
915
916 if (INTEL_INFO(dev)->gen >= 4)
917 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
918 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
919 mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
920
921 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
922 #ifdef CONFIG_PNP
923 if (mchbar_addr &&
924 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
925 return 0;
926 #endif
927
928 /* Get some space for it */
929 dev_priv->mch_res.name = "i915 MCHBAR";
930 dev_priv->mch_res.flags = IORESOURCE_MEM;
931 ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
932 &dev_priv->mch_res,
933 MCHBAR_SIZE, MCHBAR_SIZE,
934 PCIBIOS_MIN_MEM,
935 0, pcibios_align_resource,
936 dev_priv->bridge_dev);
937 if (ret) {
938 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
939 dev_priv->mch_res.start = 0;
940 return ret;
941 }
942
943 if (INTEL_INFO(dev)->gen >= 4)
944 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
945 upper_32_bits(dev_priv->mch_res.start));
946
947 pci_write_config_dword(dev_priv->bridge_dev, reg,
948 lower_32_bits(dev_priv->mch_res.start));
949 return 0;
950 }
951
952 /* Setup MCHBAR if possible, return true if we should disable it again */
953 static void
954 intel_setup_mchbar(struct drm_device *dev)
955 {
956 drm_i915_private_t *dev_priv = dev->dev_private;
957 int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
958 u32 temp;
959 bool enabled;
960
961 dev_priv->mchbar_need_disable = false;
962
963 if (IS_I915G(dev) || IS_I915GM(dev)) {
964 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
965 enabled = !!(temp & DEVEN_MCHBAR_EN);
966 } else {
967 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
968 enabled = temp & 1;
969 }
970
971 /* If it's already enabled, don't have to do anything */
972 if (enabled)
973 return;
974
975 if (intel_alloc_mchbar_resource(dev))
976 return;
977
978 dev_priv->mchbar_need_disable = true;
979
980 /* Space is allocated or reserved, so enable it. */
981 if (IS_I915G(dev) || IS_I915GM(dev)) {
982 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
983 temp | DEVEN_MCHBAR_EN);
984 } else {
985 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
986 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
987 }
988 }
989
990 static void
991 intel_teardown_mchbar(struct drm_device *dev)
992 {
993 drm_i915_private_t *dev_priv = dev->dev_private;
994 int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
995 u32 temp;
996
997 if (dev_priv->mchbar_need_disable) {
998 if (IS_I915G(dev) || IS_I915GM(dev)) {
999 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
1000 temp &= ~DEVEN_MCHBAR_EN;
1001 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp);
1002 } else {
1003 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1004 temp &= ~1;
1005 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp);
1006 }
1007 }
1008
1009 if (dev_priv->mch_res.start)
1010 release_resource(&dev_priv->mch_res);
1011 }
1012
1013 #define PTE_ADDRESS_MASK 0xfffff000
1014 #define PTE_ADDRESS_MASK_HIGH 0x000000f0 /* i915+ */
1015 #define PTE_MAPPING_TYPE_UNCACHED (0 << 1)
1016 #define PTE_MAPPING_TYPE_DCACHE (1 << 1) /* i830 only */
1017 #define PTE_MAPPING_TYPE_CACHED (3 << 1)
1018 #define PTE_MAPPING_TYPE_MASK (3 << 1)
1019 #define PTE_VALID (1 << 0)
1020
1021 /**
1022 * i915_stolen_to_phys - take an offset into stolen memory and turn it into
1023 * a physical one
1024 * @dev: drm device
1025 * @offset: address to translate
1026 *
1027 * Some chip functions require allocations from stolen space and need the
1028 * physical address of the memory in question.
1029 */
1030 static unsigned long i915_stolen_to_phys(struct drm_device *dev, u32 offset)
1031 {
1032 struct drm_i915_private *dev_priv = dev->dev_private;
1033 struct pci_dev *pdev = dev_priv->bridge_dev;
1034 u32 base;
1035
1036 #if 0
1037 /* On the machines I have tested the Graphics Base of Stolen Memory
1038 * is unreliable, so compute the base by subtracting the stolen memory
1039 * from the Top of Low Usable DRAM which is where the BIOS places
1040 * the graphics stolen memory.
1041 */
1042 if (INTEL_INFO(dev)->gen > 3 || IS_G33(dev)) {
1043 /* top 32bits are reserved = 0 */
1044 pci_read_config_dword(pdev, 0xA4, &base);
1045 } else {
1046 /* XXX presume 8xx is the same as i915 */
1047 pci_bus_read_config_dword(pdev->bus, 2, 0x5C, &base);
1048 }
1049 #else
1050 if (INTEL_INFO(dev)->gen > 3 || IS_G33(dev)) {
1051 u16 val;
1052 pci_read_config_word(pdev, 0xb0, &val);
1053 base = val >> 4 << 20;
1054 } else {
1055 u8 val;
1056 pci_read_config_byte(pdev, 0x9c, &val);
1057 base = val >> 3 << 27;
1058 }
1059 base -= dev_priv->mm.gtt->stolen_size;
1060 #endif
1061
1062 return base + offset;
1063 }
1064
1065 static void i915_warn_stolen(struct drm_device *dev)
1066 {
1067 DRM_ERROR("not enough stolen space for compressed buffer, disabling\n");
1068 DRM_ERROR("hint: you may be able to increase stolen memory size in the BIOS to avoid this\n");
1069 }
1070
1071 static void i915_setup_compression(struct drm_device *dev, int size)
1072 {
1073 struct drm_i915_private *dev_priv = dev->dev_private;
1074 struct drm_mm_node *compressed_fb, *uninitialized_var(compressed_llb);
1075 unsigned long cfb_base;
1076 unsigned long ll_base = 0;
1077
1078 /* Just in case the BIOS is doing something questionable. */
1079 intel_disable_fbc(dev);
1080
1081 compressed_fb = drm_mm_search_free(&dev_priv->mm.stolen, size, 4096, 0);
1082 if (compressed_fb)
1083 compressed_fb = drm_mm_get_block(compressed_fb, size, 4096);
1084 if (!compressed_fb)
1085 goto err;
1086
1087 cfb_base = i915_stolen_to_phys(dev, compressed_fb->start);
1088 if (!cfb_base)
1089 goto err_fb;
1090
1091 if (!(IS_GM45(dev) || HAS_PCH_SPLIT(dev))) {
1092 compressed_llb = drm_mm_search_free(&dev_priv->mm.stolen,
1093 4096, 4096, 0);
1094 if (compressed_llb)
1095 compressed_llb = drm_mm_get_block(compressed_llb,
1096 4096, 4096);
1097 if (!compressed_llb)
1098 goto err_fb;
1099
1100 ll_base = i915_stolen_to_phys(dev, compressed_llb->start);
1101 if (!ll_base)
1102 goto err_llb;
1103 }
1104
1105 dev_priv->cfb_size = size;
1106
1107 dev_priv->compressed_fb = compressed_fb;
1108 if (HAS_PCH_SPLIT(dev))
1109 I915_WRITE(ILK_DPFC_CB_BASE, compressed_fb->start);
1110 else if (IS_GM45(dev)) {
1111 I915_WRITE(DPFC_CB_BASE, compressed_fb->start);
1112 } else {
1113 I915_WRITE(FBC_CFB_BASE, cfb_base);
1114 I915_WRITE(FBC_LL_BASE, ll_base);
1115 dev_priv->compressed_llb = compressed_llb;
1116 }
1117
1118 DRM_DEBUG_KMS("FBC base 0x%08lx, ll base 0x%08lx, size %dM\n",
1119 cfb_base, ll_base, size >> 20);
1120 return;
1121
1122 err_llb:
1123 drm_mm_put_block(compressed_llb);
1124 err_fb:
1125 drm_mm_put_block(compressed_fb);
1126 err:
1127 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1128 i915_warn_stolen(dev);
1129 }
1130
1131 static void i915_cleanup_compression(struct drm_device *dev)
1132 {
1133 struct drm_i915_private *dev_priv = dev->dev_private;
1134
1135 drm_mm_put_block(dev_priv->compressed_fb);
1136 if (dev_priv->compressed_llb)
1137 drm_mm_put_block(dev_priv->compressed_llb);
1138 }
1139
1140 /* true = enable decode, false = disable decoder */
1141 static unsigned int i915_vga_set_decode(void *cookie, bool state)
1142 {
1143 struct drm_device *dev = cookie;
1144
1145 intel_modeset_vga_set_state(dev, state);
1146 if (state)
1147 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1148 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1149 else
1150 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1151 }
1152
1153 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1154 {
1155 struct drm_device *dev = pci_get_drvdata(pdev);
1156 pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
1157 if (state == VGA_SWITCHEROO_ON) {
1158 printk(KERN_INFO "i915: switched on\n");
1159 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1160 /* i915 resume handler doesn't set to D0 */
1161 pci_set_power_state(dev->pdev, PCI_D0);
1162 i915_resume(dev);
1163 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1164 } else {
1165 printk(KERN_ERR "i915: switched off\n");
1166 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1167 i915_suspend(dev, pmm);
1168 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1169 }
1170 }
1171
1172 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
1173 {
1174 struct drm_device *dev = pci_get_drvdata(pdev);
1175 bool can_switch;
1176
1177 spin_lock(&dev->count_lock);
1178 can_switch = (dev->open_count == 0);
1179 spin_unlock(&dev->count_lock);
1180 return can_switch;
1181 }
1182
1183 static int i915_load_gem_init(struct drm_device *dev)
1184 {
1185 struct drm_i915_private *dev_priv = dev->dev_private;
1186 unsigned long prealloc_size, gtt_size, mappable_size;
1187 int ret;
1188
1189 prealloc_size = dev_priv->mm.gtt->stolen_size;
1190 gtt_size = dev_priv->mm.gtt->gtt_total_entries << PAGE_SHIFT;
1191 mappable_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
1192
1193 /* Basic memrange allocator for stolen space */
1194 drm_mm_init(&dev_priv->mm.stolen, 0, prealloc_size);
1195
1196 /* Let GEM Manage all of the aperture.
1197 *
1198 * However, leave one page at the end still bound to the scratch page.
1199 * There are a number of places where the hardware apparently
1200 * prefetches past the end of the object, and we've seen multiple
1201 * hangs with the GPU head pointer stuck in a batchbuffer bound
1202 * at the last page of the aperture. One page should be enough to
1203 * keep any prefetching inside of the aperture.
1204 */
1205 i915_gem_do_init(dev, 0, mappable_size, gtt_size - PAGE_SIZE);
1206
1207 mutex_lock(&dev->struct_mutex);
1208 ret = i915_gem_init_ringbuffer(dev);
1209 mutex_unlock(&dev->struct_mutex);
1210 if (ret)
1211 return ret;
1212
1213 /* Try to set up FBC with a reasonable compressed buffer size */
1214 if (I915_HAS_FBC(dev) && i915_powersave) {
1215 int cfb_size;
1216
1217 /* Leave 1M for line length buffer & misc. */
1218
1219 /* Try to get a 32M buffer... */
1220 if (prealloc_size > (36*1024*1024))
1221 cfb_size = 32*1024*1024;
1222 else /* fall back to 7/8 of the stolen space */
1223 cfb_size = prealloc_size * 7 / 8;
1224 i915_setup_compression(dev, cfb_size);
1225 }
1226
1227 /* Allow hardware batchbuffers unless told otherwise. */
1228 dev_priv->allow_batchbuffer = 1;
1229 return 0;
1230 }
1231
1232 static int i915_load_modeset_init(struct drm_device *dev)
1233 {
1234 struct drm_i915_private *dev_priv = dev->dev_private;
1235 int ret;
1236
1237 ret = intel_parse_bios(dev);
1238 if (ret)
1239 DRM_INFO("failed to find VBIOS tables\n");
1240
1241 /* If we have > 1 VGA cards, then we need to arbitrate access
1242 * to the common VGA resources.
1243 *
1244 * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
1245 * then we do not take part in VGA arbitration and the
1246 * vga_client_register() fails with -ENODEV.
1247 */
1248 ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
1249 if (ret && ret != -ENODEV)
1250 goto out;
1251
1252 intel_register_dsm_handler();
1253
1254 ret = vga_switcheroo_register_client(dev->pdev,
1255 i915_switcheroo_set_state,
1256 NULL,
1257 i915_switcheroo_can_switch);
1258 if (ret)
1259 goto cleanup_vga_client;
1260
1261 /* IIR "flip pending" bit means done if this bit is set */
1262 if (IS_GEN3(dev) && (I915_READ(ECOSKPD) & ECO_FLIP_DONE))
1263 dev_priv->flip_pending_is_done = true;
1264
1265 intel_modeset_init(dev);
1266
1267 ret = i915_load_gem_init(dev);
1268 if (ret)
1269 goto cleanup_vga_switcheroo;
1270
1271 intel_modeset_gem_init(dev);
1272
1273 ret = drm_irq_install(dev);
1274 if (ret)
1275 goto cleanup_gem;
1276
1277 /* Always safe in the mode setting case. */
1278 /* FIXME: do pre/post-mode set stuff in core KMS code */
1279 dev->vblank_disable_allowed = 1;
1280
1281 ret = intel_fbdev_init(dev);
1282 if (ret)
1283 goto cleanup_irq;
1284
1285 drm_kms_helper_poll_init(dev);
1286
1287 /* We're off and running w/KMS */
1288 dev_priv->mm.suspended = 0;
1289
1290 return 0;
1291
1292 cleanup_irq:
1293 drm_irq_uninstall(dev);
1294 cleanup_gem:
1295 mutex_lock(&dev->struct_mutex);
1296 i915_gem_cleanup_ringbuffer(dev);
1297 mutex_unlock(&dev->struct_mutex);
1298 cleanup_vga_switcheroo:
1299 vga_switcheroo_unregister_client(dev->pdev);
1300 cleanup_vga_client:
1301 vga_client_register(dev->pdev, NULL, NULL, NULL);
1302 out:
1303 return ret;
1304 }
1305
1306 int i915_master_create(struct drm_device *dev, struct drm_master *master)
1307 {
1308 struct drm_i915_master_private *master_priv;
1309
1310 master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL);
1311 if (!master_priv)
1312 return -ENOMEM;
1313
1314 master->driver_priv = master_priv;
1315 return 0;
1316 }
1317
1318 void i915_master_destroy(struct drm_device *dev, struct drm_master *master)
1319 {
1320 struct drm_i915_master_private *master_priv = master->driver_priv;
1321
1322 if (!master_priv)
1323 return;
1324
1325 kfree(master_priv);
1326
1327 master->driver_priv = NULL;
1328 }
1329
1330 static void i915_pineview_get_mem_freq(struct drm_device *dev)
1331 {
1332 drm_i915_private_t *dev_priv = dev->dev_private;
1333 u32 tmp;
1334
1335 tmp = I915_READ(CLKCFG);
1336
1337 switch (tmp & CLKCFG_FSB_MASK) {
1338 case CLKCFG_FSB_533:
1339 dev_priv->fsb_freq = 533; /* 133*4 */
1340 break;
1341 case CLKCFG_FSB_800:
1342 dev_priv->fsb_freq = 800; /* 200*4 */
1343 break;
1344 case CLKCFG_FSB_667:
1345 dev_priv->fsb_freq = 667; /* 167*4 */
1346 break;
1347 case CLKCFG_FSB_400:
1348 dev_priv->fsb_freq = 400; /* 100*4 */
1349 break;
1350 }
1351
1352 switch (tmp & CLKCFG_MEM_MASK) {
1353 case CLKCFG_MEM_533:
1354 dev_priv->mem_freq = 533;
1355 break;
1356 case CLKCFG_MEM_667:
1357 dev_priv->mem_freq = 667;
1358 break;
1359 case CLKCFG_MEM_800:
1360 dev_priv->mem_freq = 800;
1361 break;
1362 }
1363
1364 /* detect pineview DDR3 setting */
1365 tmp = I915_READ(CSHRDDR3CTL);
1366 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
1367 }
1368
1369 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
1370 {
1371 drm_i915_private_t *dev_priv = dev->dev_private;
1372 u16 ddrpll, csipll;
1373
1374 ddrpll = I915_READ16(DDRMPLL1);
1375 csipll = I915_READ16(CSIPLL0);
1376
1377 switch (ddrpll & 0xff) {
1378 case 0xc:
1379 dev_priv->mem_freq = 800;
1380 break;
1381 case 0x10:
1382 dev_priv->mem_freq = 1066;
1383 break;
1384 case 0x14:
1385 dev_priv->mem_freq = 1333;
1386 break;
1387 case 0x18:
1388 dev_priv->mem_freq = 1600;
1389 break;
1390 default:
1391 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
1392 ddrpll & 0xff);
1393 dev_priv->mem_freq = 0;
1394 break;
1395 }
1396
1397 dev_priv->r_t = dev_priv->mem_freq;
1398
1399 switch (csipll & 0x3ff) {
1400 case 0x00c:
1401 dev_priv->fsb_freq = 3200;
1402 break;
1403 case 0x00e:
1404 dev_priv->fsb_freq = 3733;
1405 break;
1406 case 0x010:
1407 dev_priv->fsb_freq = 4266;
1408 break;
1409 case 0x012:
1410 dev_priv->fsb_freq = 4800;
1411 break;
1412 case 0x014:
1413 dev_priv->fsb_freq = 5333;
1414 break;
1415 case 0x016:
1416 dev_priv->fsb_freq = 5866;
1417 break;
1418 case 0x018:
1419 dev_priv->fsb_freq = 6400;
1420 break;
1421 default:
1422 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
1423 csipll & 0x3ff);
1424 dev_priv->fsb_freq = 0;
1425 break;
1426 }
1427
1428 if (dev_priv->fsb_freq == 3200) {
1429 dev_priv->c_m = 0;
1430 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
1431 dev_priv->c_m = 1;
1432 } else {
1433 dev_priv->c_m = 2;
1434 }
1435 }
1436
1437 static const struct cparams {
1438 u16 i;
1439 u16 t;
1440 u16 m;
1441 u16 c;
1442 } cparams[] = {
1443 { 1, 1333, 301, 28664 },
1444 { 1, 1066, 294, 24460 },
1445 { 1, 800, 294, 25192 },
1446 { 0, 1333, 276, 27605 },
1447 { 0, 1066, 276, 27605 },
1448 { 0, 800, 231, 23784 },
1449 };
1450
1451 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
1452 {
1453 u64 total_count, diff, ret;
1454 u32 count1, count2, count3, m = 0, c = 0;
1455 unsigned long now = jiffies_to_msecs(jiffies), diff1;
1456 int i;
1457
1458 diff1 = now - dev_priv->last_time1;
1459
1460 /* Prevent division-by-zero if we are asking too fast.
1461 * Also, we don't get interesting results if we are polling
1462 * faster than once in 10ms, so just return the saved value
1463 * in such cases.
1464 */
1465 if (diff1 <= 10)
1466 return dev_priv->chipset_power;
1467
1468 count1 = I915_READ(DMIEC);
1469 count2 = I915_READ(DDREC);
1470 count3 = I915_READ(CSIEC);
1471
1472 total_count = count1 + count2 + count3;
1473
1474 /* FIXME: handle per-counter overflow */
1475 if (total_count < dev_priv->last_count1) {
1476 diff = ~0UL - dev_priv->last_count1;
1477 diff += total_count;
1478 } else {
1479 diff = total_count - dev_priv->last_count1;
1480 }
1481
1482 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
1483 if (cparams[i].i == dev_priv->c_m &&
1484 cparams[i].t == dev_priv->r_t) {
1485 m = cparams[i].m;
1486 c = cparams[i].c;
1487 break;
1488 }
1489 }
1490
1491 diff = div_u64(diff, diff1);
1492 ret = ((m * diff) + c);
1493 ret = div_u64(ret, 10);
1494
1495 dev_priv->last_count1 = total_count;
1496 dev_priv->last_time1 = now;
1497
1498 dev_priv->chipset_power = ret;
1499
1500 return ret;
1501 }
1502
1503 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
1504 {
1505 unsigned long m, x, b;
1506 u32 tsfs;
1507
1508 tsfs = I915_READ(TSFS);
1509
1510 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
1511 x = I915_READ8(TR1);
1512
1513 b = tsfs & TSFS_INTR_MASK;
1514
1515 return ((m * x) / 127) - b;
1516 }
1517
1518 static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
1519 {
1520 static const struct v_table {
1521 u16 vd; /* in .1 mil */
1522 u16 vm; /* in .1 mil */
1523 } v_table[] = {
1524 { 0, 0, },
1525 { 375, 0, },
1526 { 500, 0, },
1527 { 625, 0, },
1528 { 750, 0, },
1529 { 875, 0, },
1530 { 1000, 0, },
1531 { 1125, 0, },
1532 { 4125, 3000, },
1533 { 4125, 3000, },
1534 { 4125, 3000, },
1535 { 4125, 3000, },
1536 { 4125, 3000, },
1537 { 4125, 3000, },
1538 { 4125, 3000, },
1539 { 4125, 3000, },
1540 { 4125, 3000, },
1541 { 4125, 3000, },
1542 { 4125, 3000, },
1543 { 4125, 3000, },
1544 { 4125, 3000, },
1545 { 4125, 3000, },
1546 { 4125, 3000, },
1547 { 4125, 3000, },
1548 { 4125, 3000, },
1549 { 4125, 3000, },
1550 { 4125, 3000, },
1551 { 4125, 3000, },
1552 { 4125, 3000, },
1553 { 4125, 3000, },
1554 { 4125, 3000, },
1555 { 4125, 3000, },
1556 { 4250, 3125, },
1557 { 4375, 3250, },
1558 { 4500, 3375, },
1559 { 4625, 3500, },
1560 { 4750, 3625, },
1561 { 4875, 3750, },
1562 { 5000, 3875, },
1563 { 5125, 4000, },
1564 { 5250, 4125, },
1565 { 5375, 4250, },
1566 { 5500, 4375, },
1567 { 5625, 4500, },
1568 { 5750, 4625, },
1569 { 5875, 4750, },
1570 { 6000, 4875, },
1571 { 6125, 5000, },
1572 { 6250, 5125, },
1573 { 6375, 5250, },
1574 { 6500, 5375, },
1575 { 6625, 5500, },
1576 { 6750, 5625, },
1577 { 6875, 5750, },
1578 { 7000, 5875, },
1579 { 7125, 6000, },
1580 { 7250, 6125, },
1581 { 7375, 6250, },
1582 { 7500, 6375, },
1583 { 7625, 6500, },
1584 { 7750, 6625, },
1585 { 7875, 6750, },
1586 { 8000, 6875, },
1587 { 8125, 7000, },
1588 { 8250, 7125, },
1589 { 8375, 7250, },
1590 { 8500, 7375, },
1591 { 8625, 7500, },
1592 { 8750, 7625, },
1593 { 8875, 7750, },
1594 { 9000, 7875, },
1595 { 9125, 8000, },
1596 { 9250, 8125, },
1597 { 9375, 8250, },
1598 { 9500, 8375, },
1599 { 9625, 8500, },
1600 { 9750, 8625, },
1601 { 9875, 8750, },
1602 { 10000, 8875, },
1603 { 10125, 9000, },
1604 { 10250, 9125, },
1605 { 10375, 9250, },
1606 { 10500, 9375, },
1607 { 10625, 9500, },
1608 { 10750, 9625, },
1609 { 10875, 9750, },
1610 { 11000, 9875, },
1611 { 11125, 10000, },
1612 { 11250, 10125, },
1613 { 11375, 10250, },
1614 { 11500, 10375, },
1615 { 11625, 10500, },
1616 { 11750, 10625, },
1617 { 11875, 10750, },
1618 { 12000, 10875, },
1619 { 12125, 11000, },
1620 { 12250, 11125, },
1621 { 12375, 11250, },
1622 { 12500, 11375, },
1623 { 12625, 11500, },
1624 { 12750, 11625, },
1625 { 12875, 11750, },
1626 { 13000, 11875, },
1627 { 13125, 12000, },
1628 { 13250, 12125, },
1629 { 13375, 12250, },
1630 { 13500, 12375, },
1631 { 13625, 12500, },
1632 { 13750, 12625, },
1633 { 13875, 12750, },
1634 { 14000, 12875, },
1635 { 14125, 13000, },
1636 { 14250, 13125, },
1637 { 14375, 13250, },
1638 { 14500, 13375, },
1639 { 14625, 13500, },
1640 { 14750, 13625, },
1641 { 14875, 13750, },
1642 { 15000, 13875, },
1643 { 15125, 14000, },
1644 { 15250, 14125, },
1645 { 15375, 14250, },
1646 { 15500, 14375, },
1647 { 15625, 14500, },
1648 { 15750, 14625, },
1649 { 15875, 14750, },
1650 { 16000, 14875, },
1651 { 16125, 15000, },
1652 };
1653 if (dev_priv->info->is_mobile)
1654 return v_table[pxvid].vm;
1655 else
1656 return v_table[pxvid].vd;
1657 }
1658
1659 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
1660 {
1661 struct timespec now, diff1;
1662 u64 diff;
1663 unsigned long diffms;
1664 u32 count;
1665
1666 getrawmonotonic(&now);
1667 diff1 = timespec_sub(now, dev_priv->last_time2);
1668
1669 /* Don't divide by 0 */
1670 diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
1671 if (!diffms)
1672 return;
1673
1674 count = I915_READ(GFXEC);
1675
1676 if (count < dev_priv->last_count2) {
1677 diff = ~0UL - dev_priv->last_count2;
1678 diff += count;
1679 } else {
1680 diff = count - dev_priv->last_count2;
1681 }
1682
1683 dev_priv->last_count2 = count;
1684 dev_priv->last_time2 = now;
1685
1686 /* More magic constants... */
1687 diff = diff * 1181;
1688 diff = div_u64(diff, diffms * 10);
1689 dev_priv->gfx_power = diff;
1690 }
1691
1692 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
1693 {
1694 unsigned long t, corr, state1, corr2, state2;
1695 u32 pxvid, ext_v;
1696
1697 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->cur_delay * 4));
1698 pxvid = (pxvid >> 24) & 0x7f;
1699 ext_v = pvid_to_extvid(dev_priv, pxvid);
1700
1701 state1 = ext_v;
1702
1703 t = i915_mch_val(dev_priv);
1704
1705 /* Revel in the empirically derived constants */
1706
1707 /* Correction factor in 1/100000 units */
1708 if (t > 80)
1709 corr = ((t * 2349) + 135940);
1710 else if (t >= 50)
1711 corr = ((t * 964) + 29317);
1712 else /* < 50 */
1713 corr = ((t * 301) + 1004);
1714
1715 corr = corr * ((150142 * state1) / 10000 - 78642);
1716 corr /= 100000;
1717 corr2 = (corr * dev_priv->corr);
1718
1719 state2 = (corr2 * state1) / 10000;
1720 state2 /= 100; /* convert to mW */
1721
1722 i915_update_gfx_val(dev_priv);
1723
1724 return dev_priv->gfx_power + state2;
1725 }
1726
1727 /* Global for IPS driver to get at the current i915 device */
1728 static struct drm_i915_private *i915_mch_dev;
1729 /*
1730 * Lock protecting IPS related data structures
1731 * - i915_mch_dev
1732 * - dev_priv->max_delay
1733 * - dev_priv->min_delay
1734 * - dev_priv->fmax
1735 * - dev_priv->gpu_busy
1736 */
1737 static DEFINE_SPINLOCK(mchdev_lock);
1738
1739 /**
1740 * i915_read_mch_val - return value for IPS use
1741 *
1742 * Calculate and return a value for the IPS driver to use when deciding whether
1743 * we have thermal and power headroom to increase CPU or GPU power budget.
1744 */
1745 unsigned long i915_read_mch_val(void)
1746 {
1747 struct drm_i915_private *dev_priv;
1748 unsigned long chipset_val, graphics_val, ret = 0;
1749
1750 spin_lock(&mchdev_lock);
1751 if (!i915_mch_dev)
1752 goto out_unlock;
1753 dev_priv = i915_mch_dev;
1754
1755 chipset_val = i915_chipset_val(dev_priv);
1756 graphics_val = i915_gfx_val(dev_priv);
1757
1758 ret = chipset_val + graphics_val;
1759
1760 out_unlock:
1761 spin_unlock(&mchdev_lock);
1762
1763 return ret;
1764 }
1765 EXPORT_SYMBOL_GPL(i915_read_mch_val);
1766
1767 /**
1768 * i915_gpu_raise - raise GPU frequency limit
1769 *
1770 * Raise the limit; IPS indicates we have thermal headroom.
1771 */
1772 bool i915_gpu_raise(void)
1773 {
1774 struct drm_i915_private *dev_priv;
1775 bool ret = true;
1776
1777 spin_lock(&mchdev_lock);
1778 if (!i915_mch_dev) {
1779 ret = false;
1780 goto out_unlock;
1781 }
1782 dev_priv = i915_mch_dev;
1783
1784 if (dev_priv->max_delay > dev_priv->fmax)
1785 dev_priv->max_delay--;
1786
1787 out_unlock:
1788 spin_unlock(&mchdev_lock);
1789
1790 return ret;
1791 }
1792 EXPORT_SYMBOL_GPL(i915_gpu_raise);
1793
1794 /**
1795 * i915_gpu_lower - lower GPU frequency limit
1796 *
1797 * IPS indicates we're close to a thermal limit, so throttle back the GPU
1798 * frequency maximum.
1799 */
1800 bool i915_gpu_lower(void)
1801 {
1802 struct drm_i915_private *dev_priv;
1803 bool ret = true;
1804
1805 spin_lock(&mchdev_lock);
1806 if (!i915_mch_dev) {
1807 ret = false;
1808 goto out_unlock;
1809 }
1810 dev_priv = i915_mch_dev;
1811
1812 if (dev_priv->max_delay < dev_priv->min_delay)
1813 dev_priv->max_delay++;
1814
1815 out_unlock:
1816 spin_unlock(&mchdev_lock);
1817
1818 return ret;
1819 }
1820 EXPORT_SYMBOL_GPL(i915_gpu_lower);
1821
1822 /**
1823 * i915_gpu_busy - indicate GPU business to IPS
1824 *
1825 * Tell the IPS driver whether or not the GPU is busy.
1826 */
1827 bool i915_gpu_busy(void)
1828 {
1829 struct drm_i915_private *dev_priv;
1830 bool ret = false;
1831
1832 spin_lock(&mchdev_lock);
1833 if (!i915_mch_dev)
1834 goto out_unlock;
1835 dev_priv = i915_mch_dev;
1836
1837 ret = dev_priv->busy;
1838
1839 out_unlock:
1840 spin_unlock(&mchdev_lock);
1841
1842 return ret;
1843 }
1844 EXPORT_SYMBOL_GPL(i915_gpu_busy);
1845
1846 /**
1847 * i915_gpu_turbo_disable - disable graphics turbo
1848 *
1849 * Disable graphics turbo by resetting the max frequency and setting the
1850 * current frequency to the default.
1851 */
1852 bool i915_gpu_turbo_disable(void)
1853 {
1854 struct drm_i915_private *dev_priv;
1855 bool ret = true;
1856
1857 spin_lock(&mchdev_lock);
1858 if (!i915_mch_dev) {
1859 ret = false;
1860 goto out_unlock;
1861 }
1862 dev_priv = i915_mch_dev;
1863
1864 dev_priv->max_delay = dev_priv->fstart;
1865
1866 if (!ironlake_set_drps(dev_priv->dev, dev_priv->fstart))
1867 ret = false;
1868
1869 out_unlock:
1870 spin_unlock(&mchdev_lock);
1871
1872 return ret;
1873 }
1874 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
1875
1876 /**
1877 * Tells the intel_ips driver that the i915 driver is now loaded, if
1878 * IPS got loaded first.
1879 *
1880 * This awkward dance is so that neither module has to depend on the
1881 * other in order for IPS to do the appropriate communication of
1882 * GPU turbo limits to i915.
1883 */
1884 static void
1885 ips_ping_for_i915_load(void)
1886 {
1887 void (*link)(void);
1888
1889 link = symbol_get(ips_link_to_i915_driver);
1890 if (link) {
1891 link();
1892 symbol_put(ips_link_to_i915_driver);
1893 }
1894 }
1895
1896 /**
1897 * i915_driver_load - setup chip and create an initial config
1898 * @dev: DRM device
1899 * @flags: startup flags
1900 *
1901 * The driver load routine has to do several things:
1902 * - drive output discovery via intel_modeset_init()
1903 * - initialize the memory manager
1904 * - allocate initial config memory
1905 * - setup the DRM framebuffer with the allocated memory
1906 */
1907 int i915_driver_load(struct drm_device *dev, unsigned long flags)
1908 {
1909 struct drm_i915_private *dev_priv;
1910 int ret = 0, mmio_bar;
1911 uint32_t agp_size;
1912
1913 /* i915 has 4 more counters */
1914 dev->counters += 4;
1915 dev->types[6] = _DRM_STAT_IRQ;
1916 dev->types[7] = _DRM_STAT_PRIMARY;
1917 dev->types[8] = _DRM_STAT_SECONDARY;
1918 dev->types[9] = _DRM_STAT_DMA;
1919
1920 dev_priv = kzalloc(sizeof(drm_i915_private_t), GFP_KERNEL);
1921 if (dev_priv == NULL)
1922 return -ENOMEM;
1923
1924 dev->dev_private = (void *)dev_priv;
1925 dev_priv->dev = dev;
1926 dev_priv->info = (struct intel_device_info *) flags;
1927
1928 if (i915_get_bridge_dev(dev)) {
1929 ret = -EIO;
1930 goto free_priv;
1931 }
1932
1933 /* overlay on gen2 is broken and can't address above 1G */
1934 if (IS_GEN2(dev))
1935 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30));
1936
1937 /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1938 * using 32bit addressing, overwriting memory if HWS is located
1939 * above 4GB.
1940 *
1941 * The documentation also mentions an issue with undefined
1942 * behaviour if any general state is accessed within a page above 4GB,
1943 * which also needs to be handled carefully.
1944 */
1945 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1946 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32));
1947
1948 mmio_bar = IS_GEN2(dev) ? 1 : 0;
1949 dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, 0);
1950 if (!dev_priv->regs) {
1951 DRM_ERROR("failed to map registers\n");
1952 ret = -EIO;
1953 goto put_bridge;
1954 }
1955
1956 dev_priv->mm.gtt = intel_gtt_get();
1957 if (!dev_priv->mm.gtt) {
1958 DRM_ERROR("Failed to initialize GTT\n");
1959 ret = -ENODEV;
1960 goto out_rmmap;
1961 }
1962
1963 agp_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
1964
1965 dev_priv->mm.gtt_mapping =
1966 io_mapping_create_wc(dev->agp->base, agp_size);
1967 if (dev_priv->mm.gtt_mapping == NULL) {
1968 ret = -EIO;
1969 goto out_rmmap;
1970 }
1971
1972 /* Set up a WC MTRR for non-PAT systems. This is more common than
1973 * one would think, because the kernel disables PAT on first
1974 * generation Core chips because WC PAT gets overridden by a UC
1975 * MTRR if present. Even if a UC MTRR isn't present.
1976 */
1977 dev_priv->mm.gtt_mtrr = mtrr_add(dev->agp->base,
1978 agp_size,
1979 MTRR_TYPE_WRCOMB, 1);
1980 if (dev_priv->mm.gtt_mtrr < 0) {
1981 DRM_INFO("MTRR allocation failed. Graphics "
1982 "performance may suffer.\n");
1983 }
1984
1985 /* The i915 workqueue is primarily used for batched retirement of
1986 * requests (and thus managing bo) once the task has been completed
1987 * by the GPU. i915_gem_retire_requests() is called directly when we
1988 * need high-priority retirement, such as waiting for an explicit
1989 * bo.
1990 *
1991 * It is also used for periodic low-priority events, such as
1992 * idle-timers and recording error state.
1993 *
1994 * All tasks on the workqueue are expected to acquire the dev mutex
1995 * so there is no point in running more than one instance of the
1996 * workqueue at any time: max_active = 1 and NON_REENTRANT.
1997 */
1998 dev_priv->wq = alloc_workqueue("i915",
1999 WQ_UNBOUND | WQ_NON_REENTRANT,
2000 1);
2001 if (dev_priv->wq == NULL) {
2002 DRM_ERROR("Failed to create our workqueue.\n");
2003 ret = -ENOMEM;
2004 goto out_mtrrfree;
2005 }
2006
2007 /* enable GEM by default */
2008 dev_priv->has_gem = 1;
2009
2010 intel_irq_init(dev);
2011
2012 /* Try to make sure MCHBAR is enabled before poking at it */
2013 intel_setup_mchbar(dev);
2014 intel_setup_gmbus(dev);
2015 intel_opregion_setup(dev);
2016
2017 /* Make sure the bios did its job and set up vital registers */
2018 intel_setup_bios(dev);
2019
2020 i915_gem_load(dev);
2021
2022 /* Init HWS */
2023 if (!I915_NEED_GFX_HWS(dev)) {
2024 ret = i915_init_phys_hws(dev);
2025 if (ret)
2026 goto out_gem_unload;
2027 }
2028
2029 if (IS_PINEVIEW(dev))
2030 i915_pineview_get_mem_freq(dev);
2031 else if (IS_GEN5(dev))
2032 i915_ironlake_get_mem_freq(dev);
2033
2034 /* On the 945G/GM, the chipset reports the MSI capability on the
2035 * integrated graphics even though the support isn't actually there
2036 * according to the published specs. It doesn't appear to function
2037 * correctly in testing on 945G.
2038 * This may be a side effect of MSI having been made available for PEG
2039 * and the registers being closely associated.
2040 *
2041 * According to chipset errata, on the 965GM, MSI interrupts may
2042 * be lost or delayed, but we use them anyways to avoid
2043 * stuck interrupts on some machines.
2044 */
2045 if (!IS_I945G(dev) && !IS_I945GM(dev))
2046 pci_enable_msi(dev->pdev);
2047
2048 spin_lock_init(&dev_priv->gt_lock);
2049 spin_lock_init(&dev_priv->irq_lock);
2050 spin_lock_init(&dev_priv->error_lock);
2051 spin_lock_init(&dev_priv->rps_lock);
2052
2053 if (IS_IVYBRIDGE(dev))
2054 dev_priv->num_pipe = 3;
2055 else if (IS_MOBILE(dev) || !IS_GEN2(dev))
2056 dev_priv->num_pipe = 2;
2057 else
2058 dev_priv->num_pipe = 1;
2059
2060 ret = drm_vblank_init(dev, dev_priv->num_pipe);
2061 if (ret)
2062 goto out_gem_unload;
2063
2064 /* Start out suspended */
2065 dev_priv->mm.suspended = 1;
2066
2067 intel_detect_pch(dev);
2068
2069 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
2070 ret = i915_load_modeset_init(dev);
2071 if (ret < 0) {
2072 DRM_ERROR("failed to init modeset\n");
2073 goto out_gem_unload;
2074 }
2075 }
2076
2077 /* Must be done after probing outputs */
2078 intel_opregion_init(dev);
2079 acpi_video_register();
2080
2081 setup_timer(&dev_priv->hangcheck_timer, i915_hangcheck_elapsed,
2082 (unsigned long) dev);
2083
2084 spin_lock(&mchdev_lock);
2085 i915_mch_dev = dev_priv;
2086 dev_priv->mchdev_lock = &mchdev_lock;
2087 spin_unlock(&mchdev_lock);
2088
2089 ips_ping_for_i915_load();
2090
2091 return 0;
2092
2093 out_gem_unload:
2094 if (dev_priv->mm.inactive_shrinker.shrink)
2095 unregister_shrinker(&dev_priv->mm.inactive_shrinker);
2096
2097 if (dev->pdev->msi_enabled)
2098 pci_disable_msi(dev->pdev);
2099
2100 intel_teardown_gmbus(dev);
2101 intel_teardown_mchbar(dev);
2102 destroy_workqueue(dev_priv->wq);
2103 out_mtrrfree:
2104 if (dev_priv->mm.gtt_mtrr >= 0) {
2105 mtrr_del(dev_priv->mm.gtt_mtrr, dev->agp->base,
2106 dev->agp->agp_info.aper_size * 1024 * 1024);
2107 dev_priv->mm.gtt_mtrr = -1;
2108 }
2109 io_mapping_free(dev_priv->mm.gtt_mapping);
2110 out_rmmap:
2111 pci_iounmap(dev->pdev, dev_priv->regs);
2112 put_bridge:
2113 pci_dev_put(dev_priv->bridge_dev);
2114 free_priv:
2115 kfree(dev_priv);
2116 return ret;
2117 }
2118
2119 int i915_driver_unload(struct drm_device *dev)
2120 {
2121 struct drm_i915_private *dev_priv = dev->dev_private;
2122 int ret;
2123
2124 spin_lock(&mchdev_lock);
2125 i915_mch_dev = NULL;
2126 spin_unlock(&mchdev_lock);
2127
2128 if (dev_priv->mm.inactive_shrinker.shrink)
2129 unregister_shrinker(&dev_priv->mm.inactive_shrinker);
2130
2131 mutex_lock(&dev->struct_mutex);
2132 ret = i915_gpu_idle(dev);
2133 if (ret)
2134 DRM_ERROR("failed to idle hardware: %d\n", ret);
2135 mutex_unlock(&dev->struct_mutex);
2136
2137 /* Cancel the retire work handler, which should be idle now. */
2138 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
2139
2140 io_mapping_free(dev_priv->mm.gtt_mapping);
2141 if (dev_priv->mm.gtt_mtrr >= 0) {
2142 mtrr_del(dev_priv->mm.gtt_mtrr, dev->agp->base,
2143 dev->agp->agp_info.aper_size * 1024 * 1024);
2144 dev_priv->mm.gtt_mtrr = -1;
2145 }
2146
2147 acpi_video_unregister();
2148
2149 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
2150 intel_fbdev_fini(dev);
2151 intel_modeset_cleanup(dev);
2152
2153 /*
2154 * free the memory space allocated for the child device
2155 * config parsed from VBT
2156 */
2157 if (dev_priv->child_dev && dev_priv->child_dev_num) {
2158 kfree(dev_priv->child_dev);
2159 dev_priv->child_dev = NULL;
2160 dev_priv->child_dev_num = 0;
2161 }
2162
2163 vga_switcheroo_unregister_client(dev->pdev);
2164 vga_client_register(dev->pdev, NULL, NULL, NULL);
2165 }
2166
2167 /* Free error state after interrupts are fully disabled. */
2168 del_timer_sync(&dev_priv->hangcheck_timer);
2169 cancel_work_sync(&dev_priv->error_work);
2170 i915_destroy_error_state(dev);
2171
2172 if (dev->pdev->msi_enabled)
2173 pci_disable_msi(dev->pdev);
2174
2175 intel_opregion_fini(dev);
2176
2177 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
2178 /* Flush any outstanding unpin_work. */
2179 flush_workqueue(dev_priv->wq);
2180
2181 mutex_lock(&dev->struct_mutex);
2182 i915_gem_free_all_phys_object(dev);
2183 i915_gem_cleanup_ringbuffer(dev);
2184 mutex_unlock(&dev->struct_mutex);
2185 if (I915_HAS_FBC(dev) && i915_powersave)
2186 i915_cleanup_compression(dev);
2187 drm_mm_takedown(&dev_priv->mm.stolen);
2188
2189 intel_cleanup_overlay(dev);
2190
2191 if (!I915_NEED_GFX_HWS(dev))
2192 i915_free_hws(dev);
2193 }
2194
2195 if (dev_priv->regs != NULL)
2196 pci_iounmap(dev->pdev, dev_priv->regs);
2197
2198 intel_teardown_gmbus(dev);
2199 intel_teardown_mchbar(dev);
2200
2201 destroy_workqueue(dev_priv->wq);
2202
2203 pci_dev_put(dev_priv->bridge_dev);
2204 kfree(dev->dev_private);
2205
2206 return 0;
2207 }
2208
2209 int i915_driver_open(struct drm_device *dev, struct drm_file *file)
2210 {
2211 struct drm_i915_file_private *file_priv;
2212
2213 DRM_DEBUG_DRIVER("\n");
2214 file_priv = kmalloc(sizeof(*file_priv), GFP_KERNEL);
2215 if (!file_priv)
2216 return -ENOMEM;
2217
2218 file->driver_priv = file_priv;
2219
2220 spin_lock_init(&file_priv->mm.lock);
2221 INIT_LIST_HEAD(&file_priv->mm.request_list);
2222
2223 return 0;
2224 }
2225
2226 /**
2227 * i915_driver_lastclose - clean up after all DRM clients have exited
2228 * @dev: DRM device
2229 *
2230 * Take care of cleaning up after all DRM clients have exited. In the
2231 * mode setting case, we want to restore the kernel's initial mode (just
2232 * in case the last client left us in a bad state).
2233 *
2234 * Additionally, in the non-mode setting case, we'll tear down the AGP
2235 * and DMA structures, since the kernel won't be using them, and clea
2236 * up any GEM state.
2237 */
2238 void i915_driver_lastclose(struct drm_device * dev)
2239 {
2240 drm_i915_private_t *dev_priv = dev->dev_private;
2241
2242 if (!dev_priv || drm_core_check_feature(dev, DRIVER_MODESET)) {
2243 intel_fb_restore_mode(dev);
2244 vga_switcheroo_process_delayed_switch();
2245 return;
2246 }
2247
2248 i915_gem_lastclose(dev);
2249
2250 if (dev_priv->agp_heap)
2251 i915_mem_takedown(&(dev_priv->agp_heap));
2252
2253 i915_dma_cleanup(dev);
2254 }
2255
2256 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
2257 {
2258 drm_i915_private_t *dev_priv = dev->dev_private;
2259 i915_gem_release(dev, file_priv);
2260 if (!drm_core_check_feature(dev, DRIVER_MODESET))
2261 i915_mem_release(dev, file_priv, dev_priv->agp_heap);
2262 }
2263
2264 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
2265 {
2266 struct drm_i915_file_private *file_priv = file->driver_priv;
2267
2268 kfree(file_priv);
2269 }
2270
2271 struct drm_ioctl_desc i915_ioctls[] = {
2272 DRM_IOCTL_DEF_DRV(I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2273 DRM_IOCTL_DEF_DRV(I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
2274 DRM_IOCTL_DEF_DRV(I915_FLIP, i915_flip_bufs, DRM_AUTH),
2275 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
2276 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
2277 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
2278 DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH),
2279 DRM_IOCTL_DEF_DRV(I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2280 DRM_IOCTL_DEF_DRV(I915_ALLOC, i915_mem_alloc, DRM_AUTH),
2281 DRM_IOCTL_DEF_DRV(I915_FREE, i915_mem_free, DRM_AUTH),
2282 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2283 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
2284 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2285 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2286 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, i915_vblank_pipe_get, DRM_AUTH),
2287 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
2288 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2289 DRM_IOCTL_DEF_DRV(I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2290 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED),
2291 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED),
2292 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
2293 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
2294 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
2295 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED),
2296 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2297 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2298 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED),
2299 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED),
2300 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED),
2301 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED),
2302 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED),
2303 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED),
2304 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED),
2305 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED),
2306 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED),
2307 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED),
2308 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
2309 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED),
2310 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2311 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2312 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2313 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, intel_sprite_get_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2314 };
2315
2316 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
2317
2318 /**
2319 * Determine if the device really is AGP or not.
2320 *
2321 * All Intel graphics chipsets are treated as AGP, even if they are really
2322 * PCI-e.
2323 *
2324 * \param dev The device to be tested.
2325 *
2326 * \returns
2327 * A value of 1 is always retured to indictate every i9x5 is AGP.
2328 */
2329 int i915_driver_device_is_agp(struct drm_device * dev)
2330 {
2331 return 1;
2332 }