4 * Copyright (C) 2008 Renesas Solutions Corp.
5 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
7 * Based on ov772x driver,
9 * Copyright (C) 2008 Kuninori Morimoto <morimoto.kuninori@renesas.com>
10 * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
11 * Copyright (C) 2008 Magnus Damm
12 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
19 #include <linux/init.h>
20 #include <linux/module.h>
21 #include <linux/i2c.h>
22 #include <linux/slab.h>
23 #include <linux/kernel.h>
24 #include <linux/delay.h>
25 #include <linux/v4l2-mediabus.h>
26 #include <linux/videodev2.h>
28 #include <media/soc_camera.h>
29 #include <media/tw9910.h>
30 #include <media/v4l2-chip-ident.h>
31 #include <media/v4l2-subdev.h>
33 #define GET_ID(val) ((val & 0xF8) >> 3)
34 #define GET_REV(val) (val & 0x07)
39 #define ID 0x00 /* Product ID Code Register */
40 #define STATUS1 0x01 /* Chip Status Register I */
41 #define INFORM 0x02 /* Input Format */
42 #define OPFORM 0x03 /* Output Format Control Register */
43 #define DLYCTR 0x04 /* Hysteresis and HSYNC Delay Control */
44 #define OUTCTR1 0x05 /* Output Control I */
45 #define ACNTL1 0x06 /* Analog Control Register 1 */
46 #define CROP_HI 0x07 /* Cropping Register, High */
47 #define VDELAY_LO 0x08 /* Vertical Delay Register, Low */
48 #define VACTIVE_LO 0x09 /* Vertical Active Register, Low */
49 #define HDELAY_LO 0x0A /* Horizontal Delay Register, Low */
50 #define HACTIVE_LO 0x0B /* Horizontal Active Register, Low */
51 #define CNTRL1 0x0C /* Control Register I */
52 #define VSCALE_LO 0x0D /* Vertical Scaling Register, Low */
53 #define SCALE_HI 0x0E /* Scaling Register, High */
54 #define HSCALE_LO 0x0F /* Horizontal Scaling Register, Low */
55 #define BRIGHT 0x10 /* BRIGHTNESS Control Register */
56 #define CONTRAST 0x11 /* CONTRAST Control Register */
57 #define SHARPNESS 0x12 /* SHARPNESS Control Register I */
58 #define SAT_U 0x13 /* Chroma (U) Gain Register */
59 #define SAT_V 0x14 /* Chroma (V) Gain Register */
60 #define HUE 0x15 /* Hue Control Register */
62 #define CORING2 0x18 /* Coring and IF compensation */
63 #define VBICNTL 0x19 /* VBI Control Register */
64 #define ACNTL2 0x1A /* Analog Control 2 */
65 #define OUTCTR2 0x1B /* Output Control 2 */
66 #define SDT 0x1C /* Standard Selection */
67 #define SDTR 0x1D /* Standard Recognition */
68 #define TEST 0x1F /* Test Control Register */
69 #define CLMPG 0x20 /* Clamping Gain */
70 #define IAGC 0x21 /* Individual AGC Gain */
71 #define AGCGAIN 0x22 /* AGC Gain */
72 #define PEAKWT 0x23 /* White Peak Threshold */
73 #define CLMPL 0x24 /* Clamp level */
74 #define SYNCT 0x25 /* Sync Amplitude */
75 #define MISSCNT 0x26 /* Sync Miss Count Register */
76 #define PCLAMP 0x27 /* Clamp Position Register */
77 #define VCNTL1 0x28 /* Vertical Control I */
78 #define VCNTL2 0x29 /* Vertical Control II */
79 #define CKILL 0x2A /* Color Killer Level Control */
80 #define COMB 0x2B /* Comb Filter Control */
81 #define LDLY 0x2C /* Luma Delay and H Filter Control */
82 #define MISC1 0x2D /* Miscellaneous Control I */
83 #define LOOP 0x2E /* LOOP Control Register */
84 #define MISC2 0x2F /* Miscellaneous Control II */
85 #define MVSN 0x30 /* Macrovision Detection */
86 #define STATUS2 0x31 /* Chip STATUS II */
87 #define HFREF 0x32 /* H monitor */
88 #define CLMD 0x33 /* CLAMP MODE */
89 #define IDCNTL 0x34 /* ID Detection Control */
90 #define CLCNTL1 0x35 /* Clamp Control I */
91 #define ANAPLLCTL 0x4C
126 #define VBIDELAY 0x6F
133 #define FC27_ON 0x40 /* 1 : Input crystal clock frequency is 27MHz */
134 #define FC27_FF 0x00 /* 0 : Square pixel mode. */
135 /* Must use 24.54MHz for 60Hz field rate */
136 /* source or 29.5MHz for 50Hz field rate */
137 #define IFSEL_S 0x10 /* 01 : S-video decoding */
138 #define IFSEL_C 0x00 /* 00 : Composite video decoding */
139 /* Y input video selection */
140 #define YSEL_M0 0x00 /* 00 : Mux0 selected */
141 #define YSEL_M1 0x04 /* 01 : Mux1 selected */
142 #define YSEL_M2 0x08 /* 10 : Mux2 selected */
143 #define YSEL_M3 0x10 /* 11 : Mux3 selected */
146 #define MODE 0x80 /* 0 : CCIR601 compatible YCrCb 4:2:2 format */
147 /* 1 : ITU-R-656 compatible data sequence format */
148 #define LEN 0x40 /* 0 : 8-bit YCrCb 4:2:2 output format */
149 /* 1 : 16-bit YCrCb 4:2:2 output format.*/
150 #define LLCMODE 0x20 /* 1 : LLC output mode. */
151 /* 0 : free-run output mode */
152 #define AINC 0x10 /* Serial interface auto-indexing control */
153 /* 0 : auto-increment */
155 #define VSCTL 0x08 /* 1 : Vertical out ctrl by DVALID */
156 /* 0 : Vertical out ctrl by HACTIVE and DVALID */
157 #define OEN_TRI_SEL_MASK 0x07
158 #define OEN_TRI_SEL_ALL_ON 0x00 /* Enable output for Rev0/Rev1 */
159 #define OEN_TRI_SEL_ALL_OFF_r0 0x06 /* All tri-stated for Rev0 */
160 #define OEN_TRI_SEL_ALL_OFF_r1 0x07 /* All tri-stated for Rev1 */
163 #define VSP_LO 0x00 /* 0 : VS pin output polarity is active low */
164 #define VSP_HI 0x80 /* 1 : VS pin output polarity is active high. */
165 /* VS pin output control */
166 #define VSSL_VSYNC 0x00 /* 0 : VSYNC */
167 #define VSSL_VACT 0x10 /* 1 : VACT */
168 #define VSSL_FIELD 0x20 /* 2 : FIELD */
169 #define VSSL_VVALID 0x30 /* 3 : VVALID */
170 #define VSSL_ZERO 0x70 /* 7 : 0 */
171 #define HSP_LOW 0x00 /* 0 : HS pin output polarity is active low */
172 #define HSP_HI 0x08 /* 1 : HS pin output polarity is active high.*/
173 /* HS pin output control */
174 #define HSSL_HACT 0x00 /* 0 : HACT */
175 #define HSSL_HSYNC 0x01 /* 1 : HSYNC */
176 #define HSSL_DVALID 0x02 /* 2 : DVALID */
177 #define HSSL_HLOCK 0x03 /* 3 : HLOCK */
178 #define HSSL_ASYNCW 0x04 /* 4 : ASYNCW */
179 #define HSSL_ZERO 0x07 /* 7 : 0 */
182 #define SRESET 0x80 /* resets the device to its default state
183 * but all register content remain unchanged.
184 * This bit is self-resetting.
186 #define ACNTL1_PDN_MASK 0x0e
187 #define CLK_PDN 0x08 /* system clock power down */
188 #define Y_PDN 0x04 /* Luma ADC power down */
189 #define C_PDN 0x02 /* Chroma ADC power down */
192 #define ACNTL2_PDN_MASK 0x40
193 #define PLL_PDN 0x40 /* PLL power down */
197 /* RTSEL : control the real time signal output from the MPOUT pin */
198 #define RTSEL_MASK 0x07
199 #define RTSEL_VLOSS 0x00 /* 0000 = Video loss */
200 #define RTSEL_HLOCK 0x01 /* 0001 = H-lock */
201 #define RTSEL_SLOCK 0x02 /* 0010 = S-lock */
202 #define RTSEL_VLOCK 0x03 /* 0011 = V-lock */
203 #define RTSEL_MONO 0x04 /* 0100 = MONO */
204 #define RTSEL_DET50 0x05 /* 0101 = DET50 */
205 #define RTSEL_FIELD 0x06 /* 0110 = FIELD */
206 #define RTSEL_RTCO 0x07 /* 0111 = RTCO ( Real Time Control ) */
208 /* HSYNC start and end are constant for now */
209 #define HSYNC_START 0x0260
210 #define HSYNC_END 0x0300
217 unsigned char reg_num
;
221 struct tw9910_scale_ctrl
{
223 unsigned short width
;
224 unsigned short height
;
230 struct v4l2_subdev subdev
;
231 struct tw9910_video_info
*info
;
232 const struct tw9910_scale_ctrl
*scale
;
237 static const struct tw9910_scale_ctrl tw9910_ntsc_scales
[] = {
246 .name
= "NTSC CCIR601",
253 .name
= "NTSC SQ (CIF)",
260 .name
= "NTSC CCIR601 (CIF)",
267 .name
= "NTSC SQ (QCIF)",
274 .name
= "NTSC CCIR601 (QCIF)",
282 static const struct tw9910_scale_ctrl tw9910_pal_scales
[] = {
291 .name
= "PAL CCIR601",
298 .name
= "PAL SQ (CIF)",
305 .name
= "PAL CCIR601 (CIF)",
312 .name
= "PAL SQ (QCIF)",
319 .name
= "PAL CCIR601 (QCIF)",
330 static struct tw9910_priv
*to_tw9910(const struct i2c_client
*client
)
332 return container_of(i2c_get_clientdata(client
), struct tw9910_priv
,
336 static int tw9910_mask_set(struct i2c_client
*client
, u8 command
,
339 s32 val
= i2c_smbus_read_byte_data(client
, command
);
346 return i2c_smbus_write_byte_data(client
, command
, val
);
349 static int tw9910_set_scale(struct i2c_client
*client
,
350 const struct tw9910_scale_ctrl
*scale
)
354 ret
= i2c_smbus_write_byte_data(client
, SCALE_HI
,
355 (scale
->vscale
& 0x0F00) >> 4 |
356 (scale
->hscale
& 0x0F00) >> 8);
360 ret
= i2c_smbus_write_byte_data(client
, HSCALE_LO
,
361 scale
->hscale
& 0x00FF);
365 ret
= i2c_smbus_write_byte_data(client
, VSCALE_LO
,
366 scale
->vscale
& 0x00FF);
371 static int tw9910_set_hsync(struct i2c_client
*client
)
373 struct tw9910_priv
*priv
= to_tw9910(client
);
377 ret
= i2c_smbus_write_byte_data(client
, HSBEGIN
,
378 (HSYNC_START
& 0x07F8) >> 3);
383 ret
= i2c_smbus_write_byte_data(client
, HSEND
,
384 (HSYNC_END
& 0x07F8) >> 3);
388 /* So far only revisions 0 and 1 have been seen */
390 if (1 == priv
->revision
)
391 ret
= tw9910_mask_set(client
, HSLOWCTL
, 0x77,
392 (HSYNC_START
& 0x0007) << 4 |
393 (HSYNC_END
& 0x0007));
398 static void tw9910_reset(struct i2c_client
*client
)
400 tw9910_mask_set(client
, ACNTL1
, SRESET
, SRESET
);
404 static int tw9910_power(struct i2c_client
*client
, int enable
)
414 acntl1
= CLK_PDN
| Y_PDN
| C_PDN
;
418 ret
= tw9910_mask_set(client
, ACNTL1
, ACNTL1_PDN_MASK
, acntl1
);
422 return tw9910_mask_set(client
, ACNTL2
, ACNTL2_PDN_MASK
, acntl2
);
425 static const struct tw9910_scale_ctrl
*tw9910_select_norm(v4l2_std_id norm
,
426 u32 width
, u32 height
)
428 const struct tw9910_scale_ctrl
*scale
;
429 const struct tw9910_scale_ctrl
*ret
= NULL
;
430 __u32 diff
= 0xffffffff, tmp
;
433 if (norm
& V4L2_STD_NTSC
) {
434 scale
= tw9910_ntsc_scales
;
435 size
= ARRAY_SIZE(tw9910_ntsc_scales
);
436 } else if (norm
& V4L2_STD_PAL
) {
437 scale
= tw9910_pal_scales
;
438 size
= ARRAY_SIZE(tw9910_pal_scales
);
443 for (i
= 0; i
< size
; i
++) {
444 tmp
= abs(width
- scale
[i
].width
) +
445 abs(height
- scale
[i
].height
);
456 * subdevice operations
458 static int tw9910_s_stream(struct v4l2_subdev
*sd
, int enable
)
460 struct i2c_client
*client
= v4l2_get_subdevdata(sd
);
461 struct tw9910_priv
*priv
= to_tw9910(client
);
466 switch (priv
->revision
) {
468 val
= OEN_TRI_SEL_ALL_OFF_r0
;
471 val
= OEN_TRI_SEL_ALL_OFF_r1
;
474 dev_err(&client
->dev
, "un-supported revision\n");
478 val
= OEN_TRI_SEL_ALL_ON
;
481 dev_err(&client
->dev
, "norm select error\n");
485 dev_dbg(&client
->dev
, "%s %dx%d\n",
488 priv
->scale
->height
);
491 ret
= tw9910_mask_set(client
, OPFORM
, OEN_TRI_SEL_MASK
, val
);
495 return tw9910_power(client
, enable
);
498 static int tw9910_g_std(struct v4l2_subdev
*sd
, v4l2_std_id
*norm
)
500 struct i2c_client
*client
= v4l2_get_subdevdata(sd
);
501 struct tw9910_priv
*priv
= to_tw9910(client
);
508 static int tw9910_s_std(struct v4l2_subdev
*sd
, v4l2_std_id norm
)
510 struct i2c_client
*client
= v4l2_get_subdevdata(sd
);
511 struct tw9910_priv
*priv
= to_tw9910(client
);
513 if (!(norm
& (V4L2_STD_NTSC
| V4L2_STD_PAL
)))
521 static int tw9910_g_chip_ident(struct v4l2_subdev
*sd
,
522 struct v4l2_dbg_chip_ident
*id
)
524 struct i2c_client
*client
= v4l2_get_subdevdata(sd
);
525 struct tw9910_priv
*priv
= to_tw9910(client
);
527 id
->ident
= V4L2_IDENT_TW9910
;
528 id
->revision
= priv
->revision
;
533 #ifdef CONFIG_VIDEO_ADV_DEBUG
534 static int tw9910_g_register(struct v4l2_subdev
*sd
,
535 struct v4l2_dbg_register
*reg
)
537 struct i2c_client
*client
= v4l2_get_subdevdata(sd
);
543 ret
= i2c_smbus_read_byte_data(client
, reg
->reg
);
551 reg
->val
= (__u64
)ret
;
556 static int tw9910_s_register(struct v4l2_subdev
*sd
,
557 struct v4l2_dbg_register
*reg
)
559 struct i2c_client
*client
= v4l2_get_subdevdata(sd
);
561 if (reg
->reg
> 0xff ||
565 return i2c_smbus_write_byte_data(client
, reg
->reg
, reg
->val
);
569 static int tw9910_set_frame(struct v4l2_subdev
*sd
, u32
*width
, u32
*height
)
571 struct i2c_client
*client
= v4l2_get_subdevdata(sd
);
572 struct tw9910_priv
*priv
= to_tw9910(client
);
577 * select suitable norm
579 priv
->scale
= tw9910_select_norm(priv
->norm
, *width
, *height
);
581 goto tw9910_set_fmt_error
;
586 tw9910_reset(client
);
592 if (SOCAM_DATAWIDTH_16
== priv
->info
->buswidth
)
595 ret
= tw9910_mask_set(client
, OPFORM
, LEN
, val
);
597 goto tw9910_set_fmt_error
;
600 * select MPOUT behavior
602 switch (priv
->info
->mpout
) {
603 case TW9910_MPO_VLOSS
:
604 val
= RTSEL_VLOSS
; break;
605 case TW9910_MPO_HLOCK
:
606 val
= RTSEL_HLOCK
; break;
607 case TW9910_MPO_SLOCK
:
608 val
= RTSEL_SLOCK
; break;
609 case TW9910_MPO_VLOCK
:
610 val
= RTSEL_VLOCK
; break;
611 case TW9910_MPO_MONO
:
612 val
= RTSEL_MONO
; break;
613 case TW9910_MPO_DET50
:
614 val
= RTSEL_DET50
; break;
615 case TW9910_MPO_FIELD
:
616 val
= RTSEL_FIELD
; break;
617 case TW9910_MPO_RTCO
:
618 val
= RTSEL_RTCO
; break;
623 ret
= tw9910_mask_set(client
, VBICNTL
, RTSEL_MASK
, val
);
625 goto tw9910_set_fmt_error
;
630 ret
= tw9910_set_scale(client
, priv
->scale
);
632 goto tw9910_set_fmt_error
;
637 ret
= tw9910_set_hsync(client
);
639 goto tw9910_set_fmt_error
;
641 *width
= priv
->scale
->width
;
642 *height
= priv
->scale
->height
;
646 tw9910_set_fmt_error
:
648 tw9910_reset(client
);
654 static int tw9910_g_crop(struct v4l2_subdev
*sd
, struct v4l2_crop
*a
)
656 struct i2c_client
*client
= v4l2_get_subdevdata(sd
);
657 struct tw9910_priv
*priv
= to_tw9910(client
);
661 if (priv
->norm
& V4L2_STD_NTSC
) {
668 a
->type
= V4L2_BUF_TYPE_VIDEO_CAPTURE
;
673 static int tw9910_cropcap(struct v4l2_subdev
*sd
, struct v4l2_cropcap
*a
)
675 struct i2c_client
*client
= v4l2_get_subdevdata(sd
);
676 struct tw9910_priv
*priv
= to_tw9910(client
);
680 if (priv
->norm
& V4L2_STD_NTSC
) {
681 a
->bounds
.width
= 640;
682 a
->bounds
.height
= 480;
684 a
->bounds
.width
= 768;
685 a
->bounds
.height
= 576;
687 a
->defrect
= a
->bounds
;
688 a
->type
= V4L2_BUF_TYPE_VIDEO_CAPTURE
;
689 a
->pixelaspect
.numerator
= 1;
690 a
->pixelaspect
.denominator
= 1;
695 static int tw9910_g_fmt(struct v4l2_subdev
*sd
,
696 struct v4l2_mbus_framefmt
*mf
)
698 struct i2c_client
*client
= v4l2_get_subdevdata(sd
);
699 struct tw9910_priv
*priv
= to_tw9910(client
);
703 u32 width
= 640, height
= 480;
704 ret
= tw9910_set_frame(sd
, &width
, &height
);
709 mf
->width
= priv
->scale
->width
;
710 mf
->height
= priv
->scale
->height
;
711 mf
->code
= V4L2_MBUS_FMT_UYVY8_2X8
;
712 mf
->colorspace
= V4L2_COLORSPACE_JPEG
;
713 mf
->field
= V4L2_FIELD_INTERLACED_BT
;
718 static int tw9910_s_fmt(struct v4l2_subdev
*sd
,
719 struct v4l2_mbus_framefmt
*mf
)
721 u32 width
= mf
->width
, height
= mf
->height
;
724 WARN_ON(mf
->field
!= V4L2_FIELD_ANY
&&
725 mf
->field
!= V4L2_FIELD_INTERLACED_BT
);
730 if (mf
->code
!= V4L2_MBUS_FMT_UYVY8_2X8
)
733 mf
->colorspace
= V4L2_COLORSPACE_JPEG
;
735 ret
= tw9910_set_frame(sd
, &width
, &height
);
743 static int tw9910_try_fmt(struct v4l2_subdev
*sd
,
744 struct v4l2_mbus_framefmt
*mf
)
746 struct i2c_client
*client
= v4l2_get_subdevdata(sd
);
747 struct tw9910_priv
*priv
= to_tw9910(client
);
748 const struct tw9910_scale_ctrl
*scale
;
750 if (V4L2_FIELD_ANY
== mf
->field
) {
751 mf
->field
= V4L2_FIELD_INTERLACED_BT
;
752 } else if (V4L2_FIELD_INTERLACED_BT
!= mf
->field
) {
753 dev_err(&client
->dev
, "Field type %d invalid.\n", mf
->field
);
757 mf
->code
= V4L2_MBUS_FMT_UYVY8_2X8
;
758 mf
->colorspace
= V4L2_COLORSPACE_JPEG
;
761 * select suitable norm
763 scale
= tw9910_select_norm(priv
->norm
, mf
->width
, mf
->height
);
767 mf
->width
= scale
->width
;
768 mf
->height
= scale
->height
;
773 static int tw9910_video_probe(struct i2c_client
*client
)
775 struct tw9910_priv
*priv
= to_tw9910(client
);
779 * tw9910 only use 8 or 16 bit bus width
781 if (SOCAM_DATAWIDTH_16
!= priv
->info
->buswidth
&&
782 SOCAM_DATAWIDTH_8
!= priv
->info
->buswidth
) {
783 dev_err(&client
->dev
, "bus width error\n");
788 * check and show Product ID
789 * So far only revisions 0 and 1 have been seen
791 id
= i2c_smbus_read_byte_data(client
, ID
);
792 priv
->revision
= GET_REV(id
);
796 0x01 < priv
->revision
) {
797 dev_err(&client
->dev
,
798 "Product ID error %x:%x\n",
803 dev_info(&client
->dev
,
804 "tw9910 Product ID %0x:%0x\n", id
, priv
->revision
);
806 priv
->norm
= V4L2_STD_NTSC
;
811 static struct v4l2_subdev_core_ops tw9910_subdev_core_ops
= {
812 .g_chip_ident
= tw9910_g_chip_ident
,
813 .s_std
= tw9910_s_std
,
814 .g_std
= tw9910_g_std
,
815 #ifdef CONFIG_VIDEO_ADV_DEBUG
816 .g_register
= tw9910_g_register
,
817 .s_register
= tw9910_s_register
,
821 static int tw9910_enum_fmt(struct v4l2_subdev
*sd
, unsigned int index
,
822 enum v4l2_mbus_pixelcode
*code
)
827 *code
= V4L2_MBUS_FMT_UYVY8_2X8
;
831 static int tw9910_g_mbus_config(struct v4l2_subdev
*sd
,
832 struct v4l2_mbus_config
*cfg
)
834 struct i2c_client
*client
= v4l2_get_subdevdata(sd
);
835 struct soc_camera_link
*icl
= soc_camera_i2c_to_link(client
);
837 cfg
->flags
= V4L2_MBUS_PCLK_SAMPLE_RISING
| V4L2_MBUS_MASTER
|
838 V4L2_MBUS_VSYNC_ACTIVE_HIGH
| V4L2_MBUS_VSYNC_ACTIVE_LOW
|
839 V4L2_MBUS_HSYNC_ACTIVE_HIGH
| V4L2_MBUS_HSYNC_ACTIVE_LOW
|
840 V4L2_MBUS_DATA_ACTIVE_HIGH
;
841 cfg
->type
= V4L2_MBUS_PARALLEL
;
842 cfg
->flags
= soc_camera_apply_board_flags(icl
, cfg
);
847 static int tw9910_s_mbus_config(struct v4l2_subdev
*sd
,
848 const struct v4l2_mbus_config
*cfg
)
850 struct i2c_client
*client
= v4l2_get_subdevdata(sd
);
851 struct soc_camera_link
*icl
= soc_camera_i2c_to_link(client
);
852 u8 val
= VSSL_VVALID
| HSSL_DVALID
;
853 unsigned long flags
= soc_camera_apply_board_flags(icl
, cfg
);
858 * We use VVALID and DVALID signals to control VSYNC and HSYNC
859 * outputs, in this mode their polarity is inverted.
861 if (flags
& V4L2_MBUS_HSYNC_ACTIVE_LOW
)
864 if (flags
& V4L2_MBUS_VSYNC_ACTIVE_LOW
)
867 return i2c_smbus_write_byte_data(client
, OUTCTR1
, val
);
870 static struct v4l2_subdev_video_ops tw9910_subdev_video_ops
= {
871 .s_stream
= tw9910_s_stream
,
872 .g_mbus_fmt
= tw9910_g_fmt
,
873 .s_mbus_fmt
= tw9910_s_fmt
,
874 .try_mbus_fmt
= tw9910_try_fmt
,
875 .cropcap
= tw9910_cropcap
,
876 .g_crop
= tw9910_g_crop
,
877 .enum_mbus_fmt
= tw9910_enum_fmt
,
878 .g_mbus_config
= tw9910_g_mbus_config
,
879 .s_mbus_config
= tw9910_s_mbus_config
,
882 static struct v4l2_subdev_ops tw9910_subdev_ops
= {
883 .core
= &tw9910_subdev_core_ops
,
884 .video
= &tw9910_subdev_video_ops
,
888 * i2c_driver function
891 static int tw9910_probe(struct i2c_client
*client
,
892 const struct i2c_device_id
*did
)
895 struct tw9910_priv
*priv
;
896 struct tw9910_video_info
*info
;
897 struct i2c_adapter
*adapter
=
898 to_i2c_adapter(client
->dev
.parent
);
899 struct soc_camera_link
*icl
= soc_camera_i2c_to_link(client
);
902 if (!icl
|| !icl
->priv
) {
903 dev_err(&client
->dev
, "TW9910: missing platform data!\n");
909 if (!i2c_check_functionality(adapter
, I2C_FUNC_SMBUS_BYTE_DATA
)) {
910 dev_err(&client
->dev
,
911 "I2C-Adapter doesn't support "
912 "I2C_FUNC_SMBUS_BYTE_DATA\n");
916 priv
= kzalloc(sizeof(*priv
), GFP_KERNEL
);
922 v4l2_i2c_subdev_init(&priv
->subdev
, client
, &tw9910_subdev_ops
);
924 ret
= tw9910_video_probe(client
);
931 static int tw9910_remove(struct i2c_client
*client
)
933 struct tw9910_priv
*priv
= to_tw9910(client
);
939 static const struct i2c_device_id tw9910_id
[] = {
943 MODULE_DEVICE_TABLE(i2c
, tw9910_id
);
945 static struct i2c_driver tw9910_i2c_driver
= {
949 .probe
= tw9910_probe
,
950 .remove
= tw9910_remove
,
951 .id_table
= tw9910_id
,
957 static int __init
tw9910_module_init(void)
959 return i2c_add_driver(&tw9910_i2c_driver
);
962 static void __exit
tw9910_module_exit(void)
964 i2c_del_driver(&tw9910_i2c_driver
);
967 module_init(tw9910_module_init
);
968 module_exit(tw9910_module_exit
);
970 MODULE_DESCRIPTION("SoC Camera driver for tw9910");
971 MODULE_AUTHOR("Kuninori Morimoto");
972 MODULE_LICENSE("GPL v2");